return 0;
}
+#if 0
static int FlushCacheDRI(u32 ui32Type, u32 ui32Virt, u32 ui32Length)
{
switch (ui32Type) {
return 0;
}
+#endif
static int PVRSRVMapDeviceClassMemoryBW(u32 ui32BridgeID,
struct PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY *psMapDevClassMemIN,
case PVRSRV_BRIDGE_RELEASE_MMAP_DATA:
err = PVRMMapReleaseMMapDataBW(cmd, in, out, per_proc);
break;
+#if 0
case PVRSRV_BRIDGE_CACHE_FLUSH_DRM:
err = PVRSRVCacheFlushDRIBW(cmd, in, out, per_proc);
break;
-
+#endif
case PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT:
case PVRSRV_BRIDGE_REGISTER_SIM_PROCESS:
case PVRSRV_BRIDGE_UNREGISTER_SIM_PROCESS:
(long)ps2DQueryBltsCompleteIN->
hKernSyncInfo,
ps2DQueryBltsCompleteIN->type,
- ps2DQueryBltsCompleteIN->user_data))
+#if 0
+ ps2DQueryBltsCompleteIN->user_data
+#else
+ 0
+#endif
+ ))
psRetOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY;
return 0;
if (ps2DQueryBltsCompleteIN->type == _PVR_SYNC_WAIT_EVENT) {
if (pvr_sync_event_req(priv,
(struct PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo,
- ps2DQueryBltsCompleteIN->user_data))
+#if 0
+ ps2DQueryBltsCompleteIN->user_data
+#else
+ 0
+#endif
+ ))
psRetOUT->eError = PVRSRV_ERROR_OUT_OF_MEMORY;
else
trace_query_cmd(psPerProc,
PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+26)
#define PVRSRV_BRIDGE_RELEASE_MMAP_DATA \
PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+27)
+#if 0
#define PVRSRV_BRIDGE_CACHE_FLUSH_DRM \
PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+28)
#define PVRSRV_BRIDGE_CORE_CMD_LAST \
(PVRSRV_BRIDGE_CORE_CMD_FIRST+28)
-
+#else
+#define PVRSRV_BRIDGE_CORE_CMD_LAST \
+ (PVRSRV_BRIDGE_CORE_CMD_FIRST+27)
+#endif
#define PVRSRV_BRIDGE_SIM_CMD_FIRST \
(PVRSRV_BRIDGE_CORE_CMD_LAST+1)
#define PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT \
};
enum pvr_sync_wait_seq_type {
+ _PVR_SYNC_WAIT_NONBLOCK = 0,
_PVR_SYNC_WAIT_BLOCK,
- _PVR_SYNC_WAIT_NONBLOCK,
_PVR_SYNC_WAIT_EVENT,
_PVR_SYNC_WAIT_FLIP,
_PVR_SYNC_WAIT_UPDATE,
u32 ui32BridgeFlags;
void *hDevCookie;
void *hKernSyncInfo;
+#if 0
u64 user_data;
+#endif
enum pvr_sync_wait_seq_type type;
};
#define SGX_MAX_HEAP_ID 10
#define SGX_MAX_TA_STATUS_VALS 32
+#if 0
#define SGX_MAX_3D_STATUS_VALS 4
+#else
+#define SGX_MAX_3D_STATUS_VALS 2
+#endif
#define SGX_MAX_SRC_SYNCS 4
if ((psSGXFeatures->ui32DDKVersion !=
((PVRVERSION_MAJ << 16) | (PVRVERSION_MIN << 8) |
PVRVERSION_BRANCH)) ||
- (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD)) {
+ (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD &&
+ psSGXFeatures->ui32DDKBuild != 2616)) {
pr_err("pvr: incompatible driver DDK revision (%d)"
"/device DDK revision (%d).\n",
PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
opts = psSGXFeatures->ui32BuildOptions;
opt_mismatch = opts ^ SGX_BUILD_OPTIONS;
+#if 0
/* we support the ABIs both with and without EDM tracing option */
opt_mismatch &= ~PVRSRV_USSE_EDM_STATUS_DEBUG_SET_OFFSET;
+#endif
if (opt_mismatch) {
if (SGX_BUILD_OPTIONS & opt_mismatch)
pr_err("pvr: mismatch in driver and microkernel build "