bool
default y
select HAVE_AOUT
+ select HAVE_DMA_API_DEBUG
select HAVE_IDE
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
--- select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
+++ select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_KGDB
- select HAVE_KPROBES if (!XIP_KERNEL)
+ select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
+ select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
select HAVE_GENERIC_DMA_COHERENT
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
--- select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+++ select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
+ select HAVE_C_RECORDMCOUNT
+ select HAVE_GENERIC_HARDIRQS
+ select HAVE_SPARSE_IRQ
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
config HAVE_PWM
bool
+ config MIGHT_HAVE_PCI
+ bool
+
config SYS_SUPPORTS_APM_EMULATION
bool
+ config HAVE_SCHED_CLOCK
+ bool
+
config GENERIC_GPIO
bool
depends on GENERIC_CLOCKEVENTS
default y if SMP
+++config KTIME_SCALAR
+++ bool
+++ default y
+++
config HAVE_TCM
bool
select GENERIC_ALLOCATOR
<file:Documentation/mca.txt> (and especially the web page given
there) before attempting to build an MCA bus kernel.
- config GENERIC_HARDIRQS
- bool
- default y
-
config STACKTRACE_SUPPORT
bool
default y
config ARCH_MTD_XIP
bool
- config GENERIC_HARDIRQS_NO__DO_IRQ
- def_bool y
-
---config ARM_L1_CACHE_SHIFT_6
--- bool
--- help
--- Setting ARM L1 cache line size to 64 Bytes.
---
config VECTORS_BASE
hex
default 0xffff0000 if MMU || CPU_HIGH_VECTOR
help
The base address of exception vectors.
+++config ARM_PATCH_PHYS_VIRT
+++ bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
+++ depends on EXPERIMENTAL
+++ depends on !XIP_KERNEL && MMU
+++ depends on !ARCH_REALVIEW || !SPARSEMEM
+++ help
+++ Patch phys-to-virt translation functions at runtime according to
+++ the position of the kernel in system memory.
+++
+++ This can only be used with non-XIP with MMU kernels where
+++ the base of physical memory is at a 16MB boundary.
+++
+++config ARM_PATCH_PHYS_VIRT_16BIT
+++ def_bool y
+++ depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
+++
source "init/Kconfig"
source "kernel/Kconfig.freezer"
prompt "ARM system type"
default ARCH_VERSATILE
---config ARCH_AAEC2000
--- bool "Agilent AAEC-2000 based"
--- select CPU_ARM920T
--- select ARM_AMBA
--- select HAVE_CLK
--- select ARCH_USES_GETTIMEOFFSET
--- help
--- This enables support for systems based on the Agilent AAEC-2000
---
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select ARM_AMBA
select ARCH_HAS_CPUFREQ
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ICST
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
+++ select PLAT_VERSATILE_FPGA_IRQ
help
Support for ARM's Integrator platform.
config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARM_AMBA
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
-- select HAVE_SCHED_CLOCK
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select PLAT_VERSATILE
+++ select PLAT_VERSATILE_CLCD
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
help
bool "ARM Ltd. Versatile family"
select ARM_AMBA
select ARM_VIC
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
-- select HAVE_SCHED_CLOCK
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select PLAT_VERSATILE
+++ select PLAT_VERSATILE_CLCD
+++ select PLAT_VERSATILE_FPGA_IRQ
select ARM_TIMER_SP804
help
This enables support for ARM Ltd Versatile board.
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_TIMER_SP804
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_CLK
-- select HAVE_SCHED_CLOCK
+++ select HAVE_PATA_PLATFORM
select ICST
select PLAT_VERSATILE
+++ select PLAT_VERSATILE_CLCD
help
This enables support for the ARM Ltd Versatile Express boards.
depends on MMU
select CPU_V6
select ARM_AMBA
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
help
select CPU_V6
select GENERIC_CLOCKEVENTS
select ARM_GIC
+ select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
select CPU_ARM920T
select ARM_AMBA
select ARM_VIC
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_USES_GETTIMEOFFSET
bool "FootBridge"
select CPU_SA110
select FOOTBRIDGE
--- select ARCH_USES_GETTIMEOFFSET
+++ select GENERIC_CLOCKEVENTS
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
bool "Freescale MXC/iMX-based"
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
help
Support for Freescale MXC/iMX-based family of processors
+ config ARCH_MXS
+ bool "Freescale MXS-based"
+ select GENERIC_CLOCKEVENTS
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKDEV_LOOKUP
+ help
+ Support for Freescale MXS-based family of processors
+
config ARCH_STMP3XXX
bool "Freescale STMP3xxx"
select CPU_ARM926T
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select USB_ARCH_HAS_EHCI
select CPU_XSCALE
select GENERIC_GPIO
select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
+ select MIGHT_HAVE_PCI
select DMABOUNCE if PCI
help
Support for Intel's IXP4XX (XScale) family of processors.
config ARCH_DOVE
bool "Marvell Dove"
+++ select CPU_V6K
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select HAVE_IDE
select ARM_AMBA
select USB_ARCH_HAS_OHCI
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
bool "Marvell PXA168/910/MMP2"
depends on MMU
select ARCH_REQUIRE_GPIOLIB
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
bool "Nuvoton W90X900 CPU"
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
help
Support for Nuvoton (Winbond logic dept.) ARM9 processor,
config ARCH_NUC93X
bool "Nuvoton NUC93X CPU"
select CPU_ARM926T
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
help
Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
low-power and high performance MPEG-4/JPEG multimedia controller chip.
config ARCH_TEGRA
bool "NVIDIA Tegra"
+ select CLKDEV_LOOKUP
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select HAVE_CLK
- select COMMON_CLKDEV
+ select HAVE_SCHED_CLOCK
select ARCH_HAS_BARRIERS if CACHE_L2X0
select ARCH_HAS_CPUFREQ
help
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET
help
This enables support for Philips PNX4008 mobile platform.
depends on MMU
select ARCH_MTD_XIP
select ARCH_HAS_CPUFREQ
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
(clock and power control, etc).
config ARCH_SHMOBILE
- bool "Renesas SH-Mobile"
+ bool "Renesas SH-Mobile / R-Mobile"
+ select HAVE_CLK
+ select CLKDEV_LOOKUP
+ select GENERIC_CLOCKEVENTS
+ select NO_IOPORT
+ select SPARSE_IRQ
+ select MULTI_IRQ_HANDLER
help
- Support for Renesas's SH-Mobile ARM platforms
+ Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
config ARCH_RPC
bool "RiscPC"
select CPU_FREQ
select GENERIC_CLOCKEVENTS
select HAVE_CLK
+ select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
help
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
bool "Telechips TCC ARM926-based systems"
select CPU_ARM926T
select HAVE_CLK
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
help
Support for Telechips TCC ARM926-based systems.
---config ARCH_LH7A40X
--- bool "Sharp LH7A40X"
--- select CPU_ARM922T
--- select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
--- select ARCH_USES_GETTIMEOFFSET
--- help
--- Say Y here for systems based on one of the Sharp LH7A40X
--- System on a Chip processors. These CPUs include an ARM922T
--- core with a wide array of integrated devices for
--- hand-held and low-power applications.
---
config ARCH_U300
bool "ST-Ericsson U300 Series"
depends on MMU
select CPU_ARM926T
+ select HAVE_SCHED_CLOCK
select HAVE_TCM
select ARM_AMBA
select ARM_VIC
select GENERIC_CLOCKEVENTS
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_GPIO
help
Support for ST-Ericsson U300 series mobile platforms.
select CPU_V7
select ARM_AMBA
select GENERIC_CLOCKEVENTS
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
+ select ARCH_HAS_CPUFREQ
help
Support for ST-Ericsson's Ux500 architecture
select ARM_AMBA
select ARM_VIC
select CPU_ARM926T
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
help
select ARCH_REQUIRE_GPIOLIB
select ZONE_DMA
select HAVE_IDE
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_ALLOCATOR
select ARCH_HAS_HOLES_MEMORYMODEL
help
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
select ARCH_HAS_HOLES_MEMORYMODEL
help
Support for TI's OMAP platform (OMAP1/2/3/4).
bool "ST SPEAr"
select ARM_AMBA
select ARCH_REQUIRE_GPIOLIB
- select COMMON_CLKDEV
+ select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
+++config ARCH_VT8500
+++ bool "VIA/WonderMedia 85xx"
+++ select CPU_ARM926T
+++ select GENERIC_GPIO
+++ select ARCH_HAS_CPUFREQ
+++ select GENERIC_CLOCKEVENTS
+++ select ARCH_REQUIRE_GPIOLIB
+++ select HAVE_PWM
+++ help
+++ Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
endchoice
#
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
---source "arch/arm/mach-aaec2000/Kconfig"
---
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
---source "arch/arm/mach-lh7a40x/Kconfig"
---
source "arch/arm/mach-loki/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/plat-mxc/Kconfig"
+ source "arch/arm/mach-mxs/Kconfig"
+
source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
+++ source "arch/arm/plat-versatile/Kconfig"
++
+++source "arch/arm/mach-vt8500/Kconfig"
+
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
config PLAT_IOP
bool
select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
config PLAT_ORION
bool
+ select HAVE_SCHED_CLOCK
config PLAT_PXA
bool
config IWMMXT
bool "Enable iWMMXt support"
- depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
- default y if PXA27x || PXA3xx || ARCH_MMP
+ depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
+ default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
default y
config CPU_HAS_PMU
--- depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
+++ depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
(!ARCH_OMAP3 || OMAP3_EMU)
default y
bool
+ config MULTI_IRQ_HANDLER
+ bool
+ help
+ Allow each machine to specify it's own IRQ handler at run time.
+
if !MMU
source "arch/arm/Kconfig-nommu"
endif
config ARM_ERRATA_411920
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
--- depends on CPU_V6
+++ depends on CPU_V6 || CPU_V6K
help
Invalidation of the Instruction Cache operation can
fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
config PL310_ERRATA_588369
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
--- depends on CACHE_L2X0 && ARCH_OMAP4
+++ depends on CACHE_L2X0
help
The PL310 L2 cache controller implements three types of Clean &
Invalidate maintenance operations: by Physical Address
clean operation followed immediately by an invalidate operation,
both performing to the same memory location. This functionality
is not correctly implemented in PL310 as clean lines are not
--- invalidated as a result of these operations. Note that this errata
--- uses Texas Instrument's secure monitor api.
+++ invalidated as a result of these operations.
config ARM_ERRATA_720789
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
tables. The workaround changes the TLB flushing routines to invalidate
entries regardless of the ASID.
+++config PL310_ERRATA_727915
+++ bool "Background Clean & Invalidate by Way operation can cause data corruption"
+++ depends on CACHE_L2X0
+++ help
+++ PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+++ operation (offset 0x7FC). This operation runs in background so that
+++ PL310 can handle normal accesses while it is in progress. Under very
+++ rare circumstances, due to this erratum, write data can be lost when
+++ PL310 treats a cacheable write transaction during a Clean &
+++ Invalidate by Way operation.
+++
config ARM_ERRATA_743622
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
depends on CPU_V7
visible impact on the overall performance or power consumption of the
processor.
++config ARM_ERRATA_751472
++ bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
++ depends on CPU_V7 && SMP
++ help
++ This option enables the workaround for the 751472 Cortex-A9 (prior
++ to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
++ completion of a following broadcasted operation if the second
++ operation is received by a CPU before the ICIALLUIS has completed,
++ potentially leading to corrupted entries in the cache or TLB.
++
++config ARM_ERRATA_753970
++ bool "ARM errata: cache sync operation may be faulty"
++ depends on CACHE_PL310
++ help
++ This option enables the workaround for the 753970 PL310 (r3p0) erratum.
++
++ Under some condition the effect of cache sync operation on
++ the store buffer still remains when the operation completes.
++ This means that the store buffer is always asked to drain and
++ this prevents it from merging any further writes. The workaround
++ is to replace the normal offset of cache sync operation (0x730)
++ by another offset targeting an unmapped PL310 register 0x740.
++ This has the same effect as the cache sync operation: store buffer
++ drain and waiting for all buffers empty.
++
+++config ARM_ERRATA_754322
+++ bool "ARM errata: possible faulty MMU translations following an ASID switch"
+++ depends on CPU_V7
+++ help
+++ This option enables the workaround for the 754322 Cortex-A9 (r2p*,
+++ r3p*) erratum. A speculative memory access may cause a page table walk
+++ which starts prior to an ASID switch but completes afterwards. This
+++ can populate the micro-TLB with a stale entry which may be hit with
+++ the new ASID. This workaround places two dsb instructions in the mm
+++ switching code so that no page table walks can cross the ASID switch.
+++
+++config ARM_ERRATA_754327
+++ bool "ARM errata: no automatic Store Buffer drain"
+++ depends on CPU_V7 && SMP
+++ help
+++ This option enables the workaround for the 754327 Cortex-A9 (prior to
+++ r2p0) erratum. The Store Buffer does not have any automatic draining
+++ mechanism and therefore a livelock may occur if an external agent
+++ continuously polls a memory location waiting to observe an update.
+++ This workaround defines cpu_relax() as smp_mb(), preventing correctly
+++ written polling loops from denying visibility of updates to memory.
+++
endmenu
source "arch/arm/common/Kconfig"
bool
config PCI
- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+ bool "PCI support" if MIGHT_HAVE_PCI
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
bool
depends on PCI
+ config PCI_NANOENGINE
+ bool "BSE nanoEngine PCI support"
+ depends on SA1100_NANOENGINE
+ help
+ Enable PCI on the BSE nanoEngine board.
+
config PCI_SYSCALL
def_bool PCI
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
depends on EXPERIMENTAL
+++ depends on CPU_V6K || CPU_V7
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
- MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
- ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+ ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
- select HAVE_ARM_SCU
+ select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
config SMP_ON_UP
bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
depends on EXPERIMENTAL
- depends on SMP && !XIP && !THUMB2_KERNEL
+ depends on SMP && !XIP_KERNEL
default y
help
SMP kernels contain instructions which fail on non-SMP processors.
config HAVE_ARM_TWD
bool
depends on SMP
+ select TICK_ONESHOT
help
This options enables support for the ARM timer and watchdog unit
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
depends on SMP && HOTPLUG && EXPERIMENTAL
+ depends on !ARCH_MSM
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
bool "Use local timer interrupts"
depends on SMP
default y
- select HAVE_ARM_TWD
+ select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
default 100
config THUMB2_KERNEL
- bool "Compile the kernel in Thumb-2 mode"
- depends on CPU_V7 && EXPERIMENTAL
+ bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
- - depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
+++ depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
help
If unsure, say N.
+++config THUMB2_AVOID_R_ARM_THM_JUMP11
+++ bool "Work around buggy Thumb-2 short branch relocations in gas"
+++ depends on THUMB2_KERNEL && MODULES
+++ default y
+++ help
+++ Various binutils versions can resolve Thumb-2 branches to
+++ locally-defined, preemptible global symbols as short-range "b.n"
+++ branch instructions.
+++
+++ This is a problem, because there's no guarantee the final
+++ destination of the symbol, or any candidate locations for a
+++ trampoline, are within range of the branch. For this reason, the
+++ kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
+++ relocation in modules at all, and it makes little sense to add
+++ support.
+++
+++ The symptom is that the kernel fails with an "unsupported
+++ relocation" error when loading some modules.
+++
+++ Until fixed tools are available, passing
+++ -fno-optimize-sibling-calls to gcc should prevent gcc generating
+++ code which hits this problem, at the cost of a bit of extra runtime
+++ stack usage in some cases.
+++
+++ The problem is described in more detail at:
+++ https://bugs.launchpad.net/binutils-linaro/+bug/725126
+++
+++ Only Thumb-2 kernels are affected.
+++
+++ Unless you are sure your tools don't have this problem, say Y.
+++
config ARM_ASM_UNIFIED
bool
config OABI_COMPAT
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
-- depends on AEABI && EXPERIMENTAL
++ depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
default y
help
This option preserves the old syscall interface along with the
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
- config SPARSE_IRQ
- def_bool n
- help
- This enables support for sparse irqs. This is useful in general
- as most CPUs have a fairly sparse array of IRQ vectors, which
- the irq_desc then maps directly on to. Systems with a high
- number of off-chip IRQs will want to treat this as
- experimental until they have been independently verified.
-
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
config CC_STACKPROTECTOR
bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
help
This option turns on the -fstack-protector GCC feature. This
feature puts, at the beginning of functions, a canary value on
Say Y here if you intend to execute your compressed kernel image
(zImage) directly from ROM or flash. If unsure, say N.
+++config ZBOOT_ROM_MMCIF
+++ bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
+++ depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
+++ help
+++ Say Y here to include experimental MMCIF loading code in the
+++ ROM-able zImage. With this enabled it is possible to write the
+++ the ROM-able zImage kernel image to an MMC card and boot the
+++ kernel straight from the reset vector. At reset the processor
+++ Mask ROM will load the first part of the the ROM-able zImage
+++ which in turn loads the rest the kernel image to RAM using the
+++ MMCIF hardware block.
+++
config CMDLINE
string "Default kernel command string"
default ""
Should the atags used to boot the kernel be exported in an "atags"
file in procfs. Useful with kexec.
+ config CRASH_DUMP
+ bool "Build kdump crash kernel (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ help
+ Generate crash dump after being started by kexec. This should
+ be normally only set in special crash dump kernels which are
+ loaded in the main kernel with kexec-tools into a specially
+ reserved region and then later executed after a crash by
+ kdump/kexec. The crash dump kernel must be compiled to a
+ memory address not used by the main kernel
+
+ For more details see Documentation/kdump/kdump.txt
+
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address"
depends on !ZBOOT_ROM && !ARCH_U300
Internal configuration node for common cpufreq on Samsung SoC
config CPU_FREQ_S3C24XX
- bool "CPUfreq driver for Samsung S3C24XX series CPUs"
+ bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
select CPU_FREQ_S3C
help
If in doubt, say N.
config CPU_FREQ_S3C24XX_PLL
- bool "Support CPUfreq changing of PLL frequency"
+ bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
help
Compile in support for changing the PLL frequency from the
config FPE_NWFPE
bool "NWFPE math emulation"
- depends on !AEABI || OABI_COMPAT
+ depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
---help---
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently
config VFP
bool "VFP-format floating point maths"
--- depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
+++ depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
help
Say Y to include VFP support code in the kernel. This is needed
if your hardware includes a VFP unit.
#ifndef __ASM_OUTERCACHE_H
#define __ASM_OUTERCACHE_H
++ +#include <linux/types.h>
++ +
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
#ifdef CONFIG_OUTER_CACHE_SYNC
void (*sync)(void);
#endif
+++ void (*set_debug)(unsigned long);
};
#ifdef CONFIG_OUTER_CACHE
extern struct outer_cache_fns outer_cache;
-- -static inline void outer_inv_range(unsigned long start, unsigned long end)
++ +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
{
if (outer_cache.inv_range)
outer_cache.inv_range(start, end);
}
-- -static inline void outer_clean_range(unsigned long start, unsigned long end)
++ +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
{
if (outer_cache.clean_range)
outer_cache.clean_range(start, end);
}
-- -static inline void outer_flush_range(unsigned long start, unsigned long end)
++ +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
{
if (outer_cache.flush_range)
outer_cache.flush_range(start, end);
#else
-- -static inline void outer_inv_range(unsigned long start, unsigned long end)
++ +static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
{ }
-- -static inline void outer_clean_range(unsigned long start, unsigned long end)
++ +static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
{ }
-- -static inline void outer_flush_range(unsigned long start, unsigned long end)
++ +static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
{ }
static inline void outer_flush_all(void) { }
static inline void outer_inv_all(void) { }
/*
* Memory map description
*/
---#ifdef CONFIG_ARCH_LH7A40X
---# define NR_BANKS 16
---#else
---# define NR_BANKS 8
---#endif
+++#define NR_BANKS 8
struct membank {
-- - unsigned long start;
++ + phys_addr_t start;
unsigned long size;
unsigned int highmem;
};
unsigned int processor_id;
EXPORT_SYMBOL(processor_id);
- unsigned int __machine_arch_type;
+ unsigned int __machine_arch_type __read_mostly;
EXPORT_SYMBOL(__machine_arch_type);
- unsigned int cacheid;
+ unsigned int cacheid __read_mostly;
EXPORT_SYMBOL(cacheid);
unsigned int __atags_pointer __initdata;
unsigned int system_serial_high;
EXPORT_SYMBOL(system_serial_high);
- unsigned int elf_hwcap;
+ unsigned int elf_hwcap __read_mostly;
EXPORT_SYMBOL(elf_hwcap);
#ifdef MULTI_CPU
- struct processor processor;
+ struct processor processor __read_mostly;
#endif
#ifdef MULTI_TLB
- struct cpu_tlb_fns cpu_tlb;
+ struct cpu_tlb_fns cpu_tlb __read_mostly;
#endif
#ifdef MULTI_USER
- struct cpu_user_fns cpu_user;
+ struct cpu_user_fns cpu_user __read_mostly;
#endif
#ifdef MULTI_CACHE
- struct cpu_cache_fns cpu_cache;
+ struct cpu_cache_fns cpu_cache __read_mostly;
#endif
#ifdef CONFIG_OUTER_CACHE
- struct outer_cache_fns outer_cache;
+ struct outer_cache_fns outer_cache __read_mostly;
EXPORT_SYMBOL(outer_cache);
#endif
static const char *cpu_name;
static const char *machine_name;
static char __initdata cmd_line[COMMAND_LINE_SIZE];
+ struct machine_desc *machine_desc __initdata;
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
* Register 0 and check for VMSAv7 or PMSAv7 */
asm("mrc p15, 0, %0, c0, c1, 4"
: "=r" (mmfr0));
-- if ((mmfr0 & 0x0000000f) == 0x00000003 ||
-- (mmfr0 & 0x000000f0) == 0x00000030)
++ if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
++ (mmfr0 & 0x000000f0) >= 0x00000030)
cpu_arch = CPU_ARCH_ARMv7;
else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
(mmfr0 & 0x000000f0) == 0x00000020)
* already provide the required functionality.
*/
extern struct proc_info_list *lookup_processor_type(unsigned int);
---extern struct machine_desc *lookup_machine_type(unsigned int);
+++
+++static void __init early_print(const char *str, ...)
+++{
+++ extern void printascii(const char *);
+++ char buf[256];
+++ va_list ap;
+++
+++ va_start(ap, str);
+++ vsnprintf(buf, sizeof(buf), str, ap);
+++ va_end(ap);
+++
+++#ifdef CONFIG_DEBUG_LL
+++ printascii(buf);
+++#endif
+++ printk("%s", buf);
+++}
static void __init feat_v6_fixup(void)
{
static struct machine_desc * __init setup_machine(unsigned int nr)
{
--- struct machine_desc *list;
+++ extern struct machine_desc __arch_info_begin[], __arch_info_end[];
+++ struct machine_desc *p;
/*
* locate machine in the list of supported machines.
*/
--- list = lookup_machine_type(nr);
--- if (!list) {
--- printk("Machine configuration botched (nr %d), unable "
--- "to continue.\n", nr);
--- while (1);
--- }
+++ for (p = __arch_info_begin; p < __arch_info_end; p++)
+++ if (nr == p->nr) {
+++ printk("Machine: %s\n", p->name);
+++ return p;
+++ }
+++
+++ early_print("\n"
+++ "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n"
+++ "Available machine support:\n\nID (hex)\tNAME\n", nr);
+
- - printk("Machine: %s\n", list->name);
+++ for (p = __arch_info_begin; p < __arch_info_end; p++)
+++ early_print("%08x\t%s\n", p->nr, p->name);
- - return list;
- printk("Machine: %s\n", list->name);
+++ early_print("\nPlease check your kernel config and/or bootloader.\n");
+ +
- return list;
+++ while (true)
+++ /* can't use cpu_relax() here as it may require MMU setup */;
}
-- -static int __init arm_add_memory(unsigned long start, unsigned long size)
++ +static int __init arm_add_memory(phys_addr_t start, unsigned long size)
{
struct membank *bank = &meminfo.bank[meminfo.nr_banks];
if (meminfo.nr_banks >= NR_BANKS) {
printk(KERN_CRIT "NR_BANKS too low, "
-- - "ignoring memory at %#lx\n", start);
++ + "ignoring memory at 0x%08llx\n", (long long)start);
return -EINVAL;
}
static int __init early_mem(char *p)
{
static int usermem __initdata = 0;
-- - unsigned long size, start;
++ + unsigned long size;
++ + phys_addr_t start;
char *endp;
/*
#endif
}
- static void __init
- request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc)
+ static void __init request_standard_resources(struct machine_desc *mdesc)
{
+ struct memblock_region *region;
struct resource *res;
- int i;
kernel_code.start = virt_to_phys(_text);
kernel_code.end = virt_to_phys(_etext - 1);
kernel_data.start = virt_to_phys(_sdata);
kernel_data.end = virt_to_phys(_end - 1);
- for (i = 0; i < mi->nr_banks; i++) {
- if (mi->bank[i].size == 0)
- continue;
-
+ for_each_memblock(memory, region) {
res = alloc_bootmem_low(sizeof(*res));
res->name = "System RAM";
- res->start = mi->bank[i].start;
- res->end = mi->bank[i].start + mi->bank[i].size - 1;
+ res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
+ res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
request_resource(&iomem_resource, res);
__tagtable(ATAG_REVISION, parse_tag_revision);
- #ifndef CONFIG_CMDLINE_FORCE
static int __init parse_tag_cmdline(const struct tag *tag)
{
+ #ifndef CONFIG_CMDLINE_FORCE
strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE);
+ #else
+ pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+ #endif /* CONFIG_CMDLINE_FORCE */
return 0;
}
__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
- #endif /* CONFIG_CMDLINE_FORCE */
/*
* Scan the tag table for this tag, and call its parse function.
{ tag_size(tag_core), ATAG_CORE },
{ 1, PAGE_SIZE, 0xff },
{ tag_size(tag_mem32), ATAG_MEM },
--- { MEM_SIZE, PHYS_OFFSET },
+++ { MEM_SIZE },
{ 0, ATAG_NONE }
};
- static void (*init_machine)(void) __initdata;
-
static int __init customize_machine(void)
{
/* customizes platform devices, or adds new ones */
- if (init_machine)
- init_machine();
+ if (machine_desc->init_machine)
+ machine_desc->init_machine();
return 0;
}
arch_initcall(customize_machine);
struct machine_desc *mdesc;
char *from = default_command_line;
+++ init_tags.mem.start = PHYS_OFFSET;
+++
unwind_init();
setup_processor();
mdesc = setup_machine(machine_arch_type);
+ machine_desc = mdesc;
machine_name = mdesc->name;
if (mdesc->soft_reboot)
if (__atags_pointer)
tags = phys_to_virt(__atags_pointer);
--- else if (mdesc->boot_params)
--- tags = phys_to_virt(mdesc->boot_params);
+++ else if (mdesc->boot_params) {
+++#ifdef CONFIG_MMU
+++ /*
+++ * We still are executing with a minimal MMU mapping created
+++ * with the presumption that the machine default for this
+++ * is located in the first MB of RAM. Anything else will
+++ * fault and silently hang the kernel at this point.
+++ */
+++ if (mdesc->boot_params < PHYS_OFFSET ||
+++ mdesc->boot_params >= PHYS_OFFSET + SZ_1M) {
+++ printk(KERN_WARNING
+++ "Default boot params at physical 0x%08lx out of reach\n",
+++ mdesc->boot_params);
+++ } else
+++#endif
+++ {
+++ tags = phys_to_virt(mdesc->boot_params);
+++ }
+++ }
#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
/*
arm_memblock_init(&meminfo, mdesc);
paging_init(mdesc);
- request_standard_resources(&meminfo, mdesc);
+ request_standard_resources(mdesc);
#ifdef CONFIG_SMP
if (is_smp())
cpu_init();
tcm_init();
- /*
- * Set up various architecture-specific pointers
- */
- arch_nr_irqs = mdesc->nr_irqs;
- init_arch_irq = mdesc->init_irq;
- system_timer = mdesc->timer;
- init_machine = mdesc->init_machine;
+ #ifdef CONFIG_MULTI_IRQ_HANDLER
+ handle_arch_irq = mdesc->handle_irq;
+ #endif
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
#endif
#endif
early_trap_init();
+
+ if (mdesc->init_early)
+ mdesc->init_early();
}
#include <linux/kexec.h>
#include <linux/delay.h>
#include <linux/init.h>
+++#include <linux/sched.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/unwind.h>
#include <asm/tls.h>
---#include "ptrace.h"
#include "signal.h"
static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
+ void *vectors_page;
+
#ifdef CONFIG_DEBUG_USER
unsigned int user_debug;
return ret;
}
---DEFINE_SPINLOCK(die_lock);
+++static DEFINE_SPINLOCK(die_lock);
/*
* This function is protected against re-entrancy.
void __pte_error(const char *file, int line, pte_t pte)
{
-- - printk("%s:%d: bad pte %08lx.\n", file, line, pte_val(pte));
++ + printk("%s:%d: bad pte %08llx.\n", file, line, (long long)pte_val(pte));
}
void __pmd_error(const char *file, int line, pmd_t pmd)
{
-- - printk("%s:%d: bad pmd %08lx.\n", file, line, pmd_val(pmd));
++ + printk("%s:%d: bad pmd %08llx.\n", file, line, (long long)pmd_val(pmd));
}
void __pgd_error(const char *file, int line, pgd_t pgd)
{
-- - printk("%s:%d: bad pgd %08lx.\n", file, line, pgd_val(pgd));
++ + printk("%s:%d: bad pgd %08llx.\n", file, line, (long long)pgd_val(pgd));
}
asmlinkage void __div0(void)
void __init early_trap_init(void)
{
+ #if defined(CONFIG_CPU_USE_DOMAINS)
unsigned long vectors = CONFIG_VECTORS_BASE;
+ #else
+ unsigned long vectors = (unsigned long)vectors_page;
+ #endif
extern char __stubs_start[], __stubs_end[];
extern char __vectors_start[], __vectors_end[];
extern char __kuser_helper_start[], __kuser_helper_end[];
* Copy signal return handlers into the vector page, and
* set sigreturn to be a pointer to these.
*/
- memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
- sizeof(sigreturn_codes));
- memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
- sizeof(syscall_restart_code));
+ memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+ sigreturn_codes, sizeof(sigreturn_codes));
+ memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
+ syscall_restart_code, sizeof(syscall_restart_code));
flush_icache_range(vectors, vectors + PAGE_SIZE);
modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
select SERIAL_OMAP_CONSOLE
select I2C
select I2C_OMAP
- select MFD
+ select MFD_SUPPORT
select MENELAUS if ARCH_OMAP2
select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
select CPU_V7
select USB_ARCH_HAS_EHCI
select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
+ select ARCH_HAS_OPP
+ select PM_OPP if PM
config ARCH_OMAP4
bool "TI OMAP4"
depends on ARCH_OMAP2PLUS
select CPU_V7
select ARM_GIC
+++ select LOCAL_TIMERS if SMP
select PL310_ERRATA_588369
+++ select PL310_ERRATA_727915
select ARM_ERRATA_720789
+ select ARCH_HAS_OPP
+ select PM_OPP if PM
+ select USB_ARCH_HAS_EHCI
comment "OMAP Core Type"
depends on ARCH_OMAP2
config OMAP_PACKAGE_CBP
bool
+ config OMAP_PACKAGE_CBL
+ bool
+
+ config OMAP_PACKAGE_CBS
+ bool
+
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_OMAP_LDP
bool "OMAP3 LDP board"
default y
select OMAP_PACKAGE_CBB
+ config MACH_CRANEBOARD
+ bool "AM3517/05 CRANE board"
+ depends on ARCH_OMAP3
+ select OMAP_PACKAGE_CBB
+
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
+ select REGULATOR_FIXED_VOLTAGE
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
select MACH_NOKIA_N810
select MACH_NOKIA_N810_WIMAX
+ config MACH_NOKIA_RM680
+ bool "Nokia RM-680 board"
+ depends on ARCH_OMAP3
+ default y
+ select OMAP_PACKAGE_CBB
+
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
depends on ARCH_OMAP3
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
+ select REGULATOR_FIXED_VOLTAGE
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
+ select REGULATOR_FIXED_VOLTAGE
config MACH_CM_T35
bool "CompuLab CM-T35 module"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_CM_T3517
bool "CompuLab CM-T3517 module"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
- select OMAP_MUX
config MACH_IGEP0020
bool "IGEP v2 board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CUS
- select OMAP_MUX
config MACH_OMAP_3630SDP
bool "OMAP3630 SDP board"
bool "OMAP 4430 SDP board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
default y
depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
* These devices are connected via the core APB bridge
*/
#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
--- #define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
--- #define GPIO3_DMA { 0, 0 }
#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
--- #define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
--- #define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
--- #define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
--- #define KMI1_DMA { 0, 0 }
/*
* These devices are connected directly to the multi-layer AHB switch
*/
#define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
--- #define EB_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
--- #define MPMC_DMA { 0, 0 }
#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
--- #define EB_CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
--- #define DMAC_DMA { 0, 0 }
/*
* These devices are connected via the core APB bridge
*/
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
--- #define SCTL_DMA { 0, 0 }
#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
--- #define EB_WATCHDOG_DMA { 0, 0 }
#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
--- #define EB_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
--- #define GPIO1_DMA { 0, 0 }
#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
--- #define EB_RTC_DMA { 0, 0 }
/*
* These devices are connected via the DMA APB bridge
*/
#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
--- #define SCI_DMA { 7, 6 }
#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
--- #define EB_UART0_DMA { 15, 14 }
#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
--- #define EB_UART1_DMA { 13, 12 }
#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
--- #define EB_UART2_DMA { 11, 10 }
#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
--- #define EB_UART3_DMA { 0x86, 0x87 }
#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
--- #define EB_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* core tile GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
- gic_cpu_init(0, gic_cpu_base_addr);
+ gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
+ __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
/* board GIC, secondary */
- gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
- gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
+ gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+ __io_address(REALVIEW_EB_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
#endif
} else {
/* board GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
- gic_cpu_init(0, gic_cpu_base_addr);
+ gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+ __io_address(REALVIEW_EB_GIC_CPU_BASE));
}
}
MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_eb_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_eb_timer,
.init_machine = realview_eb_init,
* RealView PB1176 AMBA devices
*/
#define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ }
--- #define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ }
--- #define GPIO3_DMA { 0, 0 }
#define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ }
--- #define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
--- #define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ }
--- #define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ }
--- #define KMI1_DMA { 0, 0 }
#define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ }
--- #define PB1176_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
--- #define MPMC_DMA { 0, 0 }
#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
--- #define PB1176_CLCD_DMA { 0, 0 }
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
--- #define SCTL_DMA { 0, 0 }
#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ }
--- #define PB1176_WATCHDOG_DMA { 0, 0 }
#define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ }
--- #define PB1176_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ }
--- #define GPIO1_DMA { 0, 0 }
#define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ }
--- #define PB1176_RTC_DMA { 0, 0 }
#define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ }
--- #define SCI_DMA { 7, 6 }
#define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ }
--- #define PB1176_UART0_DMA { 15, 14 }
#define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ }
--- #define PB1176_UART1_DMA { 13, 12 }
#define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ }
--- #define PB1176_UART2_DMA { 11, 10 }
#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ }
--- #define PB1176_UART3_DMA { 0x86, 0x87 }
#define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ }
--- #define PB1176_UART4_DMA { 0, 0 }
#define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ }
--- #define PB1176_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
static void __init gic_init_irq(void)
{
/* ARM1176 DevChip GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
- gic_cpu_init(0, gic_cpu_base_addr);
+ gic_init(0, IRQ_DC1176_GIC_START,
+ __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
+ __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
/* board GIC, secondary */
- gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
- gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+ gic_init(1, IRQ_PB1176_GIC_START,
+ __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
+ __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
}
MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_pb1176_fixup,
.map_io = realview_pb1176_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pb1176_timer,
.init_machine = realview_pb1176_init,
*/
#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ }
--- #define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ }
--- #define GPIO3_DMA { 0, 0 }
#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ }
--- #define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
--- #define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ }
--- #define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ }
--- #define KMI1_DMA { 0, 0 }
#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ }
--- #define PB11MP_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
--- #define MPMC_DMA { 0, 0 }
#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ }
--- #define PB11MP_CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ }
--- #define DMAC_DMA { 0, 0 }
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
--- #define SCTL_DMA { 0, 0 }
#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ }
--- #define PB11MP_WATCHDOG_DMA { 0, 0 }
#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ }
--- #define PB11MP_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ }
--- #define GPIO1_DMA { 0, 0 }
#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ }
--- #define PB11MP_RTC_DMA { 0, 0 }
#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ }
--- #define SCI_DMA { 7, 6 }
#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ }
--- #define PB11MP_UART0_DMA { 15, 14 }
#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ }
--- #define PB11MP_UART1_DMA { 13, 12 }
#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ }
--- #define PB11MP_UART2_DMA { 11, 10 }
#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ }
--- #define PB11MP_UART3_DMA { 0x86, 0x87 }
#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ }
--- #define PB11MP_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* ARM11MPCore test chip GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
- gic_cpu_init(0, gic_cpu_base_addr);
+ gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
+ __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/* board GIC, secondary */
- gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
- gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+ gic_init(1, IRQ_PB11MP_GIC_START,
+ __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
+ __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
}
MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_pb11mp_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pb11mp_timer,
.init_machine = realview_pb11mp_init,
*/
#define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ }
--- #define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ }
--- #define GPIO3_DMA { 0, 0 }
#define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ }
--- #define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
--- #define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ }
--- #define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ }
--- #define KMI1_DMA { 0, 0 }
#define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ }
--- #define PBA8_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
--- #define MPMC_DMA { 0, 0 }
#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ }
--- #define PBA8_CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ }
--- #define DMAC_DMA { 0, 0 }
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
--- #define SCTL_DMA { 0, 0 }
#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ }
--- #define PBA8_WATCHDOG_DMA { 0, 0 }
#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ }
--- #define PBA8_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ }
--- #define GPIO1_DMA { 0, 0 }
#define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ }
--- #define PBA8_RTC_DMA { 0, 0 }
#define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ }
--- #define SCI_DMA { 7, 6 }
#define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ }
--- #define PBA8_UART0_DMA { 15, 14 }
#define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ }
--- #define PBA8_UART1_DMA { 13, 12 }
#define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ }
--- #define PBA8_UART2_DMA { 11, 10 }
#define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ }
--- #define PBA8_UART3_DMA { 0x86, 0x87 }
#define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ }
--- #define PBA8_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
static void __init gic_init_irq(void)
{
/* ARM PB-A8 on-board GIC */
- gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START);
- gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
+ gic_init(0, IRQ_PBA8_GIC_START,
+ __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
+ __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
}
static void __init realview_pba8_timer_init(void)
MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_fixup,
.map_io = realview_pba8_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pba8_timer,
.init_machine = realview_pba8_init,
*/
#define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ }
--- #define GPIO2_DMA { 0, 0 }
#define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ }
--- #define GPIO3_DMA { 0, 0 }
#define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ }
--- #define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
--- #define MMCI0_DMA { 0x84, 0 }
#define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ }
--- #define KMI0_DMA { 0, 0 }
#define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ }
--- #define KMI1_DMA { 0, 0 }
#define PBX_SMC_IRQ { NO_IRQ, NO_IRQ }
--- #define PBX_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
--- #define MPMC_DMA { 0, 0 }
#define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ }
--- #define PBX_CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ }
--- #define DMAC_DMA { 0, 0 }
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
--- #define SCTL_DMA { 0, 0 }
#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ }
--- #define PBX_WATCHDOG_DMA { 0, 0 }
#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ }
--- #define PBX_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ }
--- #define GPIO1_DMA { 0, 0 }
#define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ }
--- #define PBX_RTC_DMA { 0, 0 }
#define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ }
--- #define SCI_DMA { 7, 6 }
#define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ }
--- #define PBX_UART0_DMA { 15, 14 }
#define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ }
--- #define PBX_UART1_DMA { 13, 12 }
#define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ }
--- #define PBX_UART2_DMA { 11, 10 }
#define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ }
--- #define PBX_UART3_DMA { 0x86, 0x87 }
#define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ }
--- #define PBX_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
{
/* ARM PBX on-board GIC */
if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
- gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
- 29);
- gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
+ gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+ __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
} else {
- gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
- IRQ_PBX_GIC_START);
- gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
+ gic_init(0, IRQ_PBX_GIC_START,
+ __io_address(REALVIEW_PBX_GIC_DIST_BASE),
+ __io_address(REALVIEW_PBX_GIC_CPU_BASE));
}
}
MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.fixup = realview_pbx_fixup,
.map_io = realview_pbx_map_io,
+++ .init_early = realview_init_early,
.init_irq = gic_init_irq,
.timer = &realview_pbx_timer,
.init_machine = realview_pbx_init,
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
+ #include <linux/clkdev.h>
- #include <asm/clkdev.h>
#include <asm/pgtable.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/pmu.h>
#include <asm/smp_twd.h>
- #include <mach/clkdev.h>
#include <mach/ct-ca9x4.h>
- #include <plat/timer-sp.h>
+ #include <asm/hardware/timer-sp.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/motherboard.h>
+++ #include <plat/clcd.h>
+++
#define V2M_PA_CS7 0x10000000
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
- void __iomem *gic_cpu_base_addr;
-
static void __init ct_ca9x4_init_irq(void)
{
- gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
- gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
- gic_cpu_init(0, gic_cpu_base_addr);
+ gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
+ MMIO_P2V(A9_MPCORE_GIC_CPU));
}
#if 0
};
#endif
--- static struct clcd_panel xvga_panel = {
--- .mode = {
--- .name = "XVGA",
--- .refresh = 60,
--- .xres = 1024,
--- .yres = 768,
--- .pixclock = 15384,
--- .left_margin = 168,
--- .right_margin = 8,
--- .upper_margin = 29,
--- .lower_margin = 3,
--- .hsync_len = 144,
--- .vsync_len = 6,
--- .sync = 0,
--- .vmode = FB_VMODE_NONINTERLACED,
--- },
--- .width = -1,
--- .height = -1,
--- .tim2 = TIM2_BCD | TIM2_IPC,
--- .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
--- .bpp = 16,
--- };
---
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
unsigned long framesize = 1024 * 768 * 2;
--- dma_addr_t dma;
--
-- fb->panel = &xvga_panel;
-- fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
-- &dma, GFP_KERNEL);
-- if (!fb->fb.screen_base) {
-- printk(KERN_ERR "CLCD: unable to map frame buffer\n");
-- return -ENOMEM;
-- }
-- fb->fb.fix.smem_start = dma;
-- fb->fb.fix.smem_len = framesize;
--
-- return 0;
-- }
--
-- static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-- {
-- return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
-- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-- }
- fb->panel = &xvga_panel;
+++ fb->panel = versatile_clcd_get_panel("XVGA");
+++ if (!fb->panel)
+++ return -EINVAL;
- fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
- &dma, GFP_KERNEL);
- if (!fb->fb.screen_base) {
- printk(KERN_ERR "CLCD: unable to map frame buffer\n");
- return -ENOMEM;
- }
- fb->fb.fix.smem_start = dma;
- fb->fb.fix.smem_len = framesize;
-
- return 0;
- }
-
- static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
- {
- return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
- }
-
--- static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
--- {
--- dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
--- fb->fb.screen_base, fb->fb.fix.smem_start);
+++ return versatile_clcd_setup_dma(fb, framesize);
}
static struct clcd_board ct_ca9x4_clcd_data = {
.name = "CT-CA9X4",
+++ .caps = CLCD_CAP_5551 | CLCD_CAP_565,
.check = clcdfb_check,
.decode = clcdfb_decode,
.enable = ct_ca9x4_clcd_enable,
.setup = ct_ca9x4_clcd_setup,
--- .mmap = ct_ca9x4_clcd_mmap,
--- .remove = ct_ca9x4_clcd_remove,
+++ .mmap = versatile_clcd_mmap_dma,
+++ .remove = versatile_clcd_remove_dma,
};
static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
.resource = pmu_resources,
};
+++ static void __init ct_ca9x4_init_early(void)
+++ {
+++ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+++
+++ v2m_init_early();
+++ }
+++
static void __init ct_ca9x4_init(void)
{
int i;
l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif
--- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
---
for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
}
MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
--- .boot_params = PHYS_OFFSET + 0x00000100,
+++ .boot_params = PLAT_PHYS_OFFSET + 0x00000100,
.map_io = ct_ca9x4_map_io,
.init_irq = ct_ca9x4_init_irq,
+++ .init_early = ct_ca9x4_init_early,
#if 0
.timer = &ct_ca9x4_timer,
#else
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
+ #include <linux/highmem.h>
#include <asm/memory.h>
#include <asm/highmem.h>
{
int ret = 0;
pgd_t *pgd;
++ + pud_t *pud;
pmd_t *pmd;
pte_t *pte;
int i = 0;
do {
pgd = pgd_offset(&init_mm, base);
-- - pmd = pmd_alloc(&init_mm, pgd, base);
++ +
++ + pud = pud_alloc(&init_mm, pgd, base);
++ + if (!pud) {
++ + printk(KERN_ERR "%s: no pud tables\n", __func__);
++ + ret = -ENOMEM;
++ + break;
++ + }
++ +
++ + pmd = pmd_alloc(&init_mm, pud, base);
if (!pmd) {
printk(KERN_ERR "%s: no pmd tables\n", __func__);
ret = -ENOMEM;
addr = page_address(page);
if (addr)
- *handle = page_to_dma(dev, page);
+ *handle = pfn_to_dma(dev, page_to_pfn(page));
return addr;
}
if (!arch_is_coherent())
__dma_free_remap(cpu_addr, size);
- __dma_free_buffer(dma_to_page(dev, handle), size);
+ __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size);
}
EXPORT_SYMBOL(dma_free_coherent);
op(vaddr, len, dir);
kunmap_high(page);
} else if (cache_is_vipt()) {
- pte_t saved_pte;
- vaddr = kmap_high_l1_vipt(page, &saved_pte);
+ /* unmapped pages might still be cached */
+ vaddr = kmap_atomic(page);
op(vaddr + offset, len, dir);
- kunmap_high_l1_vipt(page, saved_pte);
+ kunmap_atomic(vaddr);
}
} else {
vaddr = page_address(page) + offset;
struct scatterlist *s;
int i, j;
+ BUG_ON(!valid_dma_direction(dir));
+
for_each_sg(sg, s, nents, i) {
- s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
+ s->dma_address = __dma_map_page(dev, sg_page(s), s->offset,
s->length, dir);
if (dma_mapping_error(dev, s->dma_address))
goto bad_mapping;
}
+ debug_dma_map_sg(dev, sg, nents, nents, dir);
return nents;
bad_mapping:
for_each_sg(sg, s, i, j)
- dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+ __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
return 0;
}
EXPORT_SYMBOL(dma_map_sg);
* dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
* @sg: list of buffers
- * @nents: number of buffers to unmap (returned from dma_map_sg)
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
*
* Unmap a set of streaming mode DMA translations. Again, CPU access
struct scatterlist *s;
int i;
+ debug_dma_unmap_sg(dev, sg, nents, dir);
+
for_each_sg(sg, s, nents, i)
- dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+ __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
}
EXPORT_SYMBOL(dma_unmap_sg);
__dma_page_dev_to_cpu(sg_page(s), s->offset,
s->length, dir);
}
+
+ debug_dma_sync_sg_for_cpu(dev, sg, nents, dir);
}
EXPORT_SYMBOL(dma_sync_sg_for_cpu);
__dma_page_cpu_to_dev(sg_page(s), s->offset,
s->length, dir);
}
+
+ debug_dma_sync_sg_for_device(dev, sg, nents, dir);
}
EXPORT_SYMBOL(dma_sync_sg_for_device);
+
+ #define PREALLOC_DMA_DEBUG_ENTRIES 4096
+
+ static int __init dma_debug_do_init(void)
+ {
+ dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+ return 0;
+ }
+ fs_initcall(dma_debug_do_init);
memblock_reserve(__pa(_stext), _end - _stext);
#endif
#ifdef CONFIG_BLK_DEV_INITRD
++ if (phys_initrd_size &&
++ memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
++ pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
++ phys_initrd_start, phys_initrd_size);
++ phys_initrd_start = phys_initrd_size = 0;
++ }
if (phys_initrd_size) {
memblock_reserve(phys_initrd_start, phys_initrd_size);
*/
arm_bootmem_free(min, max_low, max_high);
-- - high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
++ + high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1;
/*
* This doesn't seem to be used by the Linux memory manager any
* Convert to physical addresses, and
* round start upwards and end downwards.
*/
-- - pg = PAGE_ALIGN(__pa(start_pg));
-- - pgend = __pa(end_pg) & PAGE_MASK;
++ + pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
++ + pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
/*
* If there are free pages between these,
#include <asm/smp_plat.h>
#include <asm/tlb.h>
#include <asm/highmem.h>
+ #include <asm/traps.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
{
if (pmd_none(*pmd)) {
-- - pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
++ + pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
__pmd_populate(pmd, __pa(pte), prot);
}
BUG_ON(pmd_bad(*pmd));
} while (pte++, addr += PAGE_SIZE, addr != end);
}
-- -static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
++ +static void __init alloc_init_section(pud_t *pud, unsigned long addr,
unsigned long end, phys_addr_t phys,
const struct mem_type *type)
{
-- - pmd_t *pmd = pmd_offset(pgd, addr);
++ + pmd_t *pmd = pmd_offset(pud, addr);
/*
* Try a section mapping - end, addr and phys must all be aligned
}
}
++ +static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
++ + unsigned long phys, const struct mem_type *type)
++ +{
++ + pud_t *pud = pud_offset(pgd, addr);
++ + unsigned long next;
++ +
++ + do {
++ + next = pud_addr_end(addr, end);
++ + alloc_init_section(pud, addr, next, phys, type);
++ + phys += next - addr;
++ + } while (pud++, addr = next, addr != end);
++ +}
++ +
static void __init create_36bit_mapping(struct map_desc *md,
const struct mem_type *type)
{
pgd_t *pgd;
addr = md->virtual;
-- - phys = (unsigned long)__pfn_to_phys(md->pfn);
++ + phys = __pfn_to_phys(md->pfn);
length = PAGE_ALIGN(md->length);
if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
printk(KERN_ERR "MM: CPU does not support supersection "
"mapping for 0x%08llx at 0x%08lx\n",
-- - __pfn_to_phys((u64)md->pfn), addr);
++ + (long long)__pfn_to_phys((u64)md->pfn), addr);
return;
}
if (type->domain) {
printk(KERN_ERR "MM: invalid domain in supersection "
"mapping for 0x%08llx at 0x%08lx\n",
-- - __pfn_to_phys((u64)md->pfn), addr);
++ + (long long)__pfn_to_phys((u64)md->pfn), addr);
return;
}
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
-- - printk(KERN_ERR "MM: cannot create mapping for "
-- - "0x%08llx at 0x%08lx invalid alignment\n",
-- - __pfn_to_phys((u64)md->pfn), addr);
++ + printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
++ + " at 0x%08lx invalid alignment\n",
++ + (long long)__pfn_to_phys((u64)md->pfn), addr);
return;
}
pgd = pgd_offset_k(addr);
end = addr + length;
do {
-- - pmd_t *pmd = pmd_offset(pgd, addr);
++ + pud_t *pud = pud_offset(pgd, addr);
++ + pmd_t *pmd = pmd_offset(pud, addr);
int i;
for (i = 0; i < 16; i++)
*/
static void __init create_mapping(struct map_desc *md)
{
-- - unsigned long phys, addr, length, end;
++ + unsigned long addr, length, end;
++ + phys_addr_t phys;
const struct mem_type *type;
pgd_t *pgd;
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
-- - printk(KERN_WARNING "BUG: not creating mapping for "
-- - "0x%08llx at 0x%08lx in user region\n",
-- - __pfn_to_phys((u64)md->pfn), md->virtual);
++ + printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
++ + " at 0x%08lx in user region\n",
++ + (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
return;
}
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
-- - printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
-- - "overlaps vmalloc space\n",
-- - __pfn_to_phys((u64)md->pfn), md->virtual);
++ + printk(KERN_WARNING "BUG: mapping for 0x%08llx"
++ + " at 0x%08lx overlaps vmalloc space\n",
++ + (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
}
type = &mem_types[md->type];
}
addr = md->virtual & PAGE_MASK;
-- - phys = (unsigned long)__pfn_to_phys(md->pfn);
++ + phys = __pfn_to_phys(md->pfn);
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
-- - printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
++ + printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
"be mapped using pages, ignoring.\n",
-- - __pfn_to_phys(md->pfn), addr);
++ + (long long)__pfn_to_phys(md->pfn), addr);
return;
}
do {
unsigned long next = pgd_addr_end(addr, end);
-- - alloc_init_section(pgd, addr, next, phys, type);
++ + alloc_init_pud(pgd, addr, next, phys, type);
phys += next - addr;
addr = next;
*/
if (__va(bank->start) >= vmalloc_min ||
__va(bank->start) < (void *)PAGE_OFFSET) {
-- - printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
++ + printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
"(vmalloc region overlap).\n",
-- - bank->start, bank->start + bank->size - 1);
++ + (unsigned long long)bank->start,
++ + (unsigned long long)bank->start + bank->size - 1);
continue;
}
if (__va(bank->start + bank->size) > vmalloc_min ||
__va(bank->start + bank->size) < __va(bank->start)) {
unsigned long newsize = vmalloc_min - __va(bank->start);
-- - printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
-- - "to -%.8lx (vmalloc region overlap).\n",
-- - bank->start, bank->start + bank->size - 1,
-- - bank->start + newsize - 1);
++ + printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
++ + "to -%.8llx (vmalloc region overlap).\n",
++ + (unsigned long long)bank->start,
++ + (unsigned long long)bank->start + bank->size - 1,
++ + (unsigned long long)bank->start + newsize - 1);
bank->size = newsize;
}
#endif
* rather difficult.
*/
reason = "with VIPT aliasing cache";
--- } else if (is_smp() && tlb_ops_need_broadcast()) {
--- /*
--- * kmap_high needs to occasionally flush TLB entries,
--- * however, if the TLB entries need to be broadcast
--- * we may deadlock:
--- * kmap_high(irqs off)->flush_all_zero_pkmaps->
--- * flush_tlb_kernel_range->smp_call_function_many
--- * (must not be called with irqs off)
--- */
--- reason = "without hardware TLB ops broadcasting";
}
if (reason) {
printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
{
struct map_desc map;
unsigned long addr;
- void *vectors;
/*
* Allocate the vector page early.
*/
- vectors = early_alloc(PAGE_SIZE);
+ vectors_page = early_alloc(PAGE_SIZE);
for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
pmd_clear(pmd_off_k(addr));
* location (0xffff0000). If we aren't using high-vectors, also
* create a mapping at the low-vectors virtual address.
*/
- map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+ map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
map.virtual = 0xffff0000;
map.length = PAGE_SIZE;
map.type = MT_HIGH_VECTORS;
pgd_t *pgd_alloc(struct mm_struct *mm)
{
pgd_t *new_pgd, *init_pgd;
++ + pud_t *new_pud, *init_pud;
pmd_t *new_pmd, *init_pmd;
pte_t *new_pte, *init_pte;
* On ARM, first page must always be allocated since it
* contains the machine vectors.
*/
-- - new_pmd = pmd_alloc(mm, new_pgd, 0);
++ + new_pud = pud_alloc(mm, new_pgd, 0);
++ + if (!new_pud)
++ + goto no_pud;
++ +
++ + new_pmd = pmd_alloc(mm, new_pud, 0);
if (!new_pmd)
goto no_pmd;
- new_pte = pte_alloc_map(mm, new_pmd, 0);
+ new_pte = pte_alloc_map(mm, NULL, new_pmd, 0);
if (!new_pte)
goto no_pte;
-- - init_pmd = pmd_offset(init_pgd, 0);
++ + init_pud = pud_offset(init_pgd, 0);
++ + init_pmd = pmd_offset(init_pud, 0);
init_pte = pte_offset_map(init_pmd, 0);
set_pte_ext(new_pte, *init_pte, 0);
pte_unmap(init_pte);
no_pte:
pmd_free(mm, new_pmd);
no_pmd:
++ + pud_free(mm, new_pud);
++ +no_pud:
free_pages((unsigned long)new_pgd, 2);
no_pgd:
return NULL;
void pgd_free(struct mm_struct *mm, pgd_t *pgd_base)
{
pgd_t *pgd;
++ + pud_t *pud;
pmd_t *pmd;
pgtable_t pte;
if (pgd_none_or_clear_bad(pgd))
goto no_pgd;
-- - pmd = pmd_offset(pgd, 0);
++ + pud = pud_offset(pgd, 0);
++ + if (pud_none_or_clear_bad(pud))
++ + goto no_pud;
++ +
++ + pmd = pmd_offset(pud, 0);
if (pmd_none_or_clear_bad(pmd))
goto no_pmd;
pmd_clear(pmd);
pte_free(mm, pte);
no_pmd:
-- - pgd_clear(pgd);
++ + pud_clear(pud);
pmd_free(mm, pmd);
++ +no_pud:
++ + pgd_clear(pgd);
++ + pud_free(mm, pud);
no_pgd:
free_pages((unsigned long) pgd_base, 2);
}
static int
clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
+++ u32 caps;
int ret = 0;
+++ if (fb->panel->caps && fb->board->caps)
+++ caps = fb->panel->caps & fb->board->caps;
+++ else {
+++ /* Old way of specifying what can be used */
+++ caps = fb->panel->cntl & CNTL_BGR ?
+++ CLCD_CAP_BGR : CLCD_CAP_RGB;
+++ /* But mask out 444 modes as they weren't supported */
+++ caps &= ~CLCD_CAP_444;
+++ }
+++
+++ /* Only TFT panels can do RGB888/BGR888 */
+++ if (!(fb->panel->cntl & CNTL_LCDTFT))
+++ caps &= ~CLCD_CAP_888;
+++
memset(&var->transp, 0, sizeof(var->transp));
var->red.msb_right = 0;
case 2:
case 4:
case 8:
+++ /* If we can't do 5551, reject */
+++ caps &= CLCD_CAP_5551;
+++ if (!caps) {
+++ ret = -EINVAL;
+++ break;
+++ }
+++
var->red.length = var->bits_per_pixel;
var->red.offset = 0;
var->green.length = var->bits_per_pixel;
var->blue.length = var->bits_per_pixel;
var->blue.offset = 0;
break;
+++
case 16:
--- var->red.length = 5;
--- var->blue.length = 5;
+++ /* If we can't do 444, 5551 or 565, reject */
+++ if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
+++ ret = -EINVAL;
+++ break;
+++ }
+++
/*
--- * Green length can be 5 or 6 depending whether
--- * we're operating in RGB555 or RGB565 mode.
+++ * Green length can be 4, 5 or 6 depending whether
+++ * we're operating in 444, 5551 or 565 mode.
*/
--- if (var->green.length != 5 && var->green.length != 6)
--- var->green.length = 6;
+++ if (var->green.length == 4 && caps & CLCD_CAP_444)
+++ caps &= CLCD_CAP_444;
+++ if (var->green.length == 5 && caps & CLCD_CAP_5551)
+++ caps &= CLCD_CAP_5551;
+++ else if (var->green.length == 6 && caps & CLCD_CAP_565)
+++ caps &= CLCD_CAP_565;
+++ else {
+++ /*
+++ * PL110 officially only supports RGB555,
+++ * but may be wired up to allow RGB565.
+++ */
+++ if (caps & CLCD_CAP_565) {
+++ var->green.length = 6;
+++ caps &= CLCD_CAP_565;
+++ } else if (caps & CLCD_CAP_5551) {
+++ var->green.length = 5;
+++ caps &= CLCD_CAP_5551;
+++ } else {
+++ var->green.length = 4;
+++ caps &= CLCD_CAP_444;
+++ }
+++ }
+++
+++ if (var->green.length >= 5) {
+++ var->red.length = 5;
+++ var->blue.length = 5;
+++ } else {
+++ var->red.length = 4;
+++ var->blue.length = 4;
+++ }
break;
case 32:
--- if (fb->panel->cntl & CNTL_LCDTFT) {
--- var->red.length = 8;
--- var->green.length = 8;
--- var->blue.length = 8;
+++ /* If we can't do 888, reject */
+++ caps &= CLCD_CAP_888;
+++ if (!caps) {
+++ ret = -EINVAL;
break;
}
+++
+++ var->red.length = 8;
+++ var->green.length = 8;
+++ var->blue.length = 8;
+++ break;
default:
ret = -EINVAL;
break;
* the bitfield length defined above.
*/
if (ret == 0 && var->bits_per_pixel >= 16) {
--- if (fb->panel->cntl & CNTL_BGR) {
+++ bool bgr, rgb;
+++
+++ bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
+++ rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
+++
+++ if (!bgr && !rgb)
+++ /*
+++ * The requested format was not possible, try just
+++ * our capabilities. One of BGR or RGB must be
+++ * supported.
+++ */
+++ bgr = caps & CLCD_CAP_BGR;
+++
+++ if (bgr) {
var->blue.offset = 0;
var->green.offset = var->blue.offset + var->blue.length;
var->red.offset = var->green.offset + var->green.length;
fb_set_var(&fb->fb, &fb->fb.var);
--- printk(KERN_INFO "CLCD: %s hardware, %s display\n",
--- fb->board->name, fb->panel->mode.name);
+++ dev_info(&fb->dev->dev, "%s hardware, %s display\n",
+++ fb->board->name, fb->panel->mode.name);
ret = register_framebuffer(&fb->fb);
if (ret == 0)
return ret;
}
---static int clcdfb_probe(struct amba_device *dev, struct amba_id *id)
+++static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
{
struct clcd_board *board = dev->dev.platform_data;
struct clcd_fb *fb;
fb->dev = dev;
fb->board = board;
+++ dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
+++ amba_part(dev), amba_rev(dev),
+++ (unsigned long long)dev->res.start);
+++
ret = fb->board->setup(fb);
if (ret)
goto free_fb;
git.openpandora.org / pandora-kernel.git / commitdiff