sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <sound/core.h>
  49 #include <sound/initval.h>
  50 #include "hda_codec.h"
  51
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  56 static char *model[SNDRV_CARDS];
  57 static int position_fix[SNDRV_CARDS];
  58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int single_cmd;
  61 static int enable_msi;
  62
  63 module_param_array(index, int, NULL, 0444);
  64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  65 module_param_array(id, charp, NULL, 0444);
  66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  67 module_param_array(enable, bool, NULL, 0444);
  68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  69 module_param_array(model, charp, NULL, 0444);
  70 MODULE_PARM_DESC(model, "Use the given board model.");
  71 module_param_array(position_fix, int, NULL, 0444);
  72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  73                  "(0 = auto, 1 = none, 2 = POSBUF).");
  74 module_param_array(bdl_pos_adj, int, NULL, 0644);
  75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  76 module_param_array(probe_mask, int, NULL, 0444);
  77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  78 module_param(single_cmd, bool, 0444);
  79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  80                  "(for debugging only).");
  81 module_param(enable_msi, int, 0444);
  82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  83
  84 #ifdef CONFIG_SND_HDA_POWER_SAVE
  85 /* power_save option is defined in hda_codec.c */
  86
  87 /* reset the HD-audio controller in power save mode.
  88  * this may give more power-saving, but will take longer time to
  89  * wake up.
  90  */
  91 static int power_save_controller = 1;
  92 module_param(power_save_controller, bool, 0644);
  93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  94 #endif
  95
  96 MODULE_LICENSE("GPL");
  97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  98                          "{Intel, ICH6M},"
  99                          "{Intel, ICH7},"
 100                          "{Intel, ESB2},"
 101                          "{Intel, ICH8},"
 102                          "{Intel, ICH9},"
 103                          "{Intel, ICH10},"
 104                          "{Intel, PCH},"
 105                          "{Intel, SCH},"
 106                          "{ATI, SB450},"
 107                          "{ATI, SB600},"
 108                          "{ATI, RS600},"
 109                          "{ATI, RS690},"
 110                          "{ATI, RS780},"
 111                          "{ATI, R600},"
 112                          "{ATI, RV630},"
 113                          "{ATI, RV610},"
 114                          "{ATI, RV670},"
 115                          "{ATI, RV635},"
 116                          "{ATI, RV620},"
 117                          "{ATI, RV770},"
 118                          "{VIA, VT8251},"
 119                          "{VIA, VT8237A},"
 120                          "{SiS, SIS966},"
 121                          "{ULI, M5461}}");
 122 MODULE_DESCRIPTION("Intel HDA driver");
 123
 124 #define SFX     "hda-intel: "
 125
 126
 127 /*
 128  * registers
 129  */
 130 #define ICH6_REG_GCAP                   0x00
 131 #define ICH6_REG_VMIN                   0x02
 132 #define ICH6_REG_VMAJ                   0x03
 133 #define ICH6_REG_OUTPAY                 0x04
 134 #define ICH6_REG_INPAY                  0x06
 135 #define ICH6_REG_GCTL                   0x08
 136 #define ICH6_REG_WAKEEN                 0x0c
 137 #define ICH6_REG_STATESTS               0x0e
 138 #define ICH6_REG_GSTS                   0x10
 139 #define ICH6_REG_INTCTL                 0x20
 140 #define ICH6_REG_INTSTS                 0x24
 141 #define ICH6_REG_WALCLK                 0x30
 142 #define ICH6_REG_SYNC                   0x34
 143 #define ICH6_REG_CORBLBASE              0x40
 144 #define ICH6_REG_CORBUBASE              0x44
 145 #define ICH6_REG_CORBWP                 0x48
 146 #define ICH6_REG_CORBRP                 0x4A
 147 #define ICH6_REG_CORBCTL                0x4c
 148 #define ICH6_REG_CORBSTS                0x4d
 149 #define ICH6_REG_CORBSIZE               0x4e
 150
 151 #define ICH6_REG_RIRBLBASE              0x50
 152 #define ICH6_REG_RIRBUBASE              0x54
 153 #define ICH6_REG_RIRBWP                 0x58
 154 #define ICH6_REG_RINTCNT                0x5a
 155 #define ICH6_REG_RIRBCTL                0x5c
 156 #define ICH6_REG_RIRBSTS                0x5d
 157 #define ICH6_REG_RIRBSIZE               0x5e
 158
 159 #define ICH6_REG_IC                     0x60
 160 #define ICH6_REG_IR                     0x64
 161 #define ICH6_REG_IRS                    0x68
 162 #define   ICH6_IRS_VALID        (1<<1)
 163 #define   ICH6_IRS_BUSY         (1<<0)
 164
 165 #define ICH6_REG_DPLBASE                0x70
 166 #define ICH6_REG_DPUBASE                0x74
 167 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 168
 169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 171
 172 /* stream register offsets from stream base */
 173 #define ICH6_REG_SD_CTL                 0x00
 174 #define ICH6_REG_SD_STS                 0x03
 175 #define ICH6_REG_SD_LPIB                0x04
 176 #define ICH6_REG_SD_CBL                 0x08
 177 #define ICH6_REG_SD_LVI                 0x0c
 178 #define ICH6_REG_SD_FIFOW               0x0e
 179 #define ICH6_REG_SD_FIFOSIZE            0x10
 180 #define ICH6_REG_SD_FORMAT              0x12
 181 #define ICH6_REG_SD_BDLPL               0x18
 182 #define ICH6_REG_SD_BDLPU               0x1c
 183
 184 /* PCI space */
 185 #define ICH6_PCIREG_TCSEL       0x44
 186
 187 /*
 188  * other constants
 189  */
 190
 191 /* max number of SDs */
 192 /* ICH, ATI and VIA have 4 playback and 4 capture */
 193 #define ICH6_NUM_CAPTURE        4
 194 #define ICH6_NUM_PLAYBACK       4
 195
 196 /* ULI has 6 playback and 5 capture */
 197 #define ULI_NUM_CAPTURE         5
 198 #define ULI_NUM_PLAYBACK        6
 199
 200 /* ATI HDMI has 1 playback and 0 capture */
 201 #define ATIHDMI_NUM_CAPTURE     0
 202 #define ATIHDMI_NUM_PLAYBACK    1
 203
 204 /* TERA has 4 playback and 3 capture */
 205 #define TERA_NUM_CAPTURE        3
 206 #define TERA_NUM_PLAYBACK       4
 207
 208 /* this number is statically defined for simplicity */
 209 #define MAX_AZX_DEV             16
 210
 211 /* max number of fragments - we may use more if allocating more pages for BDL */
 212 #define BDL_SIZE                4096
 213 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 214 #define AZX_MAX_FRAG            32
 215 /* max buffer size - no h/w limit, you can increase as you like */
 216 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 217 /* max number of PCM devics per card */
 218 #define AZX_MAX_PCMS            8
 219
 220 /* RIRB int mask: overrun[2], response[0] */
 221 #define RIRB_INT_RESPONSE       0x01
 222 #define RIRB_INT_OVERRUN        0x04
 223 #define RIRB_INT_MASK           0x05
 224
 225 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 226 #define AZX_MAX_CODECS          4
 227 #define STATESTS_INT_MASK       0x0f
 228
 229 /* SD_CTL bits */
 230 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 231 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 232 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 233 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 234 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 235 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 236 #define SD_CTL_STREAM_TAG_SHIFT 20
 237
 238 /* SD_CTL and SD_STS */
 239 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 240 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 241 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 242 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 243                                  SD_INT_COMPLETE)
 244
 245 /* SD_STS */
 246 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 247
 248 /* INTCTL and INTSTS */
 249 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 250 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 251 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 252
 253 /* GCTL unsolicited response enable bit */
 254 #define ICH6_GCTL_UREN          (1<<8)
 255
 256 /* GCTL reset bit */
 257 #define ICH6_GCTL_RESET         (1<<0)
 258
 259 /* CORB/RIRB control, read/write pointer */
 260 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 261 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 262 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 263 /* below are so far hardcoded - should read registers in future */
 264 #define ICH6_MAX_CORB_ENTRIES   256
 265 #define ICH6_MAX_RIRB_ENTRIES   256
 266
 267 /* position fix mode */
 268 enum {
 269         POS_FIX_AUTO,
 270         POS_FIX_LPIB,
 271         POS_FIX_POSBUF,
 272 };
 273
 274 /* Defines for ATI HD Audio support in SB450 south bridge */
 275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 277
 278 /* Defines for Nvidia HDA support */
 279 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 280 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 281 #define NVIDIA_HDA_ISTRM_COH          0x4d
 282 #define NVIDIA_HDA_OSTRM_COH          0x4c
 283 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 284
 285 /* Defines for Intel SCH HDA snoop control */
 286 #define INTEL_SCH_HDA_DEVC      0x78
 287 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 288
 289 /* Define IN stream 0 FIFO size offset in VIA controller */
 290 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 291 /* Define VIA HD Audio Device ID*/
 292 #define VIA_HDAC_DEVICE_ID              0x3288
 293
 294
 295 /*
 296  */
 297
 298 struct azx_dev {
 299         struct snd_dma_buffer bdl; /* BDL buffer */
 300         u32 *posbuf;            /* position buffer pointer */
 301
 302         unsigned int bufsize;   /* size of the play buffer in bytes */
 303         unsigned int period_bytes; /* size of the period in bytes */
 304         unsigned int frags;     /* number for period in the play buffer */
 305         unsigned int fifo_size; /* FIFO size */
 306
 307         void __iomem *sd_addr;  /* stream descriptor pointer */
 308
 309         u32 sd_int_sta_mask;    /* stream int status mask */
 310
 311         /* pcm support */
 312         struct snd_pcm_substream *substream;    /* assigned substream,
 313                                                  * set in PCM open
 314                                                  */
 315         unsigned int format_val;        /* format value to be set in the
 316                                          * controller and the codec
 317                                          */
 318         unsigned char stream_tag;       /* assigned stream */
 319         unsigned char index;            /* stream index */
 320
 321         unsigned int opened :1;
 322         unsigned int running :1;
 323         unsigned int irq_pending :1;
 324         unsigned int irq_ignore :1;
 325         /*
 326          * For VIA:
 327          *  A flag to ensure DMA position is 0
 328          *  when link position is not greater than FIFO size
 329          */
 330         unsigned int insufficient :1;
 331 };
 332
 333 /* CORB/RIRB */
 334 struct azx_rb {
 335         u32 *buf;               /* CORB/RIRB buffer
 336                                  * Each CORB entry is 4byte, RIRB is 8byte
 337                                  */
 338         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 339         /* for RIRB */
 340         unsigned short rp, wp;  /* read/write pointers */
 341         int cmds;               /* number of pending requests */
 342         u32 res;                /* last read value */
 343 };
 344
 345 struct azx {
 346         struct snd_card *card;
 347         struct pci_dev *pci;
 348         int dev_index;
 349
 350         /* chip type specific */
 351         int driver_type;
 352         int playback_streams;
 353         int playback_index_offset;
 354         int capture_streams;
 355         int capture_index_offset;
 356         int num_streams;
 357
 358         /* pci resources */
 359         unsigned long addr;
 360         void __iomem *remap_addr;
 361         int irq;
 362
 363         /* locks */
 364         spinlock_t reg_lock;
 365         struct mutex open_mutex;
 366
 367         /* streams (x num_streams) */
 368         struct azx_dev *azx_dev;
 369
 370         /* PCM */
 371         struct snd_pcm *pcm[AZX_MAX_PCMS];
 372
 373         /* HD codec */
 374         unsigned short codec_mask;
 375         struct hda_bus *bus;
 376
 377         /* CORB/RIRB */
 378         struct azx_rb corb;
 379         struct azx_rb rirb;
 380
 381         /* CORB/RIRB and position buffers */
 382         struct snd_dma_buffer rb;
 383         struct snd_dma_buffer posbuf;
 384
 385         /* flags */
 386         int position_fix;
 387         unsigned int running :1;
 388         unsigned int initialized :1;
 389         unsigned int single_cmd :1;
 390         unsigned int polling_mode :1;
 391         unsigned int msi :1;
 392         unsigned int irq_pending_warned :1;
 393         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 394
 395         /* for debugging */
 396         unsigned int last_cmd;  /* last issued command (to sync) */
 397
 398         /* for pending irqs */
 399         struct work_struct irq_pending_work;
 400 };
 401
 402 /* driver types */
 403 enum {
 404         AZX_DRIVER_ICH,
 405         AZX_DRIVER_SCH,
 406         AZX_DRIVER_ATI,
 407         AZX_DRIVER_ATIHDMI,
 408         AZX_DRIVER_VIA,
 409         AZX_DRIVER_SIS,
 410         AZX_DRIVER_ULI,
 411         AZX_DRIVER_NVIDIA,
 412         AZX_DRIVER_TERA,
 413         AZX_NUM_DRIVERS, /* keep this as last entry */
 414 };
 415
 416 static char *driver_short_names[] __devinitdata = {
 417         [AZX_DRIVER_ICH] = "HDA Intel",
 418         [AZX_DRIVER_SCH] = "HDA Intel MID",
 419         [AZX_DRIVER_ATI] = "HDA ATI SB",
 420         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 421         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 422         [AZX_DRIVER_SIS] = "HDA SIS966",
 423         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 424         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 425         [AZX_DRIVER_TERA] = "HDA Teradici",
 426 };
 427
 428 /*
 429  * macros for easy use
 430  */
 431 #define azx_writel(chip,reg,value) \
 432         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 433 #define azx_readl(chip,reg) \
 434         readl((chip)->remap_addr + ICH6_REG_##reg)
 435 #define azx_writew(chip,reg,value) \
 436         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 437 #define azx_readw(chip,reg) \
 438         readw((chip)->remap_addr + ICH6_REG_##reg)
 439 #define azx_writeb(chip,reg,value) \
 440         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 441 #define azx_readb(chip,reg) \
 442         readb((chip)->remap_addr + ICH6_REG_##reg)
 443
 444 #define azx_sd_writel(dev,reg,value) \
 445         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 446 #define azx_sd_readl(dev,reg) \
 447         readl((dev)->sd_addr + ICH6_REG_##reg)
 448 #define azx_sd_writew(dev,reg,value) \
 449         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 450 #define azx_sd_readw(dev,reg) \
 451         readw((dev)->sd_addr + ICH6_REG_##reg)
 452 #define azx_sd_writeb(dev,reg,value) \
 453         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 454 #define azx_sd_readb(dev,reg) \
 455         readb((dev)->sd_addr + ICH6_REG_##reg)
 456
 457 /* for pcm support */
 458 #define get_azx_dev(substream) (substream->runtime->private_data)
 459
 460 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 461
 462 /*
 463  * Interface for HD codec
 464  */
 465
 466 /*
 467  * CORB / RIRB interface
 468  */
 469 static int azx_alloc_cmd_io(struct azx *chip)
 470 {
 471         int err;
 472
 473         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 474         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 475                                   snd_dma_pci_data(chip->pci),
 476                                   PAGE_SIZE, &chip->rb);
 477         if (err < 0) {
 478                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 479                 return err;
 480         }
 481         return 0;
 482 }
 483
 484 static void azx_init_cmd_io(struct azx *chip)
 485 {
 486         /* CORB set up */
 487         chip->corb.addr = chip->rb.addr;
 488         chip->corb.buf = (u32 *)chip->rb.area;
 489         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 490         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 491
 492         /* set the corb size to 256 entries (ULI requires explicitly) */
 493         azx_writeb(chip, CORBSIZE, 0x02);
 494         /* set the corb write pointer to 0 */
 495         azx_writew(chip, CORBWP, 0);
 496         /* reset the corb hw read pointer */
 497         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 498         /* enable corb dma */
 499         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 500
 501         /* RIRB set up */
 502         chip->rirb.addr = chip->rb.addr + 2048;
 503         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 504         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 505         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 506
 507         /* set the rirb size to 256 entries (ULI requires explicitly) */
 508         azx_writeb(chip, RIRBSIZE, 0x02);
 509         /* reset the rirb hw write pointer */
 510         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 511         /* set N=1, get RIRB response interrupt for new entry */
 512         azx_writew(chip, RINTCNT, 1);
 513         /* enable rirb dma and response irq */
 514         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 515         chip->rirb.rp = chip->rirb.cmds = 0;
 516 }
 517
 518 static void azx_free_cmd_io(struct azx *chip)
 519 {
 520         /* disable ringbuffer DMAs */
 521         azx_writeb(chip, RIRBCTL, 0);
 522         azx_writeb(chip, CORBCTL, 0);
 523 }
 524
 525 /* send a command */
 526 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 527 {
 528         struct azx *chip = codec->bus->private_data;
 529         unsigned int wp;
 530
 531         /* add command to corb */
 532         wp = azx_readb(chip, CORBWP);
 533         wp++;
 534         wp %= ICH6_MAX_CORB_ENTRIES;
 535
 536         spin_lock_irq(&chip->reg_lock);
 537         chip->rirb.cmds++;
 538         chip->corb.buf[wp] = cpu_to_le32(val);
 539         azx_writel(chip, CORBWP, wp);
 540         spin_unlock_irq(&chip->reg_lock);
 541
 542         return 0;
 543 }
 544
 545 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 546
 547 /* retrieve RIRB entry - called from interrupt handler */
 548 static void azx_update_rirb(struct azx *chip)
 549 {
 550         unsigned int rp, wp;
 551         u32 res, res_ex;
 552
 553         wp = azx_readb(chip, RIRBWP);
 554         if (wp == chip->rirb.wp)
 555                 return;
 556         chip->rirb.wp = wp;
 557
 558         while (chip->rirb.rp != wp) {
 559                 chip->rirb.rp++;
 560                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 561
 562                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 563                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 564                 res = le32_to_cpu(chip->rirb.buf[rp]);
 565                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 566                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 567                 else if (chip->rirb.cmds) {
 568                         chip->rirb.res = res;
 569                         smp_wmb();
 570                         chip->rirb.cmds--;
 571                 }
 572         }
 573 }
 574
 575 /* receive a response */
 576 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 577 {
 578         struct azx *chip = codec->bus->private_data;
 579         unsigned long timeout;
 580
 581  again:
 582         timeout = jiffies + msecs_to_jiffies(1000);
 583         for (;;) {
 584                 if (chip->polling_mode) {
 585                         spin_lock_irq(&chip->reg_lock);
 586                         azx_update_rirb(chip);
 587                         spin_unlock_irq(&chip->reg_lock);
 588                 }
 589                 if (!chip->rirb.cmds) {
 590                         smp_rmb();
 591                         return chip->rirb.res; /* the last value */
 592                 }
 593                 if (time_after(jiffies, timeout))
 594                         break;
 595                 if (codec->bus->needs_damn_long_delay)
 596                         msleep(2); /* temporary workaround */
 597                 else {
 598                         udelay(10);
 599                         cond_resched();
 600                 }
 601         }
 602
 603         if (chip->msi) {
 604                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 605                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 606                 free_irq(chip->irq, chip);
 607                 chip->irq = -1;
 608                 pci_disable_msi(chip->pci);
 609                 chip->msi = 0;
 610                 if (azx_acquire_irq(chip, 1) < 0)
 611                         return -1;
 612                 goto again;
 613         }
 614
 615         if (!chip->polling_mode) {
 616                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 617                            "switching to polling mode: last cmd=0x%08x\n",
 618                            chip->last_cmd);
 619                 chip->polling_mode = 1;
 620                 goto again;
 621         }
 622
 623         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 624                    "switching to single_cmd mode: last cmd=0x%08x\n",
 625                    chip->last_cmd);
 626         chip->rirb.rp = azx_readb(chip, RIRBWP);
 627         chip->rirb.cmds = 0;
 628         /* switch to single_cmd mode */
 629         chip->single_cmd = 1;
 630         azx_free_cmd_io(chip);
 631         return -1;
 632 }
 633
 634 /*
 635  * Use the single immediate command instead of CORB/RIRB for simplicity
 636  *
 637  * Note: according to Intel, this is not preferred use.  The command was
 638  *       intended for the BIOS only, and may get confused with unsolicited
 639  *       responses.  So, we shouldn't use it for normal operation from the
 640  *       driver.
 641  *       I left the codes, however, for debugging/testing purposes.
 642  */
 643
 644 /* send a command */
 645 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 646 {
 647         struct azx *chip = codec->bus->private_data;
 648         int timeout = 50;
 649
 650         while (timeout--) {
 651                 /* check ICB busy bit */
 652                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 653                         /* Clear IRV valid bit */
 654                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 655                                    ICH6_IRS_VALID);
 656                         azx_writel(chip, IC, val);
 657                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 658                                    ICH6_IRS_BUSY);
 659                         return 0;
 660                 }
 661                 udelay(1);
 662         }
 663         if (printk_ratelimit())
 664                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 665                            azx_readw(chip, IRS), val);
 666         return -EIO;
 667 }
 668
 669 /* receive a response */
 670 static unsigned int azx_single_get_response(struct hda_codec *codec)
 671 {
 672         struct azx *chip = codec->bus->private_data;
 673         int timeout = 50;
 674
 675         while (timeout--) {
 676                 /* check IRV busy bit */
 677                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 678                         return azx_readl(chip, IR);
 679                 udelay(1);
 680         }
 681         if (printk_ratelimit())
 682                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 683                            azx_readw(chip, IRS));
 684         return (unsigned int)-1;
 685 }
 686
 687 /*
 688  * The below are the main callbacks from hda_codec.
 689  *
 690  * They are just the skeleton to call sub-callbacks according to the
 691  * current setting of chip->single_cmd.
 692  */
 693
 694 /* send a command */
 695 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 696                         int direct, unsigned int verb,
 697                         unsigned int para)
 698 {
 699         struct azx *chip = codec->bus->private_data;
 700         u32 val;
 701
 702         val = (u32)(codec->addr & 0x0f) << 28;
 703         val |= (u32)direct << 27;
 704         val |= (u32)nid << 20;
 705         val |= verb << 8;
 706         val |= para;
 707         chip->last_cmd = val;
 708
 709         if (chip->single_cmd)
 710                 return azx_single_send_cmd(codec, val);
 711         else
 712                 return azx_corb_send_cmd(codec, val);
 713 }
 714
 715 /* get a response */
 716 static unsigned int azx_get_response(struct hda_codec *codec)
 717 {
 718         struct azx *chip = codec->bus->private_data;
 719         if (chip->single_cmd)
 720                 return azx_single_get_response(codec);
 721         else
 722                 return azx_rirb_get_response(codec);
 723 }
 724
 725 #ifdef CONFIG_SND_HDA_POWER_SAVE
 726 static void azx_power_notify(struct hda_codec *codec);
 727 #endif
 728
 729 /* reset codec link */
 730 static int azx_reset(struct azx *chip)
 731 {
 732         int count;
 733
 734         /* clear STATESTS */
 735         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 736
 737         /* reset controller */
 738         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 739
 740         count = 50;
 741         while (azx_readb(chip, GCTL) && --count)
 742                 msleep(1);
 743
 744         /* delay for >= 100us for codec PLL to settle per spec
 745          * Rev 0.9 section 5.5.1
 746          */
 747         msleep(1);
 748
 749         /* Bring controller out of reset */
 750         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 751
 752         count = 50;
 753         while (!azx_readb(chip, GCTL) && --count)
 754                 msleep(1);
 755
 756         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 757         msleep(1);
 758
 759         /* check to see if controller is ready */
 760         if (!azx_readb(chip, GCTL)) {
 761                 snd_printd("azx_reset: controller not ready!\n");
 762                 return -EBUSY;
 763         }
 764
 765         /* Accept unsolicited responses */
 766         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 767
 768         /* detect codecs */
 769         if (!chip->codec_mask) {
 770                 chip->codec_mask = azx_readw(chip, STATESTS);
 771                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 772         }
 773
 774         return 0;
 775 }
 776
 777
 778 /*
 779  * Lowlevel interface
 780  */
 781
 782 /* enable interrupts */
 783 static void azx_int_enable(struct azx *chip)
 784 {
 785         /* enable controller CIE and GIE */
 786         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 787                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 788 }
 789
 790 /* disable interrupts */
 791 static void azx_int_disable(struct azx *chip)
 792 {
 793         int i;
 794
 795         /* disable interrupts in stream descriptor */
 796         for (i = 0; i < chip->num_streams; i++) {
 797                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 798                 azx_sd_writeb(azx_dev, SD_CTL,
 799                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 800         }
 801
 802         /* disable SIE for all streams */
 803         azx_writeb(chip, INTCTL, 0);
 804
 805         /* disable controller CIE and GIE */
 806         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 807                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 808 }
 809
 810 /* clear interrupts */
 811 static void azx_int_clear(struct azx *chip)
 812 {
 813         int i;
 814
 815         /* clear stream status */
 816         for (i = 0; i < chip->num_streams; i++) {
 817                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 818                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 819         }
 820
 821         /* clear STATESTS */
 822         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 823
 824         /* clear rirb status */
 825         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 826
 827         /* clear int status */
 828         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 829 }
 830
 831 /* start a stream */
 832 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 833 {
 834         /*
 835          * Before stream start, initialize parameter
 836          */
 837         azx_dev->insufficient = 1;
 838
 839         /* enable SIE */
 840         azx_writeb(chip, INTCTL,
 841                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 842         /* set DMA start and interrupt mask */
 843         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 844                       SD_CTL_DMA_START | SD_INT_MASK);
 845 }
 846
 847 /* stop a stream */
 848 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 849 {
 850         /* stop DMA */
 851         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 852                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 853         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 854         /* disable SIE */
 855         azx_writeb(chip, INTCTL,
 856                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 857 }
 858
 859
 860 /*
 861  * reset and start the controller registers
 862  */
 863 static void azx_init_chip(struct azx *chip)
 864 {
 865         if (chip->initialized)
 866                 return;
 867
 868         /* reset controller */
 869         azx_reset(chip);
 870
 871         /* initialize interrupts */
 872         azx_int_clear(chip);
 873         azx_int_enable(chip);
 874
 875         /* initialize the codec command I/O */
 876         if (!chip->single_cmd)
 877                 azx_init_cmd_io(chip);
 878
 879         /* program the position buffer */
 880         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 881         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 882
 883         chip->initialized = 1;
 884 }
 885
 886 /*
 887  * initialize the PCI registers
 888  */
 889 /* update bits in a PCI register byte */
 890 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 891                             unsigned char mask, unsigned char val)
 892 {
 893         unsigned char data;
 894
 895         pci_read_config_byte(pci, reg, &data);
 896         data &= ~mask;
 897         data |= (val & mask);
 898         pci_write_config_byte(pci, reg, data);
 899 }
 900
 901 static void azx_init_pci(struct azx *chip)
 902 {
 903         unsigned short snoop;
 904
 905         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 906          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 907          * Ensuring these bits are 0 clears playback static on some HD Audio
 908          * codecs
 909          */
 910         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 911
 912         switch (chip->driver_type) {
 913         case AZX_DRIVER_ATI:
 914                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 915                 update_pci_byte(chip->pci,
 916                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 917                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 918                 break;
 919         case AZX_DRIVER_NVIDIA:
 920                 /* For NVIDIA HDA, enable snoop */
 921                 update_pci_byte(chip->pci,
 922                                 NVIDIA_HDA_TRANSREG_ADDR,
 923                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 924                 update_pci_byte(chip->pci,
 925                                 NVIDIA_HDA_ISTRM_COH,
 926                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 927                 update_pci_byte(chip->pci,
 928                                 NVIDIA_HDA_OSTRM_COH,
 929                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 930                 break;
 931         case AZX_DRIVER_SCH:
 932                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 933                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 934                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 935                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 936                         pci_read_config_word(chip->pci,
 937                                 INTEL_SCH_HDA_DEVC, &snoop);
 938                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 939                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 940                                 ? "Failed" : "OK");
 941                 }
 942                 break;
 943
 944         }
 945 }
 946
 947
 948 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 949
 950 /*
 951  * interrupt handler
 952  */
 953 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 954 {
 955         struct azx *chip = dev_id;
 956         struct azx_dev *azx_dev;
 957         u32 status;
 958         int i;
 959
 960         spin_lock(&chip->reg_lock);
 961
 962         status = azx_readl(chip, INTSTS);
 963         if (status == 0) {
 964                 spin_unlock(&chip->reg_lock);
 965                 return IRQ_NONE;
 966         }
 967
 968         for (i = 0; i < chip->num_streams; i++) {
 969                 azx_dev = &chip->azx_dev[i];
 970                 if (status & azx_dev->sd_int_sta_mask) {
 971                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 972                         if (!azx_dev->substream || !azx_dev->running)
 973                                 continue;
 974                         /* ignore the first dummy IRQ (due to pos_adj) */
 975                         if (azx_dev->irq_ignore) {
 976                                 azx_dev->irq_ignore = 0;
 977                                 continue;
 978                         }
 979                         /* check whether this IRQ is really acceptable */
 980                         if (azx_position_ok(chip, azx_dev)) {
 981                                 azx_dev->irq_pending = 0;
 982                                 spin_unlock(&chip->reg_lock);
 983                                 snd_pcm_period_elapsed(azx_dev->substream);
 984                                 spin_lock(&chip->reg_lock);
 985                         } else {
 986                                 /* bogus IRQ, process it later */
 987                                 azx_dev->irq_pending = 1;
 988                                 schedule_work(&chip->irq_pending_work);
 989                         }
 990                 }
 991         }
 992
 993         /* clear rirb int */
 994         status = azx_readb(chip, RIRBSTS);
 995         if (status & RIRB_INT_MASK) {
 996                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 997                         azx_update_rirb(chip);
 998                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 999         }
1000
1001 #if 0
1002         /* clear state status int */
1003         if (azx_readb(chip, STATESTS) & 0x04)
1004                 azx_writeb(chip, STATESTS, 0x04);
1005 #endif
1006         spin_unlock(&chip->reg_lock);
1007
1008         return IRQ_HANDLED;
1009 }
1010
1011
1012 /*
1013  * set up a BDL entry
1014  */
1015 static int setup_bdle(struct snd_pcm_substream *substream,
1016                       struct azx_dev *azx_dev, u32 **bdlp,
1017                       int ofs, int size, int with_ioc)
1018 {
1019         u32 *bdl = *bdlp;
1020
1021         while (size > 0) {
1022                 dma_addr_t addr;
1023                 int chunk;
1024
1025                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1026                         return -EINVAL;
1027
1028                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1029                 /* program the address field of the BDL entry */
1030                 bdl[0] = cpu_to_le32((u32)addr);
1031                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1032                 /* program the size field of the BDL entry */
1033                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1034                 bdl[2] = cpu_to_le32(chunk);
1035                 /* program the IOC to enable interrupt
1036                  * only when the whole fragment is processed
1037                  */
1038                 size -= chunk;
1039                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1040                 bdl += 4;
1041                 azx_dev->frags++;
1042                 ofs += chunk;
1043         }
1044         *bdlp = bdl;
1045         return ofs;
1046 }
1047
1048 /*
1049  * set up BDL entries
1050  */
1051 static int azx_setup_periods(struct azx *chip,
1052                              struct snd_pcm_substream *substream,
1053                              struct azx_dev *azx_dev)
1054 {
1055         u32 *bdl;
1056         int i, ofs, periods, period_bytes;
1057         int pos_adj;
1058
1059         /* reset BDL address */
1060         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1061         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1062
1063         period_bytes = snd_pcm_lib_period_bytes(substream);
1064         azx_dev->period_bytes = period_bytes;
1065         periods = azx_dev->bufsize / period_bytes;
1066
1067         /* program the initial BDL entries */
1068         bdl = (u32 *)azx_dev->bdl.area;
1069         ofs = 0;
1070         azx_dev->frags = 0;
1071         azx_dev->irq_ignore = 0;
1072         pos_adj = bdl_pos_adj[chip->dev_index];
1073         if (pos_adj > 0) {
1074                 struct snd_pcm_runtime *runtime = substream->runtime;
1075                 int pos_align = pos_adj;
1076                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1077                 if (!pos_adj)
1078                         pos_adj = pos_align;
1079                 else
1080                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1081                                 pos_align;
1082                 pos_adj = frames_to_bytes(runtime, pos_adj);
1083                 if (pos_adj >= period_bytes) {
1084                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1085                                    bdl_pos_adj[chip->dev_index]);
1086                         pos_adj = 0;
1087                 } else {
1088                         ofs = setup_bdle(substream, azx_dev,
1089                                          &bdl, ofs, pos_adj, 1);
1090                         if (ofs < 0)
1091                                 goto error;
1092                         azx_dev->irq_ignore = 1;
1093                 }
1094         } else
1095                 pos_adj = 0;
1096         for (i = 0; i < periods; i++) {
1097                 if (i == periods - 1 && pos_adj)
1098                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1099                                          period_bytes - pos_adj, 0);
1100                 else
1101                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1102                                          period_bytes, 1);
1103                 if (ofs < 0)
1104                         goto error;
1105         }
1106         return 0;
1107
1108  error:
1109         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1110                    azx_dev->bufsize, period_bytes);
1111         /* reset */
1112         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1113         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1114         return -EINVAL;
1115 }
1116
1117 /*
1118  * set up the SD for streaming
1119  */
1120 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1121 {
1122         unsigned char val;
1123         int timeout;
1124
1125         /* make sure the run bit is zero for SD */
1126         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1127                       ~SD_CTL_DMA_START);
1128         /* reset stream */
1129         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1130                       SD_CTL_STREAM_RESET);
1131         udelay(3);
1132         timeout = 300;
1133         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1134                --timeout)
1135                 ;
1136         val &= ~SD_CTL_STREAM_RESET;
1137         azx_sd_writeb(azx_dev, SD_CTL, val);
1138         udelay(3);
1139
1140         timeout = 300;
1141         /* waiting for hardware to report that the stream is out of reset */
1142         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1143                --timeout)
1144                 ;
1145
1146         /* program the stream_tag */
1147         azx_sd_writel(azx_dev, SD_CTL,
1148                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1149                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1150
1151         /* program the length of samples in cyclic buffer */
1152         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1153
1154         /* program the stream format */
1155         /* this value needs to be the same as the one programmed */
1156         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1157
1158         /* program the stream LVI (last valid index) of the BDL */
1159         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1160
1161         /* program the BDL address */
1162         /* lower BDL address */
1163         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1164         /* upper BDL address */
1165         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1166
1167         /* enable the position buffer */
1168         if (chip->position_fix == POS_FIX_POSBUF ||
1169             chip->position_fix == POS_FIX_AUTO ||
1170             chip->via_dmapos_patch) {
1171                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1172                         azx_writel(chip, DPLBASE,
1173                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1174         }
1175
1176         /* set the interrupt enable bits in the descriptor control register */
1177         azx_sd_writel(azx_dev, SD_CTL,
1178                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1179
1180         return 0;
1181 }
1182
1183
1184 /*
1185  * Codec initialization
1186  */
1187
1188 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1189 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1190         [AZX_DRIVER_TERA] = 1,
1191 };
1192
1193 /* number of slots to probe as default
1194  * this can be different from azx_max_codecs[] -- e.g. some boards
1195  * report wrongly the non-existing 4th slot availability
1196  */
1197 static unsigned int azx_default_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1198         [AZX_DRIVER_ICH] = 3,
1199         [AZX_DRIVER_ATI] = 3,
1200 };
1201
1202 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1203                                       unsigned int codec_probe_mask)
1204 {
1205         struct hda_bus_template bus_temp;
1206         int c, codecs, audio_codecs, err;
1207         int def_slots, max_slots;
1208
1209         memset(&bus_temp, 0, sizeof(bus_temp));
1210         bus_temp.private_data = chip;
1211         bus_temp.modelname = model;
1212         bus_temp.pci = chip->pci;
1213         bus_temp.ops.command = azx_send_cmd;
1214         bus_temp.ops.get_response = azx_get_response;
1215 #ifdef CONFIG_SND_HDA_POWER_SAVE
1216         bus_temp.ops.pm_notify = azx_power_notify;
1217 #endif
1218
1219         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1220         if (err < 0)
1221                 return err;
1222
1223         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1224                 chip->bus->needs_damn_long_delay = 1;
1225
1226         codecs = audio_codecs = 0;
1227         max_slots = azx_max_codecs[chip->driver_type];
1228         if (!max_slots)
1229                 max_slots = AZX_MAX_CODECS;
1230         def_slots = azx_default_codecs[chip->driver_type];
1231         if (!def_slots)
1232                 def_slots = max_slots;
1233         for (c = 0; c < def_slots; c++) {
1234                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1235                         struct hda_codec *codec;
1236                         err = snd_hda_codec_new(chip->bus, c, &codec);
1237                         if (err < 0)
1238                                 continue;
1239                         codecs++;
1240                         if (codec->afg)
1241                                 audio_codecs++;
1242                 }
1243         }
1244         if (!audio_codecs) {
1245                 /* probe additional slots if no codec is found */
1246                 for (; c < max_slots; c++) {
1247                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1248                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1249                                 if (err < 0)
1250                                         continue;
1251                                 codecs++;
1252                         }
1253                 }
1254         }
1255         if (!codecs) {
1256                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1257                 return -ENXIO;
1258         }
1259
1260         return 0;
1261 }
1262
1263
1264 /*
1265  * PCM support
1266  */
1267
1268 /* assign a stream for the PCM */
1269 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1270 {
1271         int dev, i, nums;
1272         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1273                 dev = chip->playback_index_offset;
1274                 nums = chip->playback_streams;
1275         } else {
1276                 dev = chip->capture_index_offset;
1277                 nums = chip->capture_streams;
1278         }
1279         for (i = 0; i < nums; i++, dev++)
1280                 if (!chip->azx_dev[dev].opened) {
1281                         chip->azx_dev[dev].opened = 1;
1282                         return &chip->azx_dev[dev];
1283                 }
1284         return NULL;
1285 }
1286
1287 /* release the assigned stream */
1288 static inline void azx_release_device(struct azx_dev *azx_dev)
1289 {
1290         azx_dev->opened = 0;
1291 }
1292
1293 static struct snd_pcm_hardware azx_pcm_hw = {
1294         .info =                 (SNDRV_PCM_INFO_MMAP |
1295                                  SNDRV_PCM_INFO_INTERLEAVED |
1296                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1297                                  SNDRV_PCM_INFO_MMAP_VALID |
1298                                  /* No full-resume yet implemented */
1299                                  /* SNDRV_PCM_INFO_RESUME |*/
1300                                  SNDRV_PCM_INFO_PAUSE |
1301                                  SNDRV_PCM_INFO_SYNC_START),
1302         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1303         .rates =                SNDRV_PCM_RATE_48000,
1304         .rate_min =             48000,
1305         .rate_max =             48000,
1306         .channels_min =         2,
1307         .channels_max =         2,
1308         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1309         .period_bytes_min =     128,
1310         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1311         .periods_min =          2,
1312         .periods_max =          AZX_MAX_FRAG,
1313         .fifo_size =            0,
1314 };
1315
1316 struct azx_pcm {
1317         struct azx *chip;
1318         struct hda_codec *codec;
1319         struct hda_pcm_stream *hinfo[2];
1320 };
1321
1322 static int azx_pcm_open(struct snd_pcm_substream *substream)
1323 {
1324         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1325         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1326         struct azx *chip = apcm->chip;
1327         struct azx_dev *azx_dev;
1328         struct snd_pcm_runtime *runtime = substream->runtime;
1329         unsigned long flags;
1330         int err;
1331
1332         mutex_lock(&chip->open_mutex);
1333         azx_dev = azx_assign_device(chip, substream->stream);
1334         if (azx_dev == NULL) {
1335                 mutex_unlock(&chip->open_mutex);
1336                 return -EBUSY;
1337         }
1338         runtime->hw = azx_pcm_hw;
1339         runtime->hw.channels_min = hinfo->channels_min;
1340         runtime->hw.channels_max = hinfo->channels_max;
1341         runtime->hw.formats = hinfo->formats;
1342         runtime->hw.rates = hinfo->rates;
1343         snd_pcm_limit_hw_rates(runtime);
1344         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1345         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1346                                    128);
1347         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1348                                    128);
1349         snd_hda_power_up(apcm->codec);
1350         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1351         if (err < 0) {
1352                 azx_release_device(azx_dev);
1353                 snd_hda_power_down(apcm->codec);
1354                 mutex_unlock(&chip->open_mutex);
1355                 return err;
1356         }
1357         spin_lock_irqsave(&chip->reg_lock, flags);
1358         azx_dev->substream = substream;
1359         azx_dev->running = 0;
1360         spin_unlock_irqrestore(&chip->reg_lock, flags);
1361
1362         runtime->private_data = azx_dev;
1363         snd_pcm_set_sync(substream);
1364         mutex_unlock(&chip->open_mutex);
1365         return 0;
1366 }
1367
1368 static int azx_pcm_close(struct snd_pcm_substream *substream)
1369 {
1370         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1371         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1372         struct azx *chip = apcm->chip;
1373         struct azx_dev *azx_dev = get_azx_dev(substream);
1374         unsigned long flags;
1375
1376         mutex_lock(&chip->open_mutex);
1377         spin_lock_irqsave(&chip->reg_lock, flags);
1378         azx_dev->substream = NULL;
1379         azx_dev->running = 0;
1380         spin_unlock_irqrestore(&chip->reg_lock, flags);
1381         azx_release_device(azx_dev);
1382         hinfo->ops.close(hinfo, apcm->codec, substream);
1383         snd_hda_power_down(apcm->codec);
1384         mutex_unlock(&chip->open_mutex);
1385         return 0;
1386 }
1387
1388 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1389                              struct snd_pcm_hw_params *hw_params)
1390 {
1391         return snd_pcm_lib_malloc_pages(substream,
1392                                         params_buffer_bytes(hw_params));
1393 }
1394
1395 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1396 {
1397         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1398         struct azx_dev *azx_dev = get_azx_dev(substream);
1399         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1400
1401         /* reset BDL address */
1402         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1403         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1404         azx_sd_writel(azx_dev, SD_CTL, 0);
1405
1406         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1407
1408         return snd_pcm_lib_free_pages(substream);
1409 }
1410
1411 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1412 {
1413         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1414         struct azx *chip = apcm->chip;
1415         struct azx_dev *azx_dev = get_azx_dev(substream);
1416         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1417         struct snd_pcm_runtime *runtime = substream->runtime;
1418
1419         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1420         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1421                                                          runtime->channels,
1422                                                          runtime->format,
1423                                                          hinfo->maxbps);
1424         if (!azx_dev->format_val) {
1425                 snd_printk(KERN_ERR SFX
1426                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1427                            runtime->rate, runtime->channels, runtime->format);
1428                 return -EINVAL;
1429         }
1430
1431         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1432                     azx_dev->bufsize, azx_dev->format_val);
1433         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1434                 return -EINVAL;
1435         azx_setup_controller(chip, azx_dev);
1436         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1437                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1438         else
1439                 azx_dev->fifo_size = 0;
1440
1441         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1442                                   azx_dev->format_val, substream);
1443 }
1444
1445 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1446 {
1447         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1448         struct azx *chip = apcm->chip;
1449         struct azx_dev *azx_dev;
1450         struct snd_pcm_substream *s;
1451         int start, nsync = 0, sbits = 0;
1452         int nwait, timeout;
1453
1454         switch (cmd) {
1455         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1456         case SNDRV_PCM_TRIGGER_RESUME:
1457         case SNDRV_PCM_TRIGGER_START:
1458                 start = 1;
1459                 break;
1460         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1461         case SNDRV_PCM_TRIGGER_SUSPEND:
1462         case SNDRV_PCM_TRIGGER_STOP:
1463                 start = 0;
1464                 break;
1465         default:
1466                 return -EINVAL;
1467         }
1468
1469         snd_pcm_group_for_each_entry(s, substream) {
1470                 if (s->pcm->card != substream->pcm->card)
1471                         continue;
1472                 azx_dev = get_azx_dev(s);
1473                 sbits |= 1 << azx_dev->index;
1474                 nsync++;
1475                 snd_pcm_trigger_done(s, substream);
1476         }
1477
1478         spin_lock(&chip->reg_lock);
1479         if (nsync > 1) {
1480                 /* first, set SYNC bits of corresponding streams */
1481                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1482         }
1483         snd_pcm_group_for_each_entry(s, substream) {
1484                 if (s->pcm->card != substream->pcm->card)
1485                         continue;
1486                 azx_dev = get_azx_dev(s);
1487                 if (start)
1488                         azx_stream_start(chip, azx_dev);
1489                 else
1490                         azx_stream_stop(chip, azx_dev);
1491                 azx_dev->running = start;
1492         }
1493         spin_unlock(&chip->reg_lock);
1494         if (start) {
1495                 if (nsync == 1)
1496                         return 0;
1497                 /* wait until all FIFOs get ready */
1498                 for (timeout = 5000; timeout; timeout--) {
1499                         nwait = 0;
1500                         snd_pcm_group_for_each_entry(s, substream) {
1501                                 if (s->pcm->card != substream->pcm->card)
1502                                         continue;
1503                                 azx_dev = get_azx_dev(s);
1504                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1505                                       SD_STS_FIFO_READY))
1506                                         nwait++;
1507                         }
1508                         if (!nwait)
1509                                 break;
1510                         cpu_relax();
1511                 }
1512         } else {
1513                 /* wait until all RUN bits are cleared */
1514                 for (timeout = 5000; timeout; timeout--) {
1515                         nwait = 0;
1516                         snd_pcm_group_for_each_entry(s, substream) {
1517                                 if (s->pcm->card != substream->pcm->card)
1518                                         continue;
1519                                 azx_dev = get_azx_dev(s);
1520                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1521                                     SD_CTL_DMA_START)
1522                                         nwait++;
1523                         }
1524                         if (!nwait)
1525                                 break;
1526                         cpu_relax();
1527                 }
1528         }
1529         if (nsync > 1) {
1530                 spin_lock(&chip->reg_lock);
1531                 /* reset SYNC bits */
1532                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1533                 spin_unlock(&chip->reg_lock);
1534         }
1535         return 0;
1536 }
1537
1538 /* get the current DMA position with correction on VIA chips */
1539 static unsigned int azx_via_get_position(struct azx *chip,
1540                                          struct azx_dev *azx_dev)
1541 {
1542         unsigned int link_pos, mini_pos, bound_pos;
1543         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1544         unsigned int fifo_size;
1545
1546         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1547         if (azx_dev->index >= 4) {
1548                 /* Playback, no problem using link position */
1549                 return link_pos;
1550         }
1551
1552         /* Capture */
1553         /* For new chipset,
1554          * use mod to get the DMA position just like old chipset
1555          */
1556         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1557         mod_dma_pos %= azx_dev->period_bytes;
1558
1559         /* azx_dev->fifo_size can't get FIFO size of in stream.
1560          * Get from base address + offset.
1561          */
1562         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1563
1564         if (azx_dev->insufficient) {
1565                 /* Link position never gather than FIFO size */
1566                 if (link_pos <= fifo_size)
1567                         return 0;
1568
1569                 azx_dev->insufficient = 0;
1570         }
1571
1572         if (link_pos <= fifo_size)
1573                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1574         else
1575                 mini_pos = link_pos - fifo_size;
1576
1577         /* Find nearest previous boudary */
1578         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1579         mod_link_pos = link_pos % azx_dev->period_bytes;
1580         if (mod_link_pos >= fifo_size)
1581                 bound_pos = link_pos - mod_link_pos;
1582         else if (mod_dma_pos >= mod_mini_pos)
1583                 bound_pos = mini_pos - mod_mini_pos;
1584         else {
1585                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1586                 if (bound_pos >= azx_dev->bufsize)
1587                         bound_pos = 0;
1588         }
1589
1590         /* Calculate real DMA position we want */
1591         return bound_pos + mod_dma_pos;
1592 }
1593
1594 static unsigned int azx_get_position(struct azx *chip,
1595                                      struct azx_dev *azx_dev)
1596 {
1597         unsigned int pos;
1598
1599         if (chip->via_dmapos_patch)
1600                 pos = azx_via_get_position(chip, azx_dev);
1601         else if (chip->position_fix == POS_FIX_POSBUF ||
1602                  chip->position_fix == POS_FIX_AUTO) {
1603                 /* use the position buffer */
1604                 pos = le32_to_cpu(*azx_dev->posbuf);
1605         } else {
1606                 /* read LPIB */
1607                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1608         }
1609         if (pos >= azx_dev->bufsize)
1610                 pos = 0;
1611         return pos;
1612 }
1613
1614 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1615 {
1616         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1617         struct azx *chip = apcm->chip;
1618         struct azx_dev *azx_dev = get_azx_dev(substream);
1619         return bytes_to_frames(substream->runtime,
1620                                azx_get_position(chip, azx_dev));
1621 }
1622
1623 /*
1624  * Check whether the current DMA position is acceptable for updating
1625  * periods.  Returns non-zero if it's OK.
1626  *
1627  * Many HD-audio controllers appear pretty inaccurate about
1628  * the update-IRQ timing.  The IRQ is issued before actually the
1629  * data is processed.  So, we need to process it afterwords in a
1630  * workqueue.
1631  */
1632 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1633 {
1634         unsigned int pos;
1635
1636         pos = azx_get_position(chip, azx_dev);
1637         if (chip->position_fix == POS_FIX_AUTO) {
1638                 if (!pos) {
1639                         printk(KERN_WARNING
1640                                "hda-intel: Invalid position buffer, "
1641                                "using LPIB read method instead.\n");
1642                         chip->position_fix = POS_FIX_LPIB;
1643                         pos = azx_get_position(chip, azx_dev);
1644                 } else
1645                         chip->position_fix = POS_FIX_POSBUF;
1646         }
1647
1648         if (!bdl_pos_adj[chip->dev_index])
1649                 return 1; /* no delayed ack */
1650         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1651                 return 0; /* NG - it's below the period boundary */
1652         return 1; /* OK, it's fine */
1653 }
1654
1655 /*
1656  * The work for pending PCM period updates.
1657  */
1658 static void azx_irq_pending_work(struct work_struct *work)
1659 {
1660         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1661         int i, pending;
1662
1663         if (!chip->irq_pending_warned) {
1664                 printk(KERN_WARNING
1665                        "hda-intel: IRQ timing workaround is activated "
1666                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1667                        chip->card->number);
1668                 chip->irq_pending_warned = 1;
1669         }
1670
1671         for (;;) {
1672                 pending = 0;
1673                 spin_lock_irq(&chip->reg_lock);
1674                 for (i = 0; i < chip->num_streams; i++) {
1675                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1676                         if (!azx_dev->irq_pending ||
1677                             !azx_dev->substream ||
1678                             !azx_dev->running)
1679                                 continue;
1680                         if (azx_position_ok(chip, azx_dev)) {
1681                                 azx_dev->irq_pending = 0;
1682                                 spin_unlock(&chip->reg_lock);
1683                                 snd_pcm_period_elapsed(azx_dev->substream);
1684                                 spin_lock(&chip->reg_lock);
1685                         } else
1686                                 pending++;
1687                 }
1688                 spin_unlock_irq(&chip->reg_lock);
1689                 if (!pending)
1690                         return;
1691                 cond_resched();
1692         }
1693 }
1694
1695 /* clear irq_pending flags and assure no on-going workq */
1696 static void azx_clear_irq_pending(struct azx *chip)
1697 {
1698         int i;
1699
1700         spin_lock_irq(&chip->reg_lock);
1701         for (i = 0; i < chip->num_streams; i++)
1702                 chip->azx_dev[i].irq_pending = 0;
1703         spin_unlock_irq(&chip->reg_lock);
1704         flush_scheduled_work();
1705 }
1706
1707 static struct snd_pcm_ops azx_pcm_ops = {
1708         .open = azx_pcm_open,
1709         .close = azx_pcm_close,
1710         .ioctl = snd_pcm_lib_ioctl,
1711         .hw_params = azx_pcm_hw_params,
1712         .hw_free = azx_pcm_hw_free,
1713         .prepare = azx_pcm_prepare,
1714         .trigger = azx_pcm_trigger,
1715         .pointer = azx_pcm_pointer,
1716         .page = snd_pcm_sgbuf_ops_page,
1717 };
1718
1719 static void azx_pcm_free(struct snd_pcm *pcm)
1720 {
1721         kfree(pcm->private_data);
1722 }
1723
1724 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1725                                       struct hda_pcm *cpcm)
1726 {
1727         int err;
1728         struct snd_pcm *pcm;
1729         struct azx_pcm *apcm;
1730
1731         /* if no substreams are defined for both playback and capture,
1732          * it's just a placeholder.  ignore it.
1733          */
1734         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1735                 return 0;
1736
1737         if (snd_BUG_ON(!cpcm->name))
1738                 return -EINVAL;
1739
1740         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1741                           cpcm->stream[0].substreams,
1742                           cpcm->stream[1].substreams,
1743                           &pcm);
1744         if (err < 0)
1745                 return err;
1746         strcpy(pcm->name, cpcm->name);
1747         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1748         if (apcm == NULL)
1749                 return -ENOMEM;
1750         apcm->chip = chip;
1751         apcm->codec = codec;
1752         apcm->hinfo[0] = &cpcm->stream[0];
1753         apcm->hinfo[1] = &cpcm->stream[1];
1754         pcm->private_data = apcm;
1755         pcm->private_free = azx_pcm_free;
1756         if (cpcm->stream[0].substreams)
1757                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1758         if (cpcm->stream[1].substreams)
1759                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1760         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1761                                               snd_dma_pci_data(chip->pci),
1762                                               1024 * 64, 32 * 1024 * 1024);
1763         chip->pcm[cpcm->device] = pcm;
1764         return 0;
1765 }
1766
1767 static int __devinit azx_pcm_create(struct azx *chip)
1768 {
1769         static const char *dev_name[HDA_PCM_NTYPES] = {
1770                 "Audio", "SPDIF", "HDMI", "Modem"
1771         };
1772         /* starting device index for each PCM type */
1773         static int dev_idx[HDA_PCM_NTYPES] = {
1774                 [HDA_PCM_TYPE_AUDIO] = 0,
1775                 [HDA_PCM_TYPE_SPDIF] = 1,
1776                 [HDA_PCM_TYPE_HDMI] = 3,
1777                 [HDA_PCM_TYPE_MODEM] = 6
1778         };
1779         /* normal audio device indices; not linear to keep compatibility */
1780         static int audio_idx[4] = { 0, 2, 4, 5 };
1781         struct hda_codec *codec;
1782         int c, err;
1783         int num_devs[HDA_PCM_NTYPES];
1784
1785         err = snd_hda_build_pcms(chip->bus);
1786         if (err < 0)
1787                 return err;
1788
1789         /* create audio PCMs */
1790         memset(num_devs, 0, sizeof(num_devs));
1791         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1792                 for (c = 0; c < codec->num_pcms; c++) {
1793                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1794                         int type = cpcm->pcm_type;
1795                         switch (type) {
1796                         case HDA_PCM_TYPE_AUDIO:
1797                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1798                                         snd_printk(KERN_WARNING
1799                                                    "Too many audio devices\n");
1800                                         continue;
1801                                 }
1802                                 cpcm->device = audio_idx[num_devs[type]];
1803                                 break;
1804                         case HDA_PCM_TYPE_SPDIF:
1805                         case HDA_PCM_TYPE_HDMI:
1806                         case HDA_PCM_TYPE_MODEM:
1807                                 if (num_devs[type]) {
1808                                         snd_printk(KERN_WARNING
1809                                                    "%s already defined\n",
1810                                                    dev_name[type]);
1811                                         continue;
1812                                 }
1813                                 cpcm->device = dev_idx[type];
1814                                 break;
1815                         default:
1816                                 snd_printk(KERN_WARNING
1817                                            "Invalid PCM type %d\n", type);
1818                                 continue;
1819                         }
1820                         num_devs[type]++;
1821                         err = create_codec_pcm(chip, codec, cpcm);
1822                         if (err < 0)
1823                                 return err;
1824                 }
1825         }
1826         return 0;
1827 }
1828
1829 /*
1830  * mixer creation - all stuff is implemented in hda module
1831  */
1832 static int __devinit azx_mixer_create(struct azx *chip)
1833 {
1834         return snd_hda_build_controls(chip->bus);
1835 }
1836
1837
1838 /*
1839  * initialize SD streams
1840  */
1841 static int __devinit azx_init_stream(struct azx *chip)
1842 {
1843         int i;
1844
1845         /* initialize each stream (aka device)
1846          * assign the starting bdl address to each stream (device)
1847          * and initialize
1848          */
1849         for (i = 0; i < chip->num_streams; i++) {
1850                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1851                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1852                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1853                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1854                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1855                 azx_dev->sd_int_sta_mask = 1 << i;
1856                 /* stream tag: must be non-zero and unique */
1857                 azx_dev->index = i;
1858                 azx_dev->stream_tag = i + 1;
1859         }
1860
1861         return 0;
1862 }
1863
1864 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1865 {
1866         if (request_irq(chip->pci->irq, azx_interrupt,
1867                         chip->msi ? 0 : IRQF_SHARED,
1868                         "HDA Intel", chip)) {
1869                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1870                        "disabling device\n", chip->pci->irq);
1871                 if (do_disconnect)
1872                         snd_card_disconnect(chip->card);
1873                 return -1;
1874         }
1875         chip->irq = chip->pci->irq;
1876         pci_intx(chip->pci, !chip->msi);
1877         return 0;
1878 }
1879
1880
1881 static void azx_stop_chip(struct azx *chip)
1882 {
1883         if (!chip->initialized)
1884                 return;
1885
1886         /* disable interrupts */
1887         azx_int_disable(chip);
1888         azx_int_clear(chip);
1889
1890         /* disable CORB/RIRB */
1891         azx_free_cmd_io(chip);
1892
1893         /* disable position buffer */
1894         azx_writel(chip, DPLBASE, 0);
1895         azx_writel(chip, DPUBASE, 0);
1896
1897         chip->initialized = 0;
1898 }
1899
1900 #ifdef CONFIG_SND_HDA_POWER_SAVE
1901 /* power-up/down the controller */
1902 static void azx_power_notify(struct hda_codec *codec)
1903 {
1904         struct azx *chip = codec->bus->private_data;
1905         struct hda_codec *c;
1906         int power_on = 0;
1907
1908         list_for_each_entry(c, &codec->bus->codec_list, list) {
1909                 if (c->power_on) {
1910                         power_on = 1;
1911                         break;
1912                 }
1913         }
1914         if (power_on)
1915                 azx_init_chip(chip);
1916         else if (chip->running && power_save_controller)
1917                 azx_stop_chip(chip);
1918 }
1919 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1920
1921 #ifdef CONFIG_PM
1922 /*
1923  * power management
1924  */
1925 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1926 {
1927         struct snd_card *card = pci_get_drvdata(pci);
1928         struct azx *chip = card->private_data;
1929         int i;
1930
1931         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1932         azx_clear_irq_pending(chip);
1933         for (i = 0; i < AZX_MAX_PCMS; i++)
1934                 snd_pcm_suspend_all(chip->pcm[i]);
1935         if (chip->initialized)
1936                 snd_hda_suspend(chip->bus, state);
1937         azx_stop_chip(chip);
1938         if (chip->irq >= 0) {
1939                 free_irq(chip->irq, chip);
1940                 chip->irq = -1;
1941         }
1942         if (chip->msi)
1943                 pci_disable_msi(chip->pci);
1944         pci_disable_device(pci);
1945         pci_save_state(pci);
1946         pci_set_power_state(pci, pci_choose_state(pci, state));
1947         return 0;
1948 }
1949
1950 static int azx_resume(struct pci_dev *pci)
1951 {
1952         struct snd_card *card = pci_get_drvdata(pci);
1953         struct azx *chip = card->private_data;
1954
1955         pci_set_power_state(pci, PCI_D0);
1956         pci_restore_state(pci);
1957         if (pci_enable_device(pci) < 0) {
1958                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1959                        "disabling device\n");
1960                 snd_card_disconnect(card);
1961                 return -EIO;
1962         }
1963         pci_set_master(pci);
1964         if (chip->msi)
1965                 if (pci_enable_msi(pci) < 0)
1966                         chip->msi = 0;
1967         if (azx_acquire_irq(chip, 1) < 0)
1968                 return -EIO;
1969         azx_init_pci(chip);
1970
1971         if (snd_hda_codecs_inuse(chip->bus))
1972                 azx_init_chip(chip);
1973
1974         snd_hda_resume(chip->bus);
1975         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1976         return 0;
1977 }
1978 #endif /* CONFIG_PM */
1979
1980
1981 /*
1982  * destructor
1983  */
1984 static int azx_free(struct azx *chip)
1985 {
1986         int i;
1987
1988         if (chip->initialized) {
1989                 azx_clear_irq_pending(chip);
1990                 for (i = 0; i < chip->num_streams; i++)
1991                         azx_stream_stop(chip, &chip->azx_dev[i]);
1992                 azx_stop_chip(chip);
1993         }
1994
1995         if (chip->irq >= 0)
1996                 free_irq(chip->irq, (void*)chip);
1997         if (chip->msi)
1998                 pci_disable_msi(chip->pci);
1999         if (chip->remap_addr)
2000                 iounmap(chip->remap_addr);
2001
2002         if (chip->azx_dev) {
2003                 for (i = 0; i < chip->num_streams; i++)
2004                         if (chip->azx_dev[i].bdl.area)
2005                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2006         }
2007         if (chip->rb.area)
2008                 snd_dma_free_pages(&chip->rb);
2009         if (chip->posbuf.area)
2010                 snd_dma_free_pages(&chip->posbuf);
2011         pci_release_regions(chip->pci);
2012         pci_disable_device(chip->pci);
2013         kfree(chip->azx_dev);
2014         kfree(chip);
2015
2016         return 0;
2017 }
2018
2019 static int azx_dev_free(struct snd_device *device)
2020 {
2021         return azx_free(device->device_data);
2022 }
2023
2024 /*
2025  * white/black-listing for position_fix
2026  */
2027 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2028         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2029         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2030         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2031         {}
2032 };
2033
2034 static int __devinit check_position_fix(struct azx *chip, int fix)
2035 {
2036         const struct snd_pci_quirk *q;
2037
2038         /* Check VIA HD Audio Controller exist */
2039         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2040             chip->pci->device == VIA_HDAC_DEVICE_ID) {
2041                 chip->via_dmapos_patch = 1;
2042                 /* Use link position directly, avoid any transfer problem. */
2043                 return POS_FIX_LPIB;
2044         }
2045         chip->via_dmapos_patch = 0;
2046
2047         if (fix == POS_FIX_AUTO) {
2048                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2049                 if (q) {
2050                         printk(KERN_INFO
2051                                     "hda_intel: position_fix set to %d "
2052                                     "for device %04x:%04x\n",
2053                                     q->value, q->subvendor, q->subdevice);
2054                         return q->value;
2055                 }
2056         }
2057         return fix;
2058 }
2059
2060 /*
2061  * black-lists for probe_mask
2062  */
2063 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2064         /* Thinkpad often breaks the controller communication when accessing
2065          * to the non-working (or non-existing) modem codec slot.
2066          */
2067         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2068         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2069         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2070         {}
2071 };
2072
2073 static void __devinit check_probe_mask(struct azx *chip, int dev)
2074 {
2075         const struct snd_pci_quirk *q;
2076
2077         if (probe_mask[dev] == -1) {
2078                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2079                 if (q) {
2080                         printk(KERN_INFO
2081                                "hda_intel: probe_mask set to 0x%x "
2082                                "for device %04x:%04x\n",
2083                                q->value, q->subvendor, q->subdevice);
2084                         probe_mask[dev] = q->value;
2085                 }
2086         }
2087 }
2088
2089
2090 /*
2091  * constructor
2092  */
2093 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2094                                 int dev, int driver_type,
2095                                 struct azx **rchip)
2096 {
2097         struct azx *chip;
2098         int i, err;
2099         unsigned short gcap;
2100         static struct snd_device_ops ops = {
2101                 .dev_free = azx_dev_free,
2102         };
2103
2104         *rchip = NULL;
2105
2106         err = pci_enable_device(pci);
2107         if (err < 0)
2108                 return err;
2109
2110         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2111         if (!chip) {
2112                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2113                 pci_disable_device(pci);
2114                 return -ENOMEM;
2115         }
2116
2117         spin_lock_init(&chip->reg_lock);
2118         mutex_init(&chip->open_mutex);
2119         chip->card = card;
2120         chip->pci = pci;
2121         chip->irq = -1;
2122         chip->driver_type = driver_type;
2123         chip->msi = enable_msi;
2124         chip->dev_index = dev;
2125         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2126
2127         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2128         check_probe_mask(chip, dev);
2129
2130         chip->single_cmd = single_cmd;
2131
2132         if (bdl_pos_adj[dev] < 0) {
2133                 switch (chip->driver_type) {
2134                 case AZX_DRIVER_ICH:
2135                         bdl_pos_adj[dev] = 1;
2136                         break;
2137                 default:
2138                         bdl_pos_adj[dev] = 32;
2139                         break;
2140                 }
2141         }
2142
2143 #if BITS_PER_LONG != 64
2144         /* Fix up base address on ULI M5461 */
2145         if (chip->driver_type == AZX_DRIVER_ULI) {
2146                 u16 tmp3;
2147                 pci_read_config_word(pci, 0x40, &tmp3);
2148                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2149                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2150         }
2151 #endif
2152
2153         err = pci_request_regions(pci, "ICH HD audio");
2154         if (err < 0) {
2155                 kfree(chip);
2156                 pci_disable_device(pci);
2157                 return err;
2158         }
2159
2160         chip->addr = pci_resource_start(pci, 0);
2161         chip->remap_addr = pci_ioremap_bar(pci, 0);
2162         if (chip->remap_addr == NULL) {
2163                 snd_printk(KERN_ERR SFX "ioremap error\n");
2164                 err = -ENXIO;
2165                 goto errout;
2166         }
2167
2168         if (chip->msi)
2169                 if (pci_enable_msi(pci) < 0)
2170                         chip->msi = 0;
2171
2172         if (azx_acquire_irq(chip, 0) < 0) {
2173                 err = -EBUSY;
2174                 goto errout;
2175         }
2176
2177         pci_set_master(pci);
2178         synchronize_irq(chip->irq);
2179
2180         gcap = azx_readw(chip, GCAP);
2181         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2182
2183         /* allow 64bit DMA address if supported by H/W */
2184         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2185                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2186
2187         /* read number of streams from GCAP register instead of using
2188          * hardcoded value
2189          */
2190         chip->capture_streams = (gcap >> 8) & 0x0f;
2191         chip->playback_streams = (gcap >> 12) & 0x0f;
2192         if (!chip->playback_streams && !chip->capture_streams) {
2193                 /* gcap didn't give any info, switching to old method */
2194
2195                 switch (chip->driver_type) {
2196                 case AZX_DRIVER_ULI:
2197                         chip->playback_streams = ULI_NUM_PLAYBACK;
2198                         chip->capture_streams = ULI_NUM_CAPTURE;
2199                         break;
2200                 case AZX_DRIVER_ATIHDMI:
2201                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2202                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2203                         break;
2204                 default:
2205                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2206                         chip->capture_streams = ICH6_NUM_CAPTURE;
2207                         break;
2208                 }
2209         }
2210         chip->capture_index_offset = 0;
2211         chip->playback_index_offset = chip->capture_streams;
2212         chip->num_streams = chip->playback_streams + chip->capture_streams;
2213         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2214                                 GFP_KERNEL);
2215         if (!chip->azx_dev) {
2216                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2217                 goto errout;
2218         }
2219
2220         for (i = 0; i < chip->num_streams; i++) {
2221                 /* allocate memory for the BDL for each stream */
2222                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2223                                           snd_dma_pci_data(chip->pci),
2224                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2225                 if (err < 0) {
2226                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2227                         goto errout;
2228                 }
2229         }
2230         /* allocate memory for the position buffer */
2231         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2232                                   snd_dma_pci_data(chip->pci),
2233                                   chip->num_streams * 8, &chip->posbuf);
2234         if (err < 0) {
2235                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2236                 goto errout;
2237         }
2238         /* allocate CORB/RIRB */
2239         if (!chip->single_cmd) {
2240                 err = azx_alloc_cmd_io(chip);
2241                 if (err < 0)
2242                         goto errout;
2243         }
2244
2245         /* initialize streams */
2246         azx_init_stream(chip);
2247
2248         /* initialize chip */
2249         azx_init_pci(chip);
2250         azx_init_chip(chip);
2251
2252         /* codec detection */
2253         if (!chip->codec_mask) {
2254                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2255                 err = -ENODEV;
2256                 goto errout;
2257         }
2258
2259         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2260         if (err <0) {
2261                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2262                 goto errout;
2263         }
2264
2265         strcpy(card->driver, "HDA-Intel");
2266         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2267         sprintf(card->longname, "%s at 0x%lx irq %i",
2268                 card->shortname, chip->addr, chip->irq);
2269
2270         *rchip = chip;
2271         return 0;
2272
2273  errout:
2274         azx_free(chip);
2275         return err;
2276 }
2277
2278 static void power_down_all_codecs(struct azx *chip)
2279 {
2280 #ifdef CONFIG_SND_HDA_POWER_SAVE
2281         /* The codecs were powered up in snd_hda_codec_new().
2282          * Now all initialization done, so turn them down if possible
2283          */
2284         struct hda_codec *codec;
2285         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2286                 snd_hda_power_down(codec);
2287         }
2288 #endif
2289 }
2290
2291 static int __devinit azx_probe(struct pci_dev *pci,
2292                                const struct pci_device_id *pci_id)
2293 {
2294         static int dev;
2295         struct snd_card *card;
2296         struct azx *chip;
2297         int err;
2298
2299         if (dev >= SNDRV_CARDS)
2300                 return -ENODEV;
2301         if (!enable[dev]) {
2302                 dev++;
2303                 return -ENOENT;
2304         }
2305
2306         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2307         if (!card) {
2308                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2309                 return -ENOMEM;
2310         }
2311
2312         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2313         if (err < 0) {
2314                 snd_card_free(card);
2315                 return err;
2316         }
2317         card->private_data = chip;
2318
2319         /* create codec instances */
2320         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2321         if (err < 0) {
2322                 snd_card_free(card);
2323                 return err;
2324         }
2325
2326         /* create PCM streams */
2327         err = azx_pcm_create(chip);
2328         if (err < 0) {
2329                 snd_card_free(card);
2330                 return err;
2331         }
2332
2333         /* create mixer controls */
2334         err = azx_mixer_create(chip);
2335         if (err < 0) {
2336                 snd_card_free(card);
2337                 return err;
2338         }
2339
2340         snd_card_set_dev(card, &pci->dev);
2341
2342         err = snd_card_register(card);
2343         if (err < 0) {
2344                 snd_card_free(card);
2345                 return err;
2346         }
2347
2348         pci_set_drvdata(pci, card);
2349         chip->running = 1;
2350         power_down_all_codecs(chip);
2351
2352         dev++;
2353         return err;
2354 }
2355
2356 static void __devexit azx_remove(struct pci_dev *pci)
2357 {
2358         snd_card_free(pci_get_drvdata(pci));
2359         pci_set_drvdata(pci, NULL);
2360 }
2361
2362 /* PCI IDs */
2363 static struct pci_device_id azx_ids[] = {
2364         /* ICH 6..10 */
2365         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2366         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2367         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2368         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2369         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2370         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2371         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2372         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2373         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2374         /* PCH */
2375         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2376         /* SCH */
2377         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2378         /* ATI SB 450/600 */
2379         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2380         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2381         /* ATI HDMI */
2382         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2383         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2384         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2385         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2386         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2387         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2388         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2389         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2390         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2391         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2392         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2393         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2394         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2395         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2396         /* VIA VT8251/VT8237A */
2397         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2398         /* SIS966 */
2399         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2400         /* ULI M5461 */
2401         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2402         /* NVIDIA MCP */
2403         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2404         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2405         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2406         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2407         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2408         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2409         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2410         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2411         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2412         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2413         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2414         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2415         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2416         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2417         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2418         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2419         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2420         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2421         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2422         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2423         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2424         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2425         /* Teradici */
2426         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2427         { 0, }
2428 };
2429 MODULE_DEVICE_TABLE(pci, azx_ids);
2430
2431 /* pci_driver definition */
2432 static struct pci_driver driver = {
2433         .name = "HDA Intel",
2434         .id_table = azx_ids,
2435         .probe = azx_probe,
2436         .remove = __devexit_p(azx_remove),
2437 #ifdef CONFIG_PM
2438         .suspend = azx_suspend,
2439         .resume = azx_resume,
2440 #endif
2441 };
2442
2443 static int __init alsa_card_azx_init(void)
2444 {
2445         return pci_register_driver(&driver);
2446 }
2447
2448 static void __exit alsa_card_azx_exit(void)
2449 {
2450         pci_unregister_driver(&driver);
2451 }
2452
2453 module_init(alsa_card_azx_init)
2454 module_exit(alsa_card_azx_exit)