sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static int single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, int, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static int power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = 1;
 125 module_param(align_buffer_size, bool, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, LPT},"
 152                          "{Intel, PBG},"
 153                          "{Intel, SCH},"
 154                          "{ATI, SB450},"
 155                          "{ATI, SB600},"
 156                          "{ATI, RS600},"
 157                          "{ATI, RS690},"
 158                          "{ATI, RS780},"
 159                          "{ATI, R600},"
 160                          "{ATI, RV630},"
 161                          "{ATI, RV610},"
 162                          "{ATI, RV670},"
 163                          "{ATI, RV635},"
 164                          "{ATI, RV620},"
 165                          "{ATI, RV770},"
 166                          "{VIA, VT8251},"
 167                          "{VIA, VT8237A},"
 168                          "{SiS, SIS966},"
 169                          "{ULI, M5461}}");
 170 MODULE_DESCRIPTION("Intel HDA driver");
 171
 172 #ifdef CONFIG_SND_VERBOSE_PRINTK
 173 #define SFX     /* nop */
 174 #else
 175 #define SFX     "hda-intel: "
 176 #endif
 177
 178 /*
 179  * registers
 180  */
 181 #define ICH6_REG_GCAP                   0x00
 182 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 183 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 184 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 185 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 186 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 187 #define ICH6_REG_VMIN                   0x02
 188 #define ICH6_REG_VMAJ                   0x03
 189 #define ICH6_REG_OUTPAY                 0x04
 190 #define ICH6_REG_INPAY                  0x06
 191 #define ICH6_REG_GCTL                   0x08
 192 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 193 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 194 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 195 #define ICH6_REG_WAKEEN                 0x0c
 196 #define ICH6_REG_STATESTS               0x0e
 197 #define ICH6_REG_GSTS                   0x10
 198 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 199 #define ICH6_REG_INTCTL                 0x20
 200 #define ICH6_REG_INTSTS                 0x24
 201 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 202 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 203 #define ICH6_REG_SSYNC                  0x38
 204 #define ICH6_REG_CORBLBASE              0x40
 205 #define ICH6_REG_CORBUBASE              0x44
 206 #define ICH6_REG_CORBWP                 0x48
 207 #define ICH6_REG_CORBRP                 0x4a
 208 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 209 #define ICH6_REG_CORBCTL                0x4c
 210 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 211 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 212 #define ICH6_REG_CORBSTS                0x4d
 213 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 214 #define ICH6_REG_CORBSIZE               0x4e
 215
 216 #define ICH6_REG_RIRBLBASE              0x50
 217 #define ICH6_REG_RIRBUBASE              0x54
 218 #define ICH6_REG_RIRBWP                 0x58
 219 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 220 #define ICH6_REG_RINTCNT                0x5a
 221 #define ICH6_REG_RIRBCTL                0x5c
 222 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 223 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 224 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 225 #define ICH6_REG_RIRBSTS                0x5d
 226 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 227 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 228 #define ICH6_REG_RIRBSIZE               0x5e
 229
 230 #define ICH6_REG_IC                     0x60
 231 #define ICH6_REG_IR                     0x64
 232 #define ICH6_REG_IRS                    0x68
 233 #define   ICH6_IRS_VALID        (1<<1)
 234 #define   ICH6_IRS_BUSY         (1<<0)
 235
 236 #define ICH6_REG_DPLBASE                0x70
 237 #define ICH6_REG_DPUBASE                0x74
 238 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 239
 240 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 241 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 242
 243 /* stream register offsets from stream base */
 244 #define ICH6_REG_SD_CTL                 0x00
 245 #define ICH6_REG_SD_STS                 0x03
 246 #define ICH6_REG_SD_LPIB                0x04
 247 #define ICH6_REG_SD_CBL                 0x08
 248 #define ICH6_REG_SD_LVI                 0x0c
 249 #define ICH6_REG_SD_FIFOW               0x0e
 250 #define ICH6_REG_SD_FIFOSIZE            0x10
 251 #define ICH6_REG_SD_FORMAT              0x12
 252 #define ICH6_REG_SD_BDLPL               0x18
 253 #define ICH6_REG_SD_BDLPU               0x1c
 254
 255 /* PCI space */
 256 #define ICH6_PCIREG_TCSEL       0x44
 257
 258 /*
 259  * other constants
 260  */
 261
 262 /* max number of SDs */
 263 /* ICH, ATI and VIA have 4 playback and 4 capture */
 264 #define ICH6_NUM_CAPTURE        4
 265 #define ICH6_NUM_PLAYBACK       4
 266
 267 /* ULI has 6 playback and 5 capture */
 268 #define ULI_NUM_CAPTURE         5
 269 #define ULI_NUM_PLAYBACK        6
 270
 271 /* ATI HDMI has 1 playback and 0 capture */
 272 #define ATIHDMI_NUM_CAPTURE     0
 273 #define ATIHDMI_NUM_PLAYBACK    1
 274
 275 /* TERA has 4 playback and 3 capture */
 276 #define TERA_NUM_CAPTURE        3
 277 #define TERA_NUM_PLAYBACK       4
 278
 279 /* this number is statically defined for simplicity */
 280 #define MAX_AZX_DEV             16
 281
 282 /* max number of fragments - we may use more if allocating more pages for BDL */
 283 #define BDL_SIZE                4096
 284 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 285 #define AZX_MAX_FRAG            32
 286 /* max buffer size - no h/w limit, you can increase as you like */
 287 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 288
 289 /* RIRB int mask: overrun[2], response[0] */
 290 #define RIRB_INT_RESPONSE       0x01
 291 #define RIRB_INT_OVERRUN        0x04
 292 #define RIRB_INT_MASK           0x05
 293
 294 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 295 #define AZX_MAX_CODECS          8
 296 #define AZX_DEFAULT_CODECS      4
 297 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 298
 299 /* SD_CTL bits */
 300 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 301 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 302 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 303 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 304 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 305 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 306 #define SD_CTL_STREAM_TAG_SHIFT 20
 307
 308 /* SD_CTL and SD_STS */
 309 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 310 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 311 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 312 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 313                                  SD_INT_COMPLETE)
 314
 315 /* SD_STS */
 316 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 317
 318 /* INTCTL and INTSTS */
 319 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 320 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 321 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 322
 323 /* below are so far hardcoded - should read registers in future */
 324 #define ICH6_MAX_CORB_ENTRIES   256
 325 #define ICH6_MAX_RIRB_ENTRIES   256
 326
 327 /* position fix mode */
 328 enum {
 329         POS_FIX_AUTO,
 330         POS_FIX_LPIB,
 331         POS_FIX_POSBUF,
 332         POS_FIX_VIACOMBO,
 333 };
 334
 335 /* Defines for ATI HD Audio support in SB450 south bridge */
 336 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 337 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 338
 339 /* Defines for Nvidia HDA support */
 340 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 341 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 342 #define NVIDIA_HDA_ISTRM_COH          0x4d
 343 #define NVIDIA_HDA_OSTRM_COH          0x4c
 344 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 345
 346 /* Defines for Intel SCH HDA snoop control */
 347 #define INTEL_SCH_HDA_DEVC      0x78
 348 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 349
 350 /* Define IN stream 0 FIFO size offset in VIA controller */
 351 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 352 /* Define VIA HD Audio Device ID*/
 353 #define VIA_HDAC_DEVICE_ID              0x3288
 354
 355 /* HD Audio class code */
 356 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 357
 358 /*
 359  */
 360
 361 struct azx_dev {
 362         struct snd_dma_buffer bdl; /* BDL buffer */
 363         u32 *posbuf;            /* position buffer pointer */
 364
 365         unsigned int bufsize;   /* size of the play buffer in bytes */
 366         unsigned int period_bytes; /* size of the period in bytes */
 367         unsigned int frags;     /* number for period in the play buffer */
 368         unsigned int fifo_size; /* FIFO size */
 369         unsigned long start_wallclk;    /* start + minimum wallclk */
 370         unsigned long period_wallclk;   /* wallclk for period */
 371
 372         void __iomem *sd_addr;  /* stream descriptor pointer */
 373
 374         u32 sd_int_sta_mask;    /* stream int status mask */
 375
 376         /* pcm support */
 377         struct snd_pcm_substream *substream;    /* assigned substream,
 378                                                  * set in PCM open
 379                                                  */
 380         unsigned int format_val;        /* format value to be set in the
 381                                          * controller and the codec
 382                                          */
 383         unsigned char stream_tag;       /* assigned stream */
 384         unsigned char index;            /* stream index */
 385         int assigned_key;               /* last device# key assigned to */
 386
 387         unsigned int opened :1;
 388         unsigned int running :1;
 389         unsigned int irq_pending :1;
 390         /*
 391          * For VIA:
 392          *  A flag to ensure DMA position is 0
 393          *  when link position is not greater than FIFO size
 394          */
 395         unsigned int insufficient :1;
 396         unsigned int wc_marked:1;
 397 };
 398
 399 /* CORB/RIRB */
 400 struct azx_rb {
 401         u32 *buf;               /* CORB/RIRB buffer
 402                                  * Each CORB entry is 4byte, RIRB is 8byte
 403                                  */
 404         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 405         /* for RIRB */
 406         unsigned short rp, wp;  /* read/write pointers */
 407         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 408         u32 res[AZX_MAX_CODECS];        /* last read value */
 409 };
 410
 411 struct azx {
 412         struct snd_card *card;
 413         struct pci_dev *pci;
 414         int dev_index;
 415
 416         /* chip type specific */
 417         int driver_type;
 418         unsigned int driver_caps;
 419         int playback_streams;
 420         int playback_index_offset;
 421         int capture_streams;
 422         int capture_index_offset;
 423         int num_streams;
 424
 425         /* pci resources */
 426         unsigned long addr;
 427         void __iomem *remap_addr;
 428         int irq;
 429
 430         /* locks */
 431         spinlock_t reg_lock;
 432         struct mutex open_mutex;
 433
 434         /* streams (x num_streams) */
 435         struct azx_dev *azx_dev;
 436
 437         /* PCM */
 438         struct snd_pcm *pcm[HDA_MAX_PCMS];
 439
 440         /* HD codec */
 441         unsigned short codec_mask;
 442         int  codec_probe_mask; /* copied from probe_mask option */
 443         struct hda_bus *bus;
 444         unsigned int beep_mode;
 445
 446         /* CORB/RIRB */
 447         struct azx_rb corb;
 448         struct azx_rb rirb;
 449
 450         /* CORB/RIRB and position buffers */
 451         struct snd_dma_buffer rb;
 452         struct snd_dma_buffer posbuf;
 453
 454         /* flags */
 455         int position_fix[2]; /* for both playback/capture streams */
 456         int poll_count;
 457         unsigned int running :1;
 458         unsigned int initialized :1;
 459         unsigned int single_cmd :1;
 460         unsigned int polling_mode :1;
 461         unsigned int msi :1;
 462         unsigned int irq_pending_warned :1;
 463         unsigned int probing :1; /* codec probing phase */
 464         unsigned int snoop:1;
 465         unsigned int align_buffer_size:1;
 466
 467         /* for debugging */
 468         unsigned int last_cmd[AZX_MAX_CODECS];
 469
 470         /* for pending irqs */
 471         struct work_struct irq_pending_work;
 472
 473         /* reboot notifier (for mysterious hangup problem at power-down) */
 474         struct notifier_block reboot_notifier;
 475 };
 476
 477 /* driver types */
 478 enum {
 479         AZX_DRIVER_ICH,
 480         AZX_DRIVER_PCH,
 481         AZX_DRIVER_SCH,
 482         AZX_DRIVER_ATI,
 483         AZX_DRIVER_ATIHDMI,
 484         AZX_DRIVER_VIA,
 485         AZX_DRIVER_SIS,
 486         AZX_DRIVER_ULI,
 487         AZX_DRIVER_NVIDIA,
 488         AZX_DRIVER_TERA,
 489         AZX_DRIVER_CTX,
 490         AZX_DRIVER_GENERIC,
 491         AZX_NUM_DRIVERS, /* keep this as last entry */
 492 };
 493
 494 /* driver quirks (capabilities) */
 495 /* bits 0-7 are used for indicating driver type */
 496 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 497 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 498 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 499 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 500 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 501 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 502 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 503 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 504 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 505 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 506 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 507 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 508 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 509 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 510
 511 /* quirks for ATI SB / AMD Hudson */
 512 #define AZX_DCAPS_PRESET_ATI_SB \
 513         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 514          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 515
 516 /* quirks for ATI/AMD HDMI */
 517 #define AZX_DCAPS_PRESET_ATI_HDMI \
 518         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 519
 520 /* quirks for Nvidia */
 521 #define AZX_DCAPS_PRESET_NVIDIA \
 522         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 523
 524 static char *driver_short_names[] __devinitdata = {
 525         [AZX_DRIVER_ICH] = "HDA Intel",
 526         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 527         [AZX_DRIVER_SCH] = "HDA Intel MID",
 528         [AZX_DRIVER_ATI] = "HDA ATI SB",
 529         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 530         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 531         [AZX_DRIVER_SIS] = "HDA SIS966",
 532         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 533         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 534         [AZX_DRIVER_TERA] = "HDA Teradici",
 535         [AZX_DRIVER_CTX] = "HDA Creative",
 536         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 537 };
 538
 539 /*
 540  * macros for easy use
 541  */
 542 #define azx_writel(chip,reg,value) \
 543         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 544 #define azx_readl(chip,reg) \
 545         readl((chip)->remap_addr + ICH6_REG_##reg)
 546 #define azx_writew(chip,reg,value) \
 547         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 548 #define azx_readw(chip,reg) \
 549         readw((chip)->remap_addr + ICH6_REG_##reg)
 550 #define azx_writeb(chip,reg,value) \
 551         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 552 #define azx_readb(chip,reg) \
 553         readb((chip)->remap_addr + ICH6_REG_##reg)
 554
 555 #define azx_sd_writel(dev,reg,value) \
 556         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 557 #define azx_sd_readl(dev,reg) \
 558         readl((dev)->sd_addr + ICH6_REG_##reg)
 559 #define azx_sd_writew(dev,reg,value) \
 560         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 561 #define azx_sd_readw(dev,reg) \
 562         readw((dev)->sd_addr + ICH6_REG_##reg)
 563 #define azx_sd_writeb(dev,reg,value) \
 564         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 565 #define azx_sd_readb(dev,reg) \
 566         readb((dev)->sd_addr + ICH6_REG_##reg)
 567
 568 /* for pcm support */
 569 #define get_azx_dev(substream) (substream->runtime->private_data)
 570
 571 #ifdef CONFIG_X86
 572 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 573 {
 574         int pages;
 575
 576         if (azx_snoop(chip))
 577                 return;
 578         if (!dmab || !dmab->area || !dmab->bytes)
 579                 return;
 580
 581 #ifdef CONFIG_SND_DMA_SGBUF
 582         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 583                 struct snd_sg_buf *sgbuf = dmab->private_data;
 584                 if (on)
 585                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 586                 else
 587                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 588                 return;
 589         }
 590 #endif
 591
 592         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 593         if (on)
 594                 set_memory_wc((unsigned long)dmab->area, pages);
 595         else
 596                 set_memory_wb((unsigned long)dmab->area, pages);
 597 }
 598
 599 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 600                                  bool on)
 601 {
 602         __mark_pages_wc(chip, buf, on);
 603 }
 604 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 605                                    struct snd_pcm_substream *substream, bool on)
 606 {
 607         if (azx_dev->wc_marked != on) {
 608                 __mark_pages_wc(chip, substream->runtime->dma_buffer_p, on);
 609                 azx_dev->wc_marked = on;
 610         }
 611 }
 612 #else
 613 /* NOP for other archs */
 614 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 615                                  bool on)
 616 {
 617 }
 618 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 619                                    struct snd_pcm_substream *substream, bool on)
 620 {
 621 }
 622 #endif
 623
 624 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 625 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 626 /*
 627  * Interface for HD codec
 628  */
 629
 630 /*
 631  * CORB / RIRB interface
 632  */
 633 static int azx_alloc_cmd_io(struct azx *chip)
 634 {
 635         int err;
 636
 637         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 638         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 639                                   snd_dma_pci_data(chip->pci),
 640                                   PAGE_SIZE, &chip->rb);
 641         if (err < 0) {
 642                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 643                 return err;
 644         }
 645         mark_pages_wc(chip, &chip->rb, true);
 646         return 0;
 647 }
 648
 649 static void azx_init_cmd_io(struct azx *chip)
 650 {
 651         spin_lock_irq(&chip->reg_lock);
 652         /* CORB set up */
 653         chip->corb.addr = chip->rb.addr;
 654         chip->corb.buf = (u32 *)chip->rb.area;
 655         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 656         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 657
 658         /* set the corb size to 256 entries (ULI requires explicitly) */
 659         azx_writeb(chip, CORBSIZE, 0x02);
 660         /* set the corb write pointer to 0 */
 661         azx_writew(chip, CORBWP, 0);
 662         /* reset the corb hw read pointer */
 663         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 664         /* enable corb dma */
 665         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 666
 667         /* RIRB set up */
 668         chip->rirb.addr = chip->rb.addr + 2048;
 669         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 670         chip->rirb.wp = chip->rirb.rp = 0;
 671         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 672         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 673         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 674
 675         /* set the rirb size to 256 entries (ULI requires explicitly) */
 676         azx_writeb(chip, RIRBSIZE, 0x02);
 677         /* reset the rirb hw write pointer */
 678         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 679         /* set N=1, get RIRB response interrupt for new entry */
 680         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 681                 azx_writew(chip, RINTCNT, 0xc0);
 682         else
 683                 azx_writew(chip, RINTCNT, 1);
 684         /* enable rirb dma and response irq */
 685         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 686         spin_unlock_irq(&chip->reg_lock);
 687 }
 688
 689 static void azx_free_cmd_io(struct azx *chip)
 690 {
 691         spin_lock_irq(&chip->reg_lock);
 692         /* disable ringbuffer DMAs */
 693         azx_writeb(chip, RIRBCTL, 0);
 694         azx_writeb(chip, CORBCTL, 0);
 695         spin_unlock_irq(&chip->reg_lock);
 696 }
 697
 698 static unsigned int azx_command_addr(u32 cmd)
 699 {
 700         unsigned int addr = cmd >> 28;
 701
 702         if (addr >= AZX_MAX_CODECS) {
 703                 snd_BUG();
 704                 addr = 0;
 705         }
 706
 707         return addr;
 708 }
 709
 710 static unsigned int azx_response_addr(u32 res)
 711 {
 712         unsigned int addr = res & 0xf;
 713
 714         if (addr >= AZX_MAX_CODECS) {
 715                 snd_BUG();
 716                 addr = 0;
 717         }
 718
 719         return addr;
 720 }
 721
 722 /* send a command */
 723 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 724 {
 725         struct azx *chip = bus->private_data;
 726         unsigned int addr = azx_command_addr(val);
 727         unsigned int wp;
 728
 729         spin_lock_irq(&chip->reg_lock);
 730
 731         /* add command to corb */
 732         wp = azx_readb(chip, CORBWP);
 733         wp++;
 734         wp %= ICH6_MAX_CORB_ENTRIES;
 735
 736         chip->rirb.cmds[addr]++;
 737         chip->corb.buf[wp] = cpu_to_le32(val);
 738         azx_writel(chip, CORBWP, wp);
 739
 740         spin_unlock_irq(&chip->reg_lock);
 741
 742         return 0;
 743 }
 744
 745 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 746
 747 /* retrieve RIRB entry - called from interrupt handler */
 748 static void azx_update_rirb(struct azx *chip)
 749 {
 750         unsigned int rp, wp;
 751         unsigned int addr;
 752         u32 res, res_ex;
 753
 754         wp = azx_readb(chip, RIRBWP);
 755         if (wp == chip->rirb.wp)
 756                 return;
 757         chip->rirb.wp = wp;
 758
 759         while (chip->rirb.rp != wp) {
 760                 chip->rirb.rp++;
 761                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 762
 763                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 764                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 765                 res = le32_to_cpu(chip->rirb.buf[rp]);
 766                 addr = azx_response_addr(res_ex);
 767                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 768                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 769                 else if (chip->rirb.cmds[addr]) {
 770                         chip->rirb.res[addr] = res;
 771                         smp_wmb();
 772                         chip->rirb.cmds[addr]--;
 773                 } else
 774                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 775                                    "last cmd=%#08x\n",
 776                                    res, res_ex,
 777                                    chip->last_cmd[addr]);
 778         }
 779 }
 780
 781 /* receive a response */
 782 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 783                                           unsigned int addr)
 784 {
 785         struct azx *chip = bus->private_data;
 786         unsigned long timeout;
 787         unsigned long loopcounter;
 788         int do_poll = 0;
 789
 790  again:
 791         timeout = jiffies + msecs_to_jiffies(1000);
 792
 793         for (loopcounter = 0;; loopcounter++) {
 794                 if (chip->polling_mode || do_poll) {
 795                         spin_lock_irq(&chip->reg_lock);
 796                         azx_update_rirb(chip);
 797                         spin_unlock_irq(&chip->reg_lock);
 798                 }
 799                 if (!chip->rirb.cmds[addr]) {
 800                         smp_rmb();
 801                         bus->rirb_error = 0;
 802
 803                         if (!do_poll)
 804                                 chip->poll_count = 0;
 805                         return chip->rirb.res[addr]; /* the last value */
 806                 }
 807                 if (time_after(jiffies, timeout))
 808                         break;
 809                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 810                         msleep(2); /* temporary workaround */
 811                 else {
 812                         udelay(10);
 813                         cond_resched();
 814                 }
 815         }
 816
 817         if (!chip->polling_mode && chip->poll_count < 2) {
 818                 snd_printdd(SFX "azx_get_response timeout, "
 819                            "polling the codec once: last cmd=0x%08x\n",
 820                            chip->last_cmd[addr]);
 821                 do_poll = 1;
 822                 chip->poll_count++;
 823                 goto again;
 824         }
 825
 826
 827         if (!chip->polling_mode) {
 828                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 829                            "switching to polling mode: last cmd=0x%08x\n",
 830                            chip->last_cmd[addr]);
 831                 chip->polling_mode = 1;
 832                 goto again;
 833         }
 834
 835         if (chip->msi) {
 836                 snd_printk(KERN_WARNING SFX "No response from codec, "
 837                            "disabling MSI: last cmd=0x%08x\n",
 838                            chip->last_cmd[addr]);
 839                 free_irq(chip->irq, chip);
 840                 chip->irq = -1;
 841                 pci_disable_msi(chip->pci);
 842                 chip->msi = 0;
 843                 if (azx_acquire_irq(chip, 1) < 0) {
 844                         bus->rirb_error = 1;
 845                         return -1;
 846                 }
 847                 goto again;
 848         }
 849
 850         if (chip->probing) {
 851                 /* If this critical timeout happens during the codec probing
 852                  * phase, this is likely an access to a non-existing codec
 853                  * slot.  Better to return an error and reset the system.
 854                  */
 855                 return -1;
 856         }
 857
 858         /* a fatal communication error; need either to reset or to fallback
 859          * to the single_cmd mode
 860          */
 861         bus->rirb_error = 1;
 862         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 863                 bus->response_reset = 1;
 864                 return -1; /* give a chance to retry */
 865         }
 866
 867         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 868                    "switching to single_cmd mode: last cmd=0x%08x\n",
 869                    chip->last_cmd[addr]);
 870         chip->single_cmd = 1;
 871         bus->response_reset = 0;
 872         /* release CORB/RIRB */
 873         azx_free_cmd_io(chip);
 874         /* disable unsolicited responses */
 875         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 876         return -1;
 877 }
 878
 879 /*
 880  * Use the single immediate command instead of CORB/RIRB for simplicity
 881  *
 882  * Note: according to Intel, this is not preferred use.  The command was
 883  *       intended for the BIOS only, and may get confused with unsolicited
 884  *       responses.  So, we shouldn't use it for normal operation from the
 885  *       driver.
 886  *       I left the codes, however, for debugging/testing purposes.
 887  */
 888
 889 /* receive a response */
 890 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 891 {
 892         int timeout = 50;
 893
 894         while (timeout--) {
 895                 /* check IRV busy bit */
 896                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 897                         /* reuse rirb.res as the response return value */
 898                         chip->rirb.res[addr] = azx_readl(chip, IR);
 899                         return 0;
 900                 }
 901                 udelay(1);
 902         }
 903         if (printk_ratelimit())
 904                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 905                            azx_readw(chip, IRS));
 906         chip->rirb.res[addr] = -1;
 907         return -EIO;
 908 }
 909
 910 /* send a command */
 911 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 912 {
 913         struct azx *chip = bus->private_data;
 914         unsigned int addr = azx_command_addr(val);
 915         int timeout = 50;
 916
 917         bus->rirb_error = 0;
 918         while (timeout--) {
 919                 /* check ICB busy bit */
 920                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 921                         /* Clear IRV valid bit */
 922                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 923                                    ICH6_IRS_VALID);
 924                         azx_writel(chip, IC, val);
 925                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 926                                    ICH6_IRS_BUSY);
 927                         return azx_single_wait_for_response(chip, addr);
 928                 }
 929                 udelay(1);
 930         }
 931         if (printk_ratelimit())
 932                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 933                            azx_readw(chip, IRS), val);
 934         return -EIO;
 935 }
 936
 937 /* receive a response */
 938 static unsigned int azx_single_get_response(struct hda_bus *bus,
 939                                             unsigned int addr)
 940 {
 941         struct azx *chip = bus->private_data;
 942         return chip->rirb.res[addr];
 943 }
 944
 945 /*
 946  * The below are the main callbacks from hda_codec.
 947  *
 948  * They are just the skeleton to call sub-callbacks according to the
 949  * current setting of chip->single_cmd.
 950  */
 951
 952 /* send a command */
 953 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 954 {
 955         struct azx *chip = bus->private_data;
 956
 957         chip->last_cmd[azx_command_addr(val)] = val;
 958         if (chip->single_cmd)
 959                 return azx_single_send_cmd(bus, val);
 960         else
 961                 return azx_corb_send_cmd(bus, val);
 962 }
 963
 964 /* get a response */
 965 static unsigned int azx_get_response(struct hda_bus *bus,
 966                                      unsigned int addr)
 967 {
 968         struct azx *chip = bus->private_data;
 969         if (chip->single_cmd)
 970                 return azx_single_get_response(bus, addr);
 971         else
 972                 return azx_rirb_get_response(bus, addr);
 973 }
 974
 975 #ifdef CONFIG_SND_HDA_POWER_SAVE
 976 static void azx_power_notify(struct hda_bus *bus);
 977 #endif
 978
 979 /* reset codec link */
 980 static int azx_reset(struct azx *chip, int full_reset)
 981 {
 982         int count;
 983
 984         if (!full_reset)
 985                 goto __skip;
 986
 987         /* clear STATESTS */
 988         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 989
 990         /* reset controller */
 991         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 992
 993         count = 50;
 994         while (azx_readb(chip, GCTL) && --count)
 995                 msleep(1);
 996
 997         /* delay for >= 100us for codec PLL to settle per spec
 998          * Rev 0.9 section 5.5.1
 999          */
1000         msleep(1);
1001
1002         /* Bring controller out of reset */
1003         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1004
1005         count = 50;
1006         while (!azx_readb(chip, GCTL) && --count)
1007                 msleep(1);
1008
1009         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1010         msleep(1);
1011
1012       __skip:
1013         /* check to see if controller is ready */
1014         if (!azx_readb(chip, GCTL)) {
1015                 snd_printd(SFX "azx_reset: controller not ready!\n");
1016                 return -EBUSY;
1017         }
1018
1019         /* Accept unsolicited responses */
1020         if (!chip->single_cmd)
1021                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1022                            ICH6_GCTL_UNSOL);
1023
1024         /* detect codecs */
1025         if (!chip->codec_mask) {
1026                 chip->codec_mask = azx_readw(chip, STATESTS);
1027                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1028         }
1029
1030         return 0;
1031 }
1032
1033
1034 /*
1035  * Lowlevel interface
1036  */
1037
1038 /* enable interrupts */
1039 static void azx_int_enable(struct azx *chip)
1040 {
1041         /* enable controller CIE and GIE */
1042         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1043                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1044 }
1045
1046 /* disable interrupts */
1047 static void azx_int_disable(struct azx *chip)
1048 {
1049         int i;
1050
1051         /* disable interrupts in stream descriptor */
1052         for (i = 0; i < chip->num_streams; i++) {
1053                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1054                 azx_sd_writeb(azx_dev, SD_CTL,
1055                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1056         }
1057
1058         /* disable SIE for all streams */
1059         azx_writeb(chip, INTCTL, 0);
1060
1061         /* disable controller CIE and GIE */
1062         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1063                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1064 }
1065
1066 /* clear interrupts */
1067 static void azx_int_clear(struct azx *chip)
1068 {
1069         int i;
1070
1071         /* clear stream status */
1072         for (i = 0; i < chip->num_streams; i++) {
1073                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1074                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1075         }
1076
1077         /* clear STATESTS */
1078         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1079
1080         /* clear rirb status */
1081         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1082
1083         /* clear int status */
1084         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1085 }
1086
1087 /* start a stream */
1088 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1089 {
1090         /*
1091          * Before stream start, initialize parameter
1092          */
1093         azx_dev->insufficient = 1;
1094
1095         /* enable SIE */
1096         azx_writel(chip, INTCTL,
1097                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1098         /* set DMA start and interrupt mask */
1099         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1100                       SD_CTL_DMA_START | SD_INT_MASK);
1101 }
1102
1103 /* stop DMA */
1104 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1105 {
1106         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1107                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1108         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1109 }
1110
1111 /* stop a stream */
1112 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1113 {
1114         azx_stream_clear(chip, azx_dev);
1115         /* disable SIE */
1116         azx_writel(chip, INTCTL,
1117                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1118 }
1119
1120
1121 /*
1122  * reset and start the controller registers
1123  */
1124 static void azx_init_chip(struct azx *chip, int full_reset)
1125 {
1126         if (chip->initialized)
1127                 return;
1128
1129         /* reset controller */
1130         azx_reset(chip, full_reset);
1131
1132         /* initialize interrupts */
1133         azx_int_clear(chip);
1134         azx_int_enable(chip);
1135
1136         /* initialize the codec command I/O */
1137         if (!chip->single_cmd)
1138                 azx_init_cmd_io(chip);
1139
1140         /* program the position buffer */
1141         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1142         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1143
1144         chip->initialized = 1;
1145 }
1146
1147 /*
1148  * initialize the PCI registers
1149  */
1150 /* update bits in a PCI register byte */
1151 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1152                             unsigned char mask, unsigned char val)
1153 {
1154         unsigned char data;
1155
1156         pci_read_config_byte(pci, reg, &data);
1157         data &= ~mask;
1158         data |= (val & mask);
1159         pci_write_config_byte(pci, reg, data);
1160 }
1161
1162 static void azx_init_pci(struct azx *chip)
1163 {
1164         /* force to non-snoop mode for a new VIA controller when BIOS is set */
1165         if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1166                 u8 snoop;
1167                 pci_read_config_byte(chip->pci, 0x42, &snoop);
1168                 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1169                         chip->snoop = 0;
1170                         snd_printdd(SFX "Force to non-snoop mode\n");
1171                 }
1172         }
1173
1174         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1175          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1176          * Ensuring these bits are 0 clears playback static on some HD Audio
1177          * codecs.
1178          * The PCI register TCSEL is defined in the Intel manuals.
1179          */
1180         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1181                 snd_printdd(SFX "Clearing TCSEL\n");
1182                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1183         }
1184
1185         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1186          * we need to enable snoop.
1187          */
1188         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1189                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1190                 update_pci_byte(chip->pci,
1191                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1192                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1193         }
1194
1195         /* For NVIDIA HDA, enable snoop */
1196         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1197                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1198                 update_pci_byte(chip->pci,
1199                                 NVIDIA_HDA_TRANSREG_ADDR,
1200                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1201                 update_pci_byte(chip->pci,
1202                                 NVIDIA_HDA_ISTRM_COH,
1203                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1204                 update_pci_byte(chip->pci,
1205                                 NVIDIA_HDA_OSTRM_COH,
1206                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1207         }
1208
1209         /* Enable SCH/PCH snoop if needed */
1210         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1211                 unsigned short snoop;
1212                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1213                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1214                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1215                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1216                         if (!azx_snoop(chip))
1217                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1218                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1219                         pci_read_config_word(chip->pci,
1220                                 INTEL_SCH_HDA_DEVC, &snoop);
1221                 }
1222                 snd_printdd(SFX "SCH snoop: %s\n",
1223                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1224                                 ? "Disabled" : "Enabled");
1225         }
1226 }
1227
1228
1229 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1230
1231 /*
1232  * interrupt handler
1233  */
1234 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1235 {
1236         struct azx *chip = dev_id;
1237         struct azx_dev *azx_dev;
1238         u32 status;
1239         u8 sd_status;
1240         int i, ok;
1241
1242         spin_lock(&chip->reg_lock);
1243
1244         status = azx_readl(chip, INTSTS);
1245         if (status == 0) {
1246                 spin_unlock(&chip->reg_lock);
1247                 return IRQ_NONE;
1248         }
1249
1250         for (i = 0; i < chip->num_streams; i++) {
1251                 azx_dev = &chip->azx_dev[i];
1252                 if (status & azx_dev->sd_int_sta_mask) {
1253                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1254                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1255                         if (!azx_dev->substream || !azx_dev->running ||
1256                             !(sd_status & SD_INT_COMPLETE))
1257                                 continue;
1258                         /* check whether this IRQ is really acceptable */
1259                         ok = azx_position_ok(chip, azx_dev);
1260                         if (ok == 1) {
1261                                 azx_dev->irq_pending = 0;
1262                                 spin_unlock(&chip->reg_lock);
1263                                 snd_pcm_period_elapsed(azx_dev->substream);
1264                                 spin_lock(&chip->reg_lock);
1265                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1266                                 /* bogus IRQ, process it later */
1267                                 azx_dev->irq_pending = 1;
1268                                 queue_work(chip->bus->workq,
1269                                            &chip->irq_pending_work);
1270                         }
1271                 }
1272         }
1273
1274         /* clear rirb int */
1275         status = azx_readb(chip, RIRBSTS);
1276         if (status & RIRB_INT_MASK) {
1277                 if (status & RIRB_INT_RESPONSE) {
1278                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1279                                 udelay(80);
1280                         azx_update_rirb(chip);
1281                 }
1282                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1283         }
1284
1285 #if 0
1286         /* clear state status int */
1287         if (azx_readb(chip, STATESTS) & 0x04)
1288                 azx_writeb(chip, STATESTS, 0x04);
1289 #endif
1290         spin_unlock(&chip->reg_lock);
1291
1292         return IRQ_HANDLED;
1293 }
1294
1295
1296 /*
1297  * set up a BDL entry
1298  */
1299 static int setup_bdle(struct snd_pcm_substream *substream,
1300                       struct azx_dev *azx_dev, u32 **bdlp,
1301                       int ofs, int size, int with_ioc)
1302 {
1303         u32 *bdl = *bdlp;
1304
1305         while (size > 0) {
1306                 dma_addr_t addr;
1307                 int chunk;
1308
1309                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1310                         return -EINVAL;
1311
1312                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1313                 /* program the address field of the BDL entry */
1314                 bdl[0] = cpu_to_le32((u32)addr);
1315                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1316                 /* program the size field of the BDL entry */
1317                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1318                 bdl[2] = cpu_to_le32(chunk);
1319                 /* program the IOC to enable interrupt
1320                  * only when the whole fragment is processed
1321                  */
1322                 size -= chunk;
1323                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1324                 bdl += 4;
1325                 azx_dev->frags++;
1326                 ofs += chunk;
1327         }
1328         *bdlp = bdl;
1329         return ofs;
1330 }
1331
1332 /*
1333  * set up BDL entries
1334  */
1335 static int azx_setup_periods(struct azx *chip,
1336                              struct snd_pcm_substream *substream,
1337                              struct azx_dev *azx_dev)
1338 {
1339         u32 *bdl;
1340         int i, ofs, periods, period_bytes;
1341         int pos_adj;
1342
1343         /* reset BDL address */
1344         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1345         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1346
1347         period_bytes = azx_dev->period_bytes;
1348         periods = azx_dev->bufsize / period_bytes;
1349
1350         /* program the initial BDL entries */
1351         bdl = (u32 *)azx_dev->bdl.area;
1352         ofs = 0;
1353         azx_dev->frags = 0;
1354         pos_adj = bdl_pos_adj[chip->dev_index];
1355         if (pos_adj > 0) {
1356                 struct snd_pcm_runtime *runtime = substream->runtime;
1357                 int pos_align = pos_adj;
1358                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1359                 if (!pos_adj)
1360                         pos_adj = pos_align;
1361                 else
1362                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1363                                 pos_align;
1364                 pos_adj = frames_to_bytes(runtime, pos_adj);
1365                 if (pos_adj >= period_bytes) {
1366                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1367                                    bdl_pos_adj[chip->dev_index]);
1368                         pos_adj = 0;
1369                 } else {
1370                         ofs = setup_bdle(substream, azx_dev,
1371                                          &bdl, ofs, pos_adj,
1372                                          !substream->runtime->no_period_wakeup);
1373                         if (ofs < 0)
1374                                 goto error;
1375                 }
1376         } else
1377                 pos_adj = 0;
1378         for (i = 0; i < periods; i++) {
1379                 if (i == periods - 1 && pos_adj)
1380                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1381                                          period_bytes - pos_adj, 0);
1382                 else
1383                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1384                                          period_bytes,
1385                                          !substream->runtime->no_period_wakeup);
1386                 if (ofs < 0)
1387                         goto error;
1388         }
1389         return 0;
1390
1391  error:
1392         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1393                    azx_dev->bufsize, period_bytes);
1394         return -EINVAL;
1395 }
1396
1397 /* reset stream */
1398 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1399 {
1400         unsigned char val;
1401         int timeout;
1402
1403         azx_stream_clear(chip, azx_dev);
1404
1405         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1406                       SD_CTL_STREAM_RESET);
1407         udelay(3);
1408         timeout = 300;
1409         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1410                --timeout)
1411                 ;
1412         val &= ~SD_CTL_STREAM_RESET;
1413         azx_sd_writeb(azx_dev, SD_CTL, val);
1414         udelay(3);
1415
1416         timeout = 300;
1417         /* waiting for hardware to report that the stream is out of reset */
1418         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1419                --timeout)
1420                 ;
1421
1422         /* reset first position - may not be synced with hw at this time */
1423         *azx_dev->posbuf = 0;
1424 }
1425
1426 /*
1427  * set up the SD for streaming
1428  */
1429 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1430 {
1431         unsigned int val;
1432         /* make sure the run bit is zero for SD */
1433         azx_stream_clear(chip, azx_dev);
1434         /* program the stream_tag */
1435         val = azx_sd_readl(azx_dev, SD_CTL);
1436         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1437                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1438         if (!azx_snoop(chip))
1439                 val |= SD_CTL_TRAFFIC_PRIO;
1440         azx_sd_writel(azx_dev, SD_CTL, val);
1441
1442         /* program the length of samples in cyclic buffer */
1443         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1444
1445         /* program the stream format */
1446         /* this value needs to be the same as the one programmed */
1447         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1448
1449         /* program the stream LVI (last valid index) of the BDL */
1450         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1451
1452         /* program the BDL address */
1453         /* lower BDL address */
1454         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1455         /* upper BDL address */
1456         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1457
1458         /* enable the position buffer */
1459         if (chip->position_fix[0] != POS_FIX_LPIB ||
1460             chip->position_fix[1] != POS_FIX_LPIB) {
1461                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1462                         azx_writel(chip, DPLBASE,
1463                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1464         }
1465
1466         /* set the interrupt enable bits in the descriptor control register */
1467         azx_sd_writel(azx_dev, SD_CTL,
1468                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1469
1470         return 0;
1471 }
1472
1473 /*
1474  * Probe the given codec address
1475  */
1476 static int probe_codec(struct azx *chip, int addr)
1477 {
1478         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1479                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1480         unsigned int res;
1481
1482         mutex_lock(&chip->bus->cmd_mutex);
1483         chip->probing = 1;
1484         azx_send_cmd(chip->bus, cmd);
1485         res = azx_get_response(chip->bus, addr);
1486         chip->probing = 0;
1487         mutex_unlock(&chip->bus->cmd_mutex);
1488         if (res == -1)
1489                 return -EIO;
1490         snd_printdd(SFX "codec #%d probed OK\n", addr);
1491         return 0;
1492 }
1493
1494 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1495                                  struct hda_pcm *cpcm);
1496 static void azx_stop_chip(struct azx *chip);
1497
1498 static void azx_bus_reset(struct hda_bus *bus)
1499 {
1500         struct azx *chip = bus->private_data;
1501
1502         bus->in_reset = 1;
1503         azx_stop_chip(chip);
1504         azx_init_chip(chip, 1);
1505 #ifdef CONFIG_PM
1506         if (chip->initialized) {
1507                 int i;
1508
1509                 for (i = 0; i < HDA_MAX_PCMS; i++)
1510                         snd_pcm_suspend_all(chip->pcm[i]);
1511                 snd_hda_suspend(chip->bus);
1512                 snd_hda_resume(chip->bus);
1513         }
1514 #endif
1515         bus->in_reset = 0;
1516 }
1517
1518 /*
1519  * Codec initialization
1520  */
1521
1522 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1523 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1524         [AZX_DRIVER_NVIDIA] = 8,
1525         [AZX_DRIVER_TERA] = 1,
1526 };
1527
1528 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1529 {
1530         struct hda_bus_template bus_temp;
1531         int c, codecs, err;
1532         int max_slots;
1533
1534         memset(&bus_temp, 0, sizeof(bus_temp));
1535         bus_temp.private_data = chip;
1536         bus_temp.modelname = model;
1537         bus_temp.pci = chip->pci;
1538         bus_temp.ops.command = azx_send_cmd;
1539         bus_temp.ops.get_response = azx_get_response;
1540         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1541         bus_temp.ops.bus_reset = azx_bus_reset;
1542 #ifdef CONFIG_SND_HDA_POWER_SAVE
1543         bus_temp.power_save = &power_save;
1544         bus_temp.ops.pm_notify = azx_power_notify;
1545 #endif
1546
1547         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1548         if (err < 0)
1549                 return err;
1550
1551         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1552                 snd_printd(SFX "Enable delay in RIRB handling\n");
1553                 chip->bus->needs_damn_long_delay = 1;
1554         }
1555
1556         codecs = 0;
1557         max_slots = azx_max_codecs[chip->driver_type];
1558         if (!max_slots)
1559                 max_slots = AZX_DEFAULT_CODECS;
1560
1561         /* First try to probe all given codec slots */
1562         for (c = 0; c < max_slots; c++) {
1563                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1564                         if (probe_codec(chip, c) < 0) {
1565                                 /* Some BIOSen give you wrong codec addresses
1566                                  * that don't exist
1567                                  */
1568                                 snd_printk(KERN_WARNING SFX
1569                                            "Codec #%d probe error; "
1570                                            "disabling it...\n", c);
1571                                 chip->codec_mask &= ~(1 << c);
1572                                 /* More badly, accessing to a non-existing
1573                                  * codec often screws up the controller chip,
1574                                  * and disturbs the further communications.
1575                                  * Thus if an error occurs during probing,
1576                                  * better to reset the controller chip to
1577                                  * get back to the sanity state.
1578                                  */
1579                                 azx_stop_chip(chip);
1580                                 azx_init_chip(chip, 1);
1581                         }
1582                 }
1583         }
1584
1585         /* AMD chipsets often cause the communication stalls upon certain
1586          * sequence like the pin-detection.  It seems that forcing the synced
1587          * access works around the stall.  Grrr...
1588          */
1589         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1590                 snd_printd(SFX "Enable sync_write for stable communication\n");
1591                 chip->bus->sync_write = 1;
1592                 chip->bus->allow_bus_reset = 1;
1593         }
1594
1595         /* Then create codec instances */
1596         for (c = 0; c < max_slots; c++) {
1597                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1598                         struct hda_codec *codec;
1599                         err = snd_hda_codec_new(chip->bus, c, &codec);
1600                         if (err < 0)
1601                                 continue;
1602                         codec->beep_mode = chip->beep_mode;
1603                         codecs++;
1604                 }
1605         }
1606         if (!codecs) {
1607                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1608                 return -ENXIO;
1609         }
1610         return 0;
1611 }
1612
1613 /* configure each codec instance */
1614 static int __devinit azx_codec_configure(struct azx *chip)
1615 {
1616         struct hda_codec *codec;
1617         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1618                 snd_hda_codec_configure(codec);
1619         }
1620         return 0;
1621 }
1622
1623
1624 /*
1625  * PCM support
1626  */
1627
1628 /* assign a stream for the PCM */
1629 static inline struct azx_dev *
1630 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1631 {
1632         int dev, i, nums;
1633         struct azx_dev *res = NULL;
1634         /* make a non-zero unique key for the substream */
1635         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1636                 (substream->stream + 1);
1637
1638         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1639                 dev = chip->playback_index_offset;
1640                 nums = chip->playback_streams;
1641         } else {
1642                 dev = chip->capture_index_offset;
1643                 nums = chip->capture_streams;
1644         }
1645         for (i = 0; i < nums; i++, dev++)
1646                 if (!chip->azx_dev[dev].opened) {
1647                         res = &chip->azx_dev[dev];
1648                         if (res->assigned_key == key)
1649                                 break;
1650                 }
1651         if (res) {
1652                 res->opened = 1;
1653                 res->assigned_key = key;
1654         }
1655         return res;
1656 }
1657
1658 /* release the assigned stream */
1659 static inline void azx_release_device(struct azx_dev *azx_dev)
1660 {
1661         azx_dev->opened = 0;
1662 }
1663
1664 static struct snd_pcm_hardware azx_pcm_hw = {
1665         .info =                 (SNDRV_PCM_INFO_MMAP |
1666                                  SNDRV_PCM_INFO_INTERLEAVED |
1667                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1668                                  SNDRV_PCM_INFO_MMAP_VALID |
1669                                  /* No full-resume yet implemented */
1670                                  /* SNDRV_PCM_INFO_RESUME |*/
1671                                  SNDRV_PCM_INFO_PAUSE |
1672                                  SNDRV_PCM_INFO_SYNC_START |
1673                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1674         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1675         .rates =                SNDRV_PCM_RATE_48000,
1676         .rate_min =             48000,
1677         .rate_max =             48000,
1678         .channels_min =         2,
1679         .channels_max =         2,
1680         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1681         .period_bytes_min =     128,
1682         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1683         .periods_min =          2,
1684         .periods_max =          AZX_MAX_FRAG,
1685         .fifo_size =            0,
1686 };
1687
1688 struct azx_pcm {
1689         struct azx *chip;
1690         struct hda_codec *codec;
1691         struct hda_pcm_stream *hinfo[2];
1692 };
1693
1694 static int azx_pcm_open(struct snd_pcm_substream *substream)
1695 {
1696         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1697         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1698         struct azx *chip = apcm->chip;
1699         struct azx_dev *azx_dev;
1700         struct snd_pcm_runtime *runtime = substream->runtime;
1701         unsigned long flags;
1702         int err;
1703         int buff_step;
1704
1705         mutex_lock(&chip->open_mutex);
1706         azx_dev = azx_assign_device(chip, substream);
1707         if (azx_dev == NULL) {
1708                 mutex_unlock(&chip->open_mutex);
1709                 return -EBUSY;
1710         }
1711         runtime->hw = azx_pcm_hw;
1712         runtime->hw.channels_min = hinfo->channels_min;
1713         runtime->hw.channels_max = hinfo->channels_max;
1714         runtime->hw.formats = hinfo->formats;
1715         runtime->hw.rates = hinfo->rates;
1716         snd_pcm_limit_hw_rates(runtime);
1717         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1718         if (chip->align_buffer_size)
1719                 /* constrain buffer sizes to be multiple of 128
1720                    bytes. This is more efficient in terms of memory
1721                    access but isn't required by the HDA spec and
1722                    prevents users from specifying exact period/buffer
1723                    sizes. For example for 44.1kHz, a period size set
1724                    to 20ms will be rounded to 19.59ms. */
1725                 buff_step = 128;
1726         else
1727                 /* Don't enforce steps on buffer sizes, still need to
1728                    be multiple of 4 bytes (HDA spec). Tested on Intel
1729                    HDA controllers, may not work on all devices where
1730                    option needs to be disabled */
1731                 buff_step = 4;
1732
1733         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1734                                    buff_step);
1735         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1736                                    buff_step);
1737         snd_hda_power_up(apcm->codec);
1738         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1739         if (err < 0) {
1740                 azx_release_device(azx_dev);
1741                 snd_hda_power_down(apcm->codec);
1742                 mutex_unlock(&chip->open_mutex);
1743                 return err;
1744         }
1745         snd_pcm_limit_hw_rates(runtime);
1746         /* sanity check */
1747         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1748             snd_BUG_ON(!runtime->hw.channels_max) ||
1749             snd_BUG_ON(!runtime->hw.formats) ||
1750             snd_BUG_ON(!runtime->hw.rates)) {
1751                 azx_release_device(azx_dev);
1752                 hinfo->ops.close(hinfo, apcm->codec, substream);
1753                 snd_hda_power_down(apcm->codec);
1754                 mutex_unlock(&chip->open_mutex);
1755                 return -EINVAL;
1756         }
1757         spin_lock_irqsave(&chip->reg_lock, flags);
1758         azx_dev->substream = substream;
1759         azx_dev->running = 0;
1760         spin_unlock_irqrestore(&chip->reg_lock, flags);
1761
1762         runtime->private_data = azx_dev;
1763         snd_pcm_set_sync(substream);
1764         mutex_unlock(&chip->open_mutex);
1765         return 0;
1766 }
1767
1768 static int azx_pcm_close(struct snd_pcm_substream *substream)
1769 {
1770         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1771         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1772         struct azx *chip = apcm->chip;
1773         struct azx_dev *azx_dev = get_azx_dev(substream);
1774         unsigned long flags;
1775
1776         mutex_lock(&chip->open_mutex);
1777         spin_lock_irqsave(&chip->reg_lock, flags);
1778         azx_dev->substream = NULL;
1779         azx_dev->running = 0;
1780         spin_unlock_irqrestore(&chip->reg_lock, flags);
1781         azx_release_device(azx_dev);
1782         hinfo->ops.close(hinfo, apcm->codec, substream);
1783         snd_hda_power_down(apcm->codec);
1784         mutex_unlock(&chip->open_mutex);
1785         return 0;
1786 }
1787
1788 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1789                              struct snd_pcm_hw_params *hw_params)
1790 {
1791         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1792         struct azx *chip = apcm->chip;
1793         struct azx_dev *azx_dev = get_azx_dev(substream);
1794         int ret;
1795
1796         mark_runtime_wc(chip, azx_dev, substream, false);
1797         azx_dev->bufsize = 0;
1798         azx_dev->period_bytes = 0;
1799         azx_dev->format_val = 0;
1800         ret = snd_pcm_lib_malloc_pages(substream,
1801                                         params_buffer_bytes(hw_params));
1802         if (ret < 0)
1803                 return ret;
1804         mark_runtime_wc(chip, azx_dev, substream, true);
1805         return ret;
1806 }
1807
1808 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1809 {
1810         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1811         struct azx_dev *azx_dev = get_azx_dev(substream);
1812         struct azx *chip = apcm->chip;
1813         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1814
1815         /* reset BDL address */
1816         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1817         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1818         azx_sd_writel(azx_dev, SD_CTL, 0);
1819         azx_dev->bufsize = 0;
1820         azx_dev->period_bytes = 0;
1821         azx_dev->format_val = 0;
1822
1823         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1824
1825         mark_runtime_wc(chip, azx_dev, substream, false);
1826         return snd_pcm_lib_free_pages(substream);
1827 }
1828
1829 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1830 {
1831         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1832         struct azx *chip = apcm->chip;
1833         struct azx_dev *azx_dev = get_azx_dev(substream);
1834         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1835         struct snd_pcm_runtime *runtime = substream->runtime;
1836         unsigned int bufsize, period_bytes, format_val, stream_tag;
1837         int err;
1838         struct hda_spdif_out *spdif =
1839                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1840         unsigned short ctls = spdif ? spdif->ctls : 0;
1841
1842         azx_stream_reset(chip, azx_dev);
1843         format_val = snd_hda_calc_stream_format(runtime->rate,
1844                                                 runtime->channels,
1845                                                 runtime->format,
1846                                                 hinfo->maxbps,
1847                                                 ctls);
1848         if (!format_val) {
1849                 snd_printk(KERN_ERR SFX
1850                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1851                            runtime->rate, runtime->channels, runtime->format);
1852                 return -EINVAL;
1853         }
1854
1855         bufsize = snd_pcm_lib_buffer_bytes(substream);
1856         period_bytes = snd_pcm_lib_period_bytes(substream);
1857
1858         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1859                     bufsize, format_val);
1860
1861         if (bufsize != azx_dev->bufsize ||
1862             period_bytes != azx_dev->period_bytes ||
1863             format_val != azx_dev->format_val) {
1864                 azx_dev->bufsize = bufsize;
1865                 azx_dev->period_bytes = period_bytes;
1866                 azx_dev->format_val = format_val;
1867                 err = azx_setup_periods(chip, substream, azx_dev);
1868                 if (err < 0)
1869                         return err;
1870         }
1871
1872         /* wallclk has 24Mhz clock source */
1873         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1874                                                 runtime->rate) * 1000);
1875         azx_setup_controller(chip, azx_dev);
1876         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1877                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1878         else
1879                 azx_dev->fifo_size = 0;
1880
1881         stream_tag = azx_dev->stream_tag;
1882         /* CA-IBG chips need the playback stream starting from 1 */
1883         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1884             stream_tag > chip->capture_streams)
1885                 stream_tag -= chip->capture_streams;
1886         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1887                                      azx_dev->format_val, substream);
1888 }
1889
1890 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1891 {
1892         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1893         struct azx *chip = apcm->chip;
1894         struct azx_dev *azx_dev;
1895         struct snd_pcm_substream *s;
1896         int rstart = 0, start, nsync = 0, sbits = 0;
1897         int nwait, timeout;
1898
1899         switch (cmd) {
1900         case SNDRV_PCM_TRIGGER_START:
1901                 rstart = 1;
1902         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1903         case SNDRV_PCM_TRIGGER_RESUME:
1904                 start = 1;
1905                 break;
1906         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1907         case SNDRV_PCM_TRIGGER_SUSPEND:
1908         case SNDRV_PCM_TRIGGER_STOP:
1909                 start = 0;
1910                 break;
1911         default:
1912                 return -EINVAL;
1913         }
1914
1915         snd_pcm_group_for_each_entry(s, substream) {
1916                 if (s->pcm->card != substream->pcm->card)
1917                         continue;
1918                 azx_dev = get_azx_dev(s);
1919                 sbits |= 1 << azx_dev->index;
1920                 nsync++;
1921                 snd_pcm_trigger_done(s, substream);
1922         }
1923
1924         spin_lock(&chip->reg_lock);
1925         if (nsync > 1) {
1926                 /* first, set SYNC bits of corresponding streams */
1927                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1928                         azx_writel(chip, OLD_SSYNC,
1929                                    azx_readl(chip, OLD_SSYNC) | sbits);
1930                 else
1931                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1932         }
1933         snd_pcm_group_for_each_entry(s, substream) {
1934                 if (s->pcm->card != substream->pcm->card)
1935                         continue;
1936                 azx_dev = get_azx_dev(s);
1937                 if (start) {
1938                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1939                         if (!rstart)
1940                                 azx_dev->start_wallclk -=
1941                                                 azx_dev->period_wallclk;
1942                         azx_stream_start(chip, azx_dev);
1943                 } else {
1944                         azx_stream_stop(chip, azx_dev);
1945                 }
1946                 azx_dev->running = start;
1947         }
1948         spin_unlock(&chip->reg_lock);
1949         if (start) {
1950                 if (nsync == 1)
1951                         return 0;
1952                 /* wait until all FIFOs get ready */
1953                 for (timeout = 5000; timeout; timeout--) {
1954                         nwait = 0;
1955                         snd_pcm_group_for_each_entry(s, substream) {
1956                                 if (s->pcm->card != substream->pcm->card)
1957                                         continue;
1958                                 azx_dev = get_azx_dev(s);
1959                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1960                                       SD_STS_FIFO_READY))
1961                                         nwait++;
1962                         }
1963                         if (!nwait)
1964                                 break;
1965                         cpu_relax();
1966                 }
1967         } else {
1968                 /* wait until all RUN bits are cleared */
1969                 for (timeout = 5000; timeout; timeout--) {
1970                         nwait = 0;
1971                         snd_pcm_group_for_each_entry(s, substream) {
1972                                 if (s->pcm->card != substream->pcm->card)
1973                                         continue;
1974                                 azx_dev = get_azx_dev(s);
1975                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1976                                     SD_CTL_DMA_START)
1977                                         nwait++;
1978                         }
1979                         if (!nwait)
1980                                 break;
1981                         cpu_relax();
1982                 }
1983         }
1984         if (nsync > 1) {
1985                 spin_lock(&chip->reg_lock);
1986                 /* reset SYNC bits */
1987                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1988                         azx_writel(chip, OLD_SSYNC,
1989                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1990                 else
1991                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1992                 spin_unlock(&chip->reg_lock);
1993         }
1994         return 0;
1995 }
1996
1997 /* get the current DMA position with correction on VIA chips */
1998 static unsigned int azx_via_get_position(struct azx *chip,
1999                                          struct azx_dev *azx_dev)
2000 {
2001         unsigned int link_pos, mini_pos, bound_pos;
2002         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2003         unsigned int fifo_size;
2004
2005         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2006         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2007                 /* Playback, no problem using link position */
2008                 return link_pos;
2009         }
2010
2011         /* Capture */
2012         /* For new chipset,
2013          * use mod to get the DMA position just like old chipset
2014          */
2015         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2016         mod_dma_pos %= azx_dev->period_bytes;
2017
2018         /* azx_dev->fifo_size can't get FIFO size of in stream.
2019          * Get from base address + offset.
2020          */
2021         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2022
2023         if (azx_dev->insufficient) {
2024                 /* Link position never gather than FIFO size */
2025                 if (link_pos <= fifo_size)
2026                         return 0;
2027
2028                 azx_dev->insufficient = 0;
2029         }
2030
2031         if (link_pos <= fifo_size)
2032                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2033         else
2034                 mini_pos = link_pos - fifo_size;
2035
2036         /* Find nearest previous boudary */
2037         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2038         mod_link_pos = link_pos % azx_dev->period_bytes;
2039         if (mod_link_pos >= fifo_size)
2040                 bound_pos = link_pos - mod_link_pos;
2041         else if (mod_dma_pos >= mod_mini_pos)
2042                 bound_pos = mini_pos - mod_mini_pos;
2043         else {
2044                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2045                 if (bound_pos >= azx_dev->bufsize)
2046                         bound_pos = 0;
2047         }
2048
2049         /* Calculate real DMA position we want */
2050         return bound_pos + mod_dma_pos;
2051 }
2052
2053 static unsigned int azx_get_position(struct azx *chip,
2054                                      struct azx_dev *azx_dev,
2055                                      bool with_check)
2056 {
2057         unsigned int pos;
2058         int stream = azx_dev->substream->stream;
2059
2060         switch (chip->position_fix[stream]) {
2061         case POS_FIX_LPIB:
2062                 /* read LPIB */
2063                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2064                 break;
2065         case POS_FIX_VIACOMBO:
2066                 pos = azx_via_get_position(chip, azx_dev);
2067                 break;
2068         default:
2069                 /* use the position buffer */
2070                 pos = le32_to_cpu(*azx_dev->posbuf);
2071                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2072                         if (!pos || pos == (u32)-1) {
2073                                 printk(KERN_WARNING
2074                                        "hda-intel: Invalid position buffer, "
2075                                        "using LPIB read method instead.\n");
2076                                 chip->position_fix[stream] = POS_FIX_LPIB;
2077                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2078                         } else
2079                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2080                 }
2081                 break;
2082         }
2083
2084         if (pos >= azx_dev->bufsize)
2085                 pos = 0;
2086         return pos;
2087 }
2088
2089 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2090 {
2091         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2092         struct azx *chip = apcm->chip;
2093         struct azx_dev *azx_dev = get_azx_dev(substream);
2094         return bytes_to_frames(substream->runtime,
2095                                azx_get_position(chip, azx_dev, false));
2096 }
2097
2098 /*
2099  * Check whether the current DMA position is acceptable for updating
2100  * periods.  Returns non-zero if it's OK.
2101  *
2102  * Many HD-audio controllers appear pretty inaccurate about
2103  * the update-IRQ timing.  The IRQ is issued before actually the
2104  * data is processed.  So, we need to process it afterwords in a
2105  * workqueue.
2106  */
2107 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2108 {
2109         u32 wallclk;
2110         unsigned int pos;
2111         int stream;
2112
2113         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2114         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2115                 return -1;      /* bogus (too early) interrupt */
2116
2117         stream = azx_dev->substream->stream;
2118         pos = azx_get_position(chip, azx_dev, true);
2119
2120         if (WARN_ONCE(!azx_dev->period_bytes,
2121                       "hda-intel: zero azx_dev->period_bytes"))
2122                 return -1; /* this shouldn't happen! */
2123         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2124             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2125                 /* NG - it's below the first next period boundary */
2126                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2127         azx_dev->start_wallclk += wallclk;
2128         return 1; /* OK, it's fine */
2129 }
2130
2131 /*
2132  * The work for pending PCM period updates.
2133  */
2134 static void azx_irq_pending_work(struct work_struct *work)
2135 {
2136         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2137         int i, pending, ok;
2138
2139         if (!chip->irq_pending_warned) {
2140                 printk(KERN_WARNING
2141                        "hda-intel: IRQ timing workaround is activated "
2142                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2143                        chip->card->number);
2144                 chip->irq_pending_warned = 1;
2145         }
2146
2147         for (;;) {
2148                 pending = 0;
2149                 spin_lock_irq(&chip->reg_lock);
2150                 for (i = 0; i < chip->num_streams; i++) {
2151                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2152                         if (!azx_dev->irq_pending ||
2153                             !azx_dev->substream ||
2154                             !azx_dev->running)
2155                                 continue;
2156                         ok = azx_position_ok(chip, azx_dev);
2157                         if (ok > 0) {
2158                                 azx_dev->irq_pending = 0;
2159                                 spin_unlock(&chip->reg_lock);
2160                                 snd_pcm_period_elapsed(azx_dev->substream);
2161                                 spin_lock(&chip->reg_lock);
2162                         } else if (ok < 0) {
2163                                 pending = 0;    /* too early */
2164                         } else
2165                                 pending++;
2166                 }
2167                 spin_unlock_irq(&chip->reg_lock);
2168                 if (!pending)
2169                         return;
2170                 msleep(1);
2171         }
2172 }
2173
2174 /* clear irq_pending flags and assure no on-going workq */
2175 static void azx_clear_irq_pending(struct azx *chip)
2176 {
2177         int i;
2178
2179         spin_lock_irq(&chip->reg_lock);
2180         for (i = 0; i < chip->num_streams; i++)
2181                 chip->azx_dev[i].irq_pending = 0;
2182         spin_unlock_irq(&chip->reg_lock);
2183 }
2184
2185 #ifdef CONFIG_X86
2186 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2187                         struct vm_area_struct *area)
2188 {
2189         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2190         struct azx *chip = apcm->chip;
2191         if (!azx_snoop(chip))
2192                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2193         return snd_pcm_lib_default_mmap(substream, area);
2194 }
2195 #else
2196 #define azx_pcm_mmap    NULL
2197 #endif
2198
2199 static struct snd_pcm_ops azx_pcm_ops = {
2200         .open = azx_pcm_open,
2201         .close = azx_pcm_close,
2202         .ioctl = snd_pcm_lib_ioctl,
2203         .hw_params = azx_pcm_hw_params,
2204         .hw_free = azx_pcm_hw_free,
2205         .prepare = azx_pcm_prepare,
2206         .trigger = azx_pcm_trigger,
2207         .pointer = azx_pcm_pointer,
2208         .mmap = azx_pcm_mmap,
2209         .page = snd_pcm_sgbuf_ops_page,
2210 };
2211
2212 static void azx_pcm_free(struct snd_pcm *pcm)
2213 {
2214         struct azx_pcm *apcm = pcm->private_data;
2215         if (apcm) {
2216                 apcm->chip->pcm[pcm->device] = NULL;
2217                 kfree(apcm);
2218         }
2219 }
2220
2221 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2222
2223 static int
2224 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2225                       struct hda_pcm *cpcm)
2226 {
2227         struct azx *chip = bus->private_data;
2228         struct snd_pcm *pcm;
2229         struct azx_pcm *apcm;
2230         int pcm_dev = cpcm->device;
2231         unsigned int size;
2232         int s, err;
2233
2234         if (pcm_dev >= HDA_MAX_PCMS) {
2235                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2236                            pcm_dev);
2237                 return -EINVAL;
2238         }
2239         if (chip->pcm[pcm_dev]) {
2240                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2241                 return -EBUSY;
2242         }
2243         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2244                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2245                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2246                           &pcm);
2247         if (err < 0)
2248                 return err;
2249         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2250         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2251         if (apcm == NULL)
2252                 return -ENOMEM;
2253         apcm->chip = chip;
2254         apcm->codec = codec;
2255         pcm->private_data = apcm;
2256         pcm->private_free = azx_pcm_free;
2257         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2258                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2259         chip->pcm[pcm_dev] = pcm;
2260         cpcm->pcm = pcm;
2261         for (s = 0; s < 2; s++) {
2262                 apcm->hinfo[s] = &cpcm->stream[s];
2263                 if (cpcm->stream[s].substreams)
2264                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2265         }
2266         /* buffer pre-allocation */
2267         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2268         if (size > MAX_PREALLOC_SIZE)
2269                 size = MAX_PREALLOC_SIZE;
2270         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2271                                               snd_dma_pci_data(chip->pci),
2272                                               size, MAX_PREALLOC_SIZE);
2273         return 0;
2274 }
2275
2276 /*
2277  * mixer creation - all stuff is implemented in hda module
2278  */
2279 static int __devinit azx_mixer_create(struct azx *chip)
2280 {
2281         return snd_hda_build_controls(chip->bus);
2282 }
2283
2284
2285 /*
2286  * initialize SD streams
2287  */
2288 static int __devinit azx_init_stream(struct azx *chip)
2289 {
2290         int i;
2291
2292         /* initialize each stream (aka device)
2293          * assign the starting bdl address to each stream (device)
2294          * and initialize
2295          */
2296         for (i = 0; i < chip->num_streams; i++) {
2297                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2298                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2299                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2300                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2301                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2302                 azx_dev->sd_int_sta_mask = 1 << i;
2303                 /* stream tag: must be non-zero and unique */
2304                 azx_dev->index = i;
2305                 azx_dev->stream_tag = i + 1;
2306         }
2307
2308         return 0;
2309 }
2310
2311 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2312 {
2313         if (request_irq(chip->pci->irq, azx_interrupt,
2314                         chip->msi ? 0 : IRQF_SHARED,
2315                         KBUILD_MODNAME, chip)) {
2316                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2317                        "disabling device\n", chip->pci->irq);
2318                 if (do_disconnect)
2319                         snd_card_disconnect(chip->card);
2320                 return -1;
2321         }
2322         chip->irq = chip->pci->irq;
2323         pci_intx(chip->pci, !chip->msi);
2324         return 0;
2325 }
2326
2327
2328 static void azx_stop_chip(struct azx *chip)
2329 {
2330         if (!chip->initialized)
2331                 return;
2332
2333         /* disable interrupts */
2334         azx_int_disable(chip);
2335         azx_int_clear(chip);
2336
2337         /* disable CORB/RIRB */
2338         azx_free_cmd_io(chip);
2339
2340         /* disable position buffer */
2341         azx_writel(chip, DPLBASE, 0);
2342         azx_writel(chip, DPUBASE, 0);
2343
2344         chip->initialized = 0;
2345 }
2346
2347 #ifdef CONFIG_SND_HDA_POWER_SAVE
2348 /* power-up/down the controller */
2349 static void azx_power_notify(struct hda_bus *bus)
2350 {
2351         struct azx *chip = bus->private_data;
2352         struct hda_codec *c;
2353         int power_on = 0;
2354
2355         list_for_each_entry(c, &bus->codec_list, list) {
2356                 if (c->power_on) {
2357                         power_on = 1;
2358                         break;
2359                 }
2360         }
2361         if (power_on)
2362                 azx_init_chip(chip, 1);
2363         else if (chip->running && power_save_controller &&
2364                  !bus->power_keep_link_on)
2365                 azx_stop_chip(chip);
2366 }
2367 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2368
2369 #ifdef CONFIG_PM
2370 /*
2371  * power management
2372  */
2373
2374 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2375 {
2376         struct hda_codec *codec;
2377
2378         list_for_each_entry(codec, &bus->codec_list, list) {
2379                 if (snd_hda_codec_needs_resume(codec))
2380                         return 1;
2381         }
2382         return 0;
2383 }
2384
2385 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2386 {
2387         struct snd_card *card = pci_get_drvdata(pci);
2388         struct azx *chip = card->private_data;
2389         int i;
2390
2391         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2392         azx_clear_irq_pending(chip);
2393         for (i = 0; i < HDA_MAX_PCMS; i++)
2394                 snd_pcm_suspend_all(chip->pcm[i]);
2395         if (chip->initialized)
2396                 snd_hda_suspend(chip->bus);
2397         azx_stop_chip(chip);
2398         if (chip->irq >= 0) {
2399                 free_irq(chip->irq, chip);
2400                 chip->irq = -1;
2401         }
2402         if (chip->msi)
2403                 pci_disable_msi(chip->pci);
2404         pci_disable_device(pci);
2405         pci_save_state(pci);
2406         pci_set_power_state(pci, pci_choose_state(pci, state));
2407         return 0;
2408 }
2409
2410 static int azx_resume(struct pci_dev *pci)
2411 {
2412         struct snd_card *card = pci_get_drvdata(pci);
2413         struct azx *chip = card->private_data;
2414
2415         pci_set_power_state(pci, PCI_D0);
2416         pci_restore_state(pci);
2417         if (pci_enable_device(pci) < 0) {
2418                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2419                        "disabling device\n");
2420                 snd_card_disconnect(card);
2421                 return -EIO;
2422         }
2423         pci_set_master(pci);
2424         if (chip->msi)
2425                 if (pci_enable_msi(pci) < 0)
2426                         chip->msi = 0;
2427         if (azx_acquire_irq(chip, 1) < 0)
2428                 return -EIO;
2429         azx_init_pci(chip);
2430
2431         if (snd_hda_codecs_inuse(chip->bus))
2432                 azx_init_chip(chip, 1);
2433
2434         snd_hda_resume(chip->bus);
2435         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2436         return 0;
2437 }
2438 #endif /* CONFIG_PM */
2439
2440
2441 /*
2442  * reboot notifier for hang-up problem at power-down
2443  */
2444 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2445 {
2446         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2447         snd_hda_bus_reboot_notify(chip->bus);
2448         azx_stop_chip(chip);
2449         return NOTIFY_OK;
2450 }
2451
2452 static void azx_notifier_register(struct azx *chip)
2453 {
2454         chip->reboot_notifier.notifier_call = azx_halt;
2455         register_reboot_notifier(&chip->reboot_notifier);
2456 }
2457
2458 static void azx_notifier_unregister(struct azx *chip)
2459 {
2460         if (chip->reboot_notifier.notifier_call)
2461                 unregister_reboot_notifier(&chip->reboot_notifier);
2462 }
2463
2464 /*
2465  * destructor
2466  */
2467 static int azx_free(struct azx *chip)
2468 {
2469         int i;
2470
2471         azx_notifier_unregister(chip);
2472
2473         if (chip->initialized) {
2474                 azx_clear_irq_pending(chip);
2475                 for (i = 0; i < chip->num_streams; i++)
2476                         azx_stream_stop(chip, &chip->azx_dev[i]);
2477                 azx_stop_chip(chip);
2478         }
2479
2480         if (chip->irq >= 0)
2481                 free_irq(chip->irq, (void*)chip);
2482         if (chip->msi)
2483                 pci_disable_msi(chip->pci);
2484         if (chip->remap_addr)
2485                 iounmap(chip->remap_addr);
2486
2487         if (chip->azx_dev) {
2488                 for (i = 0; i < chip->num_streams; i++)
2489                         if (chip->azx_dev[i].bdl.area) {
2490                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2491                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2492                         }
2493         }
2494         if (chip->rb.area) {
2495                 mark_pages_wc(chip, &chip->rb, false);
2496                 snd_dma_free_pages(&chip->rb);
2497         }
2498         if (chip->posbuf.area) {
2499                 mark_pages_wc(chip, &chip->posbuf, false);
2500                 snd_dma_free_pages(&chip->posbuf);
2501         }
2502         pci_release_regions(chip->pci);
2503         pci_disable_device(chip->pci);
2504         kfree(chip->azx_dev);
2505         kfree(chip);
2506
2507         return 0;
2508 }
2509
2510 static int azx_dev_free(struct snd_device *device)
2511 {
2512         return azx_free(device->device_data);
2513 }
2514
2515 /*
2516  * white/black-listing for position_fix
2517  */
2518 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2519         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2520         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2521         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2522         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2523         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2524         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2525         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2526         SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB),
2527         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2528         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2529         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2530         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2531         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2532         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2533         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2534         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2535         {}
2536 };
2537
2538 static int __devinit check_position_fix(struct azx *chip, int fix)
2539 {
2540         const struct snd_pci_quirk *q;
2541
2542         switch (fix) {
2543         case POS_FIX_LPIB:
2544         case POS_FIX_POSBUF:
2545         case POS_FIX_VIACOMBO:
2546                 return fix;
2547         }
2548
2549         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2550         if (q) {
2551                 printk(KERN_INFO
2552                        "hda_intel: position_fix set to %d "
2553                        "for device %04x:%04x\n",
2554                        q->value, q->subvendor, q->subdevice);
2555                 return q->value;
2556         }
2557
2558         /* Check VIA/ATI HD Audio Controller exist */
2559         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2560                 snd_printd(SFX "Using VIACOMBO position fix\n");
2561                 return POS_FIX_VIACOMBO;
2562         }
2563         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2564                 snd_printd(SFX "Using LPIB position fix\n");
2565                 return POS_FIX_LPIB;
2566         }
2567         return POS_FIX_AUTO;
2568 }
2569
2570 /*
2571  * black-lists for probe_mask
2572  */
2573 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2574         /* Thinkpad often breaks the controller communication when accessing
2575          * to the non-working (or non-existing) modem codec slot.
2576          */
2577         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2578         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2579         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2580         /* broken BIOS */
2581         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2582         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2583         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2584         /* forced codec slots */
2585         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2586         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2587         {}
2588 };
2589
2590 #define AZX_FORCE_CODEC_MASK    0x100
2591
2592 static void __devinit check_probe_mask(struct azx *chip, int dev)
2593 {
2594         const struct snd_pci_quirk *q;
2595
2596         chip->codec_probe_mask = probe_mask[dev];
2597         if (chip->codec_probe_mask == -1) {
2598                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2599                 if (q) {
2600                         printk(KERN_INFO
2601                                "hda_intel: probe_mask set to 0x%x "
2602                                "for device %04x:%04x\n",
2603                                q->value, q->subvendor, q->subdevice);
2604                         chip->codec_probe_mask = q->value;
2605                 }
2606         }
2607
2608         /* check forced option */
2609         if (chip->codec_probe_mask != -1 &&
2610             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2611                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2612                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2613                        chip->codec_mask);
2614         }
2615 }
2616
2617 /*
2618  * white/black-list for enable_msi
2619  */
2620 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2621         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
2622         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
2623         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
2624         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
2625         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2626         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2627         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2628         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
2629         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2630         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2631         {}
2632 };
2633
2634 static void __devinit check_msi(struct azx *chip)
2635 {
2636         const struct snd_pci_quirk *q;
2637
2638         if (enable_msi >= 0) {
2639                 chip->msi = !!enable_msi;
2640                 return;
2641         }
2642         chip->msi = 1;  /* enable MSI as default */
2643         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2644         if (q) {
2645                 printk(KERN_INFO
2646                        "hda_intel: msi for device %04x:%04x set to %d\n",
2647                        q->subvendor, q->subdevice, q->value);
2648                 chip->msi = q->value;
2649                 return;
2650         }
2651
2652         /* NVidia chipsets seem to cause troubles with MSI */
2653         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2654                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2655                 chip->msi = 0;
2656         }
2657 }
2658
2659
2660 /*
2661  * constructor
2662  */
2663 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2664                                 int dev, unsigned int driver_caps,
2665                                 struct azx **rchip)
2666 {
2667         struct azx *chip;
2668         int i, err;
2669         unsigned short gcap;
2670         unsigned int dma_bits = 64;
2671         static struct snd_device_ops ops = {
2672                 .dev_free = azx_dev_free,
2673         };
2674
2675         *rchip = NULL;
2676
2677         err = pci_enable_device(pci);
2678         if (err < 0)
2679                 return err;
2680
2681         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2682         if (!chip) {
2683                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2684                 pci_disable_device(pci);
2685                 return -ENOMEM;
2686         }
2687
2688         spin_lock_init(&chip->reg_lock);
2689         mutex_init(&chip->open_mutex);
2690         chip->card = card;
2691         chip->pci = pci;
2692         chip->irq = -1;
2693         chip->driver_caps = driver_caps;
2694         chip->driver_type = driver_caps & 0xff;
2695         check_msi(chip);
2696         chip->dev_index = dev;
2697         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2698
2699         chip->position_fix[0] = chip->position_fix[1] =
2700                 check_position_fix(chip, position_fix[dev]);
2701         check_probe_mask(chip, dev);
2702
2703         chip->single_cmd = single_cmd;
2704         chip->snoop = hda_snoop;
2705
2706         if (bdl_pos_adj[dev] < 0) {
2707                 switch (chip->driver_type) {
2708                 case AZX_DRIVER_ICH:
2709                 case AZX_DRIVER_PCH:
2710                         bdl_pos_adj[dev] = 1;
2711                         break;
2712                 default:
2713                         bdl_pos_adj[dev] = 32;
2714                         break;
2715                 }
2716         }
2717
2718 #if BITS_PER_LONG != 64
2719         /* Fix up base address on ULI M5461 */
2720         if (chip->driver_type == AZX_DRIVER_ULI) {
2721                 u16 tmp3;
2722                 pci_read_config_word(pci, 0x40, &tmp3);
2723                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2724                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2725         }
2726 #endif
2727
2728         err = pci_request_regions(pci, "ICH HD audio");
2729         if (err < 0) {
2730                 kfree(chip);
2731                 pci_disable_device(pci);
2732                 return err;
2733         }
2734
2735         chip->addr = pci_resource_start(pci, 0);
2736         chip->remap_addr = pci_ioremap_bar(pci, 0);
2737         if (chip->remap_addr == NULL) {
2738                 snd_printk(KERN_ERR SFX "ioremap error\n");
2739                 err = -ENXIO;
2740                 goto errout;
2741         }
2742
2743         if (chip->msi)
2744                 if (pci_enable_msi(pci) < 0)
2745                         chip->msi = 0;
2746
2747         if (azx_acquire_irq(chip, 0) < 0) {
2748                 err = -EBUSY;
2749                 goto errout;
2750         }
2751
2752         pci_set_master(pci);
2753         synchronize_irq(chip->irq);
2754
2755         gcap = azx_readw(chip, GCAP);
2756         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2757
2758         /* AMD devices support 40 or 48bit DMA, take the safe one */
2759         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
2760                 dma_bits = 40;
2761
2762         /* disable SB600 64bit support for safety */
2763         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2764                 struct pci_dev *p_smbus;
2765                 dma_bits = 40;
2766                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2767                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2768                                          NULL);
2769                 if (p_smbus) {
2770                         if (p_smbus->revision < 0x30)
2771                                 gcap &= ~ICH6_GCAP_64OK;
2772                         pci_dev_put(p_smbus);
2773                 }
2774         }
2775
2776         /* disable 64bit DMA address on some devices */
2777         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2778                 snd_printd(SFX "Disabling 64bit DMA\n");
2779                 gcap &= ~ICH6_GCAP_64OK;
2780         }
2781
2782         /* disable buffer size rounding to 128-byte multiples if supported */
2783         chip->align_buffer_size = align_buffer_size;
2784         if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2785                 chip->align_buffer_size = 0;
2786
2787         /* allow 64bit DMA address if supported by H/W */
2788         if (!(gcap & ICH6_GCAP_64OK))
2789                 dma_bits = 32;
2790         if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
2791                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
2792         } else {
2793                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2794                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2795         }
2796
2797         /* read number of streams from GCAP register instead of using
2798          * hardcoded value
2799          */
2800         chip->capture_streams = (gcap >> 8) & 0x0f;
2801         chip->playback_streams = (gcap >> 12) & 0x0f;
2802         if (!chip->playback_streams && !chip->capture_streams) {
2803                 /* gcap didn't give any info, switching to old method */
2804
2805                 switch (chip->driver_type) {
2806                 case AZX_DRIVER_ULI:
2807                         chip->playback_streams = ULI_NUM_PLAYBACK;
2808                         chip->capture_streams = ULI_NUM_CAPTURE;
2809                         break;
2810                 case AZX_DRIVER_ATIHDMI:
2811                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2812                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2813                         break;
2814                 case AZX_DRIVER_GENERIC:
2815                 default:
2816                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2817                         chip->capture_streams = ICH6_NUM_CAPTURE;
2818                         break;
2819                 }
2820         }
2821         chip->capture_index_offset = 0;
2822         chip->playback_index_offset = chip->capture_streams;
2823         chip->num_streams = chip->playback_streams + chip->capture_streams;
2824         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2825                                 GFP_KERNEL);
2826         if (!chip->azx_dev) {
2827                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2828                 goto errout;
2829         }
2830
2831         for (i = 0; i < chip->num_streams; i++) {
2832                 /* allocate memory for the BDL for each stream */
2833                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2834                                           snd_dma_pci_data(chip->pci),
2835                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2836                 if (err < 0) {
2837                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2838                         goto errout;
2839                 }
2840                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2841         }
2842         /* allocate memory for the position buffer */
2843         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2844                                   snd_dma_pci_data(chip->pci),
2845                                   chip->num_streams * 8, &chip->posbuf);
2846         if (err < 0) {
2847                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2848                 goto errout;
2849         }
2850         mark_pages_wc(chip, &chip->posbuf, true);
2851         /* allocate CORB/RIRB */
2852         err = azx_alloc_cmd_io(chip);
2853         if (err < 0)
2854                 goto errout;
2855
2856         /* initialize streams */
2857         azx_init_stream(chip);
2858
2859         /* initialize chip */
2860         azx_init_pci(chip);
2861         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2862
2863         /* codec detection */
2864         if (!chip->codec_mask) {
2865                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2866                 err = -ENODEV;
2867                 goto errout;
2868         }
2869
2870         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2871         if (err <0) {
2872                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2873                 goto errout;
2874         }
2875
2876         strcpy(card->driver, "HDA-Intel");
2877         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2878                 sizeof(card->shortname));
2879         snprintf(card->longname, sizeof(card->longname),
2880                  "%s at 0x%lx irq %i",
2881                  card->shortname, chip->addr, chip->irq);
2882
2883         *rchip = chip;
2884         return 0;
2885
2886  errout:
2887         azx_free(chip);
2888         return err;
2889 }
2890
2891 static void power_down_all_codecs(struct azx *chip)
2892 {
2893 #ifdef CONFIG_SND_HDA_POWER_SAVE
2894         /* The codecs were powered up in snd_hda_codec_new().
2895          * Now all initialization done, so turn them down if possible
2896          */
2897         struct hda_codec *codec;
2898         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2899                 snd_hda_power_down(codec);
2900         }
2901 #endif
2902 }
2903
2904 static int __devinit azx_probe(struct pci_dev *pci,
2905                                const struct pci_device_id *pci_id)
2906 {
2907         static int dev;
2908         struct snd_card *card;
2909         struct azx *chip;
2910         int err;
2911
2912         if (dev >= SNDRV_CARDS)
2913                 return -ENODEV;
2914         if (!enable[dev]) {
2915                 dev++;
2916                 return -ENOENT;
2917         }
2918
2919         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2920         if (err < 0) {
2921                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2922                 return err;
2923         }
2924
2925         /* set this here since it's referred in snd_hda_load_patch() */
2926         snd_card_set_dev(card, &pci->dev);
2927
2928         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2929         if (err < 0)
2930                 goto out_free;
2931         card->private_data = chip;
2932
2933 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2934         chip->beep_mode = beep_mode[dev];
2935 #endif
2936
2937         /* create codec instances */
2938         err = azx_codec_create(chip, model[dev]);
2939         if (err < 0)
2940                 goto out_free;
2941 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2942         if (patch[dev] && *patch[dev]) {
2943                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2944                            patch[dev]);
2945                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2946                 if (err < 0)
2947                         goto out_free;
2948         }
2949 #endif
2950         if ((probe_only[dev] & 1) == 0) {
2951                 err = azx_codec_configure(chip);
2952                 if (err < 0)
2953                         goto out_free;
2954         }
2955
2956         /* create PCM streams */
2957         err = snd_hda_build_pcms(chip->bus);
2958         if (err < 0)
2959                 goto out_free;
2960
2961         /* create mixer controls */
2962         err = azx_mixer_create(chip);
2963         if (err < 0)
2964                 goto out_free;
2965
2966         err = snd_card_register(card);
2967         if (err < 0)
2968                 goto out_free;
2969
2970         pci_set_drvdata(pci, card);
2971         chip->running = 1;
2972         power_down_all_codecs(chip);
2973         azx_notifier_register(chip);
2974
2975         dev++;
2976         return err;
2977 out_free:
2978         snd_card_free(card);
2979         return err;
2980 }
2981
2982 static void __devexit azx_remove(struct pci_dev *pci)
2983 {
2984         snd_card_free(pci_get_drvdata(pci));
2985         pci_set_drvdata(pci, NULL);
2986 }
2987
2988 /* PCI IDs */
2989 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2990         /* CPT */
2991         { PCI_DEVICE(0x8086, 0x1c20),
2992           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2993           AZX_DCAPS_BUFSIZE },
2994         /* PBG */
2995         { PCI_DEVICE(0x8086, 0x1d20),
2996           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2997           AZX_DCAPS_BUFSIZE},
2998         /* Panther Point */
2999         { PCI_DEVICE(0x8086, 0x1e20),
3000           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3001           AZX_DCAPS_BUFSIZE},
3002         /* Lynx Point */
3003         { PCI_DEVICE(0x8086, 0x8c20),
3004           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3005           AZX_DCAPS_BUFSIZE},
3006         /* SCH */
3007         { PCI_DEVICE(0x8086, 0x811b),
3008           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3009           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3010         /* ICH */
3011         { PCI_DEVICE(0x8086, 0x2668),
3012           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3013           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3014         { PCI_DEVICE(0x8086, 0x27d8),
3015           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3016           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3017         { PCI_DEVICE(0x8086, 0x269a),
3018           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3019           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3020         { PCI_DEVICE(0x8086, 0x284b),
3021           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3022           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3023         { PCI_DEVICE(0x8086, 0x293e),
3024           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3025           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3026         { PCI_DEVICE(0x8086, 0x293f),
3027           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3028           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3029         { PCI_DEVICE(0x8086, 0x3a3e),
3030           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3031           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3032         { PCI_DEVICE(0x8086, 0x3a6e),
3033           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3034           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3035         /* Generic Intel */
3036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3037           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3038           .class_mask = 0xffffff,
3039           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3040         /* ATI SB 450/600/700/800/900 */
3041         { PCI_DEVICE(0x1002, 0x437b),
3042           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3043         { PCI_DEVICE(0x1002, 0x4383),
3044           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3045         /* AMD Hudson */
3046         { PCI_DEVICE(0x1022, 0x780d),
3047           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3048         /* AMD Raven */
3049         { PCI_DEVICE(0x1022, 0x15e3),
3050           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3051         /* ATI HDMI */
3052         { PCI_DEVICE(0x1002, 0x793b),
3053           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3054         { PCI_DEVICE(0x1002, 0x7919),
3055           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3056         { PCI_DEVICE(0x1002, 0x960f),
3057           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3058         { PCI_DEVICE(0x1002, 0x970f),
3059           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3060         { PCI_DEVICE(0x1002, 0xaa00),
3061           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3062         { PCI_DEVICE(0x1002, 0xaa08),
3063           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3064         { PCI_DEVICE(0x1002, 0xaa10),
3065           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3066         { PCI_DEVICE(0x1002, 0xaa18),
3067           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3068         { PCI_DEVICE(0x1002, 0xaa20),
3069           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3070         { PCI_DEVICE(0x1002, 0xaa28),
3071           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3072         { PCI_DEVICE(0x1002, 0xaa30),
3073           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3074         { PCI_DEVICE(0x1002, 0xaa38),
3075           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3076         { PCI_DEVICE(0x1002, 0xaa40),
3077           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3078         { PCI_DEVICE(0x1002, 0xaa48),
3079           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3080         /* VIA VT8251/VT8237A */
3081         { PCI_DEVICE(0x1106, 0x3288),
3082           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3083         /* SIS966 */
3084         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3085         /* ULI M5461 */
3086         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3087         /* NVIDIA MCP */
3088         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3089           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3090           .class_mask = 0xffffff,
3091           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3092         /* Teradici */
3093         { PCI_DEVICE(0x6549, 0x1200),
3094           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3095         /* Creative X-Fi (CA0110-IBG) */
3096 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3097         /* the following entry conflicts with snd-ctxfi driver,
3098          * as ctxfi driver mutates from HD-audio to native mode with
3099          * a special command sequence.
3100          */
3101         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3102           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3103           .class_mask = 0xffffff,
3104           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3105           AZX_DCAPS_NO_64BIT |
3106           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3107 #else
3108         /* this entry seems still valid -- i.e. without emu20kx chip */
3109         { PCI_DEVICE(0x1102, 0x0009),
3110           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3111           AZX_DCAPS_NO_64BIT |
3112           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3113 #endif
3114         /* Vortex86MX */
3115         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3116         /* VMware HDAudio */
3117         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3118         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3119         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3120           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3121           .class_mask = 0xffffff,
3122           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3123         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3124           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3125           .class_mask = 0xffffff,
3126           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3127         { 0, }
3128 };
3129 MODULE_DEVICE_TABLE(pci, azx_ids);
3130
3131 /* pci_driver definition */
3132 static struct pci_driver driver = {
3133         .name = KBUILD_MODNAME,
3134         .id_table = azx_ids,
3135         .probe = azx_probe,
3136         .remove = __devexit_p(azx_remove),
3137 #ifdef CONFIG_PM
3138         .suspend = azx_suspend,
3139         .resume = azx_resume,
3140 #endif
3141 };
3142
3143 static int __init alsa_card_azx_init(void)
3144 {
3145         return pci_register_driver(&driver);
3146 }
3147
3148 static void __exit alsa_card_azx_exit(void)
3149 {
3150         pci_unregister_driver(&driver);
3151 }
3152
3153 module_init(alsa_card_azx_init)
3154 module_exit(alsa_card_azx_exit)