sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define ICH6_REG_VMIN                   0x02
 142 #define ICH6_REG_VMAJ                   0x03
 143 #define ICH6_REG_OUTPAY                 0x04
 144 #define ICH6_REG_INPAY                  0x06
 145 #define ICH6_REG_GCTL                   0x08
 146 #define ICH6_REG_WAKEEN                 0x0c
 147 #define ICH6_REG_STATESTS               0x0e
 148 #define ICH6_REG_GSTS                   0x10
 149 #define ICH6_REG_INTCTL                 0x20
 150 #define ICH6_REG_INTSTS                 0x24
 151 #define ICH6_REG_WALCLK                 0x30
 152 #define ICH6_REG_SYNC                   0x34
 153 #define ICH6_REG_CORBLBASE              0x40
 154 #define ICH6_REG_CORBUBASE              0x44
 155 #define ICH6_REG_CORBWP                 0x48
 156 #define ICH6_REG_CORBRP                 0x4A
 157 #define ICH6_REG_CORBCTL                0x4c
 158 #define ICH6_REG_CORBSTS                0x4d
 159 #define ICH6_REG_CORBSIZE               0x4e
 160
 161 #define ICH6_REG_RIRBLBASE              0x50
 162 #define ICH6_REG_RIRBUBASE              0x54
 163 #define ICH6_REG_RIRBWP                 0x58
 164 #define ICH6_REG_RINTCNT                0x5a
 165 #define ICH6_REG_RIRBCTL                0x5c
 166 #define ICH6_REG_RIRBSTS                0x5d
 167 #define ICH6_REG_RIRBSIZE               0x5e
 168
 169 #define ICH6_REG_IC                     0x60
 170 #define ICH6_REG_IR                     0x64
 171 #define ICH6_REG_IRS                    0x68
 172 #define   ICH6_IRS_VALID        (1<<1)
 173 #define   ICH6_IRS_BUSY         (1<<0)
 174
 175 #define ICH6_REG_DPLBASE                0x70
 176 #define ICH6_REG_DPUBASE                0x74
 177 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 178
 179 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 180 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 181
 182 /* stream register offsets from stream base */
 183 #define ICH6_REG_SD_CTL                 0x00
 184 #define ICH6_REG_SD_STS                 0x03
 185 #define ICH6_REG_SD_LPIB                0x04
 186 #define ICH6_REG_SD_CBL                 0x08
 187 #define ICH6_REG_SD_LVI                 0x0c
 188 #define ICH6_REG_SD_FIFOW               0x0e
 189 #define ICH6_REG_SD_FIFOSIZE            0x10
 190 #define ICH6_REG_SD_FORMAT              0x12
 191 #define ICH6_REG_SD_BDLPL               0x18
 192 #define ICH6_REG_SD_BDLPU               0x1c
 193
 194 /* PCI space */
 195 #define ICH6_PCIREG_TCSEL       0x44
 196
 197 /*
 198  * other constants
 199  */
 200
 201 /* max number of SDs */
 202 /* ICH, ATI and VIA have 4 playback and 4 capture */
 203 #define ICH6_NUM_CAPTURE        4
 204 #define ICH6_NUM_PLAYBACK       4
 205
 206 /* ULI has 6 playback and 5 capture */
 207 #define ULI_NUM_CAPTURE         5
 208 #define ULI_NUM_PLAYBACK        6
 209
 210 /* ATI HDMI has 1 playback and 0 capture */
 211 #define ATIHDMI_NUM_CAPTURE     0
 212 #define ATIHDMI_NUM_PLAYBACK    1
 213
 214 /* TERA has 4 playback and 3 capture */
 215 #define TERA_NUM_CAPTURE        3
 216 #define TERA_NUM_PLAYBACK       4
 217
 218 /* this number is statically defined for simplicity */
 219 #define MAX_AZX_DEV             16
 220
 221 /* max number of fragments - we may use more if allocating more pages for BDL */
 222 #define BDL_SIZE                4096
 223 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 224 #define AZX_MAX_FRAG            32
 225 /* max buffer size - no h/w limit, you can increase as you like */
 226 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 227 /* max number of PCM devics per card */
 228 #define AZX_MAX_PCMS            8
 229
 230 /* RIRB int mask: overrun[2], response[0] */
 231 #define RIRB_INT_RESPONSE       0x01
 232 #define RIRB_INT_OVERRUN        0x04
 233 #define RIRB_INT_MASK           0x05
 234
 235 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 236 #define AZX_MAX_CODECS          4
 237 #define STATESTS_INT_MASK       0x0f
 238
 239 /* SD_CTL bits */
 240 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 241 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 242 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 243 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 244 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 245 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 246 #define SD_CTL_STREAM_TAG_SHIFT 20
 247
 248 /* SD_CTL and SD_STS */
 249 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 250 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 251 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 252 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 253                                  SD_INT_COMPLETE)
 254
 255 /* SD_STS */
 256 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 257
 258 /* INTCTL and INTSTS */
 259 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 260 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 261 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 262
 263 /* GCTL unsolicited response enable bit */
 264 #define ICH6_GCTL_UREN          (1<<8)
 265
 266 /* GCTL reset bit */
 267 #define ICH6_GCTL_RESET         (1<<0)
 268
 269 /* CORB/RIRB control, read/write pointer */
 270 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 271 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 272 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 273 /* below are so far hardcoded - should read registers in future */
 274 #define ICH6_MAX_CORB_ENTRIES   256
 275 #define ICH6_MAX_RIRB_ENTRIES   256
 276
 277 /* position fix mode */
 278 enum {
 279         POS_FIX_AUTO,
 280         POS_FIX_LPIB,
 281         POS_FIX_POSBUF,
 282 };
 283
 284 /* Defines for ATI HD Audio support in SB450 south bridge */
 285 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 286 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 287
 288 /* Defines for Nvidia HDA support */
 289 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 290 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 291 #define NVIDIA_HDA_ISTRM_COH          0x4d
 292 #define NVIDIA_HDA_OSTRM_COH          0x4c
 293 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 294
 295 /* Defines for Intel SCH HDA snoop control */
 296 #define INTEL_SCH_HDA_DEVC      0x78
 297 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 298
 299 /* Define IN stream 0 FIFO size offset in VIA controller */
 300 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 301 /* Define VIA HD Audio Device ID*/
 302 #define VIA_HDAC_DEVICE_ID              0x3288
 303
 304 /* HD Audio class code */
 305 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 306
 307 /*
 308  */
 309
 310 struct azx_dev {
 311         struct snd_dma_buffer bdl; /* BDL buffer */
 312         u32 *posbuf;            /* position buffer pointer */
 313
 314         unsigned int bufsize;   /* size of the play buffer in bytes */
 315         unsigned int period_bytes; /* size of the period in bytes */
 316         unsigned int frags;     /* number for period in the play buffer */
 317         unsigned int fifo_size; /* FIFO size */
 318         unsigned long start_jiffies;    /* start + minimum jiffies */
 319         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 320
 321         void __iomem *sd_addr;  /* stream descriptor pointer */
 322
 323         u32 sd_int_sta_mask;    /* stream int status mask */
 324
 325         /* pcm support */
 326         struct snd_pcm_substream *substream;    /* assigned substream,
 327                                                  * set in PCM open
 328                                                  */
 329         unsigned int format_val;        /* format value to be set in the
 330                                          * controller and the codec
 331                                          */
 332         unsigned char stream_tag;       /* assigned stream */
 333         unsigned char index;            /* stream index */
 334
 335         unsigned int opened :1;
 336         unsigned int running :1;
 337         unsigned int irq_pending :1;
 338         unsigned int start_flag: 1;     /* stream full start flag */
 339         /*
 340          * For VIA:
 341          *  A flag to ensure DMA position is 0
 342          *  when link position is not greater than FIFO size
 343          */
 344         unsigned int insufficient :1;
 345 };
 346
 347 /* CORB/RIRB */
 348 struct azx_rb {
 349         u32 *buf;               /* CORB/RIRB buffer
 350                                  * Each CORB entry is 4byte, RIRB is 8byte
 351                                  */
 352         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 353         /* for RIRB */
 354         unsigned short rp, wp;  /* read/write pointers */
 355         int cmds;               /* number of pending requests */
 356         u32 res;                /* last read value */
 357 };
 358
 359 struct azx {
 360         struct snd_card *card;
 361         struct pci_dev *pci;
 362         int dev_index;
 363
 364         /* chip type specific */
 365         int driver_type;
 366         int playback_streams;
 367         int playback_index_offset;
 368         int capture_streams;
 369         int capture_index_offset;
 370         int num_streams;
 371
 372         /* pci resources */
 373         unsigned long addr;
 374         void __iomem *remap_addr;
 375         int irq;
 376
 377         /* locks */
 378         spinlock_t reg_lock;
 379         struct mutex open_mutex;
 380
 381         /* streams (x num_streams) */
 382         struct azx_dev *azx_dev;
 383
 384         /* PCM */
 385         struct snd_pcm *pcm[AZX_MAX_PCMS];
 386
 387         /* HD codec */
 388         unsigned short codec_mask;
 389         int  codec_probe_mask; /* copied from probe_mask option */
 390         struct hda_bus *bus;
 391
 392         /* CORB/RIRB */
 393         struct azx_rb corb;
 394         struct azx_rb rirb;
 395
 396         /* CORB/RIRB and position buffers */
 397         struct snd_dma_buffer rb;
 398         struct snd_dma_buffer posbuf;
 399
 400         /* flags */
 401         int position_fix;
 402         unsigned int running :1;
 403         unsigned int initialized :1;
 404         unsigned int single_cmd :1;
 405         unsigned int polling_mode :1;
 406         unsigned int msi :1;
 407         unsigned int irq_pending_warned :1;
 408         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 409         unsigned int probing :1; /* codec probing phase */
 410
 411         /* for debugging */
 412         unsigned int last_cmd;  /* last issued command (to sync) */
 413
 414         /* for pending irqs */
 415         struct work_struct irq_pending_work;
 416
 417         /* reboot notifier (for mysterious hangup problem at power-down) */
 418         struct notifier_block reboot_notifier;
 419 };
 420
 421 /* driver types */
 422 enum {
 423         AZX_DRIVER_ICH,
 424         AZX_DRIVER_SCH,
 425         AZX_DRIVER_ATI,
 426         AZX_DRIVER_ATIHDMI,
 427         AZX_DRIVER_VIA,
 428         AZX_DRIVER_SIS,
 429         AZX_DRIVER_ULI,
 430         AZX_DRIVER_NVIDIA,
 431         AZX_DRIVER_TERA,
 432         AZX_DRIVER_GENERIC,
 433         AZX_NUM_DRIVERS, /* keep this as last entry */
 434 };
 435
 436 static char *driver_short_names[] __devinitdata = {
 437         [AZX_DRIVER_ICH] = "HDA Intel",
 438         [AZX_DRIVER_SCH] = "HDA Intel MID",
 439         [AZX_DRIVER_ATI] = "HDA ATI SB",
 440         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 441         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 442         [AZX_DRIVER_SIS] = "HDA SIS966",
 443         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 444         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 445         [AZX_DRIVER_TERA] = "HDA Teradici",
 446         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 447 };
 448
 449 /*
 450  * macros for easy use
 451  */
 452 #define azx_writel(chip,reg,value) \
 453         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 454 #define azx_readl(chip,reg) \
 455         readl((chip)->remap_addr + ICH6_REG_##reg)
 456 #define azx_writew(chip,reg,value) \
 457         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 458 #define azx_readw(chip,reg) \
 459         readw((chip)->remap_addr + ICH6_REG_##reg)
 460 #define azx_writeb(chip,reg,value) \
 461         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 462 #define azx_readb(chip,reg) \
 463         readb((chip)->remap_addr + ICH6_REG_##reg)
 464
 465 #define azx_sd_writel(dev,reg,value) \
 466         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 467 #define azx_sd_readl(dev,reg) \
 468         readl((dev)->sd_addr + ICH6_REG_##reg)
 469 #define azx_sd_writew(dev,reg,value) \
 470         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 471 #define azx_sd_readw(dev,reg) \
 472         readw((dev)->sd_addr + ICH6_REG_##reg)
 473 #define azx_sd_writeb(dev,reg,value) \
 474         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 475 #define azx_sd_readb(dev,reg) \
 476         readb((dev)->sd_addr + ICH6_REG_##reg)
 477
 478 /* for pcm support */
 479 #define get_azx_dev(substream) (substream->runtime->private_data)
 480
 481 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 482
 483 /*
 484  * Interface for HD codec
 485  */
 486
 487 /*
 488  * CORB / RIRB interface
 489  */
 490 static int azx_alloc_cmd_io(struct azx *chip)
 491 {
 492         int err;
 493
 494         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 495         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 496                                   snd_dma_pci_data(chip->pci),
 497                                   PAGE_SIZE, &chip->rb);
 498         if (err < 0) {
 499                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 500                 return err;
 501         }
 502         return 0;
 503 }
 504
 505 static void azx_init_cmd_io(struct azx *chip)
 506 {
 507         /* CORB set up */
 508         chip->corb.addr = chip->rb.addr;
 509         chip->corb.buf = (u32 *)chip->rb.area;
 510         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 511         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 512
 513         /* set the corb size to 256 entries (ULI requires explicitly) */
 514         azx_writeb(chip, CORBSIZE, 0x02);
 515         /* set the corb write pointer to 0 */
 516         azx_writew(chip, CORBWP, 0);
 517         /* reset the corb hw read pointer */
 518         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 519         /* enable corb dma */
 520         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 521
 522         /* RIRB set up */
 523         chip->rirb.addr = chip->rb.addr + 2048;
 524         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 525         chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
 526         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 527         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 528
 529         /* set the rirb size to 256 entries (ULI requires explicitly) */
 530         azx_writeb(chip, RIRBSIZE, 0x02);
 531         /* reset the rirb hw write pointer */
 532         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 533         /* set N=1, get RIRB response interrupt for new entry */
 534         azx_writew(chip, RINTCNT, 1);
 535         /* enable rirb dma and response irq */
 536         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 537 }
 538
 539 static void azx_free_cmd_io(struct azx *chip)
 540 {
 541         /* disable ringbuffer DMAs */
 542         azx_writeb(chip, RIRBCTL, 0);
 543         azx_writeb(chip, CORBCTL, 0);
 544 }
 545
 546 /* send a command */
 547 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 548 {
 549         struct azx *chip = bus->private_data;
 550         unsigned int wp;
 551
 552         /* add command to corb */
 553         wp = azx_readb(chip, CORBWP);
 554         wp++;
 555         wp %= ICH6_MAX_CORB_ENTRIES;
 556
 557         spin_lock_irq(&chip->reg_lock);
 558         chip->rirb.cmds++;
 559         chip->corb.buf[wp] = cpu_to_le32(val);
 560         azx_writel(chip, CORBWP, wp);
 561         spin_unlock_irq(&chip->reg_lock);
 562
 563         return 0;
 564 }
 565
 566 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 567
 568 /* retrieve RIRB entry - called from interrupt handler */
 569 static void azx_update_rirb(struct azx *chip)
 570 {
 571         unsigned int rp, wp;
 572         u32 res, res_ex;
 573
 574         wp = azx_readb(chip, RIRBWP);
 575         if (wp == chip->rirb.wp)
 576                 return;
 577         chip->rirb.wp = wp;
 578
 579         while (chip->rirb.rp != wp) {
 580                 chip->rirb.rp++;
 581                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 582
 583                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 584                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 585                 res = le32_to_cpu(chip->rirb.buf[rp]);
 586                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 587                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 588                 else if (chip->rirb.cmds) {
 589                         chip->rirb.res = res;
 590                         smp_wmb();
 591                         chip->rirb.cmds--;
 592                 }
 593         }
 594 }
 595
 596 /* receive a response */
 597 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 598 {
 599         struct azx *chip = bus->private_data;
 600         unsigned long timeout;
 601
 602  again:
 603         timeout = jiffies + msecs_to_jiffies(1000);
 604         for (;;) {
 605                 if (chip->polling_mode) {
 606                         spin_lock_irq(&chip->reg_lock);
 607                         azx_update_rirb(chip);
 608                         spin_unlock_irq(&chip->reg_lock);
 609                 }
 610                 if (!chip->rirb.cmds) {
 611                         smp_rmb();
 612                         bus->rirb_error = 0;
 613                         return chip->rirb.res; /* the last value */
 614                 }
 615                 if (time_after(jiffies, timeout))
 616                         break;
 617                 if (bus->needs_damn_long_delay)
 618                         msleep(2); /* temporary workaround */
 619                 else {
 620                         udelay(10);
 621                         cond_resched();
 622                 }
 623         }
 624
 625         if (chip->msi) {
 626                 snd_printk(KERN_WARNING SFX "No response from codec, "
 627                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 628                 free_irq(chip->irq, chip);
 629                 chip->irq = -1;
 630                 pci_disable_msi(chip->pci);
 631                 chip->msi = 0;
 632                 if (azx_acquire_irq(chip, 1) < 0) {
 633                         bus->rirb_error = 1;
 634                         return -1;
 635                 }
 636                 goto again;
 637         }
 638
 639         if (!chip->polling_mode) {
 640                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 641                            "switching to polling mode: last cmd=0x%08x\n",
 642                            chip->last_cmd);
 643                 chip->polling_mode = 1;
 644                 goto again;
 645         }
 646
 647         if (chip->probing) {
 648                 /* If this critical timeout happens during the codec probing
 649                  * phase, this is likely an access to a non-existing codec
 650                  * slot.  Better to return an error and reset the system.
 651                  */
 652                 return -1;
 653         }
 654
 655         snd_printk(KERN_ERR SFX "azx_get_response timeout (ERROR): "
 656                    "last cmd=0x%08x\n", chip->last_cmd);
 657         /* re-initialize CORB/RIRB */
 658         spin_lock_irq(&chip->reg_lock);
 659         bus->rirb_error = 1;
 660         azx_free_cmd_io(chip);
 661         azx_init_cmd_io(chip);
 662         spin_unlock_irq(&chip->reg_lock);
 663         return -1;
 664 }
 665
 666 /*
 667  * Use the single immediate command instead of CORB/RIRB for simplicity
 668  *
 669  * Note: according to Intel, this is not preferred use.  The command was
 670  *       intended for the BIOS only, and may get confused with unsolicited
 671  *       responses.  So, we shouldn't use it for normal operation from the
 672  *       driver.
 673  *       I left the codes, however, for debugging/testing purposes.
 674  */
 675
 676 /* send a command */
 677 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 678 {
 679         struct azx *chip = bus->private_data;
 680         int timeout = 50;
 681
 682         while (timeout--) {
 683                 /* check ICB busy bit */
 684                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 685                         /* Clear IRV valid bit */
 686                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 687                                    ICH6_IRS_VALID);
 688                         azx_writel(chip, IC, val);
 689                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 690                                    ICH6_IRS_BUSY);
 691                         return 0;
 692                 }
 693                 udelay(1);
 694         }
 695         if (printk_ratelimit())
 696                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 697                            azx_readw(chip, IRS), val);
 698         return -EIO;
 699 }
 700
 701 /* receive a response */
 702 static unsigned int azx_single_get_response(struct hda_bus *bus)
 703 {
 704         struct azx *chip = bus->private_data;
 705         int timeout = 50;
 706
 707         while (timeout--) {
 708                 /* check IRV busy bit */
 709                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 710                         return azx_readl(chip, IR);
 711                 udelay(1);
 712         }
 713         if (printk_ratelimit())
 714                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 715                            azx_readw(chip, IRS));
 716         return (unsigned int)-1;
 717 }
 718
 719 /*
 720  * The below are the main callbacks from hda_codec.
 721  *
 722  * They are just the skeleton to call sub-callbacks according to the
 723  * current setting of chip->single_cmd.
 724  */
 725
 726 /* send a command */
 727 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 728 {
 729         struct azx *chip = bus->private_data;
 730
 731         chip->last_cmd = val;
 732         if (chip->single_cmd)
 733                 return azx_single_send_cmd(bus, val);
 734         else
 735                 return azx_corb_send_cmd(bus, val);
 736 }
 737
 738 /* get a response */
 739 static unsigned int azx_get_response(struct hda_bus *bus)
 740 {
 741         struct azx *chip = bus->private_data;
 742         if (chip->single_cmd)
 743                 return azx_single_get_response(bus);
 744         else
 745                 return azx_rirb_get_response(bus);
 746 }
 747
 748 #ifdef CONFIG_SND_HDA_POWER_SAVE
 749 static void azx_power_notify(struct hda_bus *bus);
 750 #endif
 751
 752 /* reset codec link */
 753 static int azx_reset(struct azx *chip)
 754 {
 755         int count;
 756
 757         /* clear STATESTS */
 758         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 759
 760         /* reset controller */
 761         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 762
 763         count = 50;
 764         while (azx_readb(chip, GCTL) && --count)
 765                 msleep(1);
 766
 767         /* delay for >= 100us for codec PLL to settle per spec
 768          * Rev 0.9 section 5.5.1
 769          */
 770         msleep(1);
 771
 772         /* Bring controller out of reset */
 773         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 774
 775         count = 50;
 776         while (!azx_readb(chip, GCTL) && --count)
 777                 msleep(1);
 778
 779         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 780         msleep(1);
 781
 782         /* check to see if controller is ready */
 783         if (!azx_readb(chip, GCTL)) {
 784                 snd_printd(SFX "azx_reset: controller not ready!\n");
 785                 return -EBUSY;
 786         }
 787
 788         /* Accept unsolicited responses */
 789         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 790
 791         /* detect codecs */
 792         if (!chip->codec_mask) {
 793                 chip->codec_mask = azx_readw(chip, STATESTS);
 794                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 795         }
 796
 797         return 0;
 798 }
 799
 800
 801 /*
 802  * Lowlevel interface
 803  */
 804
 805 /* enable interrupts */
 806 static void azx_int_enable(struct azx *chip)
 807 {
 808         /* enable controller CIE and GIE */
 809         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 810                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 811 }
 812
 813 /* disable interrupts */
 814 static void azx_int_disable(struct azx *chip)
 815 {
 816         int i;
 817
 818         /* disable interrupts in stream descriptor */
 819         for (i = 0; i < chip->num_streams; i++) {
 820                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 821                 azx_sd_writeb(azx_dev, SD_CTL,
 822                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 823         }
 824
 825         /* disable SIE for all streams */
 826         azx_writeb(chip, INTCTL, 0);
 827
 828         /* disable controller CIE and GIE */
 829         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 830                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 831 }
 832
 833 /* clear interrupts */
 834 static void azx_int_clear(struct azx *chip)
 835 {
 836         int i;
 837
 838         /* clear stream status */
 839         for (i = 0; i < chip->num_streams; i++) {
 840                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 841                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 842         }
 843
 844         /* clear STATESTS */
 845         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 846
 847         /* clear rirb status */
 848         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 849
 850         /* clear int status */
 851         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 852 }
 853
 854 /* start a stream */
 855 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 856 {
 857         /*
 858          * Before stream start, initialize parameter
 859          */
 860         azx_dev->insufficient = 1;
 861
 862         /* enable SIE */
 863         azx_writeb(chip, INTCTL,
 864                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 865         /* set DMA start and interrupt mask */
 866         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 867                       SD_CTL_DMA_START | SD_INT_MASK);
 868 }
 869
 870 /* stop DMA */
 871 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 872 {
 873         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 874                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 875         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 876 }
 877
 878 /* stop a stream */
 879 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 880 {
 881         azx_stream_clear(chip, azx_dev);
 882         /* disable SIE */
 883         azx_writeb(chip, INTCTL,
 884                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 885 }
 886
 887
 888 /*
 889  * reset and start the controller registers
 890  */
 891 static void azx_init_chip(struct azx *chip)
 892 {
 893         if (chip->initialized)
 894                 return;
 895
 896         /* reset controller */
 897         azx_reset(chip);
 898
 899         /* initialize interrupts */
 900         azx_int_clear(chip);
 901         azx_int_enable(chip);
 902
 903         /* initialize the codec command I/O */
 904         azx_init_cmd_io(chip);
 905
 906         /* program the position buffer */
 907         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 908         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 909
 910         chip->initialized = 1;
 911 }
 912
 913 /*
 914  * initialize the PCI registers
 915  */
 916 /* update bits in a PCI register byte */
 917 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 918                             unsigned char mask, unsigned char val)
 919 {
 920         unsigned char data;
 921
 922         pci_read_config_byte(pci, reg, &data);
 923         data &= ~mask;
 924         data |= (val & mask);
 925         pci_write_config_byte(pci, reg, data);
 926 }
 927
 928 static void azx_init_pci(struct azx *chip)
 929 {
 930         unsigned short snoop;
 931
 932         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 933          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 934          * Ensuring these bits are 0 clears playback static on some HD Audio
 935          * codecs
 936          */
 937         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 938
 939         switch (chip->driver_type) {
 940         case AZX_DRIVER_ATI:
 941                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 942                 update_pci_byte(chip->pci,
 943                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 944                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 945                 break;
 946         case AZX_DRIVER_NVIDIA:
 947                 /* For NVIDIA HDA, enable snoop */
 948                 update_pci_byte(chip->pci,
 949                                 NVIDIA_HDA_TRANSREG_ADDR,
 950                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 951                 update_pci_byte(chip->pci,
 952                                 NVIDIA_HDA_ISTRM_COH,
 953                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 954                 update_pci_byte(chip->pci,
 955                                 NVIDIA_HDA_OSTRM_COH,
 956                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 957                 break;
 958         case AZX_DRIVER_SCH:
 959                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 960                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 961                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
 962                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 963                         pci_read_config_word(chip->pci,
 964                                 INTEL_SCH_HDA_DEVC, &snoop);
 965                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
 966                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
 967                                 ? "Failed" : "OK");
 968                 }
 969                 break;
 970
 971         }
 972 }
 973
 974
 975 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 976
 977 /*
 978  * interrupt handler
 979  */
 980 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 981 {
 982         struct azx *chip = dev_id;
 983         struct azx_dev *azx_dev;
 984         u32 status;
 985         int i, ok;
 986
 987         spin_lock(&chip->reg_lock);
 988
 989         status = azx_readl(chip, INTSTS);
 990         if (status == 0) {
 991                 spin_unlock(&chip->reg_lock);
 992                 return IRQ_NONE;
 993         }
 994
 995         for (i = 0; i < chip->num_streams; i++) {
 996                 azx_dev = &chip->azx_dev[i];
 997                 if (status & azx_dev->sd_int_sta_mask) {
 998                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 999                         if (!azx_dev->substream || !azx_dev->running)
1000                                 continue;
1001                         /* check whether this IRQ is really acceptable */
1002                         ok = azx_position_ok(chip, azx_dev);
1003                         if (ok == 1) {
1004                                 azx_dev->irq_pending = 0;
1005                                 spin_unlock(&chip->reg_lock);
1006                                 snd_pcm_period_elapsed(azx_dev->substream);
1007                                 spin_lock(&chip->reg_lock);
1008                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1009                                 /* bogus IRQ, process it later */
1010                                 azx_dev->irq_pending = 1;
1011                                 queue_work(chip->bus->workq,
1012                                            &chip->irq_pending_work);
1013                         }
1014                 }
1015         }
1016
1017         /* clear rirb int */
1018         status = azx_readb(chip, RIRBSTS);
1019         if (status & RIRB_INT_MASK) {
1020                 if (status & RIRB_INT_RESPONSE)
1021                         azx_update_rirb(chip);
1022                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1023         }
1024
1025 #if 0
1026         /* clear state status int */
1027         if (azx_readb(chip, STATESTS) & 0x04)
1028                 azx_writeb(chip, STATESTS, 0x04);
1029 #endif
1030         spin_unlock(&chip->reg_lock);
1031
1032         return IRQ_HANDLED;
1033 }
1034
1035
1036 /*
1037  * set up a BDL entry
1038  */
1039 static int setup_bdle(struct snd_pcm_substream *substream,
1040                       struct azx_dev *azx_dev, u32 **bdlp,
1041                       int ofs, int size, int with_ioc)
1042 {
1043         u32 *bdl = *bdlp;
1044
1045         while (size > 0) {
1046                 dma_addr_t addr;
1047                 int chunk;
1048
1049                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1050                         return -EINVAL;
1051
1052                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1053                 /* program the address field of the BDL entry */
1054                 bdl[0] = cpu_to_le32((u32)addr);
1055                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1056                 /* program the size field of the BDL entry */
1057                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1058                 bdl[2] = cpu_to_le32(chunk);
1059                 /* program the IOC to enable interrupt
1060                  * only when the whole fragment is processed
1061                  */
1062                 size -= chunk;
1063                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1064                 bdl += 4;
1065                 azx_dev->frags++;
1066                 ofs += chunk;
1067         }
1068         *bdlp = bdl;
1069         return ofs;
1070 }
1071
1072 /*
1073  * set up BDL entries
1074  */
1075 static int azx_setup_periods(struct azx *chip,
1076                              struct snd_pcm_substream *substream,
1077                              struct azx_dev *azx_dev)
1078 {
1079         u32 *bdl;
1080         int i, ofs, periods, period_bytes;
1081         int pos_adj;
1082
1083         /* reset BDL address */
1084         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1085         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1086
1087         period_bytes = azx_dev->period_bytes;
1088         periods = azx_dev->bufsize / period_bytes;
1089
1090         /* program the initial BDL entries */
1091         bdl = (u32 *)azx_dev->bdl.area;
1092         ofs = 0;
1093         azx_dev->frags = 0;
1094         pos_adj = bdl_pos_adj[chip->dev_index];
1095         if (pos_adj > 0) {
1096                 struct snd_pcm_runtime *runtime = substream->runtime;
1097                 int pos_align = pos_adj;
1098                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1099                 if (!pos_adj)
1100                         pos_adj = pos_align;
1101                 else
1102                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1103                                 pos_align;
1104                 pos_adj = frames_to_bytes(runtime, pos_adj);
1105                 if (pos_adj >= period_bytes) {
1106                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1107                                    bdl_pos_adj[chip->dev_index]);
1108                         pos_adj = 0;
1109                 } else {
1110                         ofs = setup_bdle(substream, azx_dev,
1111                                          &bdl, ofs, pos_adj, 1);
1112                         if (ofs < 0)
1113                                 goto error;
1114                 }
1115         } else
1116                 pos_adj = 0;
1117         for (i = 0; i < periods; i++) {
1118                 if (i == periods - 1 && pos_adj)
1119                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1120                                          period_bytes - pos_adj, 0);
1121                 else
1122                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1123                                          period_bytes, 1);
1124                 if (ofs < 0)
1125                         goto error;
1126         }
1127         return 0;
1128
1129  error:
1130         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1131                    azx_dev->bufsize, period_bytes);
1132         return -EINVAL;
1133 }
1134
1135 /* reset stream */
1136 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1137 {
1138         unsigned char val;
1139         int timeout;
1140
1141         azx_stream_clear(chip, azx_dev);
1142
1143         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1144                       SD_CTL_STREAM_RESET);
1145         udelay(3);
1146         timeout = 300;
1147         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1148                --timeout)
1149                 ;
1150         val &= ~SD_CTL_STREAM_RESET;
1151         azx_sd_writeb(azx_dev, SD_CTL, val);
1152         udelay(3);
1153
1154         timeout = 300;
1155         /* waiting for hardware to report that the stream is out of reset */
1156         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1157                --timeout)
1158                 ;
1159
1160         /* reset first position - may not be synced with hw at this time */
1161         *azx_dev->posbuf = 0;
1162 }
1163
1164 /*
1165  * set up the SD for streaming
1166  */
1167 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1168 {
1169         /* make sure the run bit is zero for SD */
1170         azx_stream_clear(chip, azx_dev);
1171         /* program the stream_tag */
1172         azx_sd_writel(azx_dev, SD_CTL,
1173                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1174                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1175
1176         /* program the length of samples in cyclic buffer */
1177         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1178
1179         /* program the stream format */
1180         /* this value needs to be the same as the one programmed */
1181         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1182
1183         /* program the stream LVI (last valid index) of the BDL */
1184         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1185
1186         /* program the BDL address */
1187         /* lower BDL address */
1188         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1189         /* upper BDL address */
1190         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1191
1192         /* enable the position buffer */
1193         if (chip->position_fix == POS_FIX_POSBUF ||
1194             chip->position_fix == POS_FIX_AUTO ||
1195             chip->via_dmapos_patch) {
1196                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1197                         azx_writel(chip, DPLBASE,
1198                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1199         }
1200
1201         /* set the interrupt enable bits in the descriptor control register */
1202         azx_sd_writel(azx_dev, SD_CTL,
1203                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1204
1205         return 0;
1206 }
1207
1208 /*
1209  * Probe the given codec address
1210  */
1211 static int probe_codec(struct azx *chip, int addr)
1212 {
1213         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1214                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1215         unsigned int res;
1216
1217         chip->probing = 1;
1218         azx_send_cmd(chip->bus, cmd);
1219         res = azx_get_response(chip->bus);
1220         chip->probing = 0;
1221         if (res == -1)
1222                 return -EIO;
1223         snd_printdd(SFX "codec #%d probed OK\n", addr);
1224         return 0;
1225 }
1226
1227 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1228                                  struct hda_pcm *cpcm);
1229 static void azx_stop_chip(struct azx *chip);
1230
1231 /*
1232  * Codec initialization
1233  */
1234
1235 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1236 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1237         [AZX_DRIVER_TERA] = 1,
1238 };
1239
1240 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1241                                       int no_init)
1242 {
1243         struct hda_bus_template bus_temp;
1244         int c, codecs, err;
1245         int max_slots;
1246
1247         memset(&bus_temp, 0, sizeof(bus_temp));
1248         bus_temp.private_data = chip;
1249         bus_temp.modelname = model;
1250         bus_temp.pci = chip->pci;
1251         bus_temp.ops.command = azx_send_cmd;
1252         bus_temp.ops.get_response = azx_get_response;
1253         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1254 #ifdef CONFIG_SND_HDA_POWER_SAVE
1255         bus_temp.power_save = &power_save;
1256         bus_temp.ops.pm_notify = azx_power_notify;
1257 #endif
1258
1259         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1260         if (err < 0)
1261                 return err;
1262
1263         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1264                 chip->bus->needs_damn_long_delay = 1;
1265
1266         codecs = 0;
1267         max_slots = azx_max_codecs[chip->driver_type];
1268         if (!max_slots)
1269                 max_slots = AZX_MAX_CODECS;
1270
1271         /* First try to probe all given codec slots */
1272         for (c = 0; c < max_slots; c++) {
1273                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1274                         if (probe_codec(chip, c) < 0) {
1275                                 /* Some BIOSen give you wrong codec addresses
1276                                  * that don't exist
1277                                  */
1278                                 snd_printk(KERN_WARNING SFX
1279                                            "Codec #%d probe error; "
1280                                            "disabling it...\n", c);
1281                                 chip->codec_mask &= ~(1 << c);
1282                                 /* More badly, accessing to a non-existing
1283                                  * codec often screws up the controller chip,
1284                                  * and distrubs the further communications.
1285                                  * Thus if an error occurs during probing,
1286                                  * better to reset the controller chip to
1287                                  * get back to the sanity state.
1288                                  */
1289                                 azx_stop_chip(chip);
1290                                 azx_init_chip(chip);
1291                         }
1292                 }
1293         }
1294
1295         /* Then create codec instances */
1296         for (c = 0; c < max_slots; c++) {
1297                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1298                         struct hda_codec *codec;
1299                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1300                         if (err < 0)
1301                                 continue;
1302                         codecs++;
1303                 }
1304         }
1305         if (!codecs) {
1306                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1307                 return -ENXIO;
1308         }
1309
1310         return 0;
1311 }
1312
1313
1314 /*
1315  * PCM support
1316  */
1317
1318 /* assign a stream for the PCM */
1319 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1320 {
1321         int dev, i, nums;
1322         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1323                 dev = chip->playback_index_offset;
1324                 nums = chip->playback_streams;
1325         } else {
1326                 dev = chip->capture_index_offset;
1327                 nums = chip->capture_streams;
1328         }
1329         for (i = 0; i < nums; i++, dev++)
1330                 if (!chip->azx_dev[dev].opened) {
1331                         chip->azx_dev[dev].opened = 1;
1332                         return &chip->azx_dev[dev];
1333                 }
1334         return NULL;
1335 }
1336
1337 /* release the assigned stream */
1338 static inline void azx_release_device(struct azx_dev *azx_dev)
1339 {
1340         azx_dev->opened = 0;
1341 }
1342
1343 static struct snd_pcm_hardware azx_pcm_hw = {
1344         .info =                 (SNDRV_PCM_INFO_MMAP |
1345                                  SNDRV_PCM_INFO_INTERLEAVED |
1346                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1347                                  SNDRV_PCM_INFO_MMAP_VALID |
1348                                  /* No full-resume yet implemented */
1349                                  /* SNDRV_PCM_INFO_RESUME |*/
1350                                  SNDRV_PCM_INFO_PAUSE |
1351                                  SNDRV_PCM_INFO_SYNC_START),
1352         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1353         .rates =                SNDRV_PCM_RATE_48000,
1354         .rate_min =             48000,
1355         .rate_max =             48000,
1356         .channels_min =         2,
1357         .channels_max =         2,
1358         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1359         .period_bytes_min =     128,
1360         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1361         .periods_min =          2,
1362         .periods_max =          AZX_MAX_FRAG,
1363         .fifo_size =            0,
1364 };
1365
1366 struct azx_pcm {
1367         struct azx *chip;
1368         struct hda_codec *codec;
1369         struct hda_pcm_stream *hinfo[2];
1370 };
1371
1372 static int azx_pcm_open(struct snd_pcm_substream *substream)
1373 {
1374         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1375         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1376         struct azx *chip = apcm->chip;
1377         struct azx_dev *azx_dev;
1378         struct snd_pcm_runtime *runtime = substream->runtime;
1379         unsigned long flags;
1380         int err;
1381
1382         mutex_lock(&chip->open_mutex);
1383         azx_dev = azx_assign_device(chip, substream->stream);
1384         if (azx_dev == NULL) {
1385                 mutex_unlock(&chip->open_mutex);
1386                 return -EBUSY;
1387         }
1388         runtime->hw = azx_pcm_hw;
1389         runtime->hw.channels_min = hinfo->channels_min;
1390         runtime->hw.channels_max = hinfo->channels_max;
1391         runtime->hw.formats = hinfo->formats;
1392         runtime->hw.rates = hinfo->rates;
1393         snd_pcm_limit_hw_rates(runtime);
1394         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1395         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1396                                    128);
1397         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1398                                    128);
1399         snd_hda_power_up(apcm->codec);
1400         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1401         if (err < 0) {
1402                 azx_release_device(azx_dev);
1403                 snd_hda_power_down(apcm->codec);
1404                 mutex_unlock(&chip->open_mutex);
1405                 return err;
1406         }
1407         spin_lock_irqsave(&chip->reg_lock, flags);
1408         azx_dev->substream = substream;
1409         azx_dev->running = 0;
1410         spin_unlock_irqrestore(&chip->reg_lock, flags);
1411
1412         runtime->private_data = azx_dev;
1413         snd_pcm_set_sync(substream);
1414         mutex_unlock(&chip->open_mutex);
1415
1416         return 0;
1417 }
1418
1419 static int azx_pcm_close(struct snd_pcm_substream *substream)
1420 {
1421         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1422         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1423         struct azx *chip = apcm->chip;
1424         struct azx_dev *azx_dev = get_azx_dev(substream);
1425         unsigned long flags;
1426
1427         mutex_lock(&chip->open_mutex);
1428         spin_lock_irqsave(&chip->reg_lock, flags);
1429         azx_dev->substream = NULL;
1430         azx_dev->running = 0;
1431         spin_unlock_irqrestore(&chip->reg_lock, flags);
1432         azx_release_device(azx_dev);
1433         hinfo->ops.close(hinfo, apcm->codec, substream);
1434         snd_hda_power_down(apcm->codec);
1435         mutex_unlock(&chip->open_mutex);
1436         return 0;
1437 }
1438
1439 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1440                              struct snd_pcm_hw_params *hw_params)
1441 {
1442         struct azx_dev *azx_dev = get_azx_dev(substream);
1443
1444         azx_dev->bufsize = 0;
1445         azx_dev->period_bytes = 0;
1446         azx_dev->format_val = 0;
1447         return snd_pcm_lib_malloc_pages(substream,
1448                                         params_buffer_bytes(hw_params));
1449 }
1450
1451 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1452 {
1453         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1454         struct azx_dev *azx_dev = get_azx_dev(substream);
1455         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1456
1457         /* reset BDL address */
1458         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1459         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1460         azx_sd_writel(azx_dev, SD_CTL, 0);
1461         azx_dev->bufsize = 0;
1462         azx_dev->period_bytes = 0;
1463         azx_dev->format_val = 0;
1464
1465         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1466
1467         return snd_pcm_lib_free_pages(substream);
1468 }
1469
1470 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1471 {
1472         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1473         struct azx *chip = apcm->chip;
1474         struct azx_dev *azx_dev = get_azx_dev(substream);
1475         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1476         struct snd_pcm_runtime *runtime = substream->runtime;
1477         unsigned int bufsize, period_bytes, format_val;
1478         int err;
1479
1480         azx_stream_reset(chip, azx_dev);
1481         format_val = snd_hda_calc_stream_format(runtime->rate,
1482                                                 runtime->channels,
1483                                                 runtime->format,
1484                                                 hinfo->maxbps);
1485         if (!format_val) {
1486                 snd_printk(KERN_ERR SFX
1487                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1488                            runtime->rate, runtime->channels, runtime->format);
1489                 return -EINVAL;
1490         }
1491
1492         bufsize = snd_pcm_lib_buffer_bytes(substream);
1493         period_bytes = snd_pcm_lib_period_bytes(substream);
1494
1495         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1496                     bufsize, format_val);
1497
1498         if (bufsize != azx_dev->bufsize ||
1499             period_bytes != azx_dev->period_bytes ||
1500             format_val != azx_dev->format_val) {
1501                 azx_dev->bufsize = bufsize;
1502                 azx_dev->period_bytes = period_bytes;
1503                 azx_dev->format_val = format_val;
1504                 err = azx_setup_periods(chip, substream, azx_dev);
1505                 if (err < 0)
1506                         return err;
1507         }
1508
1509         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1510                                                 (runtime->rate * 2);
1511         azx_setup_controller(chip, azx_dev);
1512         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1513                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1514         else
1515                 azx_dev->fifo_size = 0;
1516
1517         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1518                                   azx_dev->format_val, substream);
1519 }
1520
1521 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1522 {
1523         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1524         struct azx *chip = apcm->chip;
1525         struct azx_dev *azx_dev;
1526         struct snd_pcm_substream *s;
1527         int rstart = 0, start, nsync = 0, sbits = 0;
1528         int nwait, timeout;
1529
1530         switch (cmd) {
1531         case SNDRV_PCM_TRIGGER_START:
1532                 rstart = 1;
1533         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1534         case SNDRV_PCM_TRIGGER_RESUME:
1535                 start = 1;
1536                 break;
1537         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1538         case SNDRV_PCM_TRIGGER_SUSPEND:
1539         case SNDRV_PCM_TRIGGER_STOP:
1540                 start = 0;
1541                 break;
1542         default:
1543                 return -EINVAL;
1544         }
1545
1546         snd_pcm_group_for_each_entry(s, substream) {
1547                 if (s->pcm->card != substream->pcm->card)
1548                         continue;
1549                 azx_dev = get_azx_dev(s);
1550                 sbits |= 1 << azx_dev->index;
1551                 nsync++;
1552                 snd_pcm_trigger_done(s, substream);
1553         }
1554
1555         spin_lock(&chip->reg_lock);
1556         if (nsync > 1) {
1557                 /* first, set SYNC bits of corresponding streams */
1558                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1559         }
1560         snd_pcm_group_for_each_entry(s, substream) {
1561                 if (s->pcm->card != substream->pcm->card)
1562                         continue;
1563                 azx_dev = get_azx_dev(s);
1564                 if (rstart) {
1565                         azx_dev->start_flag = 1;
1566                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1567                 }
1568                 if (start)
1569                         azx_stream_start(chip, azx_dev);
1570                 else
1571                         azx_stream_stop(chip, azx_dev);
1572                 azx_dev->running = start;
1573         }
1574         spin_unlock(&chip->reg_lock);
1575         if (start) {
1576                 if (nsync == 1)
1577                         return 0;
1578                 /* wait until all FIFOs get ready */
1579                 for (timeout = 5000; timeout; timeout--) {
1580                         nwait = 0;
1581                         snd_pcm_group_for_each_entry(s, substream) {
1582                                 if (s->pcm->card != substream->pcm->card)
1583                                         continue;
1584                                 azx_dev = get_azx_dev(s);
1585                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1586                                       SD_STS_FIFO_READY))
1587                                         nwait++;
1588                         }
1589                         if (!nwait)
1590                                 break;
1591                         cpu_relax();
1592                 }
1593         } else {
1594                 /* wait until all RUN bits are cleared */
1595                 for (timeout = 5000; timeout; timeout--) {
1596                         nwait = 0;
1597                         snd_pcm_group_for_each_entry(s, substream) {
1598                                 if (s->pcm->card != substream->pcm->card)
1599                                         continue;
1600                                 azx_dev = get_azx_dev(s);
1601                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1602                                     SD_CTL_DMA_START)
1603                                         nwait++;
1604                         }
1605                         if (!nwait)
1606                                 break;
1607                         cpu_relax();
1608                 }
1609         }
1610         if (nsync > 1) {
1611                 spin_lock(&chip->reg_lock);
1612                 /* reset SYNC bits */
1613                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1614                 spin_unlock(&chip->reg_lock);
1615         }
1616         return 0;
1617 }
1618
1619 /* get the current DMA position with correction on VIA chips */
1620 static unsigned int azx_via_get_position(struct azx *chip,
1621                                          struct azx_dev *azx_dev)
1622 {
1623         unsigned int link_pos, mini_pos, bound_pos;
1624         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1625         unsigned int fifo_size;
1626
1627         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1628         if (azx_dev->index >= 4) {
1629                 /* Playback, no problem using link position */
1630                 return link_pos;
1631         }
1632
1633         /* Capture */
1634         /* For new chipset,
1635          * use mod to get the DMA position just like old chipset
1636          */
1637         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1638         mod_dma_pos %= azx_dev->period_bytes;
1639
1640         /* azx_dev->fifo_size can't get FIFO size of in stream.
1641          * Get from base address + offset.
1642          */
1643         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1644
1645         if (azx_dev->insufficient) {
1646                 /* Link position never gather than FIFO size */
1647                 if (link_pos <= fifo_size)
1648                         return 0;
1649
1650                 azx_dev->insufficient = 0;
1651         }
1652
1653         if (link_pos <= fifo_size)
1654                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1655         else
1656                 mini_pos = link_pos - fifo_size;
1657
1658         /* Find nearest previous boudary */
1659         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1660         mod_link_pos = link_pos % azx_dev->period_bytes;
1661         if (mod_link_pos >= fifo_size)
1662                 bound_pos = link_pos - mod_link_pos;
1663         else if (mod_dma_pos >= mod_mini_pos)
1664                 bound_pos = mini_pos - mod_mini_pos;
1665         else {
1666                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1667                 if (bound_pos >= azx_dev->bufsize)
1668                         bound_pos = 0;
1669         }
1670
1671         /* Calculate real DMA position we want */
1672         return bound_pos + mod_dma_pos;
1673 }
1674
1675 static unsigned int azx_get_position(struct azx *chip,
1676                                      struct azx_dev *azx_dev)
1677 {
1678         unsigned int pos;
1679
1680         if (chip->via_dmapos_patch)
1681                 pos = azx_via_get_position(chip, azx_dev);
1682         else if (chip->position_fix == POS_FIX_POSBUF ||
1683                  chip->position_fix == POS_FIX_AUTO) {
1684                 /* use the position buffer */
1685                 pos = le32_to_cpu(*azx_dev->posbuf);
1686         } else {
1687                 /* read LPIB */
1688                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1689         }
1690         if (pos >= azx_dev->bufsize)
1691                 pos = 0;
1692         return pos;
1693 }
1694
1695 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1696 {
1697         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1698         struct azx *chip = apcm->chip;
1699         struct azx_dev *azx_dev = get_azx_dev(substream);
1700         return bytes_to_frames(substream->runtime,
1701                                azx_get_position(chip, azx_dev));
1702 }
1703
1704 /*
1705  * Check whether the current DMA position is acceptable for updating
1706  * periods.  Returns non-zero if it's OK.
1707  *
1708  * Many HD-audio controllers appear pretty inaccurate about
1709  * the update-IRQ timing.  The IRQ is issued before actually the
1710  * data is processed.  So, we need to process it afterwords in a
1711  * workqueue.
1712  */
1713 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1714 {
1715         unsigned int pos;
1716
1717         if (azx_dev->start_flag &&
1718             time_before_eq(jiffies, azx_dev->start_jiffies))
1719                 return -1;      /* bogus (too early) interrupt */
1720         azx_dev->start_flag = 0;
1721
1722         pos = azx_get_position(chip, azx_dev);
1723         if (chip->position_fix == POS_FIX_AUTO) {
1724                 if (!pos) {
1725                         printk(KERN_WARNING
1726                                "hda-intel: Invalid position buffer, "
1727                                "using LPIB read method instead.\n");
1728                         chip->position_fix = POS_FIX_LPIB;
1729                         pos = azx_get_position(chip, azx_dev);
1730                 } else
1731                         chip->position_fix = POS_FIX_POSBUF;
1732         }
1733
1734         if (!bdl_pos_adj[chip->dev_index])
1735                 return 1; /* no delayed ack */
1736         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1737                 return 0; /* NG - it's below the period boundary */
1738         return 1; /* OK, it's fine */
1739 }
1740
1741 /*
1742  * The work for pending PCM period updates.
1743  */
1744 static void azx_irq_pending_work(struct work_struct *work)
1745 {
1746         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1747         int i, pending;
1748
1749         if (!chip->irq_pending_warned) {
1750                 printk(KERN_WARNING
1751                        "hda-intel: IRQ timing workaround is activated "
1752                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1753                        chip->card->number);
1754                 chip->irq_pending_warned = 1;
1755         }
1756
1757         for (;;) {
1758                 pending = 0;
1759                 spin_lock_irq(&chip->reg_lock);
1760                 for (i = 0; i < chip->num_streams; i++) {
1761                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1762                         if (!azx_dev->irq_pending ||
1763                             !azx_dev->substream ||
1764                             !azx_dev->running)
1765                                 continue;
1766                         if (azx_position_ok(chip, azx_dev)) {
1767                                 azx_dev->irq_pending = 0;
1768                                 spin_unlock(&chip->reg_lock);
1769                                 snd_pcm_period_elapsed(azx_dev->substream);
1770                                 spin_lock(&chip->reg_lock);
1771                         } else
1772                                 pending++;
1773                 }
1774                 spin_unlock_irq(&chip->reg_lock);
1775                 if (!pending)
1776                         return;
1777                 cond_resched();
1778         }
1779 }
1780
1781 /* clear irq_pending flags and assure no on-going workq */
1782 static void azx_clear_irq_pending(struct azx *chip)
1783 {
1784         int i;
1785
1786         spin_lock_irq(&chip->reg_lock);
1787         for (i = 0; i < chip->num_streams; i++)
1788                 chip->azx_dev[i].irq_pending = 0;
1789         spin_unlock_irq(&chip->reg_lock);
1790 }
1791
1792 static struct snd_pcm_ops azx_pcm_ops = {
1793         .open = azx_pcm_open,
1794         .close = azx_pcm_close,
1795         .ioctl = snd_pcm_lib_ioctl,
1796         .hw_params = azx_pcm_hw_params,
1797         .hw_free = azx_pcm_hw_free,
1798         .prepare = azx_pcm_prepare,
1799         .trigger = azx_pcm_trigger,
1800         .pointer = azx_pcm_pointer,
1801         .page = snd_pcm_sgbuf_ops_page,
1802 };
1803
1804 static void azx_pcm_free(struct snd_pcm *pcm)
1805 {
1806         struct azx_pcm *apcm = pcm->private_data;
1807         if (apcm) {
1808                 apcm->chip->pcm[pcm->device] = NULL;
1809                 kfree(apcm);
1810         }
1811 }
1812
1813 static int
1814 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1815                       struct hda_pcm *cpcm)
1816 {
1817         struct azx *chip = bus->private_data;
1818         struct snd_pcm *pcm;
1819         struct azx_pcm *apcm;
1820         int pcm_dev = cpcm->device;
1821         int s, err;
1822
1823         if (pcm_dev >= AZX_MAX_PCMS) {
1824                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1825                            pcm_dev);
1826                 return -EINVAL;
1827         }
1828         if (chip->pcm[pcm_dev]) {
1829                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1830                 return -EBUSY;
1831         }
1832         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1833                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1834                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1835                           &pcm);
1836         if (err < 0)
1837                 return err;
1838         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1839         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1840         if (apcm == NULL)
1841                 return -ENOMEM;
1842         apcm->chip = chip;
1843         apcm->codec = codec;
1844         pcm->private_data = apcm;
1845         pcm->private_free = azx_pcm_free;
1846         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1847                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1848         chip->pcm[pcm_dev] = pcm;
1849         cpcm->pcm = pcm;
1850         for (s = 0; s < 2; s++) {
1851                 apcm->hinfo[s] = &cpcm->stream[s];
1852                 if (cpcm->stream[s].substreams)
1853                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1854         }
1855         /* buffer pre-allocation */
1856         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1857                                               snd_dma_pci_data(chip->pci),
1858                                               1024 * 64, 32 * 1024 * 1024);
1859         return 0;
1860 }
1861
1862 /*
1863  * mixer creation - all stuff is implemented in hda module
1864  */
1865 static int __devinit azx_mixer_create(struct azx *chip)
1866 {
1867         return snd_hda_build_controls(chip->bus);
1868 }
1869
1870
1871 /*
1872  * initialize SD streams
1873  */
1874 static int __devinit azx_init_stream(struct azx *chip)
1875 {
1876         int i;
1877
1878         /* initialize each stream (aka device)
1879          * assign the starting bdl address to each stream (device)
1880          * and initialize
1881          */
1882         for (i = 0; i < chip->num_streams; i++) {
1883                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1884                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1885                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1886                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1887                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1888                 azx_dev->sd_int_sta_mask = 1 << i;
1889                 /* stream tag: must be non-zero and unique */
1890                 azx_dev->index = i;
1891                 azx_dev->stream_tag = i + 1;
1892         }
1893
1894         return 0;
1895 }
1896
1897 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1898 {
1899         if (request_irq(chip->pci->irq, azx_interrupt,
1900                         chip->msi ? 0 : IRQF_SHARED,
1901                         "HDA Intel", chip)) {
1902                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1903                        "disabling device\n", chip->pci->irq);
1904                 if (do_disconnect)
1905                         snd_card_disconnect(chip->card);
1906                 return -1;
1907         }
1908         chip->irq = chip->pci->irq;
1909         pci_intx(chip->pci, !chip->msi);
1910         return 0;
1911 }
1912
1913
1914 static void azx_stop_chip(struct azx *chip)
1915 {
1916         if (!chip->initialized)
1917                 return;
1918
1919         /* disable interrupts */
1920         azx_int_disable(chip);
1921         azx_int_clear(chip);
1922
1923         /* disable CORB/RIRB */
1924         azx_free_cmd_io(chip);
1925
1926         /* disable position buffer */
1927         azx_writel(chip, DPLBASE, 0);
1928         azx_writel(chip, DPUBASE, 0);
1929
1930         chip->initialized = 0;
1931 }
1932
1933 #ifdef CONFIG_SND_HDA_POWER_SAVE
1934 /* power-up/down the controller */
1935 static void azx_power_notify(struct hda_bus *bus)
1936 {
1937         struct azx *chip = bus->private_data;
1938         struct hda_codec *c;
1939         int power_on = 0;
1940
1941         list_for_each_entry(c, &bus->codec_list, list) {
1942                 if (c->power_on) {
1943                         power_on = 1;
1944                         break;
1945                 }
1946         }
1947         if (power_on)
1948                 azx_init_chip(chip);
1949         else if (chip->running && power_save_controller)
1950                 azx_stop_chip(chip);
1951 }
1952 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1953
1954 #ifdef CONFIG_PM
1955 /*
1956  * power management
1957  */
1958
1959 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1960 {
1961         struct hda_codec *codec;
1962
1963         list_for_each_entry(codec, &bus->codec_list, list) {
1964                 if (snd_hda_codec_needs_resume(codec))
1965                         return 1;
1966         }
1967         return 0;
1968 }
1969
1970 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1971 {
1972         struct snd_card *card = pci_get_drvdata(pci);
1973         struct azx *chip = card->private_data;
1974         int i;
1975
1976         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1977         azx_clear_irq_pending(chip);
1978         for (i = 0; i < AZX_MAX_PCMS; i++)
1979                 snd_pcm_suspend_all(chip->pcm[i]);
1980         if (chip->initialized)
1981                 snd_hda_suspend(chip->bus, state);
1982         azx_stop_chip(chip);
1983         if (chip->irq >= 0) {
1984                 free_irq(chip->irq, chip);
1985                 chip->irq = -1;
1986         }
1987         if (chip->msi)
1988                 pci_disable_msi(chip->pci);
1989         pci_disable_device(pci);
1990         pci_save_state(pci);
1991         pci_set_power_state(pci, pci_choose_state(pci, state));
1992         return 0;
1993 }
1994
1995 static int azx_resume(struct pci_dev *pci)
1996 {
1997         struct snd_card *card = pci_get_drvdata(pci);
1998         struct azx *chip = card->private_data;
1999
2000         pci_set_power_state(pci, PCI_D0);
2001         pci_restore_state(pci);
2002         if (pci_enable_device(pci) < 0) {
2003                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2004                        "disabling device\n");
2005                 snd_card_disconnect(card);
2006                 return -EIO;
2007         }
2008         pci_set_master(pci);
2009         if (chip->msi)
2010                 if (pci_enable_msi(pci) < 0)
2011                         chip->msi = 0;
2012         if (azx_acquire_irq(chip, 1) < 0)
2013                 return -EIO;
2014         azx_init_pci(chip);
2015
2016         if (snd_hda_codecs_inuse(chip->bus))
2017                 azx_init_chip(chip);
2018
2019         snd_hda_resume(chip->bus);
2020         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2021         return 0;
2022 }
2023 #endif /* CONFIG_PM */
2024
2025
2026 /*
2027  * reboot notifier for hang-up problem at power-down
2028  */
2029 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2030 {
2031         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2032         azx_stop_chip(chip);
2033         return NOTIFY_OK;
2034 }
2035
2036 static void azx_notifier_register(struct azx *chip)
2037 {
2038         chip->reboot_notifier.notifier_call = azx_halt;
2039         register_reboot_notifier(&chip->reboot_notifier);
2040 }
2041
2042 static void azx_notifier_unregister(struct azx *chip)
2043 {
2044         if (chip->reboot_notifier.notifier_call)
2045                 unregister_reboot_notifier(&chip->reboot_notifier);
2046 }
2047
2048 /*
2049  * destructor
2050  */
2051 static int azx_free(struct azx *chip)
2052 {
2053         int i;
2054
2055         azx_notifier_unregister(chip);
2056
2057         if (chip->initialized) {
2058                 azx_clear_irq_pending(chip);
2059                 for (i = 0; i < chip->num_streams; i++)
2060                         azx_stream_stop(chip, &chip->azx_dev[i]);
2061                 azx_stop_chip(chip);
2062         }
2063
2064         if (chip->irq >= 0)
2065                 free_irq(chip->irq, (void*)chip);
2066         if (chip->msi)
2067                 pci_disable_msi(chip->pci);
2068         if (chip->remap_addr)
2069                 iounmap(chip->remap_addr);
2070
2071         if (chip->azx_dev) {
2072                 for (i = 0; i < chip->num_streams; i++)
2073                         if (chip->azx_dev[i].bdl.area)
2074                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2075         }
2076         if (chip->rb.area)
2077                 snd_dma_free_pages(&chip->rb);
2078         if (chip->posbuf.area)
2079                 snd_dma_free_pages(&chip->posbuf);
2080         pci_release_regions(chip->pci);
2081         pci_disable_device(chip->pci);
2082         kfree(chip->azx_dev);
2083         kfree(chip);
2084
2085         return 0;
2086 }
2087
2088 static int azx_dev_free(struct snd_device *device)
2089 {
2090         return azx_free(device->device_data);
2091 }
2092
2093 /*
2094  * white/black-listing for position_fix
2095  */
2096 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2097         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2098         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2099         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2100         {}
2101 };
2102
2103 static int __devinit check_position_fix(struct azx *chip, int fix)
2104 {
2105         const struct snd_pci_quirk *q;
2106
2107         switch (fix) {
2108         case POS_FIX_LPIB:
2109         case POS_FIX_POSBUF:
2110                 return fix;
2111         }
2112
2113         /* Check VIA/ATI HD Audio Controller exist */
2114         switch (chip->driver_type) {
2115         case AZX_DRIVER_VIA:
2116         case AZX_DRIVER_ATI:
2117                 chip->via_dmapos_patch = 1;
2118                 /* Use link position directly, avoid any transfer problem. */
2119                 return POS_FIX_LPIB;
2120         }
2121         chip->via_dmapos_patch = 0;
2122
2123         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2124         if (q) {
2125                 printk(KERN_INFO
2126                        "hda_intel: position_fix set to %d "
2127                        "for device %04x:%04x\n",
2128                        q->value, q->subvendor, q->subdevice);
2129                 return q->value;
2130         }
2131         return POS_FIX_AUTO;
2132 }
2133
2134 /*
2135  * black-lists for probe_mask
2136  */
2137 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2138         /* Thinkpad often breaks the controller communication when accessing
2139          * to the non-working (or non-existing) modem codec slot.
2140          */
2141         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2142         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2143         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2144         /* broken BIOS */
2145         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2146         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2147         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2148         /* forced codec slots */
2149         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2150         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2151         {}
2152 };
2153
2154 #define AZX_FORCE_CODEC_MASK    0x100
2155
2156 static void __devinit check_probe_mask(struct azx *chip, int dev)
2157 {
2158         const struct snd_pci_quirk *q;
2159
2160         chip->codec_probe_mask = probe_mask[dev];
2161         if (chip->codec_probe_mask == -1) {
2162                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2163                 if (q) {
2164                         printk(KERN_INFO
2165                                "hda_intel: probe_mask set to 0x%x "
2166                                "for device %04x:%04x\n",
2167                                q->value, q->subvendor, q->subdevice);
2168                         chip->codec_probe_mask = q->value;
2169                 }
2170         }
2171
2172         /* check forced option */
2173         if (chip->codec_probe_mask != -1 &&
2174             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2175                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2176                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2177                        chip->codec_mask);
2178         }
2179 }
2180
2181
2182 /*
2183  * constructor
2184  */
2185 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2186                                 int dev, int driver_type,
2187                                 struct azx **rchip)
2188 {
2189         struct azx *chip;
2190         int i, err;
2191         unsigned short gcap;
2192         static struct snd_device_ops ops = {
2193                 .dev_free = azx_dev_free,
2194         };
2195
2196         *rchip = NULL;
2197
2198         err = pci_enable_device(pci);
2199         if (err < 0)
2200                 return err;
2201
2202         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2203         if (!chip) {
2204                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2205                 pci_disable_device(pci);
2206                 return -ENOMEM;
2207         }
2208
2209         spin_lock_init(&chip->reg_lock);
2210         mutex_init(&chip->open_mutex);
2211         chip->card = card;
2212         chip->pci = pci;
2213         chip->irq = -1;
2214         chip->driver_type = driver_type;
2215         chip->msi = enable_msi;
2216         chip->dev_index = dev;
2217         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2218
2219         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2220         check_probe_mask(chip, dev);
2221
2222         chip->single_cmd = single_cmd;
2223
2224         if (bdl_pos_adj[dev] < 0) {
2225                 switch (chip->driver_type) {
2226                 case AZX_DRIVER_ICH:
2227                         bdl_pos_adj[dev] = 1;
2228                         break;
2229                 default:
2230                         bdl_pos_adj[dev] = 32;
2231                         break;
2232                 }
2233         }
2234
2235 #if BITS_PER_LONG != 64
2236         /* Fix up base address on ULI M5461 */
2237         if (chip->driver_type == AZX_DRIVER_ULI) {
2238                 u16 tmp3;
2239                 pci_read_config_word(pci, 0x40, &tmp3);
2240                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2241                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2242         }
2243 #endif
2244
2245         err = pci_request_regions(pci, "ICH HD audio");
2246         if (err < 0) {
2247                 kfree(chip);
2248                 pci_disable_device(pci);
2249                 return err;
2250         }
2251
2252         chip->addr = pci_resource_start(pci, 0);
2253         chip->remap_addr = pci_ioremap_bar(pci, 0);
2254         if (chip->remap_addr == NULL) {
2255                 snd_printk(KERN_ERR SFX "ioremap error\n");
2256                 err = -ENXIO;
2257                 goto errout;
2258         }
2259
2260         if (chip->msi)
2261                 if (pci_enable_msi(pci) < 0)
2262                         chip->msi = 0;
2263
2264         if (azx_acquire_irq(chip, 0) < 0) {
2265                 err = -EBUSY;
2266                 goto errout;
2267         }
2268
2269         pci_set_master(pci);
2270         synchronize_irq(chip->irq);
2271
2272         gcap = azx_readw(chip, GCAP);
2273         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2274
2275         /* ATI chips seems buggy about 64bit DMA addresses */
2276         if (chip->driver_type == AZX_DRIVER_ATI)
2277                 gcap &= ~0x01;
2278
2279         /* allow 64bit DMA address if supported by H/W */
2280         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2281                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2282         else {
2283                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2284                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2285         }
2286
2287         /* read number of streams from GCAP register instead of using
2288          * hardcoded value
2289          */
2290         chip->capture_streams = (gcap >> 8) & 0x0f;
2291         chip->playback_streams = (gcap >> 12) & 0x0f;
2292         if (!chip->playback_streams && !chip->capture_streams) {
2293                 /* gcap didn't give any info, switching to old method */
2294
2295                 switch (chip->driver_type) {
2296                 case AZX_DRIVER_ULI:
2297                         chip->playback_streams = ULI_NUM_PLAYBACK;
2298                         chip->capture_streams = ULI_NUM_CAPTURE;
2299                         break;
2300                 case AZX_DRIVER_ATIHDMI:
2301                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2302                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2303                         break;
2304                 case AZX_DRIVER_GENERIC:
2305                 default:
2306                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2307                         chip->capture_streams = ICH6_NUM_CAPTURE;
2308                         break;
2309                 }
2310         }
2311         chip->capture_index_offset = 0;
2312         chip->playback_index_offset = chip->capture_streams;
2313         chip->num_streams = chip->playback_streams + chip->capture_streams;
2314         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2315                                 GFP_KERNEL);
2316         if (!chip->azx_dev) {
2317                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2318                 goto errout;
2319         }
2320
2321         for (i = 0; i < chip->num_streams; i++) {
2322                 /* allocate memory for the BDL for each stream */
2323                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2324                                           snd_dma_pci_data(chip->pci),
2325                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2326                 if (err < 0) {
2327                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2328                         goto errout;
2329                 }
2330         }
2331         /* allocate memory for the position buffer */
2332         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2333                                   snd_dma_pci_data(chip->pci),
2334                                   chip->num_streams * 8, &chip->posbuf);
2335         if (err < 0) {
2336                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2337                 goto errout;
2338         }
2339         /* allocate CORB/RIRB */
2340         err = azx_alloc_cmd_io(chip);
2341         if (err < 0)
2342                 goto errout;
2343
2344         /* initialize streams */
2345         azx_init_stream(chip);
2346
2347         /* initialize chip */
2348         azx_init_pci(chip);
2349         azx_init_chip(chip);
2350
2351         /* codec detection */
2352         if (!chip->codec_mask) {
2353                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2354                 err = -ENODEV;
2355                 goto errout;
2356         }
2357
2358         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2359         if (err <0) {
2360                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2361                 goto errout;
2362         }
2363
2364         strcpy(card->driver, "HDA-Intel");
2365         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2366                 sizeof(card->shortname));
2367         snprintf(card->longname, sizeof(card->longname),
2368                  "%s at 0x%lx irq %i",
2369                  card->shortname, chip->addr, chip->irq);
2370
2371         *rchip = chip;
2372         return 0;
2373
2374  errout:
2375         azx_free(chip);
2376         return err;
2377 }
2378
2379 static void power_down_all_codecs(struct azx *chip)
2380 {
2381 #ifdef CONFIG_SND_HDA_POWER_SAVE
2382         /* The codecs were powered up in snd_hda_codec_new().
2383          * Now all initialization done, so turn them down if possible
2384          */
2385         struct hda_codec *codec;
2386         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2387                 snd_hda_power_down(codec);
2388         }
2389 #endif
2390 }
2391
2392 static int __devinit azx_probe(struct pci_dev *pci,
2393                                const struct pci_device_id *pci_id)
2394 {
2395         static int dev;
2396         struct snd_card *card;
2397         struct azx *chip;
2398         int err;
2399
2400         if (dev >= SNDRV_CARDS)
2401                 return -ENODEV;
2402         if (!enable[dev]) {
2403                 dev++;
2404                 return -ENOENT;
2405         }
2406
2407         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2408         if (err < 0) {
2409                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2410                 return err;
2411         }
2412
2413         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2414         if (err < 0)
2415                 goto out_free;
2416         card->private_data = chip;
2417
2418         /* create codec instances */
2419         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2420         if (err < 0)
2421                 goto out_free;
2422
2423         /* create PCM streams */
2424         err = snd_hda_build_pcms(chip->bus);
2425         if (err < 0)
2426                 goto out_free;
2427
2428         /* create mixer controls */
2429         err = azx_mixer_create(chip);
2430         if (err < 0)
2431                 goto out_free;
2432
2433         snd_card_set_dev(card, &pci->dev);
2434
2435         err = snd_card_register(card);
2436         if (err < 0)
2437                 goto out_free;
2438
2439         pci_set_drvdata(pci, card);
2440         chip->running = 1;
2441         power_down_all_codecs(chip);
2442         azx_notifier_register(chip);
2443
2444         dev++;
2445         return err;
2446 out_free:
2447         snd_card_free(card);
2448         return err;
2449 }
2450
2451 static void __devexit azx_remove(struct pci_dev *pci)
2452 {
2453         snd_card_free(pci_get_drvdata(pci));
2454         pci_set_drvdata(pci, NULL);
2455 }
2456
2457 /* PCI IDs */
2458 static struct pci_device_id azx_ids[] = {
2459         /* ICH 6..10 */
2460         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2461         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2462         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2463         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2464         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2465         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2466         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2467         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2468         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2469         /* PCH */
2470         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2471         /* SCH */
2472         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2473         /* ATI SB 450/600 */
2474         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2475         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2476         /* ATI HDMI */
2477         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2478         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2479         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2480         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2481         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2482         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2483         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2484         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2485         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2486         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2487         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2488         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2489         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2490         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2491         /* VIA VT8251/VT8237A */
2492         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2493         /* SIS966 */
2494         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2495         /* ULI M5461 */
2496         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2497         /* NVIDIA MCP */
2498         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2499         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2500         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2501         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2502         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2503         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2504         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2505         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2506         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2507         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2508         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2509         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2510         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2511         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2512         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2513         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2514         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2515         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2516         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2517         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2518         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2519         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2520         /* Teradici */
2521         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2522         /* Creative X-Fi (CA0110-IBG) */
2523 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2524         /* the following entry conflicts with snd-ctxfi driver,
2525          * as ctxfi driver mutates from HD-audio to native mode with
2526          * a special command sequence.
2527          */
2528         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2529           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2530           .class_mask = 0xffffff,
2531           .driver_data = AZX_DRIVER_GENERIC },
2532 #else
2533         /* this entry seems still valid -- i.e. without emu20kx chip */
2534         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2535 #endif
2536         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2537         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2538           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2539           .class_mask = 0xffffff,
2540           .driver_data = AZX_DRIVER_GENERIC },
2541         { 0, }
2542 };
2543 MODULE_DEVICE_TABLE(pci, azx_ids);
2544
2545 /* pci_driver definition */
2546 static struct pci_driver driver = {
2547         .name = "HDA Intel",
2548         .id_table = azx_ids,
2549         .probe = azx_probe,
2550         .remove = __devexit_p(azx_remove),
2551 #ifdef CONFIG_PM
2552         .suspend = azx_suspend,
2553         .resume = azx_resume,
2554 #endif
2555 };
2556
2557 static int __init alsa_card_azx_init(void)
2558 {
2559         return pci_register_driver(&driver);
2560 }
2561
2562 static void __exit alsa_card_azx_exit(void)
2563 {
2564         pci_unregister_driver(&driver);
2565 }
2566
2567 module_init(alsa_card_azx_init)
2568 module_exit(alsa_card_azx_exit)