sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 142 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 143 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 144 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 145 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 146 #define ICH6_REG_VMIN                   0x02
 147 #define ICH6_REG_VMAJ                   0x03
 148 #define ICH6_REG_OUTPAY                 0x04
 149 #define ICH6_REG_INPAY                  0x06
 150 #define ICH6_REG_GCTL                   0x08
 151 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 152 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 153 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 154 #define ICH6_REG_WAKEEN                 0x0c
 155 #define ICH6_REG_STATESTS               0x0e
 156 #define ICH6_REG_GSTS                   0x10
 157 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 158 #define ICH6_REG_INTCTL                 0x20
 159 #define ICH6_REG_INTSTS                 0x24
 160 #define ICH6_REG_WALCLK                 0x30
 161 #define ICH6_REG_SYNC                   0x34
 162 #define ICH6_REG_CORBLBASE              0x40
 163 #define ICH6_REG_CORBUBASE              0x44
 164 #define ICH6_REG_CORBWP                 0x48
 165 #define ICH6_REG_CORBRP                 0x4a
 166 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 167 #define ICH6_REG_CORBCTL                0x4c
 168 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 169 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 170 #define ICH6_REG_CORBSTS                0x4d
 171 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 172 #define ICH6_REG_CORBSIZE               0x4e
 173
 174 #define ICH6_REG_RIRBLBASE              0x50
 175 #define ICH6_REG_RIRBUBASE              0x54
 176 #define ICH6_REG_RIRBWP                 0x58
 177 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 178 #define ICH6_REG_RINTCNT                0x5a
 179 #define ICH6_REG_RIRBCTL                0x5c
 180 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 181 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 182 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 183 #define ICH6_REG_RIRBSTS                0x5d
 184 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 185 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 186 #define ICH6_REG_RIRBSIZE               0x5e
 187
 188 #define ICH6_REG_IC                     0x60
 189 #define ICH6_REG_IR                     0x64
 190 #define ICH6_REG_IRS                    0x68
 191 #define   ICH6_IRS_VALID        (1<<1)
 192 #define   ICH6_IRS_BUSY         (1<<0)
 193
 194 #define ICH6_REG_DPLBASE                0x70
 195 #define ICH6_REG_DPUBASE                0x74
 196 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 197
 198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 200
 201 /* stream register offsets from stream base */
 202 #define ICH6_REG_SD_CTL                 0x00
 203 #define ICH6_REG_SD_STS                 0x03
 204 #define ICH6_REG_SD_LPIB                0x04
 205 #define ICH6_REG_SD_CBL                 0x08
 206 #define ICH6_REG_SD_LVI                 0x0c
 207 #define ICH6_REG_SD_FIFOW               0x0e
 208 #define ICH6_REG_SD_FIFOSIZE            0x10
 209 #define ICH6_REG_SD_FORMAT              0x12
 210 #define ICH6_REG_SD_BDLPL               0x18
 211 #define ICH6_REG_SD_BDLPU               0x1c
 212
 213 /* PCI space */
 214 #define ICH6_PCIREG_TCSEL       0x44
 215
 216 /*
 217  * other constants
 218  */
 219
 220 /* max number of SDs */
 221 /* ICH, ATI and VIA have 4 playback and 4 capture */
 222 #define ICH6_NUM_CAPTURE        4
 223 #define ICH6_NUM_PLAYBACK       4
 224
 225 /* ULI has 6 playback and 5 capture */
 226 #define ULI_NUM_CAPTURE         5
 227 #define ULI_NUM_PLAYBACK        6
 228
 229 /* ATI HDMI has 1 playback and 0 capture */
 230 #define ATIHDMI_NUM_CAPTURE     0
 231 #define ATIHDMI_NUM_PLAYBACK    1
 232
 233 /* TERA has 4 playback and 3 capture */
 234 #define TERA_NUM_CAPTURE        3
 235 #define TERA_NUM_PLAYBACK       4
 236
 237 /* this number is statically defined for simplicity */
 238 #define MAX_AZX_DEV             16
 239
 240 /* max number of fragments - we may use more if allocating more pages for BDL */
 241 #define BDL_SIZE                4096
 242 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 243 #define AZX_MAX_FRAG            32
 244 /* max buffer size - no h/w limit, you can increase as you like */
 245 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 246 /* max number of PCM devics per card */
 247 #define AZX_MAX_PCMS            8
 248
 249 /* RIRB int mask: overrun[2], response[0] */
 250 #define RIRB_INT_RESPONSE       0x01
 251 #define RIRB_INT_OVERRUN        0x04
 252 #define RIRB_INT_MASK           0x05
 253
 254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 255 #define AZX_MAX_CODECS          4
 256 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 257
 258 /* SD_CTL bits */
 259 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 260 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 261 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 262 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 263 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 264 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 265 #define SD_CTL_STREAM_TAG_SHIFT 20
 266
 267 /* SD_CTL and SD_STS */
 268 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 269 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 270 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 271 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 272                                  SD_INT_COMPLETE)
 273
 274 /* SD_STS */
 275 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 276
 277 /* INTCTL and INTSTS */
 278 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 279 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 280 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 281
 282 /* below are so far hardcoded - should read registers in future */
 283 #define ICH6_MAX_CORB_ENTRIES   256
 284 #define ICH6_MAX_RIRB_ENTRIES   256
 285
 286 /* position fix mode */
 287 enum {
 288         POS_FIX_AUTO,
 289         POS_FIX_LPIB,
 290         POS_FIX_POSBUF,
 291 };
 292
 293 /* Defines for ATI HD Audio support in SB450 south bridge */
 294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 296
 297 /* Defines for Nvidia HDA support */
 298 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 299 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 300 #define NVIDIA_HDA_ISTRM_COH          0x4d
 301 #define NVIDIA_HDA_OSTRM_COH          0x4c
 302 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 303
 304 /* Defines for Intel SCH HDA snoop control */
 305 #define INTEL_SCH_HDA_DEVC      0x78
 306 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 307
 308 /* Define IN stream 0 FIFO size offset in VIA controller */
 309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 310 /* Define VIA HD Audio Device ID*/
 311 #define VIA_HDAC_DEVICE_ID              0x3288
 312
 313 /* HD Audio class code */
 314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 315
 316 /*
 317  */
 318
 319 struct azx_dev {
 320         struct snd_dma_buffer bdl; /* BDL buffer */
 321         u32 *posbuf;            /* position buffer pointer */
 322
 323         unsigned int bufsize;   /* size of the play buffer in bytes */
 324         unsigned int period_bytes; /* size of the period in bytes */
 325         unsigned int frags;     /* number for period in the play buffer */
 326         unsigned int fifo_size; /* FIFO size */
 327         unsigned long start_jiffies;    /* start + minimum jiffies */
 328         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 329
 330         void __iomem *sd_addr;  /* stream descriptor pointer */
 331
 332         u32 sd_int_sta_mask;    /* stream int status mask */
 333
 334         /* pcm support */
 335         struct snd_pcm_substream *substream;    /* assigned substream,
 336                                                  * set in PCM open
 337                                                  */
 338         unsigned int format_val;        /* format value to be set in the
 339                                          * controller and the codec
 340                                          */
 341         unsigned char stream_tag;       /* assigned stream */
 342         unsigned char index;            /* stream index */
 343
 344         unsigned int opened :1;
 345         unsigned int running :1;
 346         unsigned int irq_pending :1;
 347         unsigned int start_flag: 1;     /* stream full start flag */
 348         /*
 349          * For VIA:
 350          *  A flag to ensure DMA position is 0
 351          *  when link position is not greater than FIFO size
 352          */
 353         unsigned int insufficient :1;
 354 };
 355
 356 /* CORB/RIRB */
 357 struct azx_rb {
 358         u32 *buf;               /* CORB/RIRB buffer
 359                                  * Each CORB entry is 4byte, RIRB is 8byte
 360                                  */
 361         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 362         /* for RIRB */
 363         unsigned short rp, wp;  /* read/write pointers */
 364         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 365         u32 res[AZX_MAX_CODECS];        /* last read value */
 366 };
 367
 368 struct azx {
 369         struct snd_card *card;
 370         struct pci_dev *pci;
 371         int dev_index;
 372
 373         /* chip type specific */
 374         int driver_type;
 375         int playback_streams;
 376         int playback_index_offset;
 377         int capture_streams;
 378         int capture_index_offset;
 379         int num_streams;
 380
 381         /* pci resources */
 382         unsigned long addr;
 383         void __iomem *remap_addr;
 384         int irq;
 385
 386         /* locks */
 387         spinlock_t reg_lock;
 388         struct mutex open_mutex;
 389
 390         /* streams (x num_streams) */
 391         struct azx_dev *azx_dev;
 392
 393         /* PCM */
 394         struct snd_pcm *pcm[AZX_MAX_PCMS];
 395
 396         /* HD codec */
 397         unsigned short codec_mask;
 398         int  codec_probe_mask; /* copied from probe_mask option */
 399         struct hda_bus *bus;
 400
 401         /* CORB/RIRB */
 402         struct azx_rb corb;
 403         struct azx_rb rirb;
 404
 405         /* CORB/RIRB and position buffers */
 406         struct snd_dma_buffer rb;
 407         struct snd_dma_buffer posbuf;
 408
 409         /* flags */
 410         int position_fix;
 411         unsigned int running :1;
 412         unsigned int initialized :1;
 413         unsigned int single_cmd :1;
 414         unsigned int polling_mode :1;
 415         unsigned int msi :1;
 416         unsigned int irq_pending_warned :1;
 417         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 418         unsigned int probing :1; /* codec probing phase */
 419
 420         /* for debugging */
 421         unsigned int last_cmd;  /* last issued command (to sync) */
 422
 423         /* for pending irqs */
 424         struct work_struct irq_pending_work;
 425
 426         /* reboot notifier (for mysterious hangup problem at power-down) */
 427         struct notifier_block reboot_notifier;
 428 };
 429
 430 /* driver types */
 431 enum {
 432         AZX_DRIVER_ICH,
 433         AZX_DRIVER_SCH,
 434         AZX_DRIVER_ATI,
 435         AZX_DRIVER_ATIHDMI,
 436         AZX_DRIVER_VIA,
 437         AZX_DRIVER_SIS,
 438         AZX_DRIVER_ULI,
 439         AZX_DRIVER_NVIDIA,
 440         AZX_DRIVER_TERA,
 441         AZX_DRIVER_GENERIC,
 442         AZX_NUM_DRIVERS, /* keep this as last entry */
 443 };
 444
 445 static char *driver_short_names[] __devinitdata = {
 446         [AZX_DRIVER_ICH] = "HDA Intel",
 447         [AZX_DRIVER_SCH] = "HDA Intel MID",
 448         [AZX_DRIVER_ATI] = "HDA ATI SB",
 449         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 450         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 451         [AZX_DRIVER_SIS] = "HDA SIS966",
 452         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 453         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 454         [AZX_DRIVER_TERA] = "HDA Teradici",
 455         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 456 };
 457
 458 /*
 459  * macros for easy use
 460  */
 461 #define azx_writel(chip,reg,value) \
 462         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 463 #define azx_readl(chip,reg) \
 464         readl((chip)->remap_addr + ICH6_REG_##reg)
 465 #define azx_writew(chip,reg,value) \
 466         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 467 #define azx_readw(chip,reg) \
 468         readw((chip)->remap_addr + ICH6_REG_##reg)
 469 #define azx_writeb(chip,reg,value) \
 470         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 471 #define azx_readb(chip,reg) \
 472         readb((chip)->remap_addr + ICH6_REG_##reg)
 473
 474 #define azx_sd_writel(dev,reg,value) \
 475         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 476 #define azx_sd_readl(dev,reg) \
 477         readl((dev)->sd_addr + ICH6_REG_##reg)
 478 #define azx_sd_writew(dev,reg,value) \
 479         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 480 #define azx_sd_readw(dev,reg) \
 481         readw((dev)->sd_addr + ICH6_REG_##reg)
 482 #define azx_sd_writeb(dev,reg,value) \
 483         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 484 #define azx_sd_readb(dev,reg) \
 485         readb((dev)->sd_addr + ICH6_REG_##reg)
 486
 487 /* for pcm support */
 488 #define get_azx_dev(substream) (substream->runtime->private_data)
 489
 490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 491
 492 /*
 493  * Interface for HD codec
 494  */
 495
 496 /*
 497  * CORB / RIRB interface
 498  */
 499 static int azx_alloc_cmd_io(struct azx *chip)
 500 {
 501         int err;
 502
 503         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 504         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 505                                   snd_dma_pci_data(chip->pci),
 506                                   PAGE_SIZE, &chip->rb);
 507         if (err < 0) {
 508                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 509                 return err;
 510         }
 511         return 0;
 512 }
 513
 514 static void azx_init_cmd_io(struct azx *chip)
 515 {
 516         /* CORB set up */
 517         chip->corb.addr = chip->rb.addr;
 518         chip->corb.buf = (u32 *)chip->rb.area;
 519         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 520         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 521
 522         /* set the corb size to 256 entries (ULI requires explicitly) */
 523         azx_writeb(chip, CORBSIZE, 0x02);
 524         /* set the corb write pointer to 0 */
 525         azx_writew(chip, CORBWP, 0);
 526         /* reset the corb hw read pointer */
 527         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 528         /* enable corb dma */
 529         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 530
 531         /* RIRB set up */
 532         chip->rirb.addr = chip->rb.addr + 2048;
 533         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 534         chip->rirb.wp = chip->rirb.rp = 0;
 535         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 536         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 537         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 538
 539         /* set the rirb size to 256 entries (ULI requires explicitly) */
 540         azx_writeb(chip, RIRBSIZE, 0x02);
 541         /* reset the rirb hw write pointer */
 542         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 543         /* set N=1, get RIRB response interrupt for new entry */
 544         azx_writew(chip, RINTCNT, 1);
 545         /* enable rirb dma and response irq */
 546         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 547 }
 548
 549 static void azx_free_cmd_io(struct azx *chip)
 550 {
 551         /* disable ringbuffer DMAs */
 552         azx_writeb(chip, RIRBCTL, 0);
 553         azx_writeb(chip, CORBCTL, 0);
 554 }
 555
 556 static unsigned int azx_command_addr(u32 cmd)
 557 {
 558         unsigned int addr = cmd >> 28;
 559
 560         if (addr >= AZX_MAX_CODECS) {
 561                 snd_BUG();
 562                 addr = 0;
 563         }
 564
 565         return addr;
 566 }
 567
 568 static unsigned int azx_response_addr(u32 res)
 569 {
 570         unsigned int addr = res & 0xf;
 571
 572         if (addr >= AZX_MAX_CODECS) {
 573                 snd_BUG();
 574                 addr = 0;
 575         }
 576
 577         return addr;
 578 }
 579
 580 /* send a command */
 581 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 582 {
 583         struct azx *chip = bus->private_data;
 584         unsigned int addr = azx_command_addr(val);
 585         unsigned int wp;
 586
 587         /* add command to corb */
 588         wp = azx_readb(chip, CORBWP);
 589         wp++;
 590         wp %= ICH6_MAX_CORB_ENTRIES;
 591
 592         spin_lock_irq(&chip->reg_lock);
 593         chip->rirb.cmds[addr]++;
 594         chip->corb.buf[wp] = cpu_to_le32(val);
 595         azx_writel(chip, CORBWP, wp);
 596         spin_unlock_irq(&chip->reg_lock);
 597
 598         return 0;
 599 }
 600
 601 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 602
 603 /* retrieve RIRB entry - called from interrupt handler */
 604 static void azx_update_rirb(struct azx *chip)
 605 {
 606         unsigned int rp, wp;
 607         unsigned int addr;
 608         u32 res, res_ex;
 609
 610         wp = azx_readb(chip, RIRBWP);
 611         if (wp == chip->rirb.wp)
 612                 return;
 613         chip->rirb.wp = wp;
 614
 615         while (chip->rirb.rp != wp) {
 616                 chip->rirb.rp++;
 617                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 618
 619                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 620                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 621                 res = le32_to_cpu(chip->rirb.buf[rp]);
 622                 addr = azx_response_addr(res_ex);
 623                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 624                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 625                 else if (chip->rirb.cmds[addr]) {
 626                         chip->rirb.res[addr] = res;
 627                         smp_wmb();
 628                         chip->rirb.cmds[addr]--;
 629                 }
 630         }
 631 }
 632
 633 /* receive a response */
 634 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 635                                           unsigned int addr)
 636 {
 637         struct azx *chip = bus->private_data;
 638         unsigned long timeout;
 639
 640  again:
 641         timeout = jiffies + msecs_to_jiffies(1000);
 642         for (;;) {
 643                 if (chip->polling_mode) {
 644                         spin_lock_irq(&chip->reg_lock);
 645                         azx_update_rirb(chip);
 646                         spin_unlock_irq(&chip->reg_lock);
 647                 }
 648                 if (!chip->rirb.cmds[addr]) {
 649                         smp_rmb();
 650                         bus->rirb_error = 0;
 651                         return chip->rirb.res[addr]; /* the last value */
 652                 }
 653                 if (time_after(jiffies, timeout))
 654                         break;
 655                 if (bus->needs_damn_long_delay)
 656                         msleep(2); /* temporary workaround */
 657                 else {
 658                         udelay(10);
 659                         cond_resched();
 660                 }
 661         }
 662
 663         if (chip->msi) {
 664                 snd_printk(KERN_WARNING SFX "No response from codec, "
 665                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 666                 free_irq(chip->irq, chip);
 667                 chip->irq = -1;
 668                 pci_disable_msi(chip->pci);
 669                 chip->msi = 0;
 670                 if (azx_acquire_irq(chip, 1) < 0) {
 671                         bus->rirb_error = 1;
 672                         return -1;
 673                 }
 674                 goto again;
 675         }
 676
 677         if (!chip->polling_mode) {
 678                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 679                            "switching to polling mode: last cmd=0x%08x\n",
 680                            chip->last_cmd);
 681                 chip->polling_mode = 1;
 682                 goto again;
 683         }
 684
 685         if (chip->probing) {
 686                 /* If this critical timeout happens during the codec probing
 687                  * phase, this is likely an access to a non-existing codec
 688                  * slot.  Better to return an error and reset the system.
 689                  */
 690                 return -1;
 691         }
 692
 693         /* a fatal communication error; need either to reset or to fallback
 694          * to the single_cmd mode
 695          */
 696         bus->rirb_error = 1;
 697         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 698                 bus->response_reset = 1;
 699                 return -1; /* give a chance to retry */
 700         }
 701
 702         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 703                    "switching to single_cmd mode: last cmd=0x%08x\n",
 704                    chip->last_cmd);
 705         chip->single_cmd = 1;
 706         bus->response_reset = 0;
 707         /* re-initialize CORB/RIRB */
 708         azx_free_cmd_io(chip);
 709         azx_init_cmd_io(chip);
 710         return -1;
 711 }
 712
 713 /*
 714  * Use the single immediate command instead of CORB/RIRB for simplicity
 715  *
 716  * Note: according to Intel, this is not preferred use.  The command was
 717  *       intended for the BIOS only, and may get confused with unsolicited
 718  *       responses.  So, we shouldn't use it for normal operation from the
 719  *       driver.
 720  *       I left the codes, however, for debugging/testing purposes.
 721  */
 722
 723 /* receive a response */
 724 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 725 {
 726         int timeout = 50;
 727
 728         while (timeout--) {
 729                 /* check IRV busy bit */
 730                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 731                         /* reuse rirb.res as the response return value */
 732                         chip->rirb.res[addr] = azx_readl(chip, IR);
 733                         return 0;
 734                 }
 735                 udelay(1);
 736         }
 737         if (printk_ratelimit())
 738                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 739                            azx_readw(chip, IRS));
 740         chip->rirb.res[addr] = -1;
 741         return -EIO;
 742 }
 743
 744 /* send a command */
 745 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 746 {
 747         struct azx *chip = bus->private_data;
 748         unsigned int addr = azx_command_addr(val);
 749         int timeout = 50;
 750
 751         bus->rirb_error = 0;
 752         while (timeout--) {
 753                 /* check ICB busy bit */
 754                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 755                         /* Clear IRV valid bit */
 756                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 757                                    ICH6_IRS_VALID);
 758                         azx_writel(chip, IC, val);
 759                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 760                                    ICH6_IRS_BUSY);
 761                         return azx_single_wait_for_response(chip, addr);
 762                 }
 763                 udelay(1);
 764         }
 765         if (printk_ratelimit())
 766                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 767                            azx_readw(chip, IRS), val);
 768         return -EIO;
 769 }
 770
 771 /* receive a response */
 772 static unsigned int azx_single_get_response(struct hda_bus *bus,
 773                                             unsigned int addr)
 774 {
 775         struct azx *chip = bus->private_data;
 776         return chip->rirb.res[addr];
 777 }
 778
 779 /*
 780  * The below are the main callbacks from hda_codec.
 781  *
 782  * They are just the skeleton to call sub-callbacks according to the
 783  * current setting of chip->single_cmd.
 784  */
 785
 786 /* send a command */
 787 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 788 {
 789         struct azx *chip = bus->private_data;
 790
 791         chip->last_cmd = val;
 792         if (chip->single_cmd)
 793                 return azx_single_send_cmd(bus, val);
 794         else
 795                 return azx_corb_send_cmd(bus, val);
 796 }
 797
 798 /* get a response */
 799 static unsigned int azx_get_response(struct hda_bus *bus,
 800                                      unsigned int addr)
 801 {
 802         struct azx *chip = bus->private_data;
 803         if (chip->single_cmd)
 804                 return azx_single_get_response(bus, addr);
 805         else
 806                 return azx_rirb_get_response(bus, addr);
 807 }
 808
 809 #ifdef CONFIG_SND_HDA_POWER_SAVE
 810 static void azx_power_notify(struct hda_bus *bus);
 811 #endif
 812
 813 /* reset codec link */
 814 static int azx_reset(struct azx *chip)
 815 {
 816         int count;
 817
 818         /* clear STATESTS */
 819         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 820
 821         /* reset controller */
 822         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 823
 824         count = 50;
 825         while (azx_readb(chip, GCTL) && --count)
 826                 msleep(1);
 827
 828         /* delay for >= 100us for codec PLL to settle per spec
 829          * Rev 0.9 section 5.5.1
 830          */
 831         msleep(1);
 832
 833         /* Bring controller out of reset */
 834         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 835
 836         count = 50;
 837         while (!azx_readb(chip, GCTL) && --count)
 838                 msleep(1);
 839
 840         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 841         msleep(1);
 842
 843         /* check to see if controller is ready */
 844         if (!azx_readb(chip, GCTL)) {
 845                 snd_printd(SFX "azx_reset: controller not ready!\n");
 846                 return -EBUSY;
 847         }
 848
 849         /* Accept unsolicited responses */
 850         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
 851
 852         /* detect codecs */
 853         if (!chip->codec_mask) {
 854                 chip->codec_mask = azx_readw(chip, STATESTS);
 855                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 856         }
 857
 858         return 0;
 859 }
 860
 861
 862 /*
 863  * Lowlevel interface
 864  */
 865
 866 /* enable interrupts */
 867 static void azx_int_enable(struct azx *chip)
 868 {
 869         /* enable controller CIE and GIE */
 870         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 871                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 872 }
 873
 874 /* disable interrupts */
 875 static void azx_int_disable(struct azx *chip)
 876 {
 877         int i;
 878
 879         /* disable interrupts in stream descriptor */
 880         for (i = 0; i < chip->num_streams; i++) {
 881                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 882                 azx_sd_writeb(azx_dev, SD_CTL,
 883                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 884         }
 885
 886         /* disable SIE for all streams */
 887         azx_writeb(chip, INTCTL, 0);
 888
 889         /* disable controller CIE and GIE */
 890         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 891                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 892 }
 893
 894 /* clear interrupts */
 895 static void azx_int_clear(struct azx *chip)
 896 {
 897         int i;
 898
 899         /* clear stream status */
 900         for (i = 0; i < chip->num_streams; i++) {
 901                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 902                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 903         }
 904
 905         /* clear STATESTS */
 906         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 907
 908         /* clear rirb status */
 909         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 910
 911         /* clear int status */
 912         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 913 }
 914
 915 /* start a stream */
 916 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 917 {
 918         /*
 919          * Before stream start, initialize parameter
 920          */
 921         azx_dev->insufficient = 1;
 922
 923         /* enable SIE */
 924         azx_writeb(chip, INTCTL,
 925                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 926         /* set DMA start and interrupt mask */
 927         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 928                       SD_CTL_DMA_START | SD_INT_MASK);
 929 }
 930
 931 /* stop DMA */
 932 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 933 {
 934         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 935                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 936         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 937 }
 938
 939 /* stop a stream */
 940 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 941 {
 942         azx_stream_clear(chip, azx_dev);
 943         /* disable SIE */
 944         azx_writeb(chip, INTCTL,
 945                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 946 }
 947
 948
 949 /*
 950  * reset and start the controller registers
 951  */
 952 static void azx_init_chip(struct azx *chip)
 953 {
 954         if (chip->initialized)
 955                 return;
 956
 957         /* reset controller */
 958         azx_reset(chip);
 959
 960         /* initialize interrupts */
 961         azx_int_clear(chip);
 962         azx_int_enable(chip);
 963
 964         /* initialize the codec command I/O */
 965         azx_init_cmd_io(chip);
 966
 967         /* program the position buffer */
 968         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 969         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 970
 971         chip->initialized = 1;
 972 }
 973
 974 /*
 975  * initialize the PCI registers
 976  */
 977 /* update bits in a PCI register byte */
 978 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 979                             unsigned char mask, unsigned char val)
 980 {
 981         unsigned char data;
 982
 983         pci_read_config_byte(pci, reg, &data);
 984         data &= ~mask;
 985         data |= (val & mask);
 986         pci_write_config_byte(pci, reg, data);
 987 }
 988
 989 static void azx_init_pci(struct azx *chip)
 990 {
 991         unsigned short snoop;
 992
 993         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 994          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 995          * Ensuring these bits are 0 clears playback static on some HD Audio
 996          * codecs
 997          */
 998         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 999
1000         switch (chip->driver_type) {
1001         case AZX_DRIVER_ATI:
1002                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1003                 update_pci_byte(chip->pci,
1004                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1005                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1006                 break;
1007         case AZX_DRIVER_NVIDIA:
1008                 /* For NVIDIA HDA, enable snoop */
1009                 update_pci_byte(chip->pci,
1010                                 NVIDIA_HDA_TRANSREG_ADDR,
1011                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1012                 update_pci_byte(chip->pci,
1013                                 NVIDIA_HDA_ISTRM_COH,
1014                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1015                 update_pci_byte(chip->pci,
1016                                 NVIDIA_HDA_OSTRM_COH,
1017                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1018                 break;
1019         case AZX_DRIVER_SCH:
1020                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1021                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1022                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1023                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1024                         pci_read_config_word(chip->pci,
1025                                 INTEL_SCH_HDA_DEVC, &snoop);
1026                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1027                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1028                                 ? "Failed" : "OK");
1029                 }
1030                 break;
1031
1032         }
1033 }
1034
1035
1036 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1037
1038 /*
1039  * interrupt handler
1040  */
1041 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1042 {
1043         struct azx *chip = dev_id;
1044         struct azx_dev *azx_dev;
1045         u32 status;
1046         int i, ok;
1047
1048         spin_lock(&chip->reg_lock);
1049
1050         status = azx_readl(chip, INTSTS);
1051         if (status == 0) {
1052                 spin_unlock(&chip->reg_lock);
1053                 return IRQ_NONE;
1054         }
1055
1056         for (i = 0; i < chip->num_streams; i++) {
1057                 azx_dev = &chip->azx_dev[i];
1058                 if (status & azx_dev->sd_int_sta_mask) {
1059                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1060                         if (!azx_dev->substream || !azx_dev->running)
1061                                 continue;
1062                         /* check whether this IRQ is really acceptable */
1063                         ok = azx_position_ok(chip, azx_dev);
1064                         if (ok == 1) {
1065                                 azx_dev->irq_pending = 0;
1066                                 spin_unlock(&chip->reg_lock);
1067                                 snd_pcm_period_elapsed(azx_dev->substream);
1068                                 spin_lock(&chip->reg_lock);
1069                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1070                                 /* bogus IRQ, process it later */
1071                                 azx_dev->irq_pending = 1;
1072                                 queue_work(chip->bus->workq,
1073                                            &chip->irq_pending_work);
1074                         }
1075                 }
1076         }
1077
1078         /* clear rirb int */
1079         status = azx_readb(chip, RIRBSTS);
1080         if (status & RIRB_INT_MASK) {
1081                 if (status & RIRB_INT_RESPONSE)
1082                         azx_update_rirb(chip);
1083                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1084         }
1085
1086 #if 0
1087         /* clear state status int */
1088         if (azx_readb(chip, STATESTS) & 0x04)
1089                 azx_writeb(chip, STATESTS, 0x04);
1090 #endif
1091         spin_unlock(&chip->reg_lock);
1092
1093         return IRQ_HANDLED;
1094 }
1095
1096
1097 /*
1098  * set up a BDL entry
1099  */
1100 static int setup_bdle(struct snd_pcm_substream *substream,
1101                       struct azx_dev *azx_dev, u32 **bdlp,
1102                       int ofs, int size, int with_ioc)
1103 {
1104         u32 *bdl = *bdlp;
1105
1106         while (size > 0) {
1107                 dma_addr_t addr;
1108                 int chunk;
1109
1110                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1111                         return -EINVAL;
1112
1113                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1114                 /* program the address field of the BDL entry */
1115                 bdl[0] = cpu_to_le32((u32)addr);
1116                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1117                 /* program the size field of the BDL entry */
1118                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1119                 bdl[2] = cpu_to_le32(chunk);
1120                 /* program the IOC to enable interrupt
1121                  * only when the whole fragment is processed
1122                  */
1123                 size -= chunk;
1124                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1125                 bdl += 4;
1126                 azx_dev->frags++;
1127                 ofs += chunk;
1128         }
1129         *bdlp = bdl;
1130         return ofs;
1131 }
1132
1133 /*
1134  * set up BDL entries
1135  */
1136 static int azx_setup_periods(struct azx *chip,
1137                              struct snd_pcm_substream *substream,
1138                              struct azx_dev *azx_dev)
1139 {
1140         u32 *bdl;
1141         int i, ofs, periods, period_bytes;
1142         int pos_adj;
1143
1144         /* reset BDL address */
1145         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1146         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1147
1148         period_bytes = azx_dev->period_bytes;
1149         periods = azx_dev->bufsize / period_bytes;
1150
1151         /* program the initial BDL entries */
1152         bdl = (u32 *)azx_dev->bdl.area;
1153         ofs = 0;
1154         azx_dev->frags = 0;
1155         pos_adj = bdl_pos_adj[chip->dev_index];
1156         if (pos_adj > 0) {
1157                 struct snd_pcm_runtime *runtime = substream->runtime;
1158                 int pos_align = pos_adj;
1159                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1160                 if (!pos_adj)
1161                         pos_adj = pos_align;
1162                 else
1163                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1164                                 pos_align;
1165                 pos_adj = frames_to_bytes(runtime, pos_adj);
1166                 if (pos_adj >= period_bytes) {
1167                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1168                                    bdl_pos_adj[chip->dev_index]);
1169                         pos_adj = 0;
1170                 } else {
1171                         ofs = setup_bdle(substream, azx_dev,
1172                                          &bdl, ofs, pos_adj, 1);
1173                         if (ofs < 0)
1174                                 goto error;
1175                 }
1176         } else
1177                 pos_adj = 0;
1178         for (i = 0; i < periods; i++) {
1179                 if (i == periods - 1 && pos_adj)
1180                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1181                                          period_bytes - pos_adj, 0);
1182                 else
1183                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1184                                          period_bytes, 1);
1185                 if (ofs < 0)
1186                         goto error;
1187         }
1188         return 0;
1189
1190  error:
1191         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1192                    azx_dev->bufsize, period_bytes);
1193         return -EINVAL;
1194 }
1195
1196 /* reset stream */
1197 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1198 {
1199         unsigned char val;
1200         int timeout;
1201
1202         azx_stream_clear(chip, azx_dev);
1203
1204         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1205                       SD_CTL_STREAM_RESET);
1206         udelay(3);
1207         timeout = 300;
1208         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1209                --timeout)
1210                 ;
1211         val &= ~SD_CTL_STREAM_RESET;
1212         azx_sd_writeb(azx_dev, SD_CTL, val);
1213         udelay(3);
1214
1215         timeout = 300;
1216         /* waiting for hardware to report that the stream is out of reset */
1217         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1218                --timeout)
1219                 ;
1220
1221         /* reset first position - may not be synced with hw at this time */
1222         *azx_dev->posbuf = 0;
1223 }
1224
1225 /*
1226  * set up the SD for streaming
1227  */
1228 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1229 {
1230         /* make sure the run bit is zero for SD */
1231         azx_stream_clear(chip, azx_dev);
1232         /* program the stream_tag */
1233         azx_sd_writel(azx_dev, SD_CTL,
1234                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1235                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1236
1237         /* program the length of samples in cyclic buffer */
1238         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1239
1240         /* program the stream format */
1241         /* this value needs to be the same as the one programmed */
1242         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1243
1244         /* program the stream LVI (last valid index) of the BDL */
1245         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1246
1247         /* program the BDL address */
1248         /* lower BDL address */
1249         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1250         /* upper BDL address */
1251         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1252
1253         /* enable the position buffer */
1254         if (chip->position_fix == POS_FIX_POSBUF ||
1255             chip->position_fix == POS_FIX_AUTO ||
1256             chip->via_dmapos_patch) {
1257                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1258                         azx_writel(chip, DPLBASE,
1259                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1260         }
1261
1262         /* set the interrupt enable bits in the descriptor control register */
1263         azx_sd_writel(azx_dev, SD_CTL,
1264                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1265
1266         return 0;
1267 }
1268
1269 /*
1270  * Probe the given codec address
1271  */
1272 static int probe_codec(struct azx *chip, int addr)
1273 {
1274         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1275                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1276         unsigned int res;
1277
1278         mutex_lock(&chip->bus->cmd_mutex);
1279         chip->probing = 1;
1280         azx_send_cmd(chip->bus, cmd);
1281         res = azx_get_response(chip->bus, addr);
1282         chip->probing = 0;
1283         mutex_unlock(&chip->bus->cmd_mutex);
1284         if (res == -1)
1285                 return -EIO;
1286         snd_printdd(SFX "codec #%d probed OK\n", addr);
1287         return 0;
1288 }
1289
1290 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1291                                  struct hda_pcm *cpcm);
1292 static void azx_stop_chip(struct azx *chip);
1293
1294 static void azx_bus_reset(struct hda_bus *bus)
1295 {
1296         struct azx *chip = bus->private_data;
1297
1298         bus->in_reset = 1;
1299         azx_stop_chip(chip);
1300         azx_init_chip(chip);
1301 #ifdef CONFIG_PM
1302         if (chip->initialized) {
1303                 int i;
1304
1305                 for (i = 0; i < AZX_MAX_PCMS; i++)
1306                         snd_pcm_suspend_all(chip->pcm[i]);
1307                 snd_hda_suspend(chip->bus);
1308                 snd_hda_resume(chip->bus);
1309         }
1310 #endif
1311         bus->in_reset = 0;
1312 }
1313
1314 /*
1315  * Codec initialization
1316  */
1317
1318 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1319 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1320         [AZX_DRIVER_TERA] = 1,
1321 };
1322
1323 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1324                                       int no_init)
1325 {
1326         struct hda_bus_template bus_temp;
1327         int c, codecs, err;
1328         int max_slots;
1329
1330         memset(&bus_temp, 0, sizeof(bus_temp));
1331         bus_temp.private_data = chip;
1332         bus_temp.modelname = model;
1333         bus_temp.pci = chip->pci;
1334         bus_temp.ops.command = azx_send_cmd;
1335         bus_temp.ops.get_response = azx_get_response;
1336         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1337         bus_temp.ops.bus_reset = azx_bus_reset;
1338 #ifdef CONFIG_SND_HDA_POWER_SAVE
1339         bus_temp.power_save = &power_save;
1340         bus_temp.ops.pm_notify = azx_power_notify;
1341 #endif
1342
1343         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1344         if (err < 0)
1345                 return err;
1346
1347         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1348                 chip->bus->needs_damn_long_delay = 1;
1349
1350         codecs = 0;
1351         max_slots = azx_max_codecs[chip->driver_type];
1352         if (!max_slots)
1353                 max_slots = AZX_MAX_CODECS;
1354
1355         /* First try to probe all given codec slots */
1356         for (c = 0; c < max_slots; c++) {
1357                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1358                         if (probe_codec(chip, c) < 0) {
1359                                 /* Some BIOSen give you wrong codec addresses
1360                                  * that don't exist
1361                                  */
1362                                 snd_printk(KERN_WARNING SFX
1363                                            "Codec #%d probe error; "
1364                                            "disabling it...\n", c);
1365                                 chip->codec_mask &= ~(1 << c);
1366                                 /* More badly, accessing to a non-existing
1367                                  * codec often screws up the controller chip,
1368                                  * and distrubs the further communications.
1369                                  * Thus if an error occurs during probing,
1370                                  * better to reset the controller chip to
1371                                  * get back to the sanity state.
1372                                  */
1373                                 azx_stop_chip(chip);
1374                                 azx_init_chip(chip);
1375                         }
1376                 }
1377         }
1378
1379         /* Then create codec instances */
1380         for (c = 0; c < max_slots; c++) {
1381                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1382                         struct hda_codec *codec;
1383                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1384                         if (err < 0)
1385                                 continue;
1386                         codecs++;
1387                 }
1388         }
1389         if (!codecs) {
1390                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1391                 return -ENXIO;
1392         }
1393
1394         return 0;
1395 }
1396
1397
1398 /*
1399  * PCM support
1400  */
1401
1402 /* assign a stream for the PCM */
1403 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1404 {
1405         int dev, i, nums;
1406         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1407                 dev = chip->playback_index_offset;
1408                 nums = chip->playback_streams;
1409         } else {
1410                 dev = chip->capture_index_offset;
1411                 nums = chip->capture_streams;
1412         }
1413         for (i = 0; i < nums; i++, dev++)
1414                 if (!chip->azx_dev[dev].opened) {
1415                         chip->azx_dev[dev].opened = 1;
1416                         return &chip->azx_dev[dev];
1417                 }
1418         return NULL;
1419 }
1420
1421 /* release the assigned stream */
1422 static inline void azx_release_device(struct azx_dev *azx_dev)
1423 {
1424         azx_dev->opened = 0;
1425 }
1426
1427 static struct snd_pcm_hardware azx_pcm_hw = {
1428         .info =                 (SNDRV_PCM_INFO_MMAP |
1429                                  SNDRV_PCM_INFO_INTERLEAVED |
1430                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1431                                  SNDRV_PCM_INFO_MMAP_VALID |
1432                                  /* No full-resume yet implemented */
1433                                  /* SNDRV_PCM_INFO_RESUME |*/
1434                                  SNDRV_PCM_INFO_PAUSE |
1435                                  SNDRV_PCM_INFO_SYNC_START),
1436         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1437         .rates =                SNDRV_PCM_RATE_48000,
1438         .rate_min =             48000,
1439         .rate_max =             48000,
1440         .channels_min =         2,
1441         .channels_max =         2,
1442         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1443         .period_bytes_min =     128,
1444         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1445         .periods_min =          2,
1446         .periods_max =          AZX_MAX_FRAG,
1447         .fifo_size =            0,
1448 };
1449
1450 struct azx_pcm {
1451         struct azx *chip;
1452         struct hda_codec *codec;
1453         struct hda_pcm_stream *hinfo[2];
1454 };
1455
1456 static int azx_pcm_open(struct snd_pcm_substream *substream)
1457 {
1458         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1459         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1460         struct azx *chip = apcm->chip;
1461         struct azx_dev *azx_dev;
1462         struct snd_pcm_runtime *runtime = substream->runtime;
1463         unsigned long flags;
1464         int err;
1465
1466         mutex_lock(&chip->open_mutex);
1467         azx_dev = azx_assign_device(chip, substream->stream);
1468         if (azx_dev == NULL) {
1469                 mutex_unlock(&chip->open_mutex);
1470                 return -EBUSY;
1471         }
1472         runtime->hw = azx_pcm_hw;
1473         runtime->hw.channels_min = hinfo->channels_min;
1474         runtime->hw.channels_max = hinfo->channels_max;
1475         runtime->hw.formats = hinfo->formats;
1476         runtime->hw.rates = hinfo->rates;
1477         snd_pcm_limit_hw_rates(runtime);
1478         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1479         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1480                                    128);
1481         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1482                                    128);
1483         snd_hda_power_up(apcm->codec);
1484         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1485         if (err < 0) {
1486                 azx_release_device(azx_dev);
1487                 snd_hda_power_down(apcm->codec);
1488                 mutex_unlock(&chip->open_mutex);
1489                 return err;
1490         }
1491         snd_pcm_limit_hw_rates(runtime);
1492         /* sanity check */
1493         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1494             snd_BUG_ON(!runtime->hw.channels_max) ||
1495             snd_BUG_ON(!runtime->hw.formats) ||
1496             snd_BUG_ON(!runtime->hw.rates)) {
1497                 azx_release_device(azx_dev);
1498                 hinfo->ops.close(hinfo, apcm->codec, substream);
1499                 snd_hda_power_down(apcm->codec);
1500                 mutex_unlock(&chip->open_mutex);
1501                 return -EINVAL;
1502         }
1503         spin_lock_irqsave(&chip->reg_lock, flags);
1504         azx_dev->substream = substream;
1505         azx_dev->running = 0;
1506         spin_unlock_irqrestore(&chip->reg_lock, flags);
1507
1508         runtime->private_data = azx_dev;
1509         snd_pcm_set_sync(substream);
1510         mutex_unlock(&chip->open_mutex);
1511         return 0;
1512 }
1513
1514 static int azx_pcm_close(struct snd_pcm_substream *substream)
1515 {
1516         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1517         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1518         struct azx *chip = apcm->chip;
1519         struct azx_dev *azx_dev = get_azx_dev(substream);
1520         unsigned long flags;
1521
1522         mutex_lock(&chip->open_mutex);
1523         spin_lock_irqsave(&chip->reg_lock, flags);
1524         azx_dev->substream = NULL;
1525         azx_dev->running = 0;
1526         spin_unlock_irqrestore(&chip->reg_lock, flags);
1527         azx_release_device(azx_dev);
1528         hinfo->ops.close(hinfo, apcm->codec, substream);
1529         snd_hda_power_down(apcm->codec);
1530         mutex_unlock(&chip->open_mutex);
1531         return 0;
1532 }
1533
1534 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1535                              struct snd_pcm_hw_params *hw_params)
1536 {
1537         struct azx_dev *azx_dev = get_azx_dev(substream);
1538
1539         azx_dev->bufsize = 0;
1540         azx_dev->period_bytes = 0;
1541         azx_dev->format_val = 0;
1542         return snd_pcm_lib_malloc_pages(substream,
1543                                         params_buffer_bytes(hw_params));
1544 }
1545
1546 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1547 {
1548         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1549         struct azx_dev *azx_dev = get_azx_dev(substream);
1550         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1551
1552         /* reset BDL address */
1553         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1554         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1555         azx_sd_writel(azx_dev, SD_CTL, 0);
1556         azx_dev->bufsize = 0;
1557         azx_dev->period_bytes = 0;
1558         azx_dev->format_val = 0;
1559
1560         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1561
1562         return snd_pcm_lib_free_pages(substream);
1563 }
1564
1565 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1566 {
1567         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1568         struct azx *chip = apcm->chip;
1569         struct azx_dev *azx_dev = get_azx_dev(substream);
1570         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1571         struct snd_pcm_runtime *runtime = substream->runtime;
1572         unsigned int bufsize, period_bytes, format_val;
1573         int err;
1574
1575         azx_stream_reset(chip, azx_dev);
1576         format_val = snd_hda_calc_stream_format(runtime->rate,
1577                                                 runtime->channels,
1578                                                 runtime->format,
1579                                                 hinfo->maxbps);
1580         if (!format_val) {
1581                 snd_printk(KERN_ERR SFX
1582                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1583                            runtime->rate, runtime->channels, runtime->format);
1584                 return -EINVAL;
1585         }
1586
1587         bufsize = snd_pcm_lib_buffer_bytes(substream);
1588         period_bytes = snd_pcm_lib_period_bytes(substream);
1589
1590         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1591                     bufsize, format_val);
1592
1593         if (bufsize != azx_dev->bufsize ||
1594             period_bytes != azx_dev->period_bytes ||
1595             format_val != azx_dev->format_val) {
1596                 azx_dev->bufsize = bufsize;
1597                 azx_dev->period_bytes = period_bytes;
1598                 azx_dev->format_val = format_val;
1599                 err = azx_setup_periods(chip, substream, azx_dev);
1600                 if (err < 0)
1601                         return err;
1602         }
1603
1604         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1605                                                 (runtime->rate * 2);
1606         azx_setup_controller(chip, azx_dev);
1607         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1608                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1609         else
1610                 azx_dev->fifo_size = 0;
1611
1612         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1613                                   azx_dev->format_val, substream);
1614 }
1615
1616 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1617 {
1618         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1619         struct azx *chip = apcm->chip;
1620         struct azx_dev *azx_dev;
1621         struct snd_pcm_substream *s;
1622         int rstart = 0, start, nsync = 0, sbits = 0;
1623         int nwait, timeout;
1624
1625         switch (cmd) {
1626         case SNDRV_PCM_TRIGGER_START:
1627                 rstart = 1;
1628         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1629         case SNDRV_PCM_TRIGGER_RESUME:
1630                 start = 1;
1631                 break;
1632         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1633         case SNDRV_PCM_TRIGGER_SUSPEND:
1634         case SNDRV_PCM_TRIGGER_STOP:
1635                 start = 0;
1636                 break;
1637         default:
1638                 return -EINVAL;
1639         }
1640
1641         snd_pcm_group_for_each_entry(s, substream) {
1642                 if (s->pcm->card != substream->pcm->card)
1643                         continue;
1644                 azx_dev = get_azx_dev(s);
1645                 sbits |= 1 << azx_dev->index;
1646                 nsync++;
1647                 snd_pcm_trigger_done(s, substream);
1648         }
1649
1650         spin_lock(&chip->reg_lock);
1651         if (nsync > 1) {
1652                 /* first, set SYNC bits of corresponding streams */
1653                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1654         }
1655         snd_pcm_group_for_each_entry(s, substream) {
1656                 if (s->pcm->card != substream->pcm->card)
1657                         continue;
1658                 azx_dev = get_azx_dev(s);
1659                 if (rstart) {
1660                         azx_dev->start_flag = 1;
1661                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1662                 }
1663                 if (start)
1664                         azx_stream_start(chip, azx_dev);
1665                 else
1666                         azx_stream_stop(chip, azx_dev);
1667                 azx_dev->running = start;
1668         }
1669         spin_unlock(&chip->reg_lock);
1670         if (start) {
1671                 if (nsync == 1)
1672                         return 0;
1673                 /* wait until all FIFOs get ready */
1674                 for (timeout = 5000; timeout; timeout--) {
1675                         nwait = 0;
1676                         snd_pcm_group_for_each_entry(s, substream) {
1677                                 if (s->pcm->card != substream->pcm->card)
1678                                         continue;
1679                                 azx_dev = get_azx_dev(s);
1680                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1681                                       SD_STS_FIFO_READY))
1682                                         nwait++;
1683                         }
1684                         if (!nwait)
1685                                 break;
1686                         cpu_relax();
1687                 }
1688         } else {
1689                 /* wait until all RUN bits are cleared */
1690                 for (timeout = 5000; timeout; timeout--) {
1691                         nwait = 0;
1692                         snd_pcm_group_for_each_entry(s, substream) {
1693                                 if (s->pcm->card != substream->pcm->card)
1694                                         continue;
1695                                 azx_dev = get_azx_dev(s);
1696                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1697                                     SD_CTL_DMA_START)
1698                                         nwait++;
1699                         }
1700                         if (!nwait)
1701                                 break;
1702                         cpu_relax();
1703                 }
1704         }
1705         if (nsync > 1) {
1706                 spin_lock(&chip->reg_lock);
1707                 /* reset SYNC bits */
1708                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1709                 spin_unlock(&chip->reg_lock);
1710         }
1711         return 0;
1712 }
1713
1714 /* get the current DMA position with correction on VIA chips */
1715 static unsigned int azx_via_get_position(struct azx *chip,
1716                                          struct azx_dev *azx_dev)
1717 {
1718         unsigned int link_pos, mini_pos, bound_pos;
1719         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1720         unsigned int fifo_size;
1721
1722         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1723         if (azx_dev->index >= 4) {
1724                 /* Playback, no problem using link position */
1725                 return link_pos;
1726         }
1727
1728         /* Capture */
1729         /* For new chipset,
1730          * use mod to get the DMA position just like old chipset
1731          */
1732         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1733         mod_dma_pos %= azx_dev->period_bytes;
1734
1735         /* azx_dev->fifo_size can't get FIFO size of in stream.
1736          * Get from base address + offset.
1737          */
1738         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1739
1740         if (azx_dev->insufficient) {
1741                 /* Link position never gather than FIFO size */
1742                 if (link_pos <= fifo_size)
1743                         return 0;
1744
1745                 azx_dev->insufficient = 0;
1746         }
1747
1748         if (link_pos <= fifo_size)
1749                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1750         else
1751                 mini_pos = link_pos - fifo_size;
1752
1753         /* Find nearest previous boudary */
1754         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1755         mod_link_pos = link_pos % azx_dev->period_bytes;
1756         if (mod_link_pos >= fifo_size)
1757                 bound_pos = link_pos - mod_link_pos;
1758         else if (mod_dma_pos >= mod_mini_pos)
1759                 bound_pos = mini_pos - mod_mini_pos;
1760         else {
1761                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1762                 if (bound_pos >= azx_dev->bufsize)
1763                         bound_pos = 0;
1764         }
1765
1766         /* Calculate real DMA position we want */
1767         return bound_pos + mod_dma_pos;
1768 }
1769
1770 static unsigned int azx_get_position(struct azx *chip,
1771                                      struct azx_dev *azx_dev)
1772 {
1773         unsigned int pos;
1774
1775         if (chip->via_dmapos_patch)
1776                 pos = azx_via_get_position(chip, azx_dev);
1777         else if (chip->position_fix == POS_FIX_POSBUF ||
1778                  chip->position_fix == POS_FIX_AUTO) {
1779                 /* use the position buffer */
1780                 pos = le32_to_cpu(*azx_dev->posbuf);
1781         } else {
1782                 /* read LPIB */
1783                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1784         }
1785         if (pos >= azx_dev->bufsize)
1786                 pos = 0;
1787         return pos;
1788 }
1789
1790 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1791 {
1792         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1793         struct azx *chip = apcm->chip;
1794         struct azx_dev *azx_dev = get_azx_dev(substream);
1795         return bytes_to_frames(substream->runtime,
1796                                azx_get_position(chip, azx_dev));
1797 }
1798
1799 /*
1800  * Check whether the current DMA position is acceptable for updating
1801  * periods.  Returns non-zero if it's OK.
1802  *
1803  * Many HD-audio controllers appear pretty inaccurate about
1804  * the update-IRQ timing.  The IRQ is issued before actually the
1805  * data is processed.  So, we need to process it afterwords in a
1806  * workqueue.
1807  */
1808 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1809 {
1810         unsigned int pos;
1811
1812         if (azx_dev->start_flag &&
1813             time_before_eq(jiffies, azx_dev->start_jiffies))
1814                 return -1;      /* bogus (too early) interrupt */
1815         azx_dev->start_flag = 0;
1816
1817         pos = azx_get_position(chip, azx_dev);
1818         if (chip->position_fix == POS_FIX_AUTO) {
1819                 if (!pos) {
1820                         printk(KERN_WARNING
1821                                "hda-intel: Invalid position buffer, "
1822                                "using LPIB read method instead.\n");
1823                         chip->position_fix = POS_FIX_LPIB;
1824                         pos = azx_get_position(chip, azx_dev);
1825                 } else
1826                         chip->position_fix = POS_FIX_POSBUF;
1827         }
1828
1829         if (!bdl_pos_adj[chip->dev_index])
1830                 return 1; /* no delayed ack */
1831         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1832                 return 0; /* NG - it's below the period boundary */
1833         return 1; /* OK, it's fine */
1834 }
1835
1836 /*
1837  * The work for pending PCM period updates.
1838  */
1839 static void azx_irq_pending_work(struct work_struct *work)
1840 {
1841         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1842         int i, pending;
1843
1844         if (!chip->irq_pending_warned) {
1845                 printk(KERN_WARNING
1846                        "hda-intel: IRQ timing workaround is activated "
1847                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1848                        chip->card->number);
1849                 chip->irq_pending_warned = 1;
1850         }
1851
1852         for (;;) {
1853                 pending = 0;
1854                 spin_lock_irq(&chip->reg_lock);
1855                 for (i = 0; i < chip->num_streams; i++) {
1856                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1857                         if (!azx_dev->irq_pending ||
1858                             !azx_dev->substream ||
1859                             !azx_dev->running)
1860                                 continue;
1861                         if (azx_position_ok(chip, azx_dev)) {
1862                                 azx_dev->irq_pending = 0;
1863                                 spin_unlock(&chip->reg_lock);
1864                                 snd_pcm_period_elapsed(azx_dev->substream);
1865                                 spin_lock(&chip->reg_lock);
1866                         } else
1867                                 pending++;
1868                 }
1869                 spin_unlock_irq(&chip->reg_lock);
1870                 if (!pending)
1871                         return;
1872                 cond_resched();
1873         }
1874 }
1875
1876 /* clear irq_pending flags and assure no on-going workq */
1877 static void azx_clear_irq_pending(struct azx *chip)
1878 {
1879         int i;
1880
1881         spin_lock_irq(&chip->reg_lock);
1882         for (i = 0; i < chip->num_streams; i++)
1883                 chip->azx_dev[i].irq_pending = 0;
1884         spin_unlock_irq(&chip->reg_lock);
1885 }
1886
1887 static struct snd_pcm_ops azx_pcm_ops = {
1888         .open = azx_pcm_open,
1889         .close = azx_pcm_close,
1890         .ioctl = snd_pcm_lib_ioctl,
1891         .hw_params = azx_pcm_hw_params,
1892         .hw_free = azx_pcm_hw_free,
1893         .prepare = azx_pcm_prepare,
1894         .trigger = azx_pcm_trigger,
1895         .pointer = azx_pcm_pointer,
1896         .page = snd_pcm_sgbuf_ops_page,
1897 };
1898
1899 static void azx_pcm_free(struct snd_pcm *pcm)
1900 {
1901         struct azx_pcm *apcm = pcm->private_data;
1902         if (apcm) {
1903                 apcm->chip->pcm[pcm->device] = NULL;
1904                 kfree(apcm);
1905         }
1906 }
1907
1908 static int
1909 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1910                       struct hda_pcm *cpcm)
1911 {
1912         struct azx *chip = bus->private_data;
1913         struct snd_pcm *pcm;
1914         struct azx_pcm *apcm;
1915         int pcm_dev = cpcm->device;
1916         int s, err;
1917
1918         if (pcm_dev >= AZX_MAX_PCMS) {
1919                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1920                            pcm_dev);
1921                 return -EINVAL;
1922         }
1923         if (chip->pcm[pcm_dev]) {
1924                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1925                 return -EBUSY;
1926         }
1927         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1928                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1929                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1930                           &pcm);
1931         if (err < 0)
1932                 return err;
1933         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1934         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1935         if (apcm == NULL)
1936                 return -ENOMEM;
1937         apcm->chip = chip;
1938         apcm->codec = codec;
1939         pcm->private_data = apcm;
1940         pcm->private_free = azx_pcm_free;
1941         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1942                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1943         chip->pcm[pcm_dev] = pcm;
1944         cpcm->pcm = pcm;
1945         for (s = 0; s < 2; s++) {
1946                 apcm->hinfo[s] = &cpcm->stream[s];
1947                 if (cpcm->stream[s].substreams)
1948                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1949         }
1950         /* buffer pre-allocation */
1951         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1952                                               snd_dma_pci_data(chip->pci),
1953                                               1024 * 64, 32 * 1024 * 1024);
1954         return 0;
1955 }
1956
1957 /*
1958  * mixer creation - all stuff is implemented in hda module
1959  */
1960 static int __devinit azx_mixer_create(struct azx *chip)
1961 {
1962         return snd_hda_build_controls(chip->bus);
1963 }
1964
1965
1966 /*
1967  * initialize SD streams
1968  */
1969 static int __devinit azx_init_stream(struct azx *chip)
1970 {
1971         int i;
1972
1973         /* initialize each stream (aka device)
1974          * assign the starting bdl address to each stream (device)
1975          * and initialize
1976          */
1977         for (i = 0; i < chip->num_streams; i++) {
1978                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1979                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1980                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1981                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1982                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1983                 azx_dev->sd_int_sta_mask = 1 << i;
1984                 /* stream tag: must be non-zero and unique */
1985                 azx_dev->index = i;
1986                 azx_dev->stream_tag = i + 1;
1987         }
1988
1989         return 0;
1990 }
1991
1992 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1993 {
1994         if (request_irq(chip->pci->irq, azx_interrupt,
1995                         chip->msi ? 0 : IRQF_SHARED,
1996                         "HDA Intel", chip)) {
1997                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1998                        "disabling device\n", chip->pci->irq);
1999                 if (do_disconnect)
2000                         snd_card_disconnect(chip->card);
2001                 return -1;
2002         }
2003         chip->irq = chip->pci->irq;
2004         pci_intx(chip->pci, !chip->msi);
2005         return 0;
2006 }
2007
2008
2009 static void azx_stop_chip(struct azx *chip)
2010 {
2011         if (!chip->initialized)
2012                 return;
2013
2014         /* disable interrupts */
2015         azx_int_disable(chip);
2016         azx_int_clear(chip);
2017
2018         /* disable CORB/RIRB */
2019         azx_free_cmd_io(chip);
2020
2021         /* disable position buffer */
2022         azx_writel(chip, DPLBASE, 0);
2023         azx_writel(chip, DPUBASE, 0);
2024
2025         chip->initialized = 0;
2026 }
2027
2028 #ifdef CONFIG_SND_HDA_POWER_SAVE
2029 /* power-up/down the controller */
2030 static void azx_power_notify(struct hda_bus *bus)
2031 {
2032         struct azx *chip = bus->private_data;
2033         struct hda_codec *c;
2034         int power_on = 0;
2035
2036         list_for_each_entry(c, &bus->codec_list, list) {
2037                 if (c->power_on) {
2038                         power_on = 1;
2039                         break;
2040                 }
2041         }
2042         if (power_on)
2043                 azx_init_chip(chip);
2044         else if (chip->running && power_save_controller)
2045                 azx_stop_chip(chip);
2046 }
2047 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2048
2049 #ifdef CONFIG_PM
2050 /*
2051  * power management
2052  */
2053
2054 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2055 {
2056         struct hda_codec *codec;
2057
2058         list_for_each_entry(codec, &bus->codec_list, list) {
2059                 if (snd_hda_codec_needs_resume(codec))
2060                         return 1;
2061         }
2062         return 0;
2063 }
2064
2065 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2066 {
2067         struct snd_card *card = pci_get_drvdata(pci);
2068         struct azx *chip = card->private_data;
2069         int i;
2070
2071         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2072         azx_clear_irq_pending(chip);
2073         for (i = 0; i < AZX_MAX_PCMS; i++)
2074                 snd_pcm_suspend_all(chip->pcm[i]);
2075         if (chip->initialized)
2076                 snd_hda_suspend(chip->bus);
2077         azx_stop_chip(chip);
2078         if (chip->irq >= 0) {
2079                 free_irq(chip->irq, chip);
2080                 chip->irq = -1;
2081         }
2082         if (chip->msi)
2083                 pci_disable_msi(chip->pci);
2084         pci_disable_device(pci);
2085         pci_save_state(pci);
2086         pci_set_power_state(pci, pci_choose_state(pci, state));
2087         return 0;
2088 }
2089
2090 static int azx_resume(struct pci_dev *pci)
2091 {
2092         struct snd_card *card = pci_get_drvdata(pci);
2093         struct azx *chip = card->private_data;
2094
2095         pci_set_power_state(pci, PCI_D0);
2096         pci_restore_state(pci);
2097         if (pci_enable_device(pci) < 0) {
2098                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2099                        "disabling device\n");
2100                 snd_card_disconnect(card);
2101                 return -EIO;
2102         }
2103         pci_set_master(pci);
2104         if (chip->msi)
2105                 if (pci_enable_msi(pci) < 0)
2106                         chip->msi = 0;
2107         if (azx_acquire_irq(chip, 1) < 0)
2108                 return -EIO;
2109         azx_init_pci(chip);
2110
2111         if (snd_hda_codecs_inuse(chip->bus))
2112                 azx_init_chip(chip);
2113
2114         snd_hda_resume(chip->bus);
2115         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2116         return 0;
2117 }
2118 #endif /* CONFIG_PM */
2119
2120
2121 /*
2122  * reboot notifier for hang-up problem at power-down
2123  */
2124 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2125 {
2126         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2127         azx_stop_chip(chip);
2128         return NOTIFY_OK;
2129 }
2130
2131 static void azx_notifier_register(struct azx *chip)
2132 {
2133         chip->reboot_notifier.notifier_call = azx_halt;
2134         register_reboot_notifier(&chip->reboot_notifier);
2135 }
2136
2137 static void azx_notifier_unregister(struct azx *chip)
2138 {
2139         if (chip->reboot_notifier.notifier_call)
2140                 unregister_reboot_notifier(&chip->reboot_notifier);
2141 }
2142
2143 /*
2144  * destructor
2145  */
2146 static int azx_free(struct azx *chip)
2147 {
2148         int i;
2149
2150         azx_notifier_unregister(chip);
2151
2152         if (chip->initialized) {
2153                 azx_clear_irq_pending(chip);
2154                 for (i = 0; i < chip->num_streams; i++)
2155                         azx_stream_stop(chip, &chip->azx_dev[i]);
2156                 azx_stop_chip(chip);
2157         }
2158
2159         if (chip->irq >= 0)
2160                 free_irq(chip->irq, (void*)chip);
2161         if (chip->msi)
2162                 pci_disable_msi(chip->pci);
2163         if (chip->remap_addr)
2164                 iounmap(chip->remap_addr);
2165
2166         if (chip->azx_dev) {
2167                 for (i = 0; i < chip->num_streams; i++)
2168                         if (chip->azx_dev[i].bdl.area)
2169                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2170         }
2171         if (chip->rb.area)
2172                 snd_dma_free_pages(&chip->rb);
2173         if (chip->posbuf.area)
2174                 snd_dma_free_pages(&chip->posbuf);
2175         pci_release_regions(chip->pci);
2176         pci_disable_device(chip->pci);
2177         kfree(chip->azx_dev);
2178         kfree(chip);
2179
2180         return 0;
2181 }
2182
2183 static int azx_dev_free(struct snd_device *device)
2184 {
2185         return azx_free(device->device_data);
2186 }
2187
2188 /*
2189  * white/black-listing for position_fix
2190  */
2191 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2192         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2193         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2194         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2195         {}
2196 };
2197
2198 static int __devinit check_position_fix(struct azx *chip, int fix)
2199 {
2200         const struct snd_pci_quirk *q;
2201
2202         switch (fix) {
2203         case POS_FIX_LPIB:
2204         case POS_FIX_POSBUF:
2205                 return fix;
2206         }
2207
2208         /* Check VIA/ATI HD Audio Controller exist */
2209         switch (chip->driver_type) {
2210         case AZX_DRIVER_VIA:
2211         case AZX_DRIVER_ATI:
2212                 chip->via_dmapos_patch = 1;
2213                 /* Use link position directly, avoid any transfer problem. */
2214                 return POS_FIX_LPIB;
2215         }
2216         chip->via_dmapos_patch = 0;
2217
2218         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2219         if (q) {
2220                 printk(KERN_INFO
2221                        "hda_intel: position_fix set to %d "
2222                        "for device %04x:%04x\n",
2223                        q->value, q->subvendor, q->subdevice);
2224                 return q->value;
2225         }
2226         return POS_FIX_AUTO;
2227 }
2228
2229 /*
2230  * black-lists for probe_mask
2231  */
2232 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2233         /* Thinkpad often breaks the controller communication when accessing
2234          * to the non-working (or non-existing) modem codec slot.
2235          */
2236         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2237         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2238         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2239         /* broken BIOS */
2240         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2241         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2242         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2243         /* forced codec slots */
2244         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2245         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2246         {}
2247 };
2248
2249 #define AZX_FORCE_CODEC_MASK    0x100
2250
2251 static void __devinit check_probe_mask(struct azx *chip, int dev)
2252 {
2253         const struct snd_pci_quirk *q;
2254
2255         chip->codec_probe_mask = probe_mask[dev];
2256         if (chip->codec_probe_mask == -1) {
2257                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2258                 if (q) {
2259                         printk(KERN_INFO
2260                                "hda_intel: probe_mask set to 0x%x "
2261                                "for device %04x:%04x\n",
2262                                q->value, q->subvendor, q->subdevice);
2263                         chip->codec_probe_mask = q->value;
2264                 }
2265         }
2266
2267         /* check forced option */
2268         if (chip->codec_probe_mask != -1 &&
2269             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2270                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2271                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2272                        chip->codec_mask);
2273         }
2274 }
2275
2276
2277 /*
2278  * constructor
2279  */
2280 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2281                                 int dev, int driver_type,
2282                                 struct azx **rchip)
2283 {
2284         struct azx *chip;
2285         int i, err;
2286         unsigned short gcap;
2287         static struct snd_device_ops ops = {
2288                 .dev_free = azx_dev_free,
2289         };
2290
2291         *rchip = NULL;
2292
2293         err = pci_enable_device(pci);
2294         if (err < 0)
2295                 return err;
2296
2297         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2298         if (!chip) {
2299                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2300                 pci_disable_device(pci);
2301                 return -ENOMEM;
2302         }
2303
2304         spin_lock_init(&chip->reg_lock);
2305         mutex_init(&chip->open_mutex);
2306         chip->card = card;
2307         chip->pci = pci;
2308         chip->irq = -1;
2309         chip->driver_type = driver_type;
2310         chip->msi = enable_msi;
2311         chip->dev_index = dev;
2312         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2313
2314         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2315         check_probe_mask(chip, dev);
2316
2317         chip->single_cmd = single_cmd;
2318
2319         if (bdl_pos_adj[dev] < 0) {
2320                 switch (chip->driver_type) {
2321                 case AZX_DRIVER_ICH:
2322                         bdl_pos_adj[dev] = 1;
2323                         break;
2324                 default:
2325                         bdl_pos_adj[dev] = 32;
2326                         break;
2327                 }
2328         }
2329
2330 #if BITS_PER_LONG != 64
2331         /* Fix up base address on ULI M5461 */
2332         if (chip->driver_type == AZX_DRIVER_ULI) {
2333                 u16 tmp3;
2334                 pci_read_config_word(pci, 0x40, &tmp3);
2335                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2336                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2337         }
2338 #endif
2339
2340         err = pci_request_regions(pci, "ICH HD audio");
2341         if (err < 0) {
2342                 kfree(chip);
2343                 pci_disable_device(pci);
2344                 return err;
2345         }
2346
2347         chip->addr = pci_resource_start(pci, 0);
2348         chip->remap_addr = pci_ioremap_bar(pci, 0);
2349         if (chip->remap_addr == NULL) {
2350                 snd_printk(KERN_ERR SFX "ioremap error\n");
2351                 err = -ENXIO;
2352                 goto errout;
2353         }
2354
2355         if (chip->msi)
2356                 if (pci_enable_msi(pci) < 0)
2357                         chip->msi = 0;
2358
2359         if (azx_acquire_irq(chip, 0) < 0) {
2360                 err = -EBUSY;
2361                 goto errout;
2362         }
2363
2364         pci_set_master(pci);
2365         synchronize_irq(chip->irq);
2366
2367         gcap = azx_readw(chip, GCAP);
2368         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2369
2370         /* disable SB600 64bit support for safety */
2371         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2372             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2373                 struct pci_dev *p_smbus;
2374                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2375                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2376                                          NULL);
2377                 if (p_smbus) {
2378                         if (p_smbus->revision < 0x30)
2379                                 gcap &= ~ICH6_GCAP_64OK;
2380                         pci_dev_put(p_smbus);
2381                 }
2382         }
2383
2384         /* allow 64bit DMA address if supported by H/W */
2385         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2386                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2387         else {
2388                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2389                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2390         }
2391
2392         /* read number of streams from GCAP register instead of using
2393          * hardcoded value
2394          */
2395         chip->capture_streams = (gcap >> 8) & 0x0f;
2396         chip->playback_streams = (gcap >> 12) & 0x0f;
2397         if (!chip->playback_streams && !chip->capture_streams) {
2398                 /* gcap didn't give any info, switching to old method */
2399
2400                 switch (chip->driver_type) {
2401                 case AZX_DRIVER_ULI:
2402                         chip->playback_streams = ULI_NUM_PLAYBACK;
2403                         chip->capture_streams = ULI_NUM_CAPTURE;
2404                         break;
2405                 case AZX_DRIVER_ATIHDMI:
2406                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2407                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2408                         break;
2409                 case AZX_DRIVER_GENERIC:
2410                 default:
2411                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2412                         chip->capture_streams = ICH6_NUM_CAPTURE;
2413                         break;
2414                 }
2415         }
2416         chip->capture_index_offset = 0;
2417         chip->playback_index_offset = chip->capture_streams;
2418         chip->num_streams = chip->playback_streams + chip->capture_streams;
2419         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2420                                 GFP_KERNEL);
2421         if (!chip->azx_dev) {
2422                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2423                 goto errout;
2424         }
2425
2426         for (i = 0; i < chip->num_streams; i++) {
2427                 /* allocate memory for the BDL for each stream */
2428                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2429                                           snd_dma_pci_data(chip->pci),
2430                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2431                 if (err < 0) {
2432                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2433                         goto errout;
2434                 }
2435         }
2436         /* allocate memory for the position buffer */
2437         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2438                                   snd_dma_pci_data(chip->pci),
2439                                   chip->num_streams * 8, &chip->posbuf);
2440         if (err < 0) {
2441                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2442                 goto errout;
2443         }
2444         /* allocate CORB/RIRB */
2445         err = azx_alloc_cmd_io(chip);
2446         if (err < 0)
2447                 goto errout;
2448
2449         /* initialize streams */
2450         azx_init_stream(chip);
2451
2452         /* initialize chip */
2453         azx_init_pci(chip);
2454         azx_init_chip(chip);
2455
2456         /* codec detection */
2457         if (!chip->codec_mask) {
2458                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2459                 err = -ENODEV;
2460                 goto errout;
2461         }
2462
2463         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2464         if (err <0) {
2465                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2466                 goto errout;
2467         }
2468
2469         strcpy(card->driver, "HDA-Intel");
2470         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2471                 sizeof(card->shortname));
2472         snprintf(card->longname, sizeof(card->longname),
2473                  "%s at 0x%lx irq %i",
2474                  card->shortname, chip->addr, chip->irq);
2475
2476         *rchip = chip;
2477         return 0;
2478
2479  errout:
2480         azx_free(chip);
2481         return err;
2482 }
2483
2484 static void power_down_all_codecs(struct azx *chip)
2485 {
2486 #ifdef CONFIG_SND_HDA_POWER_SAVE
2487         /* The codecs were powered up in snd_hda_codec_new().
2488          * Now all initialization done, so turn them down if possible
2489          */
2490         struct hda_codec *codec;
2491         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2492                 snd_hda_power_down(codec);
2493         }
2494 #endif
2495 }
2496
2497 static int __devinit azx_probe(struct pci_dev *pci,
2498                                const struct pci_device_id *pci_id)
2499 {
2500         static int dev;
2501         struct snd_card *card;
2502         struct azx *chip;
2503         int err;
2504
2505         if (dev >= SNDRV_CARDS)
2506                 return -ENODEV;
2507         if (!enable[dev]) {
2508                 dev++;
2509                 return -ENOENT;
2510         }
2511
2512         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2513         if (err < 0) {
2514                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2515                 return err;
2516         }
2517
2518         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2519         if (err < 0)
2520                 goto out_free;
2521         card->private_data = chip;
2522
2523         /* create codec instances */
2524         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2525         if (err < 0)
2526                 goto out_free;
2527
2528         /* create PCM streams */
2529         err = snd_hda_build_pcms(chip->bus);
2530         if (err < 0)
2531                 goto out_free;
2532
2533         /* create mixer controls */
2534         err = azx_mixer_create(chip);
2535         if (err < 0)
2536                 goto out_free;
2537
2538         snd_card_set_dev(card, &pci->dev);
2539
2540         err = snd_card_register(card);
2541         if (err < 0)
2542                 goto out_free;
2543
2544         pci_set_drvdata(pci, card);
2545         chip->running = 1;
2546         power_down_all_codecs(chip);
2547         azx_notifier_register(chip);
2548
2549         dev++;
2550         return err;
2551 out_free:
2552         snd_card_free(card);
2553         return err;
2554 }
2555
2556 static void __devexit azx_remove(struct pci_dev *pci)
2557 {
2558         snd_card_free(pci_get_drvdata(pci));
2559         pci_set_drvdata(pci, NULL);
2560 }
2561
2562 /* PCI IDs */
2563 static struct pci_device_id azx_ids[] = {
2564         /* ICH 6..10 */
2565         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2566         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2567         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2568         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2569         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2570         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2571         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2572         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2573         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2574         /* PCH */
2575         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2576         /* SCH */
2577         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2578         /* ATI SB 450/600 */
2579         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2580         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2581         /* ATI HDMI */
2582         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2583         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2584         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2585         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2586         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2587         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2588         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2589         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2590         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2591         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2592         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2593         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2594         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2595         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2596         /* VIA VT8251/VT8237A */
2597         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2598         /* SIS966 */
2599         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2600         /* ULI M5461 */
2601         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2602         /* NVIDIA MCP */
2603         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2604         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2605         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2606         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2607         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2608         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2609         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2610         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2611         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2612         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2613         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2614         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2615         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2616         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2617         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2618         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2619         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2620         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2621         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2622         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2623         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2624         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2625         /* Teradici */
2626         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2627         /* Creative X-Fi (CA0110-IBG) */
2628 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2629         /* the following entry conflicts with snd-ctxfi driver,
2630          * as ctxfi driver mutates from HD-audio to native mode with
2631          * a special command sequence.
2632          */
2633         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2634           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2635           .class_mask = 0xffffff,
2636           .driver_data = AZX_DRIVER_GENERIC },
2637 #else
2638         /* this entry seems still valid -- i.e. without emu20kx chip */
2639         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2640 #endif
2641         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2642         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2643           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2644           .class_mask = 0xffffff,
2645           .driver_data = AZX_DRIVER_GENERIC },
2646         { 0, }
2647 };
2648 MODULE_DEVICE_TABLE(pci, azx_ids);
2649
2650 /* pci_driver definition */
2651 static struct pci_driver driver = {
2652         .name = "HDA Intel",
2653         .id_table = azx_ids,
2654         .probe = azx_probe,
2655         .remove = __devexit_p(azx_remove),
2656 #ifdef CONFIG_PM
2657         .suspend = azx_suspend,
2658         .resume = azx_resume,
2659 #endif
2660 };
2661
2662 static int __init alsa_card_azx_init(void)
2663 {
2664         return pci_register_driver(&driver);
2665 }
2666
2667 static void __exit alsa_card_azx_exit(void)
2668 {
2669         pci_unregister_driver(&driver);
2670 }
2671
2672 module_init(alsa_card_azx_init)
2673 module_exit(alsa_card_azx_exit)