sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  82                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, int, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, PBG},"
 130                          "{Intel, SCH},"
 131                          "{ATI, SB450},"
 132                          "{ATI, SB600},"
 133                          "{ATI, RS600},"
 134                          "{ATI, RS690},"
 135                          "{ATI, RS780},"
 136                          "{ATI, R600},"
 137                          "{ATI, RV630},"
 138                          "{ATI, RV610},"
 139                          "{ATI, RV670},"
 140                          "{ATI, RV635},"
 141                          "{ATI, RV620},"
 142                          "{ATI, RV770},"
 143                          "{VIA, VT8251},"
 144                          "{VIA, VT8237A},"
 145                          "{SiS, SIS966},"
 146                          "{ULI, M5461}}");
 147 MODULE_DESCRIPTION("Intel HDA driver");
 148
 149 #ifdef CONFIG_SND_VERBOSE_PRINTK
 150 #define SFX     /* nop */
 151 #else
 152 #define SFX     "hda-intel: "
 153 #endif
 154
 155 /*
 156  * registers
 157  */
 158 #define ICH6_REG_GCAP                   0x00
 159 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 160 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 161 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 162 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 163 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 164 #define ICH6_REG_VMIN                   0x02
 165 #define ICH6_REG_VMAJ                   0x03
 166 #define ICH6_REG_OUTPAY                 0x04
 167 #define ICH6_REG_INPAY                  0x06
 168 #define ICH6_REG_GCTL                   0x08
 169 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 170 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 171 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 172 #define ICH6_REG_WAKEEN                 0x0c
 173 #define ICH6_REG_STATESTS               0x0e
 174 #define ICH6_REG_GSTS                   0x10
 175 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 176 #define ICH6_REG_INTCTL                 0x20
 177 #define ICH6_REG_INTSTS                 0x24
 178 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 179 #define ICH6_REG_SYNC                   0x34
 180 #define ICH6_REG_CORBLBASE              0x40
 181 #define ICH6_REG_CORBUBASE              0x44
 182 #define ICH6_REG_CORBWP                 0x48
 183 #define ICH6_REG_CORBRP                 0x4a
 184 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 185 #define ICH6_REG_CORBCTL                0x4c
 186 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 187 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 188 #define ICH6_REG_CORBSTS                0x4d
 189 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 190 #define ICH6_REG_CORBSIZE               0x4e
 191
 192 #define ICH6_REG_RIRBLBASE              0x50
 193 #define ICH6_REG_RIRBUBASE              0x54
 194 #define ICH6_REG_RIRBWP                 0x58
 195 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 196 #define ICH6_REG_RINTCNT                0x5a
 197 #define ICH6_REG_RIRBCTL                0x5c
 198 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 199 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 200 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 201 #define ICH6_REG_RIRBSTS                0x5d
 202 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 203 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 204 #define ICH6_REG_RIRBSIZE               0x5e
 205
 206 #define ICH6_REG_IC                     0x60
 207 #define ICH6_REG_IR                     0x64
 208 #define ICH6_REG_IRS                    0x68
 209 #define   ICH6_IRS_VALID        (1<<1)
 210 #define   ICH6_IRS_BUSY         (1<<0)
 211
 212 #define ICH6_REG_DPLBASE                0x70
 213 #define ICH6_REG_DPUBASE                0x74
 214 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 215
 216 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 217 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 218
 219 /* stream register offsets from stream base */
 220 #define ICH6_REG_SD_CTL                 0x00
 221 #define ICH6_REG_SD_STS                 0x03
 222 #define ICH6_REG_SD_LPIB                0x04
 223 #define ICH6_REG_SD_CBL                 0x08
 224 #define ICH6_REG_SD_LVI                 0x0c
 225 #define ICH6_REG_SD_FIFOW               0x0e
 226 #define ICH6_REG_SD_FIFOSIZE            0x10
 227 #define ICH6_REG_SD_FORMAT              0x12
 228 #define ICH6_REG_SD_BDLPL               0x18
 229 #define ICH6_REG_SD_BDLPU               0x1c
 230
 231 /* PCI space */
 232 #define ICH6_PCIREG_TCSEL       0x44
 233
 234 /*
 235  * other constants
 236  */
 237
 238 /* max number of SDs */
 239 /* ICH, ATI and VIA have 4 playback and 4 capture */
 240 #define ICH6_NUM_CAPTURE        4
 241 #define ICH6_NUM_PLAYBACK       4
 242
 243 /* ULI has 6 playback and 5 capture */
 244 #define ULI_NUM_CAPTURE         5
 245 #define ULI_NUM_PLAYBACK        6
 246
 247 /* ATI HDMI has 1 playback and 0 capture */
 248 #define ATIHDMI_NUM_CAPTURE     0
 249 #define ATIHDMI_NUM_PLAYBACK    1
 250
 251 /* TERA has 4 playback and 3 capture */
 252 #define TERA_NUM_CAPTURE        3
 253 #define TERA_NUM_PLAYBACK       4
 254
 255 /* this number is statically defined for simplicity */
 256 #define MAX_AZX_DEV             16
 257
 258 /* max number of fragments - we may use more if allocating more pages for BDL */
 259 #define BDL_SIZE                4096
 260 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 261 #define AZX_MAX_FRAG            32
 262 /* max buffer size - no h/w limit, you can increase as you like */
 263 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 264
 265 /* RIRB int mask: overrun[2], response[0] */
 266 #define RIRB_INT_RESPONSE       0x01
 267 #define RIRB_INT_OVERRUN        0x04
 268 #define RIRB_INT_MASK           0x05
 269
 270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 271 #define AZX_MAX_CODECS          8
 272 #define AZX_DEFAULT_CODECS      4
 273 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 274
 275 /* SD_CTL bits */
 276 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 277 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 278 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 279 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 280 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 281 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 282 #define SD_CTL_STREAM_TAG_SHIFT 20
 283
 284 /* SD_CTL and SD_STS */
 285 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 286 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 287 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 288 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 289                                  SD_INT_COMPLETE)
 290
 291 /* SD_STS */
 292 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 293
 294 /* INTCTL and INTSTS */
 295 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 296 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 297 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 298
 299 /* below are so far hardcoded - should read registers in future */
 300 #define ICH6_MAX_CORB_ENTRIES   256
 301 #define ICH6_MAX_RIRB_ENTRIES   256
 302
 303 /* position fix mode */
 304 enum {
 305         POS_FIX_AUTO,
 306         POS_FIX_LPIB,
 307         POS_FIX_POSBUF,
 308         POS_FIX_VIACOMBO,
 309 };
 310
 311 /* Defines for ATI HD Audio support in SB450 south bridge */
 312 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 313 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 314
 315 /* Defines for Nvidia HDA support */
 316 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 317 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 318 #define NVIDIA_HDA_ISTRM_COH          0x4d
 319 #define NVIDIA_HDA_OSTRM_COH          0x4c
 320 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 321
 322 /* Defines for Intel SCH HDA snoop control */
 323 #define INTEL_SCH_HDA_DEVC      0x78
 324 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 325
 326 /* Define IN stream 0 FIFO size offset in VIA controller */
 327 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 328 /* Define VIA HD Audio Device ID*/
 329 #define VIA_HDAC_DEVICE_ID              0x3288
 330
 331 /* HD Audio class code */
 332 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 333
 334 /*
 335  */
 336
 337 struct azx_dev {
 338         struct snd_dma_buffer bdl; /* BDL buffer */
 339         u32 *posbuf;            /* position buffer pointer */
 340
 341         unsigned int bufsize;   /* size of the play buffer in bytes */
 342         unsigned int period_bytes; /* size of the period in bytes */
 343         unsigned int frags;     /* number for period in the play buffer */
 344         unsigned int fifo_size; /* FIFO size */
 345         unsigned long start_wallclk;    /* start + minimum wallclk */
 346         unsigned long period_wallclk;   /* wallclk for period */
 347
 348         void __iomem *sd_addr;  /* stream descriptor pointer */
 349
 350         u32 sd_int_sta_mask;    /* stream int status mask */
 351
 352         /* pcm support */
 353         struct snd_pcm_substream *substream;    /* assigned substream,
 354                                                  * set in PCM open
 355                                                  */
 356         unsigned int format_val;        /* format value to be set in the
 357                                          * controller and the codec
 358                                          */
 359         unsigned char stream_tag;       /* assigned stream */
 360         unsigned char index;            /* stream index */
 361         int device;                     /* last device number assigned to */
 362
 363         unsigned int opened :1;
 364         unsigned int running :1;
 365         unsigned int irq_pending :1;
 366         /*
 367          * For VIA:
 368          *  A flag to ensure DMA position is 0
 369          *  when link position is not greater than FIFO size
 370          */
 371         unsigned int insufficient :1;
 372 };
 373
 374 /* CORB/RIRB */
 375 struct azx_rb {
 376         u32 *buf;               /* CORB/RIRB buffer
 377                                  * Each CORB entry is 4byte, RIRB is 8byte
 378                                  */
 379         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 380         /* for RIRB */
 381         unsigned short rp, wp;  /* read/write pointers */
 382         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 383         u32 res[AZX_MAX_CODECS];        /* last read value */
 384 };
 385
 386 struct azx {
 387         struct snd_card *card;
 388         struct pci_dev *pci;
 389         int dev_index;
 390
 391         /* chip type specific */
 392         int driver_type;
 393         int playback_streams;
 394         int playback_index_offset;
 395         int capture_streams;
 396         int capture_index_offset;
 397         int num_streams;
 398
 399         /* pci resources */
 400         unsigned long addr;
 401         void __iomem *remap_addr;
 402         int irq;
 403
 404         /* locks */
 405         spinlock_t reg_lock;
 406         struct mutex open_mutex;
 407
 408         /* streams (x num_streams) */
 409         struct azx_dev *azx_dev;
 410
 411         /* PCM */
 412         struct snd_pcm *pcm[HDA_MAX_PCMS];
 413
 414         /* HD codec */
 415         unsigned short codec_mask;
 416         int  codec_probe_mask; /* copied from probe_mask option */
 417         struct hda_bus *bus;
 418         unsigned int beep_mode;
 419
 420         /* CORB/RIRB */
 421         struct azx_rb corb;
 422         struct azx_rb rirb;
 423
 424         /* CORB/RIRB and position buffers */
 425         struct snd_dma_buffer rb;
 426         struct snd_dma_buffer posbuf;
 427
 428         /* flags */
 429         int position_fix[2]; /* for both playback/capture streams */
 430         int poll_count;
 431         unsigned int running :1;
 432         unsigned int initialized :1;
 433         unsigned int single_cmd :1;
 434         unsigned int polling_mode :1;
 435         unsigned int msi :1;
 436         unsigned int irq_pending_warned :1;
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_PCH,
 453         AZX_DRIVER_SCH,
 454         AZX_DRIVER_ATI,
 455         AZX_DRIVER_ATIHDMI,
 456         AZX_DRIVER_VIA,
 457         AZX_DRIVER_SIS,
 458         AZX_DRIVER_ULI,
 459         AZX_DRIVER_NVIDIA,
 460         AZX_DRIVER_TERA,
 461         AZX_DRIVER_CTX,
 462         AZX_DRIVER_GENERIC,
 463         AZX_NUM_DRIVERS, /* keep this as last entry */
 464 };
 465
 466 static char *driver_short_names[] __devinitdata = {
 467         [AZX_DRIVER_ICH] = "HDA Intel",
 468         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 469         [AZX_DRIVER_SCH] = "HDA Intel MID",
 470         [AZX_DRIVER_ATI] = "HDA ATI SB",
 471         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 472         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 473         [AZX_DRIVER_SIS] = "HDA SIS966",
 474         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 475         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 476         [AZX_DRIVER_TERA] = "HDA Teradici",
 477         [AZX_DRIVER_CTX] = "HDA Creative",
 478         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 479 };
 480
 481 /*
 482  * macros for easy use
 483  */
 484 #define azx_writel(chip,reg,value) \
 485         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_readl(chip,reg) \
 487         readl((chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_writew(chip,reg,value) \
 489         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_readw(chip,reg) \
 491         readw((chip)->remap_addr + ICH6_REG_##reg)
 492 #define azx_writeb(chip,reg,value) \
 493         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 494 #define azx_readb(chip,reg) \
 495         readb((chip)->remap_addr + ICH6_REG_##reg)
 496
 497 #define azx_sd_writel(dev,reg,value) \
 498         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_readl(dev,reg) \
 500         readl((dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_writew(dev,reg,value) \
 502         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_readw(dev,reg) \
 504         readw((dev)->sd_addr + ICH6_REG_##reg)
 505 #define azx_sd_writeb(dev,reg,value) \
 506         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 507 #define azx_sd_readb(dev,reg) \
 508         readb((dev)->sd_addr + ICH6_REG_##reg)
 509
 510 /* for pcm support */
 511 #define get_azx_dev(substream) (substream->runtime->private_data)
 512
 513 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 514 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 515 /*
 516  * Interface for HD codec
 517  */
 518
 519 /*
 520  * CORB / RIRB interface
 521  */
 522 static int azx_alloc_cmd_io(struct azx *chip)
 523 {
 524         int err;
 525
 526         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 527         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 528                                   snd_dma_pci_data(chip->pci),
 529                                   PAGE_SIZE, &chip->rb);
 530         if (err < 0) {
 531                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 532                 return err;
 533         }
 534         return 0;
 535 }
 536
 537 static void azx_init_cmd_io(struct azx *chip)
 538 {
 539         spin_lock_irq(&chip->reg_lock);
 540         /* CORB set up */
 541         chip->corb.addr = chip->rb.addr;
 542         chip->corb.buf = (u32 *)chip->rb.area;
 543         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 544         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 545
 546         /* set the corb size to 256 entries (ULI requires explicitly) */
 547         azx_writeb(chip, CORBSIZE, 0x02);
 548         /* set the corb write pointer to 0 */
 549         azx_writew(chip, CORBWP, 0);
 550         /* reset the corb hw read pointer */
 551         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 552         /* enable corb dma */
 553         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 554
 555         /* RIRB set up */
 556         chip->rirb.addr = chip->rb.addr + 2048;
 557         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 558         chip->rirb.wp = chip->rirb.rp = 0;
 559         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 560         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 561         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 562
 563         /* set the rirb size to 256 entries (ULI requires explicitly) */
 564         azx_writeb(chip, RIRBSIZE, 0x02);
 565         /* reset the rirb hw write pointer */
 566         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 567         /* set N=1, get RIRB response interrupt for new entry */
 568         if (chip->driver_type == AZX_DRIVER_CTX)
 569                 azx_writew(chip, RINTCNT, 0xc0);
 570         else
 571                 azx_writew(chip, RINTCNT, 1);
 572         /* enable rirb dma and response irq */
 573         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 574         spin_unlock_irq(&chip->reg_lock);
 575 }
 576
 577 static void azx_free_cmd_io(struct azx *chip)
 578 {
 579         spin_lock_irq(&chip->reg_lock);
 580         /* disable ringbuffer DMAs */
 581         azx_writeb(chip, RIRBCTL, 0);
 582         azx_writeb(chip, CORBCTL, 0);
 583         spin_unlock_irq(&chip->reg_lock);
 584 }
 585
 586 static unsigned int azx_command_addr(u32 cmd)
 587 {
 588         unsigned int addr = cmd >> 28;
 589
 590         if (addr >= AZX_MAX_CODECS) {
 591                 snd_BUG();
 592                 addr = 0;
 593         }
 594
 595         return addr;
 596 }
 597
 598 static unsigned int azx_response_addr(u32 res)
 599 {
 600         unsigned int addr = res & 0xf;
 601
 602         if (addr >= AZX_MAX_CODECS) {
 603                 snd_BUG();
 604                 addr = 0;
 605         }
 606
 607         return addr;
 608 }
 609
 610 /* send a command */
 611 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 612 {
 613         struct azx *chip = bus->private_data;
 614         unsigned int addr = azx_command_addr(val);
 615         unsigned int wp;
 616
 617         spin_lock_irq(&chip->reg_lock);
 618
 619         /* add command to corb */
 620         wp = azx_readb(chip, CORBWP);
 621         wp++;
 622         wp %= ICH6_MAX_CORB_ENTRIES;
 623
 624         chip->rirb.cmds[addr]++;
 625         chip->corb.buf[wp] = cpu_to_le32(val);
 626         azx_writel(chip, CORBWP, wp);
 627
 628         spin_unlock_irq(&chip->reg_lock);
 629
 630         return 0;
 631 }
 632
 633 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 634
 635 /* retrieve RIRB entry - called from interrupt handler */
 636 static void azx_update_rirb(struct azx *chip)
 637 {
 638         unsigned int rp, wp;
 639         unsigned int addr;
 640         u32 res, res_ex;
 641
 642         wp = azx_readb(chip, RIRBWP);
 643         if (wp == chip->rirb.wp)
 644                 return;
 645         chip->rirb.wp = wp;
 646
 647         while (chip->rirb.rp != wp) {
 648                 chip->rirb.rp++;
 649                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 650
 651                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 652                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 653                 res = le32_to_cpu(chip->rirb.buf[rp]);
 654                 addr = azx_response_addr(res_ex);
 655                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 656                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 657                 else if (chip->rirb.cmds[addr]) {
 658                         chip->rirb.res[addr] = res;
 659                         smp_wmb();
 660                         chip->rirb.cmds[addr]--;
 661                 } else
 662                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 663                                    "last cmd=%#08x\n",
 664                                    res, res_ex,
 665                                    chip->last_cmd[addr]);
 666         }
 667 }
 668
 669 /* receive a response */
 670 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 671                                           unsigned int addr)
 672 {
 673         struct azx *chip = bus->private_data;
 674         unsigned long timeout;
 675         int do_poll = 0;
 676
 677  again:
 678         timeout = jiffies + msecs_to_jiffies(1000);
 679         for (;;) {
 680                 if (chip->polling_mode || do_poll) {
 681                         spin_lock_irq(&chip->reg_lock);
 682                         azx_update_rirb(chip);
 683                         spin_unlock_irq(&chip->reg_lock);
 684                 }
 685                 if (!chip->rirb.cmds[addr]) {
 686                         smp_rmb();
 687                         bus->rirb_error = 0;
 688
 689                         if (!do_poll)
 690                                 chip->poll_count = 0;
 691                         return chip->rirb.res[addr]; /* the last value */
 692                 }
 693                 if (time_after(jiffies, timeout))
 694                         break;
 695                 if (bus->needs_damn_long_delay)
 696                         msleep(2); /* temporary workaround */
 697                 else {
 698                         udelay(10);
 699                         cond_resched();
 700                 }
 701         }
 702
 703         if (!chip->polling_mode && chip->poll_count < 2) {
 704                 snd_printdd(SFX "azx_get_response timeout, "
 705                            "polling the codec once: last cmd=0x%08x\n",
 706                            chip->last_cmd[addr]);
 707                 do_poll = 1;
 708                 chip->poll_count++;
 709                 goto again;
 710         }
 711
 712
 713         if (!chip->polling_mode) {
 714                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 715                            "switching to polling mode: last cmd=0x%08x\n",
 716                            chip->last_cmd[addr]);
 717                 chip->polling_mode = 1;
 718                 goto again;
 719         }
 720
 721         if (chip->msi) {
 722                 snd_printk(KERN_WARNING SFX "No response from codec, "
 723                            "disabling MSI: last cmd=0x%08x\n",
 724                            chip->last_cmd[addr]);
 725                 free_irq(chip->irq, chip);
 726                 chip->irq = -1;
 727                 pci_disable_msi(chip->pci);
 728                 chip->msi = 0;
 729                 if (azx_acquire_irq(chip, 1) < 0) {
 730                         bus->rirb_error = 1;
 731                         return -1;
 732                 }
 733                 goto again;
 734         }
 735
 736         if (chip->probing) {
 737                 /* If this critical timeout happens during the codec probing
 738                  * phase, this is likely an access to a non-existing codec
 739                  * slot.  Better to return an error and reset the system.
 740                  */
 741                 return -1;
 742         }
 743
 744         /* a fatal communication error; need either to reset or to fallback
 745          * to the single_cmd mode
 746          */
 747         bus->rirb_error = 1;
 748         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 749                 bus->response_reset = 1;
 750                 return -1; /* give a chance to retry */
 751         }
 752
 753         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 754                    "switching to single_cmd mode: last cmd=0x%08x\n",
 755                    chip->last_cmd[addr]);
 756         chip->single_cmd = 1;
 757         bus->response_reset = 0;
 758         /* release CORB/RIRB */
 759         azx_free_cmd_io(chip);
 760         /* disable unsolicited responses */
 761         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 762         return -1;
 763 }
 764
 765 /*
 766  * Use the single immediate command instead of CORB/RIRB for simplicity
 767  *
 768  * Note: according to Intel, this is not preferred use.  The command was
 769  *       intended for the BIOS only, and may get confused with unsolicited
 770  *       responses.  So, we shouldn't use it for normal operation from the
 771  *       driver.
 772  *       I left the codes, however, for debugging/testing purposes.
 773  */
 774
 775 /* receive a response */
 776 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 777 {
 778         int timeout = 50;
 779
 780         while (timeout--) {
 781                 /* check IRV busy bit */
 782                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 783                         /* reuse rirb.res as the response return value */
 784                         chip->rirb.res[addr] = azx_readl(chip, IR);
 785                         return 0;
 786                 }
 787                 udelay(1);
 788         }
 789         if (printk_ratelimit())
 790                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 791                            azx_readw(chip, IRS));
 792         chip->rirb.res[addr] = -1;
 793         return -EIO;
 794 }
 795
 796 /* send a command */
 797 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 798 {
 799         struct azx *chip = bus->private_data;
 800         unsigned int addr = azx_command_addr(val);
 801         int timeout = 50;
 802
 803         bus->rirb_error = 0;
 804         while (timeout--) {
 805                 /* check ICB busy bit */
 806                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 807                         /* Clear IRV valid bit */
 808                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 809                                    ICH6_IRS_VALID);
 810                         azx_writel(chip, IC, val);
 811                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 812                                    ICH6_IRS_BUSY);
 813                         return azx_single_wait_for_response(chip, addr);
 814                 }
 815                 udelay(1);
 816         }
 817         if (printk_ratelimit())
 818                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 819                            azx_readw(chip, IRS), val);
 820         return -EIO;
 821 }
 822
 823 /* receive a response */
 824 static unsigned int azx_single_get_response(struct hda_bus *bus,
 825                                             unsigned int addr)
 826 {
 827         struct azx *chip = bus->private_data;
 828         return chip->rirb.res[addr];
 829 }
 830
 831 /*
 832  * The below are the main callbacks from hda_codec.
 833  *
 834  * They are just the skeleton to call sub-callbacks according to the
 835  * current setting of chip->single_cmd.
 836  */
 837
 838 /* send a command */
 839 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 840 {
 841         struct azx *chip = bus->private_data;
 842
 843         chip->last_cmd[azx_command_addr(val)] = val;
 844         if (chip->single_cmd)
 845                 return azx_single_send_cmd(bus, val);
 846         else
 847                 return azx_corb_send_cmd(bus, val);
 848 }
 849
 850 /* get a response */
 851 static unsigned int azx_get_response(struct hda_bus *bus,
 852                                      unsigned int addr)
 853 {
 854         struct azx *chip = bus->private_data;
 855         if (chip->single_cmd)
 856                 return azx_single_get_response(bus, addr);
 857         else
 858                 return azx_rirb_get_response(bus, addr);
 859 }
 860
 861 #ifdef CONFIG_SND_HDA_POWER_SAVE
 862 static void azx_power_notify(struct hda_bus *bus);
 863 #endif
 864
 865 /* reset codec link */
 866 static int azx_reset(struct azx *chip, int full_reset)
 867 {
 868         int count;
 869
 870         if (!full_reset)
 871                 goto __skip;
 872
 873         /* clear STATESTS */
 874         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 875
 876         /* reset controller */
 877         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 878
 879         count = 50;
 880         while (azx_readb(chip, GCTL) && --count)
 881                 msleep(1);
 882
 883         /* delay for >= 100us for codec PLL to settle per spec
 884          * Rev 0.9 section 5.5.1
 885          */
 886         msleep(1);
 887
 888         /* Bring controller out of reset */
 889         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 890
 891         count = 50;
 892         while (!azx_readb(chip, GCTL) && --count)
 893                 msleep(1);
 894
 895         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 896         msleep(1);
 897
 898       __skip:
 899         /* check to see if controller is ready */
 900         if (!azx_readb(chip, GCTL)) {
 901                 snd_printd(SFX "azx_reset: controller not ready!\n");
 902                 return -EBUSY;
 903         }
 904
 905         /* Accept unsolicited responses */
 906         if (!chip->single_cmd)
 907                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 908                            ICH6_GCTL_UNSOL);
 909
 910         /* detect codecs */
 911         if (!chip->codec_mask) {
 912                 chip->codec_mask = azx_readw(chip, STATESTS);
 913                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 914         }
 915
 916         return 0;
 917 }
 918
 919
 920 /*
 921  * Lowlevel interface
 922  */
 923
 924 /* enable interrupts */
 925 static void azx_int_enable(struct azx *chip)
 926 {
 927         /* enable controller CIE and GIE */
 928         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 929                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 930 }
 931
 932 /* disable interrupts */
 933 static void azx_int_disable(struct azx *chip)
 934 {
 935         int i;
 936
 937         /* disable interrupts in stream descriptor */
 938         for (i = 0; i < chip->num_streams; i++) {
 939                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 940                 azx_sd_writeb(azx_dev, SD_CTL,
 941                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 942         }
 943
 944         /* disable SIE for all streams */
 945         azx_writeb(chip, INTCTL, 0);
 946
 947         /* disable controller CIE and GIE */
 948         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 949                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 950 }
 951
 952 /* clear interrupts */
 953 static void azx_int_clear(struct azx *chip)
 954 {
 955         int i;
 956
 957         /* clear stream status */
 958         for (i = 0; i < chip->num_streams; i++) {
 959                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 960                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 961         }
 962
 963         /* clear STATESTS */
 964         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 965
 966         /* clear rirb status */
 967         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 968
 969         /* clear int status */
 970         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 971 }
 972
 973 /* start a stream */
 974 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 975 {
 976         /*
 977          * Before stream start, initialize parameter
 978          */
 979         azx_dev->insufficient = 1;
 980
 981         /* enable SIE */
 982         azx_writel(chip, INTCTL,
 983                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
 984         /* set DMA start and interrupt mask */
 985         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 986                       SD_CTL_DMA_START | SD_INT_MASK);
 987 }
 988
 989 /* stop DMA */
 990 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 991 {
 992         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 993                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 994         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 995 }
 996
 997 /* stop a stream */
 998 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 999 {
1000         azx_stream_clear(chip, azx_dev);
1001         /* disable SIE */
1002         azx_writel(chip, INTCTL,
1003                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1004 }
1005
1006
1007 /*
1008  * reset and start the controller registers
1009  */
1010 static void azx_init_chip(struct azx *chip, int full_reset)
1011 {
1012         if (chip->initialized)
1013                 return;
1014
1015         /* reset controller */
1016         azx_reset(chip, full_reset);
1017
1018         /* initialize interrupts */
1019         azx_int_clear(chip);
1020         azx_int_enable(chip);
1021
1022         /* initialize the codec command I/O */
1023         if (!chip->single_cmd)
1024                 azx_init_cmd_io(chip);
1025
1026         /* program the position buffer */
1027         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1028         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1029
1030         chip->initialized = 1;
1031 }
1032
1033 /*
1034  * initialize the PCI registers
1035  */
1036 /* update bits in a PCI register byte */
1037 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1038                             unsigned char mask, unsigned char val)
1039 {
1040         unsigned char data;
1041
1042         pci_read_config_byte(pci, reg, &data);
1043         data &= ~mask;
1044         data |= (val & mask);
1045         pci_write_config_byte(pci, reg, data);
1046 }
1047
1048 static void azx_init_pci(struct azx *chip)
1049 {
1050         unsigned short snoop;
1051
1052         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054          * Ensuring these bits are 0 clears playback static on some HD Audio
1055          * codecs.
1056          * The PCI register TCSEL is defined in the Intel manuals.
1057          */
1058         if (chip->driver_type != AZX_DRIVER_ATI &&
1059             chip->driver_type != AZX_DRIVER_ATIHDMI)
1060                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1061
1062         switch (chip->driver_type) {
1063         case AZX_DRIVER_ATI:
1064                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1065                 update_pci_byte(chip->pci,
1066                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1067                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1068                 break;
1069         case AZX_DRIVER_NVIDIA:
1070                 /* For NVIDIA HDA, enable snoop */
1071                 update_pci_byte(chip->pci,
1072                                 NVIDIA_HDA_TRANSREG_ADDR,
1073                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1074                 update_pci_byte(chip->pci,
1075                                 NVIDIA_HDA_ISTRM_COH,
1076                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1077                 update_pci_byte(chip->pci,
1078                                 NVIDIA_HDA_OSTRM_COH,
1079                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1080                 break;
1081         case AZX_DRIVER_SCH:
1082         case AZX_DRIVER_PCH:
1083                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1084                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1085                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1086                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1087                         pci_read_config_word(chip->pci,
1088                                 INTEL_SCH_HDA_DEVC, &snoop);
1089                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1090                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1091                                 ? "Failed" : "OK");
1092                 }
1093                 break;
1094
1095         }
1096 }
1097
1098
1099 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1100
1101 /*
1102  * interrupt handler
1103  */
1104 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1105 {
1106         struct azx *chip = dev_id;
1107         struct azx_dev *azx_dev;
1108         u32 status;
1109         u8 sd_status;
1110         int i, ok;
1111
1112         spin_lock(&chip->reg_lock);
1113
1114         status = azx_readl(chip, INTSTS);
1115         if (status == 0) {
1116                 spin_unlock(&chip->reg_lock);
1117                 return IRQ_NONE;
1118         }
1119
1120         for (i = 0; i < chip->num_streams; i++) {
1121                 azx_dev = &chip->azx_dev[i];
1122                 if (status & azx_dev->sd_int_sta_mask) {
1123                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1124                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1125                         if (!azx_dev->substream || !azx_dev->running ||
1126                             !(sd_status & SD_INT_COMPLETE))
1127                                 continue;
1128                         /* check whether this IRQ is really acceptable */
1129                         ok = azx_position_ok(chip, azx_dev);
1130                         if (ok == 1) {
1131                                 azx_dev->irq_pending = 0;
1132                                 spin_unlock(&chip->reg_lock);
1133                                 snd_pcm_period_elapsed(azx_dev->substream);
1134                                 spin_lock(&chip->reg_lock);
1135                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1136                                 /* bogus IRQ, process it later */
1137                                 azx_dev->irq_pending = 1;
1138                                 queue_work(chip->bus->workq,
1139                                            &chip->irq_pending_work);
1140                         }
1141                 }
1142         }
1143
1144         /* clear rirb int */
1145         status = azx_readb(chip, RIRBSTS);
1146         if (status & RIRB_INT_MASK) {
1147                 if (status & RIRB_INT_RESPONSE) {
1148                         if (chip->driver_type == AZX_DRIVER_CTX)
1149                                 udelay(80);
1150                         azx_update_rirb(chip);
1151                 }
1152                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1153         }
1154
1155 #if 0
1156         /* clear state status int */
1157         if (azx_readb(chip, STATESTS) & 0x04)
1158                 azx_writeb(chip, STATESTS, 0x04);
1159 #endif
1160         spin_unlock(&chip->reg_lock);
1161
1162         return IRQ_HANDLED;
1163 }
1164
1165
1166 /*
1167  * set up a BDL entry
1168  */
1169 static int setup_bdle(struct snd_pcm_substream *substream,
1170                       struct azx_dev *azx_dev, u32 **bdlp,
1171                       int ofs, int size, int with_ioc)
1172 {
1173         u32 *bdl = *bdlp;
1174
1175         while (size > 0) {
1176                 dma_addr_t addr;
1177                 int chunk;
1178
1179                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1180                         return -EINVAL;
1181
1182                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1183                 /* program the address field of the BDL entry */
1184                 bdl[0] = cpu_to_le32((u32)addr);
1185                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1186                 /* program the size field of the BDL entry */
1187                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1188                 bdl[2] = cpu_to_le32(chunk);
1189                 /* program the IOC to enable interrupt
1190                  * only when the whole fragment is processed
1191                  */
1192                 size -= chunk;
1193                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1194                 bdl += 4;
1195                 azx_dev->frags++;
1196                 ofs += chunk;
1197         }
1198         *bdlp = bdl;
1199         return ofs;
1200 }
1201
1202 /*
1203  * set up BDL entries
1204  */
1205 static int azx_setup_periods(struct azx *chip,
1206                              struct snd_pcm_substream *substream,
1207                              struct azx_dev *azx_dev)
1208 {
1209         u32 *bdl;
1210         int i, ofs, periods, period_bytes;
1211         int pos_adj;
1212
1213         /* reset BDL address */
1214         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1215         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1216
1217         period_bytes = azx_dev->period_bytes;
1218         periods = azx_dev->bufsize / period_bytes;
1219
1220         /* program the initial BDL entries */
1221         bdl = (u32 *)azx_dev->bdl.area;
1222         ofs = 0;
1223         azx_dev->frags = 0;
1224         pos_adj = bdl_pos_adj[chip->dev_index];
1225         if (pos_adj > 0) {
1226                 struct snd_pcm_runtime *runtime = substream->runtime;
1227                 int pos_align = pos_adj;
1228                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1229                 if (!pos_adj)
1230                         pos_adj = pos_align;
1231                 else
1232                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1233                                 pos_align;
1234                 pos_adj = frames_to_bytes(runtime, pos_adj);
1235                 if (pos_adj >= period_bytes) {
1236                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1237                                    bdl_pos_adj[chip->dev_index]);
1238                         pos_adj = 0;
1239                 } else {
1240                         ofs = setup_bdle(substream, azx_dev,
1241                                          &bdl, ofs, pos_adj,
1242                                          !substream->runtime->no_period_wakeup);
1243                         if (ofs < 0)
1244                                 goto error;
1245                 }
1246         } else
1247                 pos_adj = 0;
1248         for (i = 0; i < periods; i++) {
1249                 if (i == periods - 1 && pos_adj)
1250                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1251                                          period_bytes - pos_adj, 0);
1252                 else
1253                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1254                                          period_bytes,
1255                                          !substream->runtime->no_period_wakeup);
1256                 if (ofs < 0)
1257                         goto error;
1258         }
1259         return 0;
1260
1261  error:
1262         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1263                    azx_dev->bufsize, period_bytes);
1264         return -EINVAL;
1265 }
1266
1267 /* reset stream */
1268 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1269 {
1270         unsigned char val;
1271         int timeout;
1272
1273         azx_stream_clear(chip, azx_dev);
1274
1275         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1276                       SD_CTL_STREAM_RESET);
1277         udelay(3);
1278         timeout = 300;
1279         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1280                --timeout)
1281                 ;
1282         val &= ~SD_CTL_STREAM_RESET;
1283         azx_sd_writeb(azx_dev, SD_CTL, val);
1284         udelay(3);
1285
1286         timeout = 300;
1287         /* waiting for hardware to report that the stream is out of reset */
1288         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1289                --timeout)
1290                 ;
1291
1292         /* reset first position - may not be synced with hw at this time */
1293         *azx_dev->posbuf = 0;
1294 }
1295
1296 /*
1297  * set up the SD for streaming
1298  */
1299 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1300 {
1301         /* make sure the run bit is zero for SD */
1302         azx_stream_clear(chip, azx_dev);
1303         /* program the stream_tag */
1304         azx_sd_writel(azx_dev, SD_CTL,
1305                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1306                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1307
1308         /* program the length of samples in cyclic buffer */
1309         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1310
1311         /* program the stream format */
1312         /* this value needs to be the same as the one programmed */
1313         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1314
1315         /* program the stream LVI (last valid index) of the BDL */
1316         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1317
1318         /* program the BDL address */
1319         /* lower BDL address */
1320         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1321         /* upper BDL address */
1322         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1323
1324         /* enable the position buffer */
1325         if (chip->position_fix[0] != POS_FIX_LPIB ||
1326             chip->position_fix[1] != POS_FIX_LPIB) {
1327                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1328                         azx_writel(chip, DPLBASE,
1329                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1330         }
1331
1332         /* set the interrupt enable bits in the descriptor control register */
1333         azx_sd_writel(azx_dev, SD_CTL,
1334                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1335
1336         return 0;
1337 }
1338
1339 /*
1340  * Probe the given codec address
1341  */
1342 static int probe_codec(struct azx *chip, int addr)
1343 {
1344         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1345                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1346         unsigned int res;
1347
1348         mutex_lock(&chip->bus->cmd_mutex);
1349         chip->probing = 1;
1350         azx_send_cmd(chip->bus, cmd);
1351         res = azx_get_response(chip->bus, addr);
1352         chip->probing = 0;
1353         mutex_unlock(&chip->bus->cmd_mutex);
1354         if (res == -1)
1355                 return -EIO;
1356         snd_printdd(SFX "codec #%d probed OK\n", addr);
1357         return 0;
1358 }
1359
1360 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1361                                  struct hda_pcm *cpcm);
1362 static void azx_stop_chip(struct azx *chip);
1363
1364 static void azx_bus_reset(struct hda_bus *bus)
1365 {
1366         struct azx *chip = bus->private_data;
1367
1368         bus->in_reset = 1;
1369         azx_stop_chip(chip);
1370         azx_init_chip(chip, 1);
1371 #ifdef CONFIG_PM
1372         if (chip->initialized) {
1373                 int i;
1374
1375                 for (i = 0; i < HDA_MAX_PCMS; i++)
1376                         snd_pcm_suspend_all(chip->pcm[i]);
1377                 snd_hda_suspend(chip->bus);
1378                 snd_hda_resume(chip->bus);
1379         }
1380 #endif
1381         bus->in_reset = 0;
1382 }
1383
1384 /*
1385  * Codec initialization
1386  */
1387
1388 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1389 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1390         [AZX_DRIVER_NVIDIA] = 8,
1391         [AZX_DRIVER_TERA] = 1,
1392 };
1393
1394 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1395 {
1396         struct hda_bus_template bus_temp;
1397         int c, codecs, err;
1398         int max_slots;
1399
1400         memset(&bus_temp, 0, sizeof(bus_temp));
1401         bus_temp.private_data = chip;
1402         bus_temp.modelname = model;
1403         bus_temp.pci = chip->pci;
1404         bus_temp.ops.command = azx_send_cmd;
1405         bus_temp.ops.get_response = azx_get_response;
1406         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1407         bus_temp.ops.bus_reset = azx_bus_reset;
1408 #ifdef CONFIG_SND_HDA_POWER_SAVE
1409         bus_temp.power_save = &power_save;
1410         bus_temp.ops.pm_notify = azx_power_notify;
1411 #endif
1412
1413         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1414         if (err < 0)
1415                 return err;
1416
1417         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1418                 chip->bus->needs_damn_long_delay = 1;
1419
1420         codecs = 0;
1421         max_slots = azx_max_codecs[chip->driver_type];
1422         if (!max_slots)
1423                 max_slots = AZX_DEFAULT_CODECS;
1424
1425         /* First try to probe all given codec slots */
1426         for (c = 0; c < max_slots; c++) {
1427                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1428                         if (probe_codec(chip, c) < 0) {
1429                                 /* Some BIOSen give you wrong codec addresses
1430                                  * that don't exist
1431                                  */
1432                                 snd_printk(KERN_WARNING SFX
1433                                            "Codec #%d probe error; "
1434                                            "disabling it...\n", c);
1435                                 chip->codec_mask &= ~(1 << c);
1436                                 /* More badly, accessing to a non-existing
1437                                  * codec often screws up the controller chip,
1438                                  * and disturbs the further communications.
1439                                  * Thus if an error occurs during probing,
1440                                  * better to reset the controller chip to
1441                                  * get back to the sanity state.
1442                                  */
1443                                 azx_stop_chip(chip);
1444                                 azx_init_chip(chip, 1);
1445                         }
1446                 }
1447         }
1448
1449         /* Then create codec instances */
1450         for (c = 0; c < max_slots; c++) {
1451                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1452                         struct hda_codec *codec;
1453                         err = snd_hda_codec_new(chip->bus, c, &codec);
1454                         if (err < 0)
1455                                 continue;
1456                         codec->beep_mode = chip->beep_mode;
1457                         codecs++;
1458                 }
1459         }
1460         if (!codecs) {
1461                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1462                 return -ENXIO;
1463         }
1464         return 0;
1465 }
1466
1467 /* configure each codec instance */
1468 static int __devinit azx_codec_configure(struct azx *chip)
1469 {
1470         struct hda_codec *codec;
1471         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1472                 snd_hda_codec_configure(codec);
1473         }
1474         return 0;
1475 }
1476
1477
1478 /*
1479  * PCM support
1480  */
1481
1482 /* assign a stream for the PCM */
1483 static inline struct azx_dev *
1484 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1485 {
1486         int dev, i, nums;
1487         struct azx_dev *res = NULL;
1488
1489         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1490                 dev = chip->playback_index_offset;
1491                 nums = chip->playback_streams;
1492         } else {
1493                 dev = chip->capture_index_offset;
1494                 nums = chip->capture_streams;
1495         }
1496         for (i = 0; i < nums; i++, dev++)
1497                 if (!chip->azx_dev[dev].opened) {
1498                         res = &chip->azx_dev[dev];
1499                         if (res->device == substream->pcm->device)
1500                                 break;
1501                 }
1502         if (res) {
1503                 res->opened = 1;
1504                 res->device = substream->pcm->device;
1505         }
1506         return res;
1507 }
1508
1509 /* release the assigned stream */
1510 static inline void azx_release_device(struct azx_dev *azx_dev)
1511 {
1512         azx_dev->opened = 0;
1513 }
1514
1515 static struct snd_pcm_hardware azx_pcm_hw = {
1516         .info =                 (SNDRV_PCM_INFO_MMAP |
1517                                  SNDRV_PCM_INFO_INTERLEAVED |
1518                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1519                                  SNDRV_PCM_INFO_MMAP_VALID |
1520                                  /* No full-resume yet implemented */
1521                                  /* SNDRV_PCM_INFO_RESUME |*/
1522                                  SNDRV_PCM_INFO_PAUSE |
1523                                  SNDRV_PCM_INFO_SYNC_START |
1524                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1525         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1526         .rates =                SNDRV_PCM_RATE_48000,
1527         .rate_min =             48000,
1528         .rate_max =             48000,
1529         .channels_min =         2,
1530         .channels_max =         2,
1531         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1532         .period_bytes_min =     128,
1533         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1534         .periods_min =          2,
1535         .periods_max =          AZX_MAX_FRAG,
1536         .fifo_size =            0,
1537 };
1538
1539 struct azx_pcm {
1540         struct azx *chip;
1541         struct hda_codec *codec;
1542         struct hda_pcm_stream *hinfo[2];
1543 };
1544
1545 static int azx_pcm_open(struct snd_pcm_substream *substream)
1546 {
1547         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1548         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1549         struct azx *chip = apcm->chip;
1550         struct azx_dev *azx_dev;
1551         struct snd_pcm_runtime *runtime = substream->runtime;
1552         unsigned long flags;
1553         int err;
1554
1555         mutex_lock(&chip->open_mutex);
1556         azx_dev = azx_assign_device(chip, substream);
1557         if (azx_dev == NULL) {
1558                 mutex_unlock(&chip->open_mutex);
1559                 return -EBUSY;
1560         }
1561         runtime->hw = azx_pcm_hw;
1562         runtime->hw.channels_min = hinfo->channels_min;
1563         runtime->hw.channels_max = hinfo->channels_max;
1564         runtime->hw.formats = hinfo->formats;
1565         runtime->hw.rates = hinfo->rates;
1566         snd_pcm_limit_hw_rates(runtime);
1567         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1568         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1569                                    128);
1570         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1571                                    128);
1572         snd_hda_power_up(apcm->codec);
1573         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1574         if (err < 0) {
1575                 azx_release_device(azx_dev);
1576                 snd_hda_power_down(apcm->codec);
1577                 mutex_unlock(&chip->open_mutex);
1578                 return err;
1579         }
1580         snd_pcm_limit_hw_rates(runtime);
1581         /* sanity check */
1582         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1583             snd_BUG_ON(!runtime->hw.channels_max) ||
1584             snd_BUG_ON(!runtime->hw.formats) ||
1585             snd_BUG_ON(!runtime->hw.rates)) {
1586                 azx_release_device(azx_dev);
1587                 hinfo->ops.close(hinfo, apcm->codec, substream);
1588                 snd_hda_power_down(apcm->codec);
1589                 mutex_unlock(&chip->open_mutex);
1590                 return -EINVAL;
1591         }
1592         spin_lock_irqsave(&chip->reg_lock, flags);
1593         azx_dev->substream = substream;
1594         azx_dev->running = 0;
1595         spin_unlock_irqrestore(&chip->reg_lock, flags);
1596
1597         runtime->private_data = azx_dev;
1598         snd_pcm_set_sync(substream);
1599         mutex_unlock(&chip->open_mutex);
1600         return 0;
1601 }
1602
1603 static int azx_pcm_close(struct snd_pcm_substream *substream)
1604 {
1605         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1606         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1607         struct azx *chip = apcm->chip;
1608         struct azx_dev *azx_dev = get_azx_dev(substream);
1609         unsigned long flags;
1610
1611         mutex_lock(&chip->open_mutex);
1612         spin_lock_irqsave(&chip->reg_lock, flags);
1613         azx_dev->substream = NULL;
1614         azx_dev->running = 0;
1615         spin_unlock_irqrestore(&chip->reg_lock, flags);
1616         azx_release_device(azx_dev);
1617         hinfo->ops.close(hinfo, apcm->codec, substream);
1618         snd_hda_power_down(apcm->codec);
1619         mutex_unlock(&chip->open_mutex);
1620         return 0;
1621 }
1622
1623 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1624                              struct snd_pcm_hw_params *hw_params)
1625 {
1626         struct azx_dev *azx_dev = get_azx_dev(substream);
1627
1628         azx_dev->bufsize = 0;
1629         azx_dev->period_bytes = 0;
1630         azx_dev->format_val = 0;
1631         return snd_pcm_lib_malloc_pages(substream,
1632                                         params_buffer_bytes(hw_params));
1633 }
1634
1635 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1636 {
1637         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1638         struct azx_dev *azx_dev = get_azx_dev(substream);
1639         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1640
1641         /* reset BDL address */
1642         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1643         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1644         azx_sd_writel(azx_dev, SD_CTL, 0);
1645         azx_dev->bufsize = 0;
1646         azx_dev->period_bytes = 0;
1647         azx_dev->format_val = 0;
1648
1649         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1650
1651         return snd_pcm_lib_free_pages(substream);
1652 }
1653
1654 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1655 {
1656         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1657         struct azx *chip = apcm->chip;
1658         struct azx_dev *azx_dev = get_azx_dev(substream);
1659         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1660         struct snd_pcm_runtime *runtime = substream->runtime;
1661         unsigned int bufsize, period_bytes, format_val, stream_tag;
1662         int err;
1663
1664         azx_stream_reset(chip, azx_dev);
1665         format_val = snd_hda_calc_stream_format(runtime->rate,
1666                                                 runtime->channels,
1667                                                 runtime->format,
1668                                                 hinfo->maxbps,
1669                                                 apcm->codec->spdif_ctls);
1670         if (!format_val) {
1671                 snd_printk(KERN_ERR SFX
1672                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1673                            runtime->rate, runtime->channels, runtime->format);
1674                 return -EINVAL;
1675         }
1676
1677         bufsize = snd_pcm_lib_buffer_bytes(substream);
1678         period_bytes = snd_pcm_lib_period_bytes(substream);
1679
1680         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1681                     bufsize, format_val);
1682
1683         if (bufsize != azx_dev->bufsize ||
1684             period_bytes != azx_dev->period_bytes ||
1685             format_val != azx_dev->format_val) {
1686                 azx_dev->bufsize = bufsize;
1687                 azx_dev->period_bytes = period_bytes;
1688                 azx_dev->format_val = format_val;
1689                 err = azx_setup_periods(chip, substream, azx_dev);
1690                 if (err < 0)
1691                         return err;
1692         }
1693
1694         /* wallclk has 24Mhz clock source */
1695         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1696                                                 runtime->rate) * 1000);
1697         azx_setup_controller(chip, azx_dev);
1698         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1699                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1700         else
1701                 azx_dev->fifo_size = 0;
1702
1703         stream_tag = azx_dev->stream_tag;
1704         /* CA-IBG chips need the playback stream starting from 1 */
1705         if (chip->driver_type == AZX_DRIVER_CTX &&
1706             stream_tag > chip->capture_streams)
1707                 stream_tag -= chip->capture_streams;
1708         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1709                                      azx_dev->format_val, substream);
1710 }
1711
1712 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1713 {
1714         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1715         struct azx *chip = apcm->chip;
1716         struct azx_dev *azx_dev;
1717         struct snd_pcm_substream *s;
1718         int rstart = 0, start, nsync = 0, sbits = 0;
1719         int nwait, timeout;
1720
1721         switch (cmd) {
1722         case SNDRV_PCM_TRIGGER_START:
1723                 rstart = 1;
1724         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1725         case SNDRV_PCM_TRIGGER_RESUME:
1726                 start = 1;
1727                 break;
1728         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1729         case SNDRV_PCM_TRIGGER_SUSPEND:
1730         case SNDRV_PCM_TRIGGER_STOP:
1731                 start = 0;
1732                 break;
1733         default:
1734                 return -EINVAL;
1735         }
1736
1737         snd_pcm_group_for_each_entry(s, substream) {
1738                 if (s->pcm->card != substream->pcm->card)
1739                         continue;
1740                 azx_dev = get_azx_dev(s);
1741                 sbits |= 1 << azx_dev->index;
1742                 nsync++;
1743                 snd_pcm_trigger_done(s, substream);
1744         }
1745
1746         spin_lock(&chip->reg_lock);
1747         if (nsync > 1) {
1748                 /* first, set SYNC bits of corresponding streams */
1749                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1750         }
1751         snd_pcm_group_for_each_entry(s, substream) {
1752                 if (s->pcm->card != substream->pcm->card)
1753                         continue;
1754                 azx_dev = get_azx_dev(s);
1755                 if (start) {
1756                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1757                         if (!rstart)
1758                                 azx_dev->start_wallclk -=
1759                                                 azx_dev->period_wallclk;
1760                         azx_stream_start(chip, azx_dev);
1761                 } else {
1762                         azx_stream_stop(chip, azx_dev);
1763                 }
1764                 azx_dev->running = start;
1765         }
1766         spin_unlock(&chip->reg_lock);
1767         if (start) {
1768                 if (nsync == 1)
1769                         return 0;
1770                 /* wait until all FIFOs get ready */
1771                 for (timeout = 5000; timeout; timeout--) {
1772                         nwait = 0;
1773                         snd_pcm_group_for_each_entry(s, substream) {
1774                                 if (s->pcm->card != substream->pcm->card)
1775                                         continue;
1776                                 azx_dev = get_azx_dev(s);
1777                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1778                                       SD_STS_FIFO_READY))
1779                                         nwait++;
1780                         }
1781                         if (!nwait)
1782                                 break;
1783                         cpu_relax();
1784                 }
1785         } else {
1786                 /* wait until all RUN bits are cleared */
1787                 for (timeout = 5000; timeout; timeout--) {
1788                         nwait = 0;
1789                         snd_pcm_group_for_each_entry(s, substream) {
1790                                 if (s->pcm->card != substream->pcm->card)
1791                                         continue;
1792                                 azx_dev = get_azx_dev(s);
1793                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1794                                     SD_CTL_DMA_START)
1795                                         nwait++;
1796                         }
1797                         if (!nwait)
1798                                 break;
1799                         cpu_relax();
1800                 }
1801         }
1802         if (nsync > 1) {
1803                 spin_lock(&chip->reg_lock);
1804                 /* reset SYNC bits */
1805                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1806                 spin_unlock(&chip->reg_lock);
1807         }
1808         return 0;
1809 }
1810
1811 /* get the current DMA position with correction on VIA chips */
1812 static unsigned int azx_via_get_position(struct azx *chip,
1813                                          struct azx_dev *azx_dev)
1814 {
1815         unsigned int link_pos, mini_pos, bound_pos;
1816         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1817         unsigned int fifo_size;
1818
1819         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1820         if (azx_dev->index >= 4) {
1821                 /* Playback, no problem using link position */
1822                 return link_pos;
1823         }
1824
1825         /* Capture */
1826         /* For new chipset,
1827          * use mod to get the DMA position just like old chipset
1828          */
1829         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1830         mod_dma_pos %= azx_dev->period_bytes;
1831
1832         /* azx_dev->fifo_size can't get FIFO size of in stream.
1833          * Get from base address + offset.
1834          */
1835         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1836
1837         if (azx_dev->insufficient) {
1838                 /* Link position never gather than FIFO size */
1839                 if (link_pos <= fifo_size)
1840                         return 0;
1841
1842                 azx_dev->insufficient = 0;
1843         }
1844
1845         if (link_pos <= fifo_size)
1846                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1847         else
1848                 mini_pos = link_pos - fifo_size;
1849
1850         /* Find nearest previous boudary */
1851         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1852         mod_link_pos = link_pos % azx_dev->period_bytes;
1853         if (mod_link_pos >= fifo_size)
1854                 bound_pos = link_pos - mod_link_pos;
1855         else if (mod_dma_pos >= mod_mini_pos)
1856                 bound_pos = mini_pos - mod_mini_pos;
1857         else {
1858                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1859                 if (bound_pos >= azx_dev->bufsize)
1860                         bound_pos = 0;
1861         }
1862
1863         /* Calculate real DMA position we want */
1864         return bound_pos + mod_dma_pos;
1865 }
1866
1867 static unsigned int azx_get_position(struct azx *chip,
1868                                      struct azx_dev *azx_dev)
1869 {
1870         unsigned int pos;
1871         int stream = azx_dev->substream->stream;
1872
1873         switch (chip->position_fix[stream]) {
1874         case POS_FIX_LPIB:
1875                 /* read LPIB */
1876                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1877                 break;
1878         case POS_FIX_VIACOMBO:
1879                 pos = azx_via_get_position(chip, azx_dev);
1880                 break;
1881         default:
1882                 /* use the position buffer */
1883                 pos = le32_to_cpu(*azx_dev->posbuf);
1884         }
1885
1886         if (pos >= azx_dev->bufsize)
1887                 pos = 0;
1888         return pos;
1889 }
1890
1891 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1892 {
1893         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1894         struct azx *chip = apcm->chip;
1895         struct azx_dev *azx_dev = get_azx_dev(substream);
1896         return bytes_to_frames(substream->runtime,
1897                                azx_get_position(chip, azx_dev));
1898 }
1899
1900 /*
1901  * Check whether the current DMA position is acceptable for updating
1902  * periods.  Returns non-zero if it's OK.
1903  *
1904  * Many HD-audio controllers appear pretty inaccurate about
1905  * the update-IRQ timing.  The IRQ is issued before actually the
1906  * data is processed.  So, we need to process it afterwords in a
1907  * workqueue.
1908  */
1909 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1910 {
1911         u32 wallclk;
1912         unsigned int pos;
1913         int stream;
1914
1915         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1916         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1917                 return -1;      /* bogus (too early) interrupt */
1918
1919         stream = azx_dev->substream->stream;
1920         pos = azx_get_position(chip, azx_dev);
1921         if (chip->position_fix[stream] == POS_FIX_AUTO) {
1922                 if (!pos) {
1923                         printk(KERN_WARNING
1924                                "hda-intel: Invalid position buffer, "
1925                                "using LPIB read method instead.\n");
1926                         chip->position_fix[stream] = POS_FIX_LPIB;
1927                         pos = azx_get_position(chip, azx_dev);
1928                 } else
1929                         chip->position_fix[stream] = POS_FIX_POSBUF;
1930         }
1931
1932         if (WARN_ONCE(!azx_dev->period_bytes,
1933                       "hda-intel: zero azx_dev->period_bytes"))
1934                 return -1; /* this shouldn't happen! */
1935         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1936             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1937                 /* NG - it's below the first next period boundary */
1938                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1939         azx_dev->start_wallclk += wallclk;
1940         return 1; /* OK, it's fine */
1941 }
1942
1943 /*
1944  * The work for pending PCM period updates.
1945  */
1946 static void azx_irq_pending_work(struct work_struct *work)
1947 {
1948         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1949         int i, pending, ok;
1950
1951         if (!chip->irq_pending_warned) {
1952                 printk(KERN_WARNING
1953                        "hda-intel: IRQ timing workaround is activated "
1954                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1955                        chip->card->number);
1956                 chip->irq_pending_warned = 1;
1957         }
1958
1959         for (;;) {
1960                 pending = 0;
1961                 spin_lock_irq(&chip->reg_lock);
1962                 for (i = 0; i < chip->num_streams; i++) {
1963                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1964                         if (!azx_dev->irq_pending ||
1965                             !azx_dev->substream ||
1966                             !azx_dev->running)
1967                                 continue;
1968                         ok = azx_position_ok(chip, azx_dev);
1969                         if (ok > 0) {
1970                                 azx_dev->irq_pending = 0;
1971                                 spin_unlock(&chip->reg_lock);
1972                                 snd_pcm_period_elapsed(azx_dev->substream);
1973                                 spin_lock(&chip->reg_lock);
1974                         } else if (ok < 0) {
1975                                 pending = 0;    /* too early */
1976                         } else
1977                                 pending++;
1978                 }
1979                 spin_unlock_irq(&chip->reg_lock);
1980                 if (!pending)
1981                         return;
1982                 msleep(1);
1983         }
1984 }
1985
1986 /* clear irq_pending flags and assure no on-going workq */
1987 static void azx_clear_irq_pending(struct azx *chip)
1988 {
1989         int i;
1990
1991         spin_lock_irq(&chip->reg_lock);
1992         for (i = 0; i < chip->num_streams; i++)
1993                 chip->azx_dev[i].irq_pending = 0;
1994         spin_unlock_irq(&chip->reg_lock);
1995 }
1996
1997 static struct snd_pcm_ops azx_pcm_ops = {
1998         .open = azx_pcm_open,
1999         .close = azx_pcm_close,
2000         .ioctl = snd_pcm_lib_ioctl,
2001         .hw_params = azx_pcm_hw_params,
2002         .hw_free = azx_pcm_hw_free,
2003         .prepare = azx_pcm_prepare,
2004         .trigger = azx_pcm_trigger,
2005         .pointer = azx_pcm_pointer,
2006         .page = snd_pcm_sgbuf_ops_page,
2007 };
2008
2009 static void azx_pcm_free(struct snd_pcm *pcm)
2010 {
2011         struct azx_pcm *apcm = pcm->private_data;
2012         if (apcm) {
2013                 apcm->chip->pcm[pcm->device] = NULL;
2014                 kfree(apcm);
2015         }
2016 }
2017
2018 static int
2019 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2020                       struct hda_pcm *cpcm)
2021 {
2022         struct azx *chip = bus->private_data;
2023         struct snd_pcm *pcm;
2024         struct azx_pcm *apcm;
2025         int pcm_dev = cpcm->device;
2026         int s, err;
2027
2028         if (pcm_dev >= HDA_MAX_PCMS) {
2029                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2030                            pcm_dev);
2031                 return -EINVAL;
2032         }
2033         if (chip->pcm[pcm_dev]) {
2034                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2035                 return -EBUSY;
2036         }
2037         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2038                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2039                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2040                           &pcm);
2041         if (err < 0)
2042                 return err;
2043         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2044         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2045         if (apcm == NULL)
2046                 return -ENOMEM;
2047         apcm->chip = chip;
2048         apcm->codec = codec;
2049         pcm->private_data = apcm;
2050         pcm->private_free = azx_pcm_free;
2051         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2052                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2053         chip->pcm[pcm_dev] = pcm;
2054         cpcm->pcm = pcm;
2055         for (s = 0; s < 2; s++) {
2056                 apcm->hinfo[s] = &cpcm->stream[s];
2057                 if (cpcm->stream[s].substreams)
2058                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2059         }
2060         /* buffer pre-allocation */
2061         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2062                                               snd_dma_pci_data(chip->pci),
2063                                               1024 * 64, 32 * 1024 * 1024);
2064         return 0;
2065 }
2066
2067 /*
2068  * mixer creation - all stuff is implemented in hda module
2069  */
2070 static int __devinit azx_mixer_create(struct azx *chip)
2071 {
2072         return snd_hda_build_controls(chip->bus);
2073 }
2074
2075
2076 /*
2077  * initialize SD streams
2078  */
2079 static int __devinit azx_init_stream(struct azx *chip)
2080 {
2081         int i;
2082
2083         /* initialize each stream (aka device)
2084          * assign the starting bdl address to each stream (device)
2085          * and initialize
2086          */
2087         for (i = 0; i < chip->num_streams; i++) {
2088                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2089                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2090                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2091                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2092                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2093                 azx_dev->sd_int_sta_mask = 1 << i;
2094                 /* stream tag: must be non-zero and unique */
2095                 azx_dev->index = i;
2096                 azx_dev->stream_tag = i + 1;
2097         }
2098
2099         return 0;
2100 }
2101
2102 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2103 {
2104         if (request_irq(chip->pci->irq, azx_interrupt,
2105                         chip->msi ? 0 : IRQF_SHARED,
2106                         "hda_intel", chip)) {
2107                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2108                        "disabling device\n", chip->pci->irq);
2109                 if (do_disconnect)
2110                         snd_card_disconnect(chip->card);
2111                 return -1;
2112         }
2113         chip->irq = chip->pci->irq;
2114         pci_intx(chip->pci, !chip->msi);
2115         return 0;
2116 }
2117
2118
2119 static void azx_stop_chip(struct azx *chip)
2120 {
2121         if (!chip->initialized)
2122                 return;
2123
2124         /* disable interrupts */
2125         azx_int_disable(chip);
2126         azx_int_clear(chip);
2127
2128         /* disable CORB/RIRB */
2129         azx_free_cmd_io(chip);
2130
2131         /* disable position buffer */
2132         azx_writel(chip, DPLBASE, 0);
2133         azx_writel(chip, DPUBASE, 0);
2134
2135         chip->initialized = 0;
2136 }
2137
2138 #ifdef CONFIG_SND_HDA_POWER_SAVE
2139 /* power-up/down the controller */
2140 static void azx_power_notify(struct hda_bus *bus)
2141 {
2142         struct azx *chip = bus->private_data;
2143         struct hda_codec *c;
2144         int power_on = 0;
2145
2146         list_for_each_entry(c, &bus->codec_list, list) {
2147                 if (c->power_on) {
2148                         power_on = 1;
2149                         break;
2150                 }
2151         }
2152         if (power_on)
2153                 azx_init_chip(chip, 1);
2154         else if (chip->running && power_save_controller &&
2155                  !bus->power_keep_link_on)
2156                 azx_stop_chip(chip);
2157 }
2158 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2159
2160 #ifdef CONFIG_PM
2161 /*
2162  * power management
2163  */
2164
2165 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2166 {
2167         struct hda_codec *codec;
2168
2169         list_for_each_entry(codec, &bus->codec_list, list) {
2170                 if (snd_hda_codec_needs_resume(codec))
2171                         return 1;
2172         }
2173         return 0;
2174 }
2175
2176 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2177 {
2178         struct snd_card *card = pci_get_drvdata(pci);
2179         struct azx *chip = card->private_data;
2180         int i;
2181
2182         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2183         azx_clear_irq_pending(chip);
2184         for (i = 0; i < HDA_MAX_PCMS; i++)
2185                 snd_pcm_suspend_all(chip->pcm[i]);
2186         if (chip->initialized)
2187                 snd_hda_suspend(chip->bus);
2188         azx_stop_chip(chip);
2189         if (chip->irq >= 0) {
2190                 free_irq(chip->irq, chip);
2191                 chip->irq = -1;
2192         }
2193         if (chip->msi)
2194                 pci_disable_msi(chip->pci);
2195         pci_disable_device(pci);
2196         pci_save_state(pci);
2197         pci_set_power_state(pci, pci_choose_state(pci, state));
2198         return 0;
2199 }
2200
2201 static int azx_resume(struct pci_dev *pci)
2202 {
2203         struct snd_card *card = pci_get_drvdata(pci);
2204         struct azx *chip = card->private_data;
2205
2206         pci_set_power_state(pci, PCI_D0);
2207         pci_restore_state(pci);
2208         if (pci_enable_device(pci) < 0) {
2209                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2210                        "disabling device\n");
2211                 snd_card_disconnect(card);
2212                 return -EIO;
2213         }
2214         pci_set_master(pci);
2215         if (chip->msi)
2216                 if (pci_enable_msi(pci) < 0)
2217                         chip->msi = 0;
2218         if (azx_acquire_irq(chip, 1) < 0)
2219                 return -EIO;
2220         azx_init_pci(chip);
2221
2222         if (snd_hda_codecs_inuse(chip->bus))
2223                 azx_init_chip(chip, 1);
2224
2225         snd_hda_resume(chip->bus);
2226         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2227         return 0;
2228 }
2229 #endif /* CONFIG_PM */
2230
2231
2232 /*
2233  * reboot notifier for hang-up problem at power-down
2234  */
2235 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2236 {
2237         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2238         snd_hda_bus_reboot_notify(chip->bus);
2239         azx_stop_chip(chip);
2240         return NOTIFY_OK;
2241 }
2242
2243 static void azx_notifier_register(struct azx *chip)
2244 {
2245         chip->reboot_notifier.notifier_call = azx_halt;
2246         register_reboot_notifier(&chip->reboot_notifier);
2247 }
2248
2249 static void azx_notifier_unregister(struct azx *chip)
2250 {
2251         if (chip->reboot_notifier.notifier_call)
2252                 unregister_reboot_notifier(&chip->reboot_notifier);
2253 }
2254
2255 /*
2256  * destructor
2257  */
2258 static int azx_free(struct azx *chip)
2259 {
2260         int i;
2261
2262         azx_notifier_unregister(chip);
2263
2264         if (chip->initialized) {
2265                 azx_clear_irq_pending(chip);
2266                 for (i = 0; i < chip->num_streams; i++)
2267                         azx_stream_stop(chip, &chip->azx_dev[i]);
2268                 azx_stop_chip(chip);
2269         }
2270
2271         if (chip->irq >= 0)
2272                 free_irq(chip->irq, (void*)chip);
2273         if (chip->msi)
2274                 pci_disable_msi(chip->pci);
2275         if (chip->remap_addr)
2276                 iounmap(chip->remap_addr);
2277
2278         if (chip->azx_dev) {
2279                 for (i = 0; i < chip->num_streams; i++)
2280                         if (chip->azx_dev[i].bdl.area)
2281                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2282         }
2283         if (chip->rb.area)
2284                 snd_dma_free_pages(&chip->rb);
2285         if (chip->posbuf.area)
2286                 snd_dma_free_pages(&chip->posbuf);
2287         pci_release_regions(chip->pci);
2288         pci_disable_device(chip->pci);
2289         kfree(chip->azx_dev);
2290         kfree(chip);
2291
2292         return 0;
2293 }
2294
2295 static int azx_dev_free(struct snd_device *device)
2296 {
2297         return azx_free(device->device_data);
2298 }
2299
2300 /*
2301  * white/black-listing for position_fix
2302  */
2303 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2304         SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2305         SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2306         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2307         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2308         SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2309         SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2310         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2311         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2312         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2313         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2314         SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
2315         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2316         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2317         SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2318         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2319         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2320         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2321         SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2322         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2323         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2324         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2325         SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2326         {}
2327 };
2328
2329 static int __devinit check_position_fix(struct azx *chip, int fix)
2330 {
2331         const struct snd_pci_quirk *q;
2332
2333         switch (fix) {
2334         case POS_FIX_LPIB:
2335         case POS_FIX_POSBUF:
2336         case POS_FIX_VIACOMBO:
2337                 return fix;
2338         }
2339
2340         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2341         if (q) {
2342                 printk(KERN_INFO
2343                        "hda_intel: position_fix set to %d "
2344                        "for device %04x:%04x\n",
2345                        q->value, q->subvendor, q->subdevice);
2346                 return q->value;
2347         }
2348
2349         /* Check VIA/ATI HD Audio Controller exist */
2350         switch (chip->driver_type) {
2351         case AZX_DRIVER_VIA:
2352         case AZX_DRIVER_ATI:
2353                 /* Use link position directly, avoid any transfer problem. */
2354                 return POS_FIX_VIACOMBO;
2355         }
2356
2357         return POS_FIX_AUTO;
2358 }
2359
2360 /*
2361  * black-lists for probe_mask
2362  */
2363 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2364         /* Thinkpad often breaks the controller communication when accessing
2365          * to the non-working (or non-existing) modem codec slot.
2366          */
2367         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2368         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2369         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2370         /* broken BIOS */
2371         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2372         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2373         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2374         /* forced codec slots */
2375         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2376         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2377         {}
2378 };
2379
2380 #define AZX_FORCE_CODEC_MASK    0x100
2381
2382 static void __devinit check_probe_mask(struct azx *chip, int dev)
2383 {
2384         const struct snd_pci_quirk *q;
2385
2386         chip->codec_probe_mask = probe_mask[dev];
2387         if (chip->codec_probe_mask == -1) {
2388                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2389                 if (q) {
2390                         printk(KERN_INFO
2391                                "hda_intel: probe_mask set to 0x%x "
2392                                "for device %04x:%04x\n",
2393                                q->value, q->subvendor, q->subdevice);
2394                         chip->codec_probe_mask = q->value;
2395                 }
2396         }
2397
2398         /* check forced option */
2399         if (chip->codec_probe_mask != -1 &&
2400             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2401                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2402                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2403                        chip->codec_mask);
2404         }
2405 }
2406
2407 /*
2408  * white/black-list for enable_msi
2409  */
2410 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2411         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2412         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2413         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2414         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2415         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2416         {}
2417 };
2418
2419 static void __devinit check_msi(struct azx *chip)
2420 {
2421         const struct snd_pci_quirk *q;
2422
2423         if (enable_msi >= 0) {
2424                 chip->msi = !!enable_msi;
2425                 return;
2426         }
2427         chip->msi = 1;  /* enable MSI as default */
2428         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2429         if (q) {
2430                 printk(KERN_INFO
2431                        "hda_intel: msi for device %04x:%04x set to %d\n",
2432                        q->subvendor, q->subdevice, q->value);
2433                 chip->msi = q->value;
2434                 return;
2435         }
2436
2437         /* NVidia chipsets seem to cause troubles with MSI */
2438         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2439                 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2440                 chip->msi = 0;
2441         }
2442 }
2443
2444
2445 /*
2446  * constructor
2447  */
2448 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2449                                 int dev, int driver_type,
2450                                 struct azx **rchip)
2451 {
2452         struct azx *chip;
2453         int i, err;
2454         unsigned short gcap;
2455         static struct snd_device_ops ops = {
2456                 .dev_free = azx_dev_free,
2457         };
2458
2459         *rchip = NULL;
2460
2461         err = pci_enable_device(pci);
2462         if (err < 0)
2463                 return err;
2464
2465         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2466         if (!chip) {
2467                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2468                 pci_disable_device(pci);
2469                 return -ENOMEM;
2470         }
2471
2472         spin_lock_init(&chip->reg_lock);
2473         mutex_init(&chip->open_mutex);
2474         chip->card = card;
2475         chip->pci = pci;
2476         chip->irq = -1;
2477         chip->driver_type = driver_type;
2478         check_msi(chip);
2479         chip->dev_index = dev;
2480         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2481
2482         chip->position_fix[0] = chip->position_fix[1] =
2483                 check_position_fix(chip, position_fix[dev]);
2484         check_probe_mask(chip, dev);
2485
2486         chip->single_cmd = single_cmd;
2487
2488         if (bdl_pos_adj[dev] < 0) {
2489                 switch (chip->driver_type) {
2490                 case AZX_DRIVER_ICH:
2491                 case AZX_DRIVER_PCH:
2492                         bdl_pos_adj[dev] = 1;
2493                         break;
2494                 default:
2495                         bdl_pos_adj[dev] = 32;
2496                         break;
2497                 }
2498         }
2499
2500 #if BITS_PER_LONG != 64
2501         /* Fix up base address on ULI M5461 */
2502         if (chip->driver_type == AZX_DRIVER_ULI) {
2503                 u16 tmp3;
2504                 pci_read_config_word(pci, 0x40, &tmp3);
2505                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2506                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2507         }
2508 #endif
2509
2510         err = pci_request_regions(pci, "ICH HD audio");
2511         if (err < 0) {
2512                 kfree(chip);
2513                 pci_disable_device(pci);
2514                 return err;
2515         }
2516
2517         chip->addr = pci_resource_start(pci, 0);
2518         chip->remap_addr = pci_ioremap_bar(pci, 0);
2519         if (chip->remap_addr == NULL) {
2520                 snd_printk(KERN_ERR SFX "ioremap error\n");
2521                 err = -ENXIO;
2522                 goto errout;
2523         }
2524
2525         if (chip->msi)
2526                 if (pci_enable_msi(pci) < 0)
2527                         chip->msi = 0;
2528
2529         if (azx_acquire_irq(chip, 0) < 0) {
2530                 err = -EBUSY;
2531                 goto errout;
2532         }
2533
2534         pci_set_master(pci);
2535         synchronize_irq(chip->irq);
2536
2537         gcap = azx_readw(chip, GCAP);
2538         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2539
2540         /* disable SB600 64bit support for safety */
2541         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2542             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2543                 struct pci_dev *p_smbus;
2544                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2545                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2546                                          NULL);
2547                 if (p_smbus) {
2548                         if (p_smbus->revision < 0x30)
2549                                 gcap &= ~ICH6_GCAP_64OK;
2550                         pci_dev_put(p_smbus);
2551                 }
2552         }
2553
2554         /* disable 64bit DMA address for Teradici */
2555         /* it does not work with device 6549:1200 subsys e4a2:040b */
2556         if (chip->driver_type == AZX_DRIVER_TERA)
2557                 gcap &= ~ICH6_GCAP_64OK;
2558
2559         /* allow 64bit DMA address if supported by H/W */
2560         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2561                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2562         else {
2563                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2564                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2565         }
2566
2567         /* read number of streams from GCAP register instead of using
2568          * hardcoded value
2569          */
2570         chip->capture_streams = (gcap >> 8) & 0x0f;
2571         chip->playback_streams = (gcap >> 12) & 0x0f;
2572         if (!chip->playback_streams && !chip->capture_streams) {
2573                 /* gcap didn't give any info, switching to old method */
2574
2575                 switch (chip->driver_type) {
2576                 case AZX_DRIVER_ULI:
2577                         chip->playback_streams = ULI_NUM_PLAYBACK;
2578                         chip->capture_streams = ULI_NUM_CAPTURE;
2579                         break;
2580                 case AZX_DRIVER_ATIHDMI:
2581                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2582                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2583                         break;
2584                 case AZX_DRIVER_GENERIC:
2585                 default:
2586                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2587                         chip->capture_streams = ICH6_NUM_CAPTURE;
2588                         break;
2589                 }
2590         }
2591         chip->capture_index_offset = 0;
2592         chip->playback_index_offset = chip->capture_streams;
2593         chip->num_streams = chip->playback_streams + chip->capture_streams;
2594         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2595                                 GFP_KERNEL);
2596         if (!chip->azx_dev) {
2597                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2598                 goto errout;
2599         }
2600
2601         for (i = 0; i < chip->num_streams; i++) {
2602                 /* allocate memory for the BDL for each stream */
2603                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2604                                           snd_dma_pci_data(chip->pci),
2605                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2606                 if (err < 0) {
2607                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2608                         goto errout;
2609                 }
2610         }
2611         /* allocate memory for the position buffer */
2612         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2613                                   snd_dma_pci_data(chip->pci),
2614                                   chip->num_streams * 8, &chip->posbuf);
2615         if (err < 0) {
2616                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2617                 goto errout;
2618         }
2619         /* allocate CORB/RIRB */
2620         err = azx_alloc_cmd_io(chip);
2621         if (err < 0)
2622                 goto errout;
2623
2624         /* initialize streams */
2625         azx_init_stream(chip);
2626
2627         /* initialize chip */
2628         azx_init_pci(chip);
2629         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2630
2631         /* codec detection */
2632         if (!chip->codec_mask) {
2633                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2634                 err = -ENODEV;
2635                 goto errout;
2636         }
2637
2638         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2639         if (err <0) {
2640                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2641                 goto errout;
2642         }
2643
2644         strcpy(card->driver, "HDA-Intel");
2645         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2646                 sizeof(card->shortname));
2647         snprintf(card->longname, sizeof(card->longname),
2648                  "%s at 0x%lx irq %i",
2649                  card->shortname, chip->addr, chip->irq);
2650
2651         *rchip = chip;
2652         return 0;
2653
2654  errout:
2655         azx_free(chip);
2656         return err;
2657 }
2658
2659 static void power_down_all_codecs(struct azx *chip)
2660 {
2661 #ifdef CONFIG_SND_HDA_POWER_SAVE
2662         /* The codecs were powered up in snd_hda_codec_new().
2663          * Now all initialization done, so turn them down if possible
2664          */
2665         struct hda_codec *codec;
2666         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2667                 snd_hda_power_down(codec);
2668         }
2669 #endif
2670 }
2671
2672 static int __devinit azx_probe(struct pci_dev *pci,
2673                                const struct pci_device_id *pci_id)
2674 {
2675         static int dev;
2676         struct snd_card *card;
2677         struct azx *chip;
2678         int err;
2679
2680         if (dev >= SNDRV_CARDS)
2681                 return -ENODEV;
2682         if (!enable[dev]) {
2683                 dev++;
2684                 return -ENOENT;
2685         }
2686
2687         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2688         if (err < 0) {
2689                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2690                 return err;
2691         }
2692
2693         /* set this here since it's referred in snd_hda_load_patch() */
2694         snd_card_set_dev(card, &pci->dev);
2695
2696         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2697         if (err < 0)
2698                 goto out_free;
2699         card->private_data = chip;
2700
2701 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2702         chip->beep_mode = beep_mode[dev];
2703 #endif
2704
2705         /* create codec instances */
2706         err = azx_codec_create(chip, model[dev]);
2707         if (err < 0)
2708                 goto out_free;
2709 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2710         if (patch[dev] && *patch[dev]) {
2711                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2712                            patch[dev]);
2713                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2714                 if (err < 0)
2715                         goto out_free;
2716         }
2717 #endif
2718         if ((probe_only[dev] & 1) == 0) {
2719                 err = azx_codec_configure(chip);
2720                 if (err < 0)
2721                         goto out_free;
2722         }
2723
2724         /* create PCM streams */
2725         err = snd_hda_build_pcms(chip->bus);
2726         if (err < 0)
2727                 goto out_free;
2728
2729         /* create mixer controls */
2730         err = azx_mixer_create(chip);
2731         if (err < 0)
2732                 goto out_free;
2733
2734         err = snd_card_register(card);
2735         if (err < 0)
2736                 goto out_free;
2737
2738         pci_set_drvdata(pci, card);
2739         chip->running = 1;
2740         power_down_all_codecs(chip);
2741         azx_notifier_register(chip);
2742
2743         dev++;
2744         return err;
2745 out_free:
2746         snd_card_free(card);
2747         return err;
2748 }
2749
2750 static void __devexit azx_remove(struct pci_dev *pci)
2751 {
2752         snd_card_free(pci_get_drvdata(pci));
2753         pci_set_drvdata(pci, NULL);
2754 }
2755
2756 /* PCI IDs */
2757 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2758         /* CPT */
2759         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2760         /* PBG */
2761         { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
2762         /* SCH */
2763         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2764         /* Generic Intel */
2765         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2766           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2767           .class_mask = 0xffffff,
2768           .driver_data = AZX_DRIVER_ICH },
2769         /* ATI SB 450/600 */
2770         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2771         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2772         /* ATI HDMI */
2773         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2774         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2775         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2776         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2777         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2778         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2779         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2780         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2781         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2782         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2783         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2784         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2785         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2786         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2787         /* VIA VT8251/VT8237A */
2788         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2789         /* SIS966 */
2790         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2791         /* ULI M5461 */
2792         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2793         /* NVIDIA MCP */
2794         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2795           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2796           .class_mask = 0xffffff,
2797           .driver_data = AZX_DRIVER_NVIDIA },
2798         /* Teradici */
2799         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2800         /* Creative X-Fi (CA0110-IBG) */
2801 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2802         /* the following entry conflicts with snd-ctxfi driver,
2803          * as ctxfi driver mutates from HD-audio to native mode with
2804          * a special command sequence.
2805          */
2806         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2807           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2808           .class_mask = 0xffffff,
2809           .driver_data = AZX_DRIVER_CTX },
2810 #else
2811         /* this entry seems still valid -- i.e. without emu20kx chip */
2812         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
2813 #endif
2814         /* Vortex86MX */
2815         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2816         /* VMware HDAudio */
2817         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2818         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2819         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2820           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2821           .class_mask = 0xffffff,
2822           .driver_data = AZX_DRIVER_GENERIC },
2823         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2824           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2825           .class_mask = 0xffffff,
2826           .driver_data = AZX_DRIVER_GENERIC },
2827         { 0, }
2828 };
2829 MODULE_DEVICE_TABLE(pci, azx_ids);
2830
2831 /* pci_driver definition */
2832 static struct pci_driver driver = {
2833         .name = "HDA Intel",
2834         .id_table = azx_ids,
2835         .probe = azx_probe,
2836         .remove = __devexit_p(azx_remove),
2837 #ifdef CONFIG_PM
2838         .suspend = azx_suspend,
2839         .resume = azx_resume,
2840 #endif
2841 };
2842
2843 static int __init alsa_card_azx_init(void)
2844 {
2845         return pci_register_driver(&driver);
2846 }
2847
2848 static void __exit alsa_card_azx_exit(void)
2849 {
2850         pci_unregister_driver(&driver);
2851 }
2852
2853 module_init(alsa_card_azx_init)
2854 module_exit(alsa_card_azx_exit)