sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static int single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, int, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static int power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = 1;
 125 module_param(align_buffer_size, bool, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, PBG},"
 152                          "{Intel, SCH},"
 153                          "{ATI, SB450},"
 154                          "{ATI, SB600},"
 155                          "{ATI, RS600},"
 156                          "{ATI, RS690},"
 157                          "{ATI, RS780},"
 158                          "{ATI, R600},"
 159                          "{ATI, RV630},"
 160                          "{ATI, RV610},"
 161                          "{ATI, RV670},"
 162                          "{ATI, RV635},"
 163                          "{ATI, RV620},"
 164                          "{ATI, RV770},"
 165                          "{VIA, VT8251},"
 166                          "{VIA, VT8237A},"
 167                          "{SiS, SIS966},"
 168                          "{ULI, M5461}}");
 169 MODULE_DESCRIPTION("Intel HDA driver");
 170
 171 #ifdef CONFIG_SND_VERBOSE_PRINTK
 172 #define SFX     /* nop */
 173 #else
 174 #define SFX     "hda-intel: "
 175 #endif
 176
 177 /*
 178  * registers
 179  */
 180 #define ICH6_REG_GCAP                   0x00
 181 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 182 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 183 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 184 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 185 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 186 #define ICH6_REG_VMIN                   0x02
 187 #define ICH6_REG_VMAJ                   0x03
 188 #define ICH6_REG_OUTPAY                 0x04
 189 #define ICH6_REG_INPAY                  0x06
 190 #define ICH6_REG_GCTL                   0x08
 191 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 192 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 193 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 194 #define ICH6_REG_WAKEEN                 0x0c
 195 #define ICH6_REG_STATESTS               0x0e
 196 #define ICH6_REG_GSTS                   0x10
 197 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 198 #define ICH6_REG_INTCTL                 0x20
 199 #define ICH6_REG_INTSTS                 0x24
 200 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 201 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 202 #define ICH6_REG_SSYNC                  0x38
 203 #define ICH6_REG_CORBLBASE              0x40
 204 #define ICH6_REG_CORBUBASE              0x44
 205 #define ICH6_REG_CORBWP                 0x48
 206 #define ICH6_REG_CORBRP                 0x4a
 207 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 208 #define ICH6_REG_CORBCTL                0x4c
 209 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 210 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 211 #define ICH6_REG_CORBSTS                0x4d
 212 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 213 #define ICH6_REG_CORBSIZE               0x4e
 214
 215 #define ICH6_REG_RIRBLBASE              0x50
 216 #define ICH6_REG_RIRBUBASE              0x54
 217 #define ICH6_REG_RIRBWP                 0x58
 218 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 219 #define ICH6_REG_RINTCNT                0x5a
 220 #define ICH6_REG_RIRBCTL                0x5c
 221 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 222 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 223 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 224 #define ICH6_REG_RIRBSTS                0x5d
 225 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 226 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 227 #define ICH6_REG_RIRBSIZE               0x5e
 228
 229 #define ICH6_REG_IC                     0x60
 230 #define ICH6_REG_IR                     0x64
 231 #define ICH6_REG_IRS                    0x68
 232 #define   ICH6_IRS_VALID        (1<<1)
 233 #define   ICH6_IRS_BUSY         (1<<0)
 234
 235 #define ICH6_REG_DPLBASE                0x70
 236 #define ICH6_REG_DPUBASE                0x74
 237 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 238
 239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 241
 242 /* stream register offsets from stream base */
 243 #define ICH6_REG_SD_CTL                 0x00
 244 #define ICH6_REG_SD_STS                 0x03
 245 #define ICH6_REG_SD_LPIB                0x04
 246 #define ICH6_REG_SD_CBL                 0x08
 247 #define ICH6_REG_SD_LVI                 0x0c
 248 #define ICH6_REG_SD_FIFOW               0x0e
 249 #define ICH6_REG_SD_FIFOSIZE            0x10
 250 #define ICH6_REG_SD_FORMAT              0x12
 251 #define ICH6_REG_SD_BDLPL               0x18
 252 #define ICH6_REG_SD_BDLPU               0x1c
 253
 254 /* PCI space */
 255 #define ICH6_PCIREG_TCSEL       0x44
 256
 257 /*
 258  * other constants
 259  */
 260
 261 /* max number of SDs */
 262 /* ICH, ATI and VIA have 4 playback and 4 capture */
 263 #define ICH6_NUM_CAPTURE        4
 264 #define ICH6_NUM_PLAYBACK       4
 265
 266 /* ULI has 6 playback and 5 capture */
 267 #define ULI_NUM_CAPTURE         5
 268 #define ULI_NUM_PLAYBACK        6
 269
 270 /* ATI HDMI has 1 playback and 0 capture */
 271 #define ATIHDMI_NUM_CAPTURE     0
 272 #define ATIHDMI_NUM_PLAYBACK    1
 273
 274 /* TERA has 4 playback and 3 capture */
 275 #define TERA_NUM_CAPTURE        3
 276 #define TERA_NUM_PLAYBACK       4
 277
 278 /* this number is statically defined for simplicity */
 279 #define MAX_AZX_DEV             16
 280
 281 /* max number of fragments - we may use more if allocating more pages for BDL */
 282 #define BDL_SIZE                4096
 283 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 284 #define AZX_MAX_FRAG            32
 285 /* max buffer size - no h/w limit, you can increase as you like */
 286 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 287
 288 /* RIRB int mask: overrun[2], response[0] */
 289 #define RIRB_INT_RESPONSE       0x01
 290 #define RIRB_INT_OVERRUN        0x04
 291 #define RIRB_INT_MASK           0x05
 292
 293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 294 #define AZX_MAX_CODECS          8
 295 #define AZX_DEFAULT_CODECS      4
 296 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 297
 298 /* SD_CTL bits */
 299 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 300 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 301 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 302 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 303 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 304 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 305 #define SD_CTL_STREAM_TAG_SHIFT 20
 306
 307 /* SD_CTL and SD_STS */
 308 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 309 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 310 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 311 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 312                                  SD_INT_COMPLETE)
 313
 314 /* SD_STS */
 315 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 316
 317 /* INTCTL and INTSTS */
 318 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 319 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 320 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 321
 322 /* below are so far hardcoded - should read registers in future */
 323 #define ICH6_MAX_CORB_ENTRIES   256
 324 #define ICH6_MAX_RIRB_ENTRIES   256
 325
 326 /* position fix mode */
 327 enum {
 328         POS_FIX_AUTO,
 329         POS_FIX_LPIB,
 330         POS_FIX_POSBUF,
 331         POS_FIX_VIACOMBO,
 332 };
 333
 334 /* Defines for ATI HD Audio support in SB450 south bridge */
 335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 337
 338 /* Defines for Nvidia HDA support */
 339 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 340 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 341 #define NVIDIA_HDA_ISTRM_COH          0x4d
 342 #define NVIDIA_HDA_OSTRM_COH          0x4c
 343 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 344
 345 /* Defines for Intel SCH HDA snoop control */
 346 #define INTEL_SCH_HDA_DEVC      0x78
 347 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 348
 349 /* Define IN stream 0 FIFO size offset in VIA controller */
 350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 351 /* Define VIA HD Audio Device ID*/
 352 #define VIA_HDAC_DEVICE_ID              0x3288
 353
 354 /* HD Audio class code */
 355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 356
 357 /*
 358  */
 359
 360 struct azx_dev {
 361         struct snd_dma_buffer bdl; /* BDL buffer */
 362         u32 *posbuf;            /* position buffer pointer */
 363
 364         unsigned int bufsize;   /* size of the play buffer in bytes */
 365         unsigned int period_bytes; /* size of the period in bytes */
 366         unsigned int frags;     /* number for period in the play buffer */
 367         unsigned int fifo_size; /* FIFO size */
 368         unsigned long start_wallclk;    /* start + minimum wallclk */
 369         unsigned long period_wallclk;   /* wallclk for period */
 370
 371         void __iomem *sd_addr;  /* stream descriptor pointer */
 372
 373         u32 sd_int_sta_mask;    /* stream int status mask */
 374
 375         /* pcm support */
 376         struct snd_pcm_substream *substream;    /* assigned substream,
 377                                                  * set in PCM open
 378                                                  */
 379         unsigned int format_val;        /* format value to be set in the
 380                                          * controller and the codec
 381                                          */
 382         unsigned char stream_tag;       /* assigned stream */
 383         unsigned char index;            /* stream index */
 384         int assigned_key;               /* last device# key assigned to */
 385
 386         unsigned int opened :1;
 387         unsigned int running :1;
 388         unsigned int irq_pending :1;
 389         /*
 390          * For VIA:
 391          *  A flag to ensure DMA position is 0
 392          *  when link position is not greater than FIFO size
 393          */
 394         unsigned int insufficient :1;
 395         unsigned int wc_marked:1;
 396 };
 397
 398 /* CORB/RIRB */
 399 struct azx_rb {
 400         u32 *buf;               /* CORB/RIRB buffer
 401                                  * Each CORB entry is 4byte, RIRB is 8byte
 402                                  */
 403         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 404         /* for RIRB */
 405         unsigned short rp, wp;  /* read/write pointers */
 406         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 407         u32 res[AZX_MAX_CODECS];        /* last read value */
 408 };
 409
 410 struct azx {
 411         struct snd_card *card;
 412         struct pci_dev *pci;
 413         int dev_index;
 414
 415         /* chip type specific */
 416         int driver_type;
 417         unsigned int driver_caps;
 418         int playback_streams;
 419         int playback_index_offset;
 420         int capture_streams;
 421         int capture_index_offset;
 422         int num_streams;
 423
 424         /* pci resources */
 425         unsigned long addr;
 426         void __iomem *remap_addr;
 427         int irq;
 428
 429         /* locks */
 430         spinlock_t reg_lock;
 431         struct mutex open_mutex;
 432
 433         /* streams (x num_streams) */
 434         struct azx_dev *azx_dev;
 435
 436         /* PCM */
 437         struct snd_pcm *pcm[HDA_MAX_PCMS];
 438
 439         /* HD codec */
 440         unsigned short codec_mask;
 441         int  codec_probe_mask; /* copied from probe_mask option */
 442         struct hda_bus *bus;
 443         unsigned int beep_mode;
 444
 445         /* CORB/RIRB */
 446         struct azx_rb corb;
 447         struct azx_rb rirb;
 448
 449         /* CORB/RIRB and position buffers */
 450         struct snd_dma_buffer rb;
 451         struct snd_dma_buffer posbuf;
 452
 453         /* flags */
 454         int position_fix[2]; /* for both playback/capture streams */
 455         int poll_count;
 456         unsigned int running :1;
 457         unsigned int initialized :1;
 458         unsigned int single_cmd :1;
 459         unsigned int polling_mode :1;
 460         unsigned int msi :1;
 461         unsigned int irq_pending_warned :1;
 462         unsigned int probing :1; /* codec probing phase */
 463         unsigned int snoop:1;
 464         unsigned int align_buffer_size:1;
 465
 466         /* for debugging */
 467         unsigned int last_cmd[AZX_MAX_CODECS];
 468
 469         /* for pending irqs */
 470         struct work_struct irq_pending_work;
 471
 472         /* reboot notifier (for mysterious hangup problem at power-down) */
 473         struct notifier_block reboot_notifier;
 474 };
 475
 476 /* driver types */
 477 enum {
 478         AZX_DRIVER_ICH,
 479         AZX_DRIVER_PCH,
 480         AZX_DRIVER_SCH,
 481         AZX_DRIVER_ATI,
 482         AZX_DRIVER_ATIHDMI,
 483         AZX_DRIVER_VIA,
 484         AZX_DRIVER_SIS,
 485         AZX_DRIVER_ULI,
 486         AZX_DRIVER_NVIDIA,
 487         AZX_DRIVER_TERA,
 488         AZX_DRIVER_CTX,
 489         AZX_DRIVER_GENERIC,
 490         AZX_NUM_DRIVERS, /* keep this as last entry */
 491 };
 492
 493 /* driver quirks (capabilities) */
 494 /* bits 0-7 are used for indicating driver type */
 495 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 496 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 497 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 498 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 499 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 500 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 501 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 502 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 503 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 504 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 505 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 506 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 507 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 508 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 509
 510 /* quirks for ATI SB / AMD Hudson */
 511 #define AZX_DCAPS_PRESET_ATI_SB \
 512         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 513          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 514
 515 /* quirks for ATI/AMD HDMI */
 516 #define AZX_DCAPS_PRESET_ATI_HDMI \
 517         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 518
 519 /* quirks for Nvidia */
 520 #define AZX_DCAPS_PRESET_NVIDIA \
 521         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 522
 523 static char *driver_short_names[] __devinitdata = {
 524         [AZX_DRIVER_ICH] = "HDA Intel",
 525         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 526         [AZX_DRIVER_SCH] = "HDA Intel MID",
 527         [AZX_DRIVER_ATI] = "HDA ATI SB",
 528         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 529         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 530         [AZX_DRIVER_SIS] = "HDA SIS966",
 531         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 532         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 533         [AZX_DRIVER_TERA] = "HDA Teradici",
 534         [AZX_DRIVER_CTX] = "HDA Creative",
 535         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 536 };
 537
 538 /*
 539  * macros for easy use
 540  */
 541 #define azx_writel(chip,reg,value) \
 542         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 543 #define azx_readl(chip,reg) \
 544         readl((chip)->remap_addr + ICH6_REG_##reg)
 545 #define azx_writew(chip,reg,value) \
 546         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 547 #define azx_readw(chip,reg) \
 548         readw((chip)->remap_addr + ICH6_REG_##reg)
 549 #define azx_writeb(chip,reg,value) \
 550         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 551 #define azx_readb(chip,reg) \
 552         readb((chip)->remap_addr + ICH6_REG_##reg)
 553
 554 #define azx_sd_writel(dev,reg,value) \
 555         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 556 #define azx_sd_readl(dev,reg) \
 557         readl((dev)->sd_addr + ICH6_REG_##reg)
 558 #define azx_sd_writew(dev,reg,value) \
 559         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 560 #define azx_sd_readw(dev,reg) \
 561         readw((dev)->sd_addr + ICH6_REG_##reg)
 562 #define azx_sd_writeb(dev,reg,value) \
 563         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 564 #define azx_sd_readb(dev,reg) \
 565         readb((dev)->sd_addr + ICH6_REG_##reg)
 566
 567 /* for pcm support */
 568 #define get_azx_dev(substream) (substream->runtime->private_data)
 569
 570 #ifdef CONFIG_X86
 571 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 572 {
 573         if (azx_snoop(chip))
 574                 return;
 575         if (addr && size) {
 576                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 577                 if (on)
 578                         set_memory_wc((unsigned long)addr, pages);
 579                 else
 580                         set_memory_wb((unsigned long)addr, pages);
 581         }
 582 }
 583
 584 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 585                                  bool on)
 586 {
 587         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 588 }
 589 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 590                                    struct snd_pcm_runtime *runtime, bool on)
 591 {
 592         if (azx_dev->wc_marked != on) {
 593                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 594                 azx_dev->wc_marked = on;
 595         }
 596 }
 597 #else
 598 /* NOP for other archs */
 599 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 600                                  bool on)
 601 {
 602 }
 603 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 604                                    struct snd_pcm_runtime *runtime, bool on)
 605 {
 606 }
 607 #endif
 608
 609 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 610 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 611 /*
 612  * Interface for HD codec
 613  */
 614
 615 /*
 616  * CORB / RIRB interface
 617  */
 618 static int azx_alloc_cmd_io(struct azx *chip)
 619 {
 620         int err;
 621
 622         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 623         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 624                                   snd_dma_pci_data(chip->pci),
 625                                   PAGE_SIZE, &chip->rb);
 626         if (err < 0) {
 627                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 628                 return err;
 629         }
 630         mark_pages_wc(chip, &chip->rb, true);
 631         return 0;
 632 }
 633
 634 static void azx_init_cmd_io(struct azx *chip)
 635 {
 636         spin_lock_irq(&chip->reg_lock);
 637         /* CORB set up */
 638         chip->corb.addr = chip->rb.addr;
 639         chip->corb.buf = (u32 *)chip->rb.area;
 640         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 641         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 642
 643         /* set the corb size to 256 entries (ULI requires explicitly) */
 644         azx_writeb(chip, CORBSIZE, 0x02);
 645         /* set the corb write pointer to 0 */
 646         azx_writew(chip, CORBWP, 0);
 647         /* reset the corb hw read pointer */
 648         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 649         /* enable corb dma */
 650         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 651
 652         /* RIRB set up */
 653         chip->rirb.addr = chip->rb.addr + 2048;
 654         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 655         chip->rirb.wp = chip->rirb.rp = 0;
 656         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 657         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 658         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 659
 660         /* set the rirb size to 256 entries (ULI requires explicitly) */
 661         azx_writeb(chip, RIRBSIZE, 0x02);
 662         /* reset the rirb hw write pointer */
 663         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 664         /* set N=1, get RIRB response interrupt for new entry */
 665         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 666                 azx_writew(chip, RINTCNT, 0xc0);
 667         else
 668                 azx_writew(chip, RINTCNT, 1);
 669         /* enable rirb dma and response irq */
 670         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 671         spin_unlock_irq(&chip->reg_lock);
 672 }
 673
 674 static void azx_free_cmd_io(struct azx *chip)
 675 {
 676         spin_lock_irq(&chip->reg_lock);
 677         /* disable ringbuffer DMAs */
 678         azx_writeb(chip, RIRBCTL, 0);
 679         azx_writeb(chip, CORBCTL, 0);
 680         spin_unlock_irq(&chip->reg_lock);
 681 }
 682
 683 static unsigned int azx_command_addr(u32 cmd)
 684 {
 685         unsigned int addr = cmd >> 28;
 686
 687         if (addr >= AZX_MAX_CODECS) {
 688                 snd_BUG();
 689                 addr = 0;
 690         }
 691
 692         return addr;
 693 }
 694
 695 static unsigned int azx_response_addr(u32 res)
 696 {
 697         unsigned int addr = res & 0xf;
 698
 699         if (addr >= AZX_MAX_CODECS) {
 700                 snd_BUG();
 701                 addr = 0;
 702         }
 703
 704         return addr;
 705 }
 706
 707 /* send a command */
 708 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 709 {
 710         struct azx *chip = bus->private_data;
 711         unsigned int addr = azx_command_addr(val);
 712         unsigned int wp;
 713
 714         spin_lock_irq(&chip->reg_lock);
 715
 716         /* add command to corb */
 717         wp = azx_readb(chip, CORBWP);
 718         wp++;
 719         wp %= ICH6_MAX_CORB_ENTRIES;
 720
 721         chip->rirb.cmds[addr]++;
 722         chip->corb.buf[wp] = cpu_to_le32(val);
 723         azx_writel(chip, CORBWP, wp);
 724
 725         spin_unlock_irq(&chip->reg_lock);
 726
 727         return 0;
 728 }
 729
 730 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 731
 732 /* retrieve RIRB entry - called from interrupt handler */
 733 static void azx_update_rirb(struct azx *chip)
 734 {
 735         unsigned int rp, wp;
 736         unsigned int addr;
 737         u32 res, res_ex;
 738
 739         wp = azx_readb(chip, RIRBWP);
 740         if (wp == chip->rirb.wp)
 741                 return;
 742         chip->rirb.wp = wp;
 743
 744         while (chip->rirb.rp != wp) {
 745                 chip->rirb.rp++;
 746                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 747
 748                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 749                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 750                 res = le32_to_cpu(chip->rirb.buf[rp]);
 751                 addr = azx_response_addr(res_ex);
 752                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 753                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 754                 else if (chip->rirb.cmds[addr]) {
 755                         chip->rirb.res[addr] = res;
 756                         smp_wmb();
 757                         chip->rirb.cmds[addr]--;
 758                 } else
 759                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 760                                    "last cmd=%#08x\n",
 761                                    res, res_ex,
 762                                    chip->last_cmd[addr]);
 763         }
 764 }
 765
 766 /* receive a response */
 767 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 768                                           unsigned int addr)
 769 {
 770         struct azx *chip = bus->private_data;
 771         unsigned long timeout;
 772         unsigned long loopcounter;
 773         int do_poll = 0;
 774
 775  again:
 776         timeout = jiffies + msecs_to_jiffies(1000);
 777
 778         for (loopcounter = 0;; loopcounter++) {
 779                 if (chip->polling_mode || do_poll) {
 780                         spin_lock_irq(&chip->reg_lock);
 781                         azx_update_rirb(chip);
 782                         spin_unlock_irq(&chip->reg_lock);
 783                 }
 784                 if (!chip->rirb.cmds[addr]) {
 785                         smp_rmb();
 786                         bus->rirb_error = 0;
 787
 788                         if (!do_poll)
 789                                 chip->poll_count = 0;
 790                         return chip->rirb.res[addr]; /* the last value */
 791                 }
 792                 if (time_after(jiffies, timeout))
 793                         break;
 794                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 795                         msleep(2); /* temporary workaround */
 796                 else {
 797                         udelay(10);
 798                         cond_resched();
 799                 }
 800         }
 801
 802         if (!chip->polling_mode && chip->poll_count < 2) {
 803                 snd_printdd(SFX "azx_get_response timeout, "
 804                            "polling the codec once: last cmd=0x%08x\n",
 805                            chip->last_cmd[addr]);
 806                 do_poll = 1;
 807                 chip->poll_count++;
 808                 goto again;
 809         }
 810
 811
 812         if (!chip->polling_mode) {
 813                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 814                            "switching to polling mode: last cmd=0x%08x\n",
 815                            chip->last_cmd[addr]);
 816                 chip->polling_mode = 1;
 817                 goto again;
 818         }
 819
 820         if (chip->msi) {
 821                 snd_printk(KERN_WARNING SFX "No response from codec, "
 822                            "disabling MSI: last cmd=0x%08x\n",
 823                            chip->last_cmd[addr]);
 824                 free_irq(chip->irq, chip);
 825                 chip->irq = -1;
 826                 pci_disable_msi(chip->pci);
 827                 chip->msi = 0;
 828                 if (azx_acquire_irq(chip, 1) < 0) {
 829                         bus->rirb_error = 1;
 830                         return -1;
 831                 }
 832                 goto again;
 833         }
 834
 835         if (chip->probing) {
 836                 /* If this critical timeout happens during the codec probing
 837                  * phase, this is likely an access to a non-existing codec
 838                  * slot.  Better to return an error and reset the system.
 839                  */
 840                 return -1;
 841         }
 842
 843         /* a fatal communication error; need either to reset or to fallback
 844          * to the single_cmd mode
 845          */
 846         bus->rirb_error = 1;
 847         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 848                 bus->response_reset = 1;
 849                 return -1; /* give a chance to retry */
 850         }
 851
 852         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 853                    "switching to single_cmd mode: last cmd=0x%08x\n",
 854                    chip->last_cmd[addr]);
 855         chip->single_cmd = 1;
 856         bus->response_reset = 0;
 857         /* release CORB/RIRB */
 858         azx_free_cmd_io(chip);
 859         /* disable unsolicited responses */
 860         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 861         return -1;
 862 }
 863
 864 /*
 865  * Use the single immediate command instead of CORB/RIRB for simplicity
 866  *
 867  * Note: according to Intel, this is not preferred use.  The command was
 868  *       intended for the BIOS only, and may get confused with unsolicited
 869  *       responses.  So, we shouldn't use it for normal operation from the
 870  *       driver.
 871  *       I left the codes, however, for debugging/testing purposes.
 872  */
 873
 874 /* receive a response */
 875 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 876 {
 877         int timeout = 50;
 878
 879         while (timeout--) {
 880                 /* check IRV busy bit */
 881                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 882                         /* reuse rirb.res as the response return value */
 883                         chip->rirb.res[addr] = azx_readl(chip, IR);
 884                         return 0;
 885                 }
 886                 udelay(1);
 887         }
 888         if (printk_ratelimit())
 889                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 890                            azx_readw(chip, IRS));
 891         chip->rirb.res[addr] = -1;
 892         return -EIO;
 893 }
 894
 895 /* send a command */
 896 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 897 {
 898         struct azx *chip = bus->private_data;
 899         unsigned int addr = azx_command_addr(val);
 900         int timeout = 50;
 901
 902         bus->rirb_error = 0;
 903         while (timeout--) {
 904                 /* check ICB busy bit */
 905                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 906                         /* Clear IRV valid bit */
 907                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 908                                    ICH6_IRS_VALID);
 909                         azx_writel(chip, IC, val);
 910                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 911                                    ICH6_IRS_BUSY);
 912                         return azx_single_wait_for_response(chip, addr);
 913                 }
 914                 udelay(1);
 915         }
 916         if (printk_ratelimit())
 917                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 918                            azx_readw(chip, IRS), val);
 919         return -EIO;
 920 }
 921
 922 /* receive a response */
 923 static unsigned int azx_single_get_response(struct hda_bus *bus,
 924                                             unsigned int addr)
 925 {
 926         struct azx *chip = bus->private_data;
 927         return chip->rirb.res[addr];
 928 }
 929
 930 /*
 931  * The below are the main callbacks from hda_codec.
 932  *
 933  * They are just the skeleton to call sub-callbacks according to the
 934  * current setting of chip->single_cmd.
 935  */
 936
 937 /* send a command */
 938 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 939 {
 940         struct azx *chip = bus->private_data;
 941
 942         chip->last_cmd[azx_command_addr(val)] = val;
 943         if (chip->single_cmd)
 944                 return azx_single_send_cmd(bus, val);
 945         else
 946                 return azx_corb_send_cmd(bus, val);
 947 }
 948
 949 /* get a response */
 950 static unsigned int azx_get_response(struct hda_bus *bus,
 951                                      unsigned int addr)
 952 {
 953         struct azx *chip = bus->private_data;
 954         if (chip->single_cmd)
 955                 return azx_single_get_response(bus, addr);
 956         else
 957                 return azx_rirb_get_response(bus, addr);
 958 }
 959
 960 #ifdef CONFIG_SND_HDA_POWER_SAVE
 961 static void azx_power_notify(struct hda_bus *bus);
 962 #endif
 963
 964 /* reset codec link */
 965 static int azx_reset(struct azx *chip, int full_reset)
 966 {
 967         int count;
 968
 969         if (!full_reset)
 970                 goto __skip;
 971
 972         /* clear STATESTS */
 973         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 974
 975         /* reset controller */
 976         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 977
 978         count = 50;
 979         while (azx_readb(chip, GCTL) && --count)
 980                 msleep(1);
 981
 982         /* delay for >= 100us for codec PLL to settle per spec
 983          * Rev 0.9 section 5.5.1
 984          */
 985         msleep(1);
 986
 987         /* Bring controller out of reset */
 988         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 989
 990         count = 50;
 991         while (!azx_readb(chip, GCTL) && --count)
 992                 msleep(1);
 993
 994         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 995         msleep(1);
 996
 997       __skip:
 998         /* check to see if controller is ready */
 999         if (!azx_readb(chip, GCTL)) {
1000                 snd_printd(SFX "azx_reset: controller not ready!\n");
1001                 return -EBUSY;
1002         }
1003
1004         /* Accept unsolicited responses */
1005         if (!chip->single_cmd)
1006                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1007                            ICH6_GCTL_UNSOL);
1008
1009         /* detect codecs */
1010         if (!chip->codec_mask) {
1011                 chip->codec_mask = azx_readw(chip, STATESTS);
1012                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1013         }
1014
1015         return 0;
1016 }
1017
1018
1019 /*
1020  * Lowlevel interface
1021  */
1022
1023 /* enable interrupts */
1024 static void azx_int_enable(struct azx *chip)
1025 {
1026         /* enable controller CIE and GIE */
1027         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1028                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1029 }
1030
1031 /* disable interrupts */
1032 static void azx_int_disable(struct azx *chip)
1033 {
1034         int i;
1035
1036         /* disable interrupts in stream descriptor */
1037         for (i = 0; i < chip->num_streams; i++) {
1038                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1039                 azx_sd_writeb(azx_dev, SD_CTL,
1040                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1041         }
1042
1043         /* disable SIE for all streams */
1044         azx_writeb(chip, INTCTL, 0);
1045
1046         /* disable controller CIE and GIE */
1047         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1048                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1049 }
1050
1051 /* clear interrupts */
1052 static void azx_int_clear(struct azx *chip)
1053 {
1054         int i;
1055
1056         /* clear stream status */
1057         for (i = 0; i < chip->num_streams; i++) {
1058                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1059                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1060         }
1061
1062         /* clear STATESTS */
1063         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1064
1065         /* clear rirb status */
1066         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1067
1068         /* clear int status */
1069         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1070 }
1071
1072 /* start a stream */
1073 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1074 {
1075         /*
1076          * Before stream start, initialize parameter
1077          */
1078         azx_dev->insufficient = 1;
1079
1080         /* enable SIE */
1081         azx_writel(chip, INTCTL,
1082                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1083         /* set DMA start and interrupt mask */
1084         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1085                       SD_CTL_DMA_START | SD_INT_MASK);
1086 }
1087
1088 /* stop DMA */
1089 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1090 {
1091         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1092                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1093         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1094 }
1095
1096 /* stop a stream */
1097 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1098 {
1099         azx_stream_clear(chip, azx_dev);
1100         /* disable SIE */
1101         azx_writel(chip, INTCTL,
1102                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1103 }
1104
1105
1106 /*
1107  * reset and start the controller registers
1108  */
1109 static void azx_init_chip(struct azx *chip, int full_reset)
1110 {
1111         if (chip->initialized)
1112                 return;
1113
1114         /* reset controller */
1115         azx_reset(chip, full_reset);
1116
1117         /* initialize interrupts */
1118         azx_int_clear(chip);
1119         azx_int_enable(chip);
1120
1121         /* initialize the codec command I/O */
1122         if (!chip->single_cmd)
1123                 azx_init_cmd_io(chip);
1124
1125         /* program the position buffer */
1126         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1127         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1128
1129         chip->initialized = 1;
1130 }
1131
1132 /*
1133  * initialize the PCI registers
1134  */
1135 /* update bits in a PCI register byte */
1136 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1137                             unsigned char mask, unsigned char val)
1138 {
1139         unsigned char data;
1140
1141         pci_read_config_byte(pci, reg, &data);
1142         data &= ~mask;
1143         data |= (val & mask);
1144         pci_write_config_byte(pci, reg, data);
1145 }
1146
1147 static void azx_init_pci(struct azx *chip)
1148 {
1149         /* force to non-snoop mode for a new VIA controller when BIOS is set */
1150         if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1151                 u8 snoop;
1152                 pci_read_config_byte(chip->pci, 0x42, &snoop);
1153                 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1154                         chip->snoop = 0;
1155                         snd_printdd(SFX "Force to non-snoop mode\n");
1156                 }
1157         }
1158
1159         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1160          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1161          * Ensuring these bits are 0 clears playback static on some HD Audio
1162          * codecs.
1163          * The PCI register TCSEL is defined in the Intel manuals.
1164          */
1165         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1166                 snd_printdd(SFX "Clearing TCSEL\n");
1167                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1168         }
1169
1170         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1171          * we need to enable snoop.
1172          */
1173         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1174                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1175                 update_pci_byte(chip->pci,
1176                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1177                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1178         }
1179
1180         /* For NVIDIA HDA, enable snoop */
1181         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1182                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1183                 update_pci_byte(chip->pci,
1184                                 NVIDIA_HDA_TRANSREG_ADDR,
1185                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1186                 update_pci_byte(chip->pci,
1187                                 NVIDIA_HDA_ISTRM_COH,
1188                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1189                 update_pci_byte(chip->pci,
1190                                 NVIDIA_HDA_OSTRM_COH,
1191                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1192         }
1193
1194         /* Enable SCH/PCH snoop if needed */
1195         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1196                 unsigned short snoop;
1197                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1198                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1199                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1200                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1201                         if (!azx_snoop(chip))
1202                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1203                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1204                         pci_read_config_word(chip->pci,
1205                                 INTEL_SCH_HDA_DEVC, &snoop);
1206                 }
1207                 snd_printdd(SFX "SCH snoop: %s\n",
1208                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1209                                 ? "Disabled" : "Enabled");
1210         }
1211 }
1212
1213
1214 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1215
1216 /*
1217  * interrupt handler
1218  */
1219 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1220 {
1221         struct azx *chip = dev_id;
1222         struct azx_dev *azx_dev;
1223         u32 status;
1224         u8 sd_status;
1225         int i, ok;
1226
1227         spin_lock(&chip->reg_lock);
1228
1229         status = azx_readl(chip, INTSTS);
1230         if (status == 0) {
1231                 spin_unlock(&chip->reg_lock);
1232                 return IRQ_NONE;
1233         }
1234
1235         for (i = 0; i < chip->num_streams; i++) {
1236                 azx_dev = &chip->azx_dev[i];
1237                 if (status & azx_dev->sd_int_sta_mask) {
1238                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1239                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1240                         if (!azx_dev->substream || !azx_dev->running ||
1241                             !(sd_status & SD_INT_COMPLETE))
1242                                 continue;
1243                         /* check whether this IRQ is really acceptable */
1244                         ok = azx_position_ok(chip, azx_dev);
1245                         if (ok == 1) {
1246                                 azx_dev->irq_pending = 0;
1247                                 spin_unlock(&chip->reg_lock);
1248                                 snd_pcm_period_elapsed(azx_dev->substream);
1249                                 spin_lock(&chip->reg_lock);
1250                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1251                                 /* bogus IRQ, process it later */
1252                                 azx_dev->irq_pending = 1;
1253                                 queue_work(chip->bus->workq,
1254                                            &chip->irq_pending_work);
1255                         }
1256                 }
1257         }
1258
1259         /* clear rirb int */
1260         status = azx_readb(chip, RIRBSTS);
1261         if (status & RIRB_INT_MASK) {
1262                 if (status & RIRB_INT_RESPONSE) {
1263                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1264                                 udelay(80);
1265                         azx_update_rirb(chip);
1266                 }
1267                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1268         }
1269
1270 #if 0
1271         /* clear state status int */
1272         if (azx_readb(chip, STATESTS) & 0x04)
1273                 azx_writeb(chip, STATESTS, 0x04);
1274 #endif
1275         spin_unlock(&chip->reg_lock);
1276
1277         return IRQ_HANDLED;
1278 }
1279
1280
1281 /*
1282  * set up a BDL entry
1283  */
1284 static int setup_bdle(struct snd_pcm_substream *substream,
1285                       struct azx_dev *azx_dev, u32 **bdlp,
1286                       int ofs, int size, int with_ioc)
1287 {
1288         u32 *bdl = *bdlp;
1289
1290         while (size > 0) {
1291                 dma_addr_t addr;
1292                 int chunk;
1293
1294                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1295                         return -EINVAL;
1296
1297                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1298                 /* program the address field of the BDL entry */
1299                 bdl[0] = cpu_to_le32((u32)addr);
1300                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1301                 /* program the size field of the BDL entry */
1302                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1303                 bdl[2] = cpu_to_le32(chunk);
1304                 /* program the IOC to enable interrupt
1305                  * only when the whole fragment is processed
1306                  */
1307                 size -= chunk;
1308                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1309                 bdl += 4;
1310                 azx_dev->frags++;
1311                 ofs += chunk;
1312         }
1313         *bdlp = bdl;
1314         return ofs;
1315 }
1316
1317 /*
1318  * set up BDL entries
1319  */
1320 static int azx_setup_periods(struct azx *chip,
1321                              struct snd_pcm_substream *substream,
1322                              struct azx_dev *azx_dev)
1323 {
1324         u32 *bdl;
1325         int i, ofs, periods, period_bytes;
1326         int pos_adj;
1327
1328         /* reset BDL address */
1329         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1330         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1331
1332         period_bytes = azx_dev->period_bytes;
1333         periods = azx_dev->bufsize / period_bytes;
1334
1335         /* program the initial BDL entries */
1336         bdl = (u32 *)azx_dev->bdl.area;
1337         ofs = 0;
1338         azx_dev->frags = 0;
1339         pos_adj = bdl_pos_adj[chip->dev_index];
1340         if (pos_adj > 0) {
1341                 struct snd_pcm_runtime *runtime = substream->runtime;
1342                 int pos_align = pos_adj;
1343                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1344                 if (!pos_adj)
1345                         pos_adj = pos_align;
1346                 else
1347                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1348                                 pos_align;
1349                 pos_adj = frames_to_bytes(runtime, pos_adj);
1350                 if (pos_adj >= period_bytes) {
1351                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1352                                    bdl_pos_adj[chip->dev_index]);
1353                         pos_adj = 0;
1354                 } else {
1355                         ofs = setup_bdle(substream, azx_dev,
1356                                          &bdl, ofs, pos_adj,
1357                                          !substream->runtime->no_period_wakeup);
1358                         if (ofs < 0)
1359                                 goto error;
1360                 }
1361         } else
1362                 pos_adj = 0;
1363         for (i = 0; i < periods; i++) {
1364                 if (i == periods - 1 && pos_adj)
1365                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1366                                          period_bytes - pos_adj, 0);
1367                 else
1368                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1369                                          period_bytes,
1370                                          !substream->runtime->no_period_wakeup);
1371                 if (ofs < 0)
1372                         goto error;
1373         }
1374         return 0;
1375
1376  error:
1377         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1378                    azx_dev->bufsize, period_bytes);
1379         return -EINVAL;
1380 }
1381
1382 /* reset stream */
1383 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1384 {
1385         unsigned char val;
1386         int timeout;
1387
1388         azx_stream_clear(chip, azx_dev);
1389
1390         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1391                       SD_CTL_STREAM_RESET);
1392         udelay(3);
1393         timeout = 300;
1394         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1395                --timeout)
1396                 ;
1397         val &= ~SD_CTL_STREAM_RESET;
1398         azx_sd_writeb(azx_dev, SD_CTL, val);
1399         udelay(3);
1400
1401         timeout = 300;
1402         /* waiting for hardware to report that the stream is out of reset */
1403         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1404                --timeout)
1405                 ;
1406
1407         /* reset first position - may not be synced with hw at this time */
1408         *azx_dev->posbuf = 0;
1409 }
1410
1411 /*
1412  * set up the SD for streaming
1413  */
1414 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1415 {
1416         unsigned int val;
1417         /* make sure the run bit is zero for SD */
1418         azx_stream_clear(chip, azx_dev);
1419         /* program the stream_tag */
1420         val = azx_sd_readl(azx_dev, SD_CTL);
1421         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1422                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1423         if (!azx_snoop(chip))
1424                 val |= SD_CTL_TRAFFIC_PRIO;
1425         azx_sd_writel(azx_dev, SD_CTL, val);
1426
1427         /* program the length of samples in cyclic buffer */
1428         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1429
1430         /* program the stream format */
1431         /* this value needs to be the same as the one programmed */
1432         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1433
1434         /* program the stream LVI (last valid index) of the BDL */
1435         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1436
1437         /* program the BDL address */
1438         /* lower BDL address */
1439         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1440         /* upper BDL address */
1441         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1442
1443         /* enable the position buffer */
1444         if (chip->position_fix[0] != POS_FIX_LPIB ||
1445             chip->position_fix[1] != POS_FIX_LPIB) {
1446                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1447                         azx_writel(chip, DPLBASE,
1448                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1449         }
1450
1451         /* set the interrupt enable bits in the descriptor control register */
1452         azx_sd_writel(azx_dev, SD_CTL,
1453                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1454
1455         return 0;
1456 }
1457
1458 /*
1459  * Probe the given codec address
1460  */
1461 static int probe_codec(struct azx *chip, int addr)
1462 {
1463         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1464                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1465         unsigned int res;
1466
1467         mutex_lock(&chip->bus->cmd_mutex);
1468         chip->probing = 1;
1469         azx_send_cmd(chip->bus, cmd);
1470         res = azx_get_response(chip->bus, addr);
1471         chip->probing = 0;
1472         mutex_unlock(&chip->bus->cmd_mutex);
1473         if (res == -1)
1474                 return -EIO;
1475         snd_printdd(SFX "codec #%d probed OK\n", addr);
1476         return 0;
1477 }
1478
1479 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1480                                  struct hda_pcm *cpcm);
1481 static void azx_stop_chip(struct azx *chip);
1482
1483 static void azx_bus_reset(struct hda_bus *bus)
1484 {
1485         struct azx *chip = bus->private_data;
1486
1487         bus->in_reset = 1;
1488         azx_stop_chip(chip);
1489         azx_init_chip(chip, 1);
1490 #ifdef CONFIG_PM
1491         if (chip->initialized) {
1492                 int i;
1493
1494                 for (i = 0; i < HDA_MAX_PCMS; i++)
1495                         snd_pcm_suspend_all(chip->pcm[i]);
1496                 snd_hda_suspend(chip->bus);
1497                 snd_hda_resume(chip->bus);
1498         }
1499 #endif
1500         bus->in_reset = 0;
1501 }
1502
1503 /*
1504  * Codec initialization
1505  */
1506
1507 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1508 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1509         [AZX_DRIVER_NVIDIA] = 8,
1510         [AZX_DRIVER_TERA] = 1,
1511 };
1512
1513 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1514 {
1515         struct hda_bus_template bus_temp;
1516         int c, codecs, err;
1517         int max_slots;
1518
1519         memset(&bus_temp, 0, sizeof(bus_temp));
1520         bus_temp.private_data = chip;
1521         bus_temp.modelname = model;
1522         bus_temp.pci = chip->pci;
1523         bus_temp.ops.command = azx_send_cmd;
1524         bus_temp.ops.get_response = azx_get_response;
1525         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1526         bus_temp.ops.bus_reset = azx_bus_reset;
1527 #ifdef CONFIG_SND_HDA_POWER_SAVE
1528         bus_temp.power_save = &power_save;
1529         bus_temp.ops.pm_notify = azx_power_notify;
1530 #endif
1531
1532         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1533         if (err < 0)
1534                 return err;
1535
1536         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1537                 snd_printd(SFX "Enable delay in RIRB handling\n");
1538                 chip->bus->needs_damn_long_delay = 1;
1539         }
1540
1541         codecs = 0;
1542         max_slots = azx_max_codecs[chip->driver_type];
1543         if (!max_slots)
1544                 max_slots = AZX_DEFAULT_CODECS;
1545
1546         /* First try to probe all given codec slots */
1547         for (c = 0; c < max_slots; c++) {
1548                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1549                         if (probe_codec(chip, c) < 0) {
1550                                 /* Some BIOSen give you wrong codec addresses
1551                                  * that don't exist
1552                                  */
1553                                 snd_printk(KERN_WARNING SFX
1554                                            "Codec #%d probe error; "
1555                                            "disabling it...\n", c);
1556                                 chip->codec_mask &= ~(1 << c);
1557                                 /* More badly, accessing to a non-existing
1558                                  * codec often screws up the controller chip,
1559                                  * and disturbs the further communications.
1560                                  * Thus if an error occurs during probing,
1561                                  * better to reset the controller chip to
1562                                  * get back to the sanity state.
1563                                  */
1564                                 azx_stop_chip(chip);
1565                                 azx_init_chip(chip, 1);
1566                         }
1567                 }
1568         }
1569
1570         /* AMD chipsets often cause the communication stalls upon certain
1571          * sequence like the pin-detection.  It seems that forcing the synced
1572          * access works around the stall.  Grrr...
1573          */
1574         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1575                 snd_printd(SFX "Enable sync_write for stable communication\n");
1576                 chip->bus->sync_write = 1;
1577                 chip->bus->allow_bus_reset = 1;
1578         }
1579
1580         /* Then create codec instances */
1581         for (c = 0; c < max_slots; c++) {
1582                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1583                         struct hda_codec *codec;
1584                         err = snd_hda_codec_new(chip->bus, c, &codec);
1585                         if (err < 0)
1586                                 continue;
1587                         codec->beep_mode = chip->beep_mode;
1588                         codecs++;
1589                 }
1590         }
1591         if (!codecs) {
1592                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1593                 return -ENXIO;
1594         }
1595         return 0;
1596 }
1597
1598 /* configure each codec instance */
1599 static int __devinit azx_codec_configure(struct azx *chip)
1600 {
1601         struct hda_codec *codec;
1602         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1603                 snd_hda_codec_configure(codec);
1604         }
1605         return 0;
1606 }
1607
1608
1609 /*
1610  * PCM support
1611  */
1612
1613 /* assign a stream for the PCM */
1614 static inline struct azx_dev *
1615 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1616 {
1617         int dev, i, nums;
1618         struct azx_dev *res = NULL;
1619         /* make a non-zero unique key for the substream */
1620         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1621                 (substream->stream + 1);
1622
1623         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1624                 dev = chip->playback_index_offset;
1625                 nums = chip->playback_streams;
1626         } else {
1627                 dev = chip->capture_index_offset;
1628                 nums = chip->capture_streams;
1629         }
1630         for (i = 0; i < nums; i++, dev++)
1631                 if (!chip->azx_dev[dev].opened) {
1632                         res = &chip->azx_dev[dev];
1633                         if (res->assigned_key == key)
1634                                 break;
1635                 }
1636         if (res) {
1637                 res->opened = 1;
1638                 res->assigned_key = key;
1639         }
1640         return res;
1641 }
1642
1643 /* release the assigned stream */
1644 static inline void azx_release_device(struct azx_dev *azx_dev)
1645 {
1646         azx_dev->opened = 0;
1647 }
1648
1649 static struct snd_pcm_hardware azx_pcm_hw = {
1650         .info =                 (SNDRV_PCM_INFO_MMAP |
1651                                  SNDRV_PCM_INFO_INTERLEAVED |
1652                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1653                                  SNDRV_PCM_INFO_MMAP_VALID |
1654                                  /* No full-resume yet implemented */
1655                                  /* SNDRV_PCM_INFO_RESUME |*/
1656                                  SNDRV_PCM_INFO_PAUSE |
1657                                  SNDRV_PCM_INFO_SYNC_START |
1658                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1659         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1660         .rates =                SNDRV_PCM_RATE_48000,
1661         .rate_min =             48000,
1662         .rate_max =             48000,
1663         .channels_min =         2,
1664         .channels_max =         2,
1665         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1666         .period_bytes_min =     128,
1667         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1668         .periods_min =          2,
1669         .periods_max =          AZX_MAX_FRAG,
1670         .fifo_size =            0,
1671 };
1672
1673 struct azx_pcm {
1674         struct azx *chip;
1675         struct hda_codec *codec;
1676         struct hda_pcm_stream *hinfo[2];
1677 };
1678
1679 static int azx_pcm_open(struct snd_pcm_substream *substream)
1680 {
1681         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1682         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1683         struct azx *chip = apcm->chip;
1684         struct azx_dev *azx_dev;
1685         struct snd_pcm_runtime *runtime = substream->runtime;
1686         unsigned long flags;
1687         int err;
1688         int buff_step;
1689
1690         mutex_lock(&chip->open_mutex);
1691         azx_dev = azx_assign_device(chip, substream);
1692         if (azx_dev == NULL) {
1693                 mutex_unlock(&chip->open_mutex);
1694                 return -EBUSY;
1695         }
1696         runtime->hw = azx_pcm_hw;
1697         runtime->hw.channels_min = hinfo->channels_min;
1698         runtime->hw.channels_max = hinfo->channels_max;
1699         runtime->hw.formats = hinfo->formats;
1700         runtime->hw.rates = hinfo->rates;
1701         snd_pcm_limit_hw_rates(runtime);
1702         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1703         if (chip->align_buffer_size)
1704                 /* constrain buffer sizes to be multiple of 128
1705                    bytes. This is more efficient in terms of memory
1706                    access but isn't required by the HDA spec and
1707                    prevents users from specifying exact period/buffer
1708                    sizes. For example for 44.1kHz, a period size set
1709                    to 20ms will be rounded to 19.59ms. */
1710                 buff_step = 128;
1711         else
1712                 /* Don't enforce steps on buffer sizes, still need to
1713                    be multiple of 4 bytes (HDA spec). Tested on Intel
1714                    HDA controllers, may not work on all devices where
1715                    option needs to be disabled */
1716                 buff_step = 4;
1717
1718         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1719                                    buff_step);
1720         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1721                                    buff_step);
1722         snd_hda_power_up(apcm->codec);
1723         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1724         if (err < 0) {
1725                 azx_release_device(azx_dev);
1726                 snd_hda_power_down(apcm->codec);
1727                 mutex_unlock(&chip->open_mutex);
1728                 return err;
1729         }
1730         snd_pcm_limit_hw_rates(runtime);
1731         /* sanity check */
1732         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1733             snd_BUG_ON(!runtime->hw.channels_max) ||
1734             snd_BUG_ON(!runtime->hw.formats) ||
1735             snd_BUG_ON(!runtime->hw.rates)) {
1736                 azx_release_device(azx_dev);
1737                 hinfo->ops.close(hinfo, apcm->codec, substream);
1738                 snd_hda_power_down(apcm->codec);
1739                 mutex_unlock(&chip->open_mutex);
1740                 return -EINVAL;
1741         }
1742         spin_lock_irqsave(&chip->reg_lock, flags);
1743         azx_dev->substream = substream;
1744         azx_dev->running = 0;
1745         spin_unlock_irqrestore(&chip->reg_lock, flags);
1746
1747         runtime->private_data = azx_dev;
1748         snd_pcm_set_sync(substream);
1749         mutex_unlock(&chip->open_mutex);
1750         return 0;
1751 }
1752
1753 static int azx_pcm_close(struct snd_pcm_substream *substream)
1754 {
1755         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1756         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1757         struct azx *chip = apcm->chip;
1758         struct azx_dev *azx_dev = get_azx_dev(substream);
1759         unsigned long flags;
1760
1761         mutex_lock(&chip->open_mutex);
1762         spin_lock_irqsave(&chip->reg_lock, flags);
1763         azx_dev->substream = NULL;
1764         azx_dev->running = 0;
1765         spin_unlock_irqrestore(&chip->reg_lock, flags);
1766         azx_release_device(azx_dev);
1767         hinfo->ops.close(hinfo, apcm->codec, substream);
1768         snd_hda_power_down(apcm->codec);
1769         mutex_unlock(&chip->open_mutex);
1770         return 0;
1771 }
1772
1773 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1774                              struct snd_pcm_hw_params *hw_params)
1775 {
1776         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1777         struct azx *chip = apcm->chip;
1778         struct snd_pcm_runtime *runtime = substream->runtime;
1779         struct azx_dev *azx_dev = get_azx_dev(substream);
1780         int ret;
1781
1782         mark_runtime_wc(chip, azx_dev, runtime, false);
1783         azx_dev->bufsize = 0;
1784         azx_dev->period_bytes = 0;
1785         azx_dev->format_val = 0;
1786         ret = snd_pcm_lib_malloc_pages(substream,
1787                                         params_buffer_bytes(hw_params));
1788         if (ret < 0)
1789                 return ret;
1790         mark_runtime_wc(chip, azx_dev, runtime, true);
1791         return ret;
1792 }
1793
1794 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1795 {
1796         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1797         struct azx_dev *azx_dev = get_azx_dev(substream);
1798         struct azx *chip = apcm->chip;
1799         struct snd_pcm_runtime *runtime = substream->runtime;
1800         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1801
1802         /* reset BDL address */
1803         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1804         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1805         azx_sd_writel(azx_dev, SD_CTL, 0);
1806         azx_dev->bufsize = 0;
1807         azx_dev->period_bytes = 0;
1808         azx_dev->format_val = 0;
1809
1810         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1811
1812         mark_runtime_wc(chip, azx_dev, runtime, false);
1813         return snd_pcm_lib_free_pages(substream);
1814 }
1815
1816 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1817 {
1818         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1819         struct azx *chip = apcm->chip;
1820         struct azx_dev *azx_dev = get_azx_dev(substream);
1821         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1822         struct snd_pcm_runtime *runtime = substream->runtime;
1823         unsigned int bufsize, period_bytes, format_val, stream_tag;
1824         int err;
1825         struct hda_spdif_out *spdif =
1826                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1827         unsigned short ctls = spdif ? spdif->ctls : 0;
1828
1829         azx_stream_reset(chip, azx_dev);
1830         format_val = snd_hda_calc_stream_format(runtime->rate,
1831                                                 runtime->channels,
1832                                                 runtime->format,
1833                                                 hinfo->maxbps,
1834                                                 ctls);
1835         if (!format_val) {
1836                 snd_printk(KERN_ERR SFX
1837                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1838                            runtime->rate, runtime->channels, runtime->format);
1839                 return -EINVAL;
1840         }
1841
1842         bufsize = snd_pcm_lib_buffer_bytes(substream);
1843         period_bytes = snd_pcm_lib_period_bytes(substream);
1844
1845         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1846                     bufsize, format_val);
1847
1848         if (bufsize != azx_dev->bufsize ||
1849             period_bytes != azx_dev->period_bytes ||
1850             format_val != azx_dev->format_val) {
1851                 azx_dev->bufsize = bufsize;
1852                 azx_dev->period_bytes = period_bytes;
1853                 azx_dev->format_val = format_val;
1854                 err = azx_setup_periods(chip, substream, azx_dev);
1855                 if (err < 0)
1856                         return err;
1857         }
1858
1859         /* wallclk has 24Mhz clock source */
1860         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1861                                                 runtime->rate) * 1000);
1862         azx_setup_controller(chip, azx_dev);
1863         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1864                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1865         else
1866                 azx_dev->fifo_size = 0;
1867
1868         stream_tag = azx_dev->stream_tag;
1869         /* CA-IBG chips need the playback stream starting from 1 */
1870         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1871             stream_tag > chip->capture_streams)
1872                 stream_tag -= chip->capture_streams;
1873         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1874                                      azx_dev->format_val, substream);
1875 }
1876
1877 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1878 {
1879         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1880         struct azx *chip = apcm->chip;
1881         struct azx_dev *azx_dev;
1882         struct snd_pcm_substream *s;
1883         int rstart = 0, start, nsync = 0, sbits = 0;
1884         int nwait, timeout;
1885
1886         switch (cmd) {
1887         case SNDRV_PCM_TRIGGER_START:
1888                 rstart = 1;
1889         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1890         case SNDRV_PCM_TRIGGER_RESUME:
1891                 start = 1;
1892                 break;
1893         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1894         case SNDRV_PCM_TRIGGER_SUSPEND:
1895         case SNDRV_PCM_TRIGGER_STOP:
1896                 start = 0;
1897                 break;
1898         default:
1899                 return -EINVAL;
1900         }
1901
1902         snd_pcm_group_for_each_entry(s, substream) {
1903                 if (s->pcm->card != substream->pcm->card)
1904                         continue;
1905                 azx_dev = get_azx_dev(s);
1906                 sbits |= 1 << azx_dev->index;
1907                 nsync++;
1908                 snd_pcm_trigger_done(s, substream);
1909         }
1910
1911         spin_lock(&chip->reg_lock);
1912         if (nsync > 1) {
1913                 /* first, set SYNC bits of corresponding streams */
1914                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1915                         azx_writel(chip, OLD_SSYNC,
1916                                    azx_readl(chip, OLD_SSYNC) | sbits);
1917                 else
1918                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1919         }
1920         snd_pcm_group_for_each_entry(s, substream) {
1921                 if (s->pcm->card != substream->pcm->card)
1922                         continue;
1923                 azx_dev = get_azx_dev(s);
1924                 if (start) {
1925                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1926                         if (!rstart)
1927                                 azx_dev->start_wallclk -=
1928                                                 azx_dev->period_wallclk;
1929                         azx_stream_start(chip, azx_dev);
1930                 } else {
1931                         azx_stream_stop(chip, azx_dev);
1932                 }
1933                 azx_dev->running = start;
1934         }
1935         spin_unlock(&chip->reg_lock);
1936         if (start) {
1937                 if (nsync == 1)
1938                         return 0;
1939                 /* wait until all FIFOs get ready */
1940                 for (timeout = 5000; timeout; timeout--) {
1941                         nwait = 0;
1942                         snd_pcm_group_for_each_entry(s, substream) {
1943                                 if (s->pcm->card != substream->pcm->card)
1944                                         continue;
1945                                 azx_dev = get_azx_dev(s);
1946                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1947                                       SD_STS_FIFO_READY))
1948                                         nwait++;
1949                         }
1950                         if (!nwait)
1951                                 break;
1952                         cpu_relax();
1953                 }
1954         } else {
1955                 /* wait until all RUN bits are cleared */
1956                 for (timeout = 5000; timeout; timeout--) {
1957                         nwait = 0;
1958                         snd_pcm_group_for_each_entry(s, substream) {
1959                                 if (s->pcm->card != substream->pcm->card)
1960                                         continue;
1961                                 azx_dev = get_azx_dev(s);
1962                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1963                                     SD_CTL_DMA_START)
1964                                         nwait++;
1965                         }
1966                         if (!nwait)
1967                                 break;
1968                         cpu_relax();
1969                 }
1970         }
1971         if (nsync > 1) {
1972                 spin_lock(&chip->reg_lock);
1973                 /* reset SYNC bits */
1974                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1975                         azx_writel(chip, OLD_SSYNC,
1976                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1977                 else
1978                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1979                 spin_unlock(&chip->reg_lock);
1980         }
1981         return 0;
1982 }
1983
1984 /* get the current DMA position with correction on VIA chips */
1985 static unsigned int azx_via_get_position(struct azx *chip,
1986                                          struct azx_dev *azx_dev)
1987 {
1988         unsigned int link_pos, mini_pos, bound_pos;
1989         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1990         unsigned int fifo_size;
1991
1992         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1993         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1994                 /* Playback, no problem using link position */
1995                 return link_pos;
1996         }
1997
1998         /* Capture */
1999         /* For new chipset,
2000          * use mod to get the DMA position just like old chipset
2001          */
2002         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2003         mod_dma_pos %= azx_dev->period_bytes;
2004
2005         /* azx_dev->fifo_size can't get FIFO size of in stream.
2006          * Get from base address + offset.
2007          */
2008         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2009
2010         if (azx_dev->insufficient) {
2011                 /* Link position never gather than FIFO size */
2012                 if (link_pos <= fifo_size)
2013                         return 0;
2014
2015                 azx_dev->insufficient = 0;
2016         }
2017
2018         if (link_pos <= fifo_size)
2019                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2020         else
2021                 mini_pos = link_pos - fifo_size;
2022
2023         /* Find nearest previous boudary */
2024         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2025         mod_link_pos = link_pos % azx_dev->period_bytes;
2026         if (mod_link_pos >= fifo_size)
2027                 bound_pos = link_pos - mod_link_pos;
2028         else if (mod_dma_pos >= mod_mini_pos)
2029                 bound_pos = mini_pos - mod_mini_pos;
2030         else {
2031                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2032                 if (bound_pos >= azx_dev->bufsize)
2033                         bound_pos = 0;
2034         }
2035
2036         /* Calculate real DMA position we want */
2037         return bound_pos + mod_dma_pos;
2038 }
2039
2040 static unsigned int azx_get_position(struct azx *chip,
2041                                      struct azx_dev *azx_dev,
2042                                      bool with_check)
2043 {
2044         unsigned int pos;
2045         int stream = azx_dev->substream->stream;
2046
2047         switch (chip->position_fix[stream]) {
2048         case POS_FIX_LPIB:
2049                 /* read LPIB */
2050                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2051                 break;
2052         case POS_FIX_VIACOMBO:
2053                 pos = azx_via_get_position(chip, azx_dev);
2054                 break;
2055         default:
2056                 /* use the position buffer */
2057                 pos = le32_to_cpu(*azx_dev->posbuf);
2058                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2059                         if (!pos || pos == (u32)-1) {
2060                                 printk(KERN_WARNING
2061                                        "hda-intel: Invalid position buffer, "
2062                                        "using LPIB read method instead.\n");
2063                                 chip->position_fix[stream] = POS_FIX_LPIB;
2064                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2065                         } else
2066                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2067                 }
2068                 break;
2069         }
2070
2071         if (pos >= azx_dev->bufsize)
2072                 pos = 0;
2073         return pos;
2074 }
2075
2076 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2077 {
2078         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2079         struct azx *chip = apcm->chip;
2080         struct azx_dev *azx_dev = get_azx_dev(substream);
2081         return bytes_to_frames(substream->runtime,
2082                                azx_get_position(chip, azx_dev, false));
2083 }
2084
2085 /*
2086  * Check whether the current DMA position is acceptable for updating
2087  * periods.  Returns non-zero if it's OK.
2088  *
2089  * Many HD-audio controllers appear pretty inaccurate about
2090  * the update-IRQ timing.  The IRQ is issued before actually the
2091  * data is processed.  So, we need to process it afterwords in a
2092  * workqueue.
2093  */
2094 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2095 {
2096         u32 wallclk;
2097         unsigned int pos;
2098         int stream;
2099
2100         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2101         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2102                 return -1;      /* bogus (too early) interrupt */
2103
2104         stream = azx_dev->substream->stream;
2105         pos = azx_get_position(chip, azx_dev, true);
2106
2107         if (WARN_ONCE(!azx_dev->period_bytes,
2108                       "hda-intel: zero azx_dev->period_bytes"))
2109                 return -1; /* this shouldn't happen! */
2110         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2111             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2112                 /* NG - it's below the first next period boundary */
2113                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2114         azx_dev->start_wallclk += wallclk;
2115         return 1; /* OK, it's fine */
2116 }
2117
2118 /*
2119  * The work for pending PCM period updates.
2120  */
2121 static void azx_irq_pending_work(struct work_struct *work)
2122 {
2123         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2124         int i, pending, ok;
2125
2126         if (!chip->irq_pending_warned) {
2127                 printk(KERN_WARNING
2128                        "hda-intel: IRQ timing workaround is activated "
2129                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2130                        chip->card->number);
2131                 chip->irq_pending_warned = 1;
2132         }
2133
2134         for (;;) {
2135                 pending = 0;
2136                 spin_lock_irq(&chip->reg_lock);
2137                 for (i = 0; i < chip->num_streams; i++) {
2138                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2139                         if (!azx_dev->irq_pending ||
2140                             !azx_dev->substream ||
2141                             !azx_dev->running)
2142                                 continue;
2143                         ok = azx_position_ok(chip, azx_dev);
2144                         if (ok > 0) {
2145                                 azx_dev->irq_pending = 0;
2146                                 spin_unlock(&chip->reg_lock);
2147                                 snd_pcm_period_elapsed(azx_dev->substream);
2148                                 spin_lock(&chip->reg_lock);
2149                         } else if (ok < 0) {
2150                                 pending = 0;    /* too early */
2151                         } else
2152                                 pending++;
2153                 }
2154                 spin_unlock_irq(&chip->reg_lock);
2155                 if (!pending)
2156                         return;
2157                 msleep(1);
2158         }
2159 }
2160
2161 /* clear irq_pending flags and assure no on-going workq */
2162 static void azx_clear_irq_pending(struct azx *chip)
2163 {
2164         int i;
2165
2166         spin_lock_irq(&chip->reg_lock);
2167         for (i = 0; i < chip->num_streams; i++)
2168                 chip->azx_dev[i].irq_pending = 0;
2169         spin_unlock_irq(&chip->reg_lock);
2170 }
2171
2172 #ifdef CONFIG_X86
2173 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2174                         struct vm_area_struct *area)
2175 {
2176         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2177         struct azx *chip = apcm->chip;
2178         if (!azx_snoop(chip))
2179                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2180         return snd_pcm_lib_default_mmap(substream, area);
2181 }
2182 #else
2183 #define azx_pcm_mmap    NULL
2184 #endif
2185
2186 static struct snd_pcm_ops azx_pcm_ops = {
2187         .open = azx_pcm_open,
2188         .close = azx_pcm_close,
2189         .ioctl = snd_pcm_lib_ioctl,
2190         .hw_params = azx_pcm_hw_params,
2191         .hw_free = azx_pcm_hw_free,
2192         .prepare = azx_pcm_prepare,
2193         .trigger = azx_pcm_trigger,
2194         .pointer = azx_pcm_pointer,
2195         .mmap = azx_pcm_mmap,
2196         .page = snd_pcm_sgbuf_ops_page,
2197 };
2198
2199 static void azx_pcm_free(struct snd_pcm *pcm)
2200 {
2201         struct azx_pcm *apcm = pcm->private_data;
2202         if (apcm) {
2203                 apcm->chip->pcm[pcm->device] = NULL;
2204                 kfree(apcm);
2205         }
2206 }
2207
2208 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2209
2210 static int
2211 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2212                       struct hda_pcm *cpcm)
2213 {
2214         struct azx *chip = bus->private_data;
2215         struct snd_pcm *pcm;
2216         struct azx_pcm *apcm;
2217         int pcm_dev = cpcm->device;
2218         unsigned int size;
2219         int s, err;
2220
2221         if (pcm_dev >= HDA_MAX_PCMS) {
2222                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2223                            pcm_dev);
2224                 return -EINVAL;
2225         }
2226         if (chip->pcm[pcm_dev]) {
2227                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2228                 return -EBUSY;
2229         }
2230         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2231                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2232                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2233                           &pcm);
2234         if (err < 0)
2235                 return err;
2236         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2237         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2238         if (apcm == NULL)
2239                 return -ENOMEM;
2240         apcm->chip = chip;
2241         apcm->codec = codec;
2242         pcm->private_data = apcm;
2243         pcm->private_free = azx_pcm_free;
2244         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2245                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2246         chip->pcm[pcm_dev] = pcm;
2247         cpcm->pcm = pcm;
2248         for (s = 0; s < 2; s++) {
2249                 apcm->hinfo[s] = &cpcm->stream[s];
2250                 if (cpcm->stream[s].substreams)
2251                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2252         }
2253         /* buffer pre-allocation */
2254         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2255         if (size > MAX_PREALLOC_SIZE)
2256                 size = MAX_PREALLOC_SIZE;
2257         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2258                                               snd_dma_pci_data(chip->pci),
2259                                               size, MAX_PREALLOC_SIZE);
2260         return 0;
2261 }
2262
2263 /*
2264  * mixer creation - all stuff is implemented in hda module
2265  */
2266 static int __devinit azx_mixer_create(struct azx *chip)
2267 {
2268         return snd_hda_build_controls(chip->bus);
2269 }
2270
2271
2272 /*
2273  * initialize SD streams
2274  */
2275 static int __devinit azx_init_stream(struct azx *chip)
2276 {
2277         int i;
2278
2279         /* initialize each stream (aka device)
2280          * assign the starting bdl address to each stream (device)
2281          * and initialize
2282          */
2283         for (i = 0; i < chip->num_streams; i++) {
2284                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2285                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2286                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2287                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2288                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2289                 azx_dev->sd_int_sta_mask = 1 << i;
2290                 /* stream tag: must be non-zero and unique */
2291                 azx_dev->index = i;
2292                 azx_dev->stream_tag = i + 1;
2293         }
2294
2295         return 0;
2296 }
2297
2298 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2299 {
2300         if (request_irq(chip->pci->irq, azx_interrupt,
2301                         chip->msi ? 0 : IRQF_SHARED,
2302                         KBUILD_MODNAME, chip)) {
2303                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2304                        "disabling device\n", chip->pci->irq);
2305                 if (do_disconnect)
2306                         snd_card_disconnect(chip->card);
2307                 return -1;
2308         }
2309         chip->irq = chip->pci->irq;
2310         pci_intx(chip->pci, !chip->msi);
2311         return 0;
2312 }
2313
2314
2315 static void azx_stop_chip(struct azx *chip)
2316 {
2317         if (!chip->initialized)
2318                 return;
2319
2320         /* disable interrupts */
2321         azx_int_disable(chip);
2322         azx_int_clear(chip);
2323
2324         /* disable CORB/RIRB */
2325         azx_free_cmd_io(chip);
2326
2327         /* disable position buffer */
2328         azx_writel(chip, DPLBASE, 0);
2329         azx_writel(chip, DPUBASE, 0);
2330
2331         chip->initialized = 0;
2332 }
2333
2334 #ifdef CONFIG_SND_HDA_POWER_SAVE
2335 /* power-up/down the controller */
2336 static void azx_power_notify(struct hda_bus *bus)
2337 {
2338         struct azx *chip = bus->private_data;
2339         struct hda_codec *c;
2340         int power_on = 0;
2341
2342         list_for_each_entry(c, &bus->codec_list, list) {
2343                 if (c->power_on) {
2344                         power_on = 1;
2345                         break;
2346                 }
2347         }
2348         if (power_on)
2349                 azx_init_chip(chip, 1);
2350         else if (chip->running && power_save_controller &&
2351                  !bus->power_keep_link_on)
2352                 azx_stop_chip(chip);
2353 }
2354 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2355
2356 #ifdef CONFIG_PM
2357 /*
2358  * power management
2359  */
2360
2361 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2362 {
2363         struct hda_codec *codec;
2364
2365         list_for_each_entry(codec, &bus->codec_list, list) {
2366                 if (snd_hda_codec_needs_resume(codec))
2367                         return 1;
2368         }
2369         return 0;
2370 }
2371
2372 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2373 {
2374         struct snd_card *card = pci_get_drvdata(pci);
2375         struct azx *chip = card->private_data;
2376         int i;
2377
2378         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2379         azx_clear_irq_pending(chip);
2380         for (i = 0; i < HDA_MAX_PCMS; i++)
2381                 snd_pcm_suspend_all(chip->pcm[i]);
2382         if (chip->initialized)
2383                 snd_hda_suspend(chip->bus);
2384         azx_stop_chip(chip);
2385         if (chip->irq >= 0) {
2386                 free_irq(chip->irq, chip);
2387                 chip->irq = -1;
2388         }
2389         if (chip->msi)
2390                 pci_disable_msi(chip->pci);
2391         pci_disable_device(pci);
2392         pci_save_state(pci);
2393         pci_set_power_state(pci, pci_choose_state(pci, state));
2394         return 0;
2395 }
2396
2397 static int azx_resume(struct pci_dev *pci)
2398 {
2399         struct snd_card *card = pci_get_drvdata(pci);
2400         struct azx *chip = card->private_data;
2401
2402         pci_set_power_state(pci, PCI_D0);
2403         pci_restore_state(pci);
2404         if (pci_enable_device(pci) < 0) {
2405                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2406                        "disabling device\n");
2407                 snd_card_disconnect(card);
2408                 return -EIO;
2409         }
2410         pci_set_master(pci);
2411         if (chip->msi)
2412                 if (pci_enable_msi(pci) < 0)
2413                         chip->msi = 0;
2414         if (azx_acquire_irq(chip, 1) < 0)
2415                 return -EIO;
2416         azx_init_pci(chip);
2417
2418         if (snd_hda_codecs_inuse(chip->bus))
2419                 azx_init_chip(chip, 1);
2420
2421         snd_hda_resume(chip->bus);
2422         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2423         return 0;
2424 }
2425 #endif /* CONFIG_PM */
2426
2427
2428 /*
2429  * reboot notifier for hang-up problem at power-down
2430  */
2431 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2432 {
2433         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2434         snd_hda_bus_reboot_notify(chip->bus);
2435         azx_stop_chip(chip);
2436         return NOTIFY_OK;
2437 }
2438
2439 static void azx_notifier_register(struct azx *chip)
2440 {
2441         chip->reboot_notifier.notifier_call = azx_halt;
2442         register_reboot_notifier(&chip->reboot_notifier);
2443 }
2444
2445 static void azx_notifier_unregister(struct azx *chip)
2446 {
2447         if (chip->reboot_notifier.notifier_call)
2448                 unregister_reboot_notifier(&chip->reboot_notifier);
2449 }
2450
2451 /*
2452  * destructor
2453  */
2454 static int azx_free(struct azx *chip)
2455 {
2456         int i;
2457
2458         azx_notifier_unregister(chip);
2459
2460         if (chip->initialized) {
2461                 azx_clear_irq_pending(chip);
2462                 for (i = 0; i < chip->num_streams; i++)
2463                         azx_stream_stop(chip, &chip->azx_dev[i]);
2464                 azx_stop_chip(chip);
2465         }
2466
2467         if (chip->irq >= 0)
2468                 free_irq(chip->irq, (void*)chip);
2469         if (chip->msi)
2470                 pci_disable_msi(chip->pci);
2471         if (chip->remap_addr)
2472                 iounmap(chip->remap_addr);
2473
2474         if (chip->azx_dev) {
2475                 for (i = 0; i < chip->num_streams; i++)
2476                         if (chip->azx_dev[i].bdl.area) {
2477                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2478                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2479                         }
2480         }
2481         if (chip->rb.area) {
2482                 mark_pages_wc(chip, &chip->rb, false);
2483                 snd_dma_free_pages(&chip->rb);
2484         }
2485         if (chip->posbuf.area) {
2486                 mark_pages_wc(chip, &chip->posbuf, false);
2487                 snd_dma_free_pages(&chip->posbuf);
2488         }
2489         pci_release_regions(chip->pci);
2490         pci_disable_device(chip->pci);
2491         kfree(chip->azx_dev);
2492         kfree(chip);
2493
2494         return 0;
2495 }
2496
2497 static int azx_dev_free(struct snd_device *device)
2498 {
2499         return azx_free(device->device_data);
2500 }
2501
2502 /*
2503  * white/black-listing for position_fix
2504  */
2505 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2506         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2507         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2508         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2509         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2510         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2511         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2512         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2513         SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB),
2514         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2515         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2516         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2517         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2518         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2519         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2520         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2521         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2522         {}
2523 };
2524
2525 static int __devinit check_position_fix(struct azx *chip, int fix)
2526 {
2527         const struct snd_pci_quirk *q;
2528
2529         switch (fix) {
2530         case POS_FIX_LPIB:
2531         case POS_FIX_POSBUF:
2532         case POS_FIX_VIACOMBO:
2533                 return fix;
2534         }
2535
2536         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2537         if (q) {
2538                 printk(KERN_INFO
2539                        "hda_intel: position_fix set to %d "
2540                        "for device %04x:%04x\n",
2541                        q->value, q->subvendor, q->subdevice);
2542                 return q->value;
2543         }
2544
2545         /* Check VIA/ATI HD Audio Controller exist */
2546         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2547                 snd_printd(SFX "Using VIACOMBO position fix\n");
2548                 return POS_FIX_VIACOMBO;
2549         }
2550         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2551                 snd_printd(SFX "Using LPIB position fix\n");
2552                 return POS_FIX_LPIB;
2553         }
2554         return POS_FIX_AUTO;
2555 }
2556
2557 /*
2558  * black-lists for probe_mask
2559  */
2560 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2561         /* Thinkpad often breaks the controller communication when accessing
2562          * to the non-working (or non-existing) modem codec slot.
2563          */
2564         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2565         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2566         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2567         /* broken BIOS */
2568         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2569         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2570         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2571         /* forced codec slots */
2572         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2573         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2574         {}
2575 };
2576
2577 #define AZX_FORCE_CODEC_MASK    0x100
2578
2579 static void __devinit check_probe_mask(struct azx *chip, int dev)
2580 {
2581         const struct snd_pci_quirk *q;
2582
2583         chip->codec_probe_mask = probe_mask[dev];
2584         if (chip->codec_probe_mask == -1) {
2585                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2586                 if (q) {
2587                         printk(KERN_INFO
2588                                "hda_intel: probe_mask set to 0x%x "
2589                                "for device %04x:%04x\n",
2590                                q->value, q->subvendor, q->subdevice);
2591                         chip->codec_probe_mask = q->value;
2592                 }
2593         }
2594
2595         /* check forced option */
2596         if (chip->codec_probe_mask != -1 &&
2597             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2598                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2599                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2600                        chip->codec_mask);
2601         }
2602 }
2603
2604 /*
2605  * white/black-list for enable_msi
2606  */
2607 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2608         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2609         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2610         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2611         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2612         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2613         {}
2614 };
2615
2616 static void __devinit check_msi(struct azx *chip)
2617 {
2618         const struct snd_pci_quirk *q;
2619
2620         if (enable_msi >= 0) {
2621                 chip->msi = !!enable_msi;
2622                 return;
2623         }
2624         chip->msi = 1;  /* enable MSI as default */
2625         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2626         if (q) {
2627                 printk(KERN_INFO
2628                        "hda_intel: msi for device %04x:%04x set to %d\n",
2629                        q->subvendor, q->subdevice, q->value);
2630                 chip->msi = q->value;
2631                 return;
2632         }
2633
2634         /* NVidia chipsets seem to cause troubles with MSI */
2635         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2636                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2637                 chip->msi = 0;
2638         }
2639 }
2640
2641
2642 /*
2643  * constructor
2644  */
2645 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2646                                 int dev, unsigned int driver_caps,
2647                                 struct azx **rchip)
2648 {
2649         struct azx *chip;
2650         int i, err;
2651         unsigned short gcap;
2652         static struct snd_device_ops ops = {
2653                 .dev_free = azx_dev_free,
2654         };
2655
2656         *rchip = NULL;
2657
2658         err = pci_enable_device(pci);
2659         if (err < 0)
2660                 return err;
2661
2662         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2663         if (!chip) {
2664                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2665                 pci_disable_device(pci);
2666                 return -ENOMEM;
2667         }
2668
2669         spin_lock_init(&chip->reg_lock);
2670         mutex_init(&chip->open_mutex);
2671         chip->card = card;
2672         chip->pci = pci;
2673         chip->irq = -1;
2674         chip->driver_caps = driver_caps;
2675         chip->driver_type = driver_caps & 0xff;
2676         check_msi(chip);
2677         chip->dev_index = dev;
2678         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2679
2680         chip->position_fix[0] = chip->position_fix[1] =
2681                 check_position_fix(chip, position_fix[dev]);
2682         check_probe_mask(chip, dev);
2683
2684         chip->single_cmd = single_cmd;
2685         chip->snoop = hda_snoop;
2686
2687         if (bdl_pos_adj[dev] < 0) {
2688                 switch (chip->driver_type) {
2689                 case AZX_DRIVER_ICH:
2690                 case AZX_DRIVER_PCH:
2691                         bdl_pos_adj[dev] = 1;
2692                         break;
2693                 default:
2694                         bdl_pos_adj[dev] = 32;
2695                         break;
2696                 }
2697         }
2698
2699 #if BITS_PER_LONG != 64
2700         /* Fix up base address on ULI M5461 */
2701         if (chip->driver_type == AZX_DRIVER_ULI) {
2702                 u16 tmp3;
2703                 pci_read_config_word(pci, 0x40, &tmp3);
2704                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2705                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2706         }
2707 #endif
2708
2709         err = pci_request_regions(pci, "ICH HD audio");
2710         if (err < 0) {
2711                 kfree(chip);
2712                 pci_disable_device(pci);
2713                 return err;
2714         }
2715
2716         chip->addr = pci_resource_start(pci, 0);
2717         chip->remap_addr = pci_ioremap_bar(pci, 0);
2718         if (chip->remap_addr == NULL) {
2719                 snd_printk(KERN_ERR SFX "ioremap error\n");
2720                 err = -ENXIO;
2721                 goto errout;
2722         }
2723
2724         if (chip->msi)
2725                 if (pci_enable_msi(pci) < 0)
2726                         chip->msi = 0;
2727
2728         if (azx_acquire_irq(chip, 0) < 0) {
2729                 err = -EBUSY;
2730                 goto errout;
2731         }
2732
2733         pci_set_master(pci);
2734         synchronize_irq(chip->irq);
2735
2736         gcap = azx_readw(chip, GCAP);
2737         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2738
2739         /* disable SB600 64bit support for safety */
2740         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2741                 struct pci_dev *p_smbus;
2742                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2743                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2744                                          NULL);
2745                 if (p_smbus) {
2746                         if (p_smbus->revision < 0x30)
2747                                 gcap &= ~ICH6_GCAP_64OK;
2748                         pci_dev_put(p_smbus);
2749                 }
2750         }
2751
2752         /* disable 64bit DMA address on some devices */
2753         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2754                 snd_printd(SFX "Disabling 64bit DMA\n");
2755                 gcap &= ~ICH6_GCAP_64OK;
2756         }
2757
2758         /* disable buffer size rounding to 128-byte multiples if supported */
2759         chip->align_buffer_size = align_buffer_size;
2760         if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2761                 chip->align_buffer_size = 0;
2762
2763         /* allow 64bit DMA address if supported by H/W */
2764         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2765                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2766         else {
2767                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2768                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2769         }
2770
2771         /* read number of streams from GCAP register instead of using
2772          * hardcoded value
2773          */
2774         chip->capture_streams = (gcap >> 8) & 0x0f;
2775         chip->playback_streams = (gcap >> 12) & 0x0f;
2776         if (!chip->playback_streams && !chip->capture_streams) {
2777                 /* gcap didn't give any info, switching to old method */
2778
2779                 switch (chip->driver_type) {
2780                 case AZX_DRIVER_ULI:
2781                         chip->playback_streams = ULI_NUM_PLAYBACK;
2782                         chip->capture_streams = ULI_NUM_CAPTURE;
2783                         break;
2784                 case AZX_DRIVER_ATIHDMI:
2785                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2786                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2787                         break;
2788                 case AZX_DRIVER_GENERIC:
2789                 default:
2790                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2791                         chip->capture_streams = ICH6_NUM_CAPTURE;
2792                         break;
2793                 }
2794         }
2795         chip->capture_index_offset = 0;
2796         chip->playback_index_offset = chip->capture_streams;
2797         chip->num_streams = chip->playback_streams + chip->capture_streams;
2798         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2799                                 GFP_KERNEL);
2800         if (!chip->azx_dev) {
2801                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2802                 goto errout;
2803         }
2804
2805         for (i = 0; i < chip->num_streams; i++) {
2806                 /* allocate memory for the BDL for each stream */
2807                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2808                                           snd_dma_pci_data(chip->pci),
2809                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2810                 if (err < 0) {
2811                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2812                         goto errout;
2813                 }
2814                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2815         }
2816         /* allocate memory for the position buffer */
2817         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2818                                   snd_dma_pci_data(chip->pci),
2819                                   chip->num_streams * 8, &chip->posbuf);
2820         if (err < 0) {
2821                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2822                 goto errout;
2823         }
2824         mark_pages_wc(chip, &chip->posbuf, true);
2825         /* allocate CORB/RIRB */
2826         err = azx_alloc_cmd_io(chip);
2827         if (err < 0)
2828                 goto errout;
2829
2830         /* initialize streams */
2831         azx_init_stream(chip);
2832
2833         /* initialize chip */
2834         azx_init_pci(chip);
2835         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2836
2837         /* codec detection */
2838         if (!chip->codec_mask) {
2839                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2840                 err = -ENODEV;
2841                 goto errout;
2842         }
2843
2844         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2845         if (err <0) {
2846                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2847                 goto errout;
2848         }
2849
2850         strcpy(card->driver, "HDA-Intel");
2851         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2852                 sizeof(card->shortname));
2853         snprintf(card->longname, sizeof(card->longname),
2854                  "%s at 0x%lx irq %i",
2855                  card->shortname, chip->addr, chip->irq);
2856
2857         *rchip = chip;
2858         return 0;
2859
2860  errout:
2861         azx_free(chip);
2862         return err;
2863 }
2864
2865 static void power_down_all_codecs(struct azx *chip)
2866 {
2867 #ifdef CONFIG_SND_HDA_POWER_SAVE
2868         /* The codecs were powered up in snd_hda_codec_new().
2869          * Now all initialization done, so turn them down if possible
2870          */
2871         struct hda_codec *codec;
2872         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2873                 snd_hda_power_down(codec);
2874         }
2875 #endif
2876 }
2877
2878 static int __devinit azx_probe(struct pci_dev *pci,
2879                                const struct pci_device_id *pci_id)
2880 {
2881         static int dev;
2882         struct snd_card *card;
2883         struct azx *chip;
2884         int err;
2885
2886         if (dev >= SNDRV_CARDS)
2887                 return -ENODEV;
2888         if (!enable[dev]) {
2889                 dev++;
2890                 return -ENOENT;
2891         }
2892
2893         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2894         if (err < 0) {
2895                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2896                 return err;
2897         }
2898
2899         /* set this here since it's referred in snd_hda_load_patch() */
2900         snd_card_set_dev(card, &pci->dev);
2901
2902         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2903         if (err < 0)
2904                 goto out_free;
2905         card->private_data = chip;
2906
2907 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2908         chip->beep_mode = beep_mode[dev];
2909 #endif
2910
2911         /* create codec instances */
2912         err = azx_codec_create(chip, model[dev]);
2913         if (err < 0)
2914                 goto out_free;
2915 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2916         if (patch[dev] && *patch[dev]) {
2917                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2918                            patch[dev]);
2919                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2920                 if (err < 0)
2921                         goto out_free;
2922         }
2923 #endif
2924         if ((probe_only[dev] & 1) == 0) {
2925                 err = azx_codec_configure(chip);
2926                 if (err < 0)
2927                         goto out_free;
2928         }
2929
2930         /* create PCM streams */
2931         err = snd_hda_build_pcms(chip->bus);
2932         if (err < 0)
2933                 goto out_free;
2934
2935         /* create mixer controls */
2936         err = azx_mixer_create(chip);
2937         if (err < 0)
2938                 goto out_free;
2939
2940         err = snd_card_register(card);
2941         if (err < 0)
2942                 goto out_free;
2943
2944         pci_set_drvdata(pci, card);
2945         chip->running = 1;
2946         power_down_all_codecs(chip);
2947         azx_notifier_register(chip);
2948
2949         dev++;
2950         return err;
2951 out_free:
2952         snd_card_free(card);
2953         return err;
2954 }
2955
2956 static void __devexit azx_remove(struct pci_dev *pci)
2957 {
2958         snd_card_free(pci_get_drvdata(pci));
2959         pci_set_drvdata(pci, NULL);
2960 }
2961
2962 /* PCI IDs */
2963 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2964         /* CPT */
2965         { PCI_DEVICE(0x8086, 0x1c20),
2966           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2967           AZX_DCAPS_BUFSIZE },
2968         /* PBG */
2969         { PCI_DEVICE(0x8086, 0x1d20),
2970           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2971           AZX_DCAPS_BUFSIZE},
2972         /* Panther Point */
2973         { PCI_DEVICE(0x8086, 0x1e20),
2974           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2975           AZX_DCAPS_BUFSIZE},
2976         /* SCH */
2977         { PCI_DEVICE(0x8086, 0x811b),
2978           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2979           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
2980         /* ICH */
2981         { PCI_DEVICE(0x8086, 0x2668),
2982           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2983           AZX_DCAPS_BUFSIZE },  /* ICH6 */
2984         { PCI_DEVICE(0x8086, 0x27d8),
2985           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2986           AZX_DCAPS_BUFSIZE },  /* ICH7 */
2987         { PCI_DEVICE(0x8086, 0x269a),
2988           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2989           AZX_DCAPS_BUFSIZE },  /* ESB2 */
2990         { PCI_DEVICE(0x8086, 0x284b),
2991           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2992           AZX_DCAPS_BUFSIZE },  /* ICH8 */
2993         { PCI_DEVICE(0x8086, 0x293e),
2994           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2995           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2996         { PCI_DEVICE(0x8086, 0x293f),
2997           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2998           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2999         { PCI_DEVICE(0x8086, 0x3a3e),
3000           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3001           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3002         { PCI_DEVICE(0x8086, 0x3a6e),
3003           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3004           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3005         /* Generic Intel */
3006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3007           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3008           .class_mask = 0xffffff,
3009           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3010         /* ATI SB 450/600/700/800/900 */
3011         { PCI_DEVICE(0x1002, 0x437b),
3012           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3013         { PCI_DEVICE(0x1002, 0x4383),
3014           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3015         /* AMD Hudson */
3016         { PCI_DEVICE(0x1022, 0x780d),
3017           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3018         /* ATI HDMI */
3019         { PCI_DEVICE(0x1002, 0x793b),
3020           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3021         { PCI_DEVICE(0x1002, 0x7919),
3022           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3023         { PCI_DEVICE(0x1002, 0x960f),
3024           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3025         { PCI_DEVICE(0x1002, 0x970f),
3026           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3027         { PCI_DEVICE(0x1002, 0xaa00),
3028           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3029         { PCI_DEVICE(0x1002, 0xaa08),
3030           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3031         { PCI_DEVICE(0x1002, 0xaa10),
3032           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3033         { PCI_DEVICE(0x1002, 0xaa18),
3034           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3035         { PCI_DEVICE(0x1002, 0xaa20),
3036           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3037         { PCI_DEVICE(0x1002, 0xaa28),
3038           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3039         { PCI_DEVICE(0x1002, 0xaa30),
3040           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3041         { PCI_DEVICE(0x1002, 0xaa38),
3042           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3043         { PCI_DEVICE(0x1002, 0xaa40),
3044           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3045         { PCI_DEVICE(0x1002, 0xaa48),
3046           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3047         /* VIA VT8251/VT8237A */
3048         { PCI_DEVICE(0x1106, 0x3288),
3049           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3050         /* SIS966 */
3051         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3052         /* ULI M5461 */
3053         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3054         /* NVIDIA MCP */
3055         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3056           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3057           .class_mask = 0xffffff,
3058           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3059         /* Teradici */
3060         { PCI_DEVICE(0x6549, 0x1200),
3061           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3062         /* Creative X-Fi (CA0110-IBG) */
3063 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3064         /* the following entry conflicts with snd-ctxfi driver,
3065          * as ctxfi driver mutates from HD-audio to native mode with
3066          * a special command sequence.
3067          */
3068         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3069           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3070           .class_mask = 0xffffff,
3071           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3072           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3073 #else
3074         /* this entry seems still valid -- i.e. without emu20kx chip */
3075         { PCI_DEVICE(0x1102, 0x0009),
3076           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3077           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3078 #endif
3079         /* Vortex86MX */
3080         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3081         /* VMware HDAudio */
3082         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3083         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3084         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3085           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3086           .class_mask = 0xffffff,
3087           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3088         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3089           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3090           .class_mask = 0xffffff,
3091           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3092         { 0, }
3093 };
3094 MODULE_DEVICE_TABLE(pci, azx_ids);
3095
3096 /* pci_driver definition */
3097 static struct pci_driver driver = {
3098         .name = KBUILD_MODNAME,
3099         .id_table = azx_ids,
3100         .probe = azx_probe,
3101         .remove = __devexit_p(azx_remove),
3102 #ifdef CONFIG_PM
3103         .suspend = azx_suspend,
3104         .resume = azx_resume,
3105 #endif
3106 };
3107
3108 static int __init alsa_card_azx_init(void)
3109 {
3110         return pci_register_driver(&driver);
3111 }
3112
3113 static void __exit alsa_card_azx_exit(void)
3114 {
3115         pci_unregister_driver(&driver);
3116 }
3117
3118 module_init(alsa_card_azx_init)
3119 module_exit(alsa_card_azx_exit)