3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
129 MODULE_DESCRIPTION("Intel HDA driver");
131 #ifdef CONFIG_SND_VERBOSE_PRINTK
132 #define SFX /* nop */
134 #define SFX "hda-intel: "
140 #define ICH6_REG_GCAP 0x00
141 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
142 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
143 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
144 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
145 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
146 #define ICH6_REG_VMIN 0x02
147 #define ICH6_REG_VMAJ 0x03
148 #define ICH6_REG_OUTPAY 0x04
149 #define ICH6_REG_INPAY 0x06
150 #define ICH6_REG_GCTL 0x08
151 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
152 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
153 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
154 #define ICH6_REG_WAKEEN 0x0c
155 #define ICH6_REG_STATESTS 0x0e
156 #define ICH6_REG_GSTS 0x10
157 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
158 #define ICH6_REG_INTCTL 0x20
159 #define ICH6_REG_INTSTS 0x24
160 #define ICH6_REG_WALCLK 0x30
161 #define ICH6_REG_SYNC 0x34
162 #define ICH6_REG_CORBLBASE 0x40
163 #define ICH6_REG_CORBUBASE 0x44
164 #define ICH6_REG_CORBWP 0x48
165 #define ICH6_REG_CORBRP 0x4a
166 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
167 #define ICH6_REG_CORBCTL 0x4c
168 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
169 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
170 #define ICH6_REG_CORBSTS 0x4d
171 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
172 #define ICH6_REG_CORBSIZE 0x4e
174 #define ICH6_REG_RIRBLBASE 0x50
175 #define ICH6_REG_RIRBUBASE 0x54
176 #define ICH6_REG_RIRBWP 0x58
177 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
178 #define ICH6_REG_RINTCNT 0x5a
179 #define ICH6_REG_RIRBCTL 0x5c
180 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
181 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
182 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
183 #define ICH6_REG_RIRBSTS 0x5d
184 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
185 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
186 #define ICH6_REG_RIRBSIZE 0x5e
188 #define ICH6_REG_IC 0x60
189 #define ICH6_REG_IR 0x64
190 #define ICH6_REG_IRS 0x68
191 #define ICH6_IRS_VALID (1<<1)
192 #define ICH6_IRS_BUSY (1<<0)
194 #define ICH6_REG_DPLBASE 0x70
195 #define ICH6_REG_DPUBASE 0x74
196 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
201 /* stream register offsets from stream base */
202 #define ICH6_REG_SD_CTL 0x00
203 #define ICH6_REG_SD_STS 0x03
204 #define ICH6_REG_SD_LPIB 0x04
205 #define ICH6_REG_SD_CBL 0x08
206 #define ICH6_REG_SD_LVI 0x0c
207 #define ICH6_REG_SD_FIFOW 0x0e
208 #define ICH6_REG_SD_FIFOSIZE 0x10
209 #define ICH6_REG_SD_FORMAT 0x12
210 #define ICH6_REG_SD_BDLPL 0x18
211 #define ICH6_REG_SD_BDLPU 0x1c
214 #define ICH6_PCIREG_TCSEL 0x44
220 /* max number of SDs */
221 /* ICH, ATI and VIA have 4 playback and 4 capture */
222 #define ICH6_NUM_CAPTURE 4
223 #define ICH6_NUM_PLAYBACK 4
225 /* ULI has 6 playback and 5 capture */
226 #define ULI_NUM_CAPTURE 5
227 #define ULI_NUM_PLAYBACK 6
229 /* ATI HDMI has 1 playback and 0 capture */
230 #define ATIHDMI_NUM_CAPTURE 0
231 #define ATIHDMI_NUM_PLAYBACK 1
233 /* TERA has 4 playback and 3 capture */
234 #define TERA_NUM_CAPTURE 3
235 #define TERA_NUM_PLAYBACK 4
237 /* this number is statically defined for simplicity */
238 #define MAX_AZX_DEV 16
240 /* max number of fragments - we may use more if allocating more pages for BDL */
241 #define BDL_SIZE 4096
242 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
243 #define AZX_MAX_FRAG 32
244 /* max buffer size - no h/w limit, you can increase as you like */
245 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
246 /* max number of PCM devics per card */
247 #define AZX_MAX_PCMS 8
249 /* RIRB int mask: overrun[2], response[0] */
250 #define RIRB_INT_RESPONSE 0x01
251 #define RIRB_INT_OVERRUN 0x04
252 #define RIRB_INT_MASK 0x05
254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
255 #define AZX_MAX_CODECS 4
256 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
259 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
260 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
261 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
262 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
263 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
264 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
265 #define SD_CTL_STREAM_TAG_SHIFT 20
267 /* SD_CTL and SD_STS */
268 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
269 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
270 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
271 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
275 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
277 /* INTCTL and INTSTS */
278 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
279 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
280 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
282 /* below are so far hardcoded - should read registers in future */
283 #define ICH6_MAX_CORB_ENTRIES 256
284 #define ICH6_MAX_RIRB_ENTRIES 256
286 /* position fix mode */
293 /* Defines for ATI HD Audio support in SB450 south bridge */
294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
297 /* Defines for Nvidia HDA support */
298 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
299 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
300 #define NVIDIA_HDA_ISTRM_COH 0x4d
301 #define NVIDIA_HDA_OSTRM_COH 0x4c
302 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
304 /* Defines for Intel SCH HDA snoop control */
305 #define INTEL_SCH_HDA_DEVC 0x78
306 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
308 /* Define IN stream 0 FIFO size offset in VIA controller */
309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
310 /* Define VIA HD Audio Device ID*/
311 #define VIA_HDAC_DEVICE_ID 0x3288
313 /* HD Audio class code */
314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
320 struct snd_dma_buffer bdl; /* BDL buffer */
321 u32 *posbuf; /* position buffer pointer */
323 unsigned int bufsize; /* size of the play buffer in bytes */
324 unsigned int period_bytes; /* size of the period in bytes */
325 unsigned int frags; /* number for period in the play buffer */
326 unsigned int fifo_size; /* FIFO size */
327 unsigned long start_jiffies; /* start + minimum jiffies */
328 unsigned long min_jiffies; /* minimum jiffies before position is valid */
330 void __iomem *sd_addr; /* stream descriptor pointer */
332 u32 sd_int_sta_mask; /* stream int status mask */
335 struct snd_pcm_substream *substream; /* assigned substream,
338 unsigned int format_val; /* format value to be set in the
339 * controller and the codec
341 unsigned char stream_tag; /* assigned stream */
342 unsigned char index; /* stream index */
344 unsigned int opened :1;
345 unsigned int running :1;
346 unsigned int irq_pending :1;
347 unsigned int start_flag: 1; /* stream full start flag */
350 * A flag to ensure DMA position is 0
351 * when link position is not greater than FIFO size
353 unsigned int insufficient :1;
358 u32 *buf; /* CORB/RIRB buffer
359 * Each CORB entry is 4byte, RIRB is 8byte
361 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
363 unsigned short rp, wp; /* read/write pointers */
364 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
365 u32 res[AZX_MAX_CODECS]; /* last read value */
369 struct snd_card *card;
373 /* chip type specific */
375 int playback_streams;
376 int playback_index_offset;
378 int capture_index_offset;
383 void __iomem *remap_addr;
388 struct mutex open_mutex;
390 /* streams (x num_streams) */
391 struct azx_dev *azx_dev;
394 struct snd_pcm *pcm[AZX_MAX_PCMS];
397 unsigned short codec_mask;
398 int codec_probe_mask; /* copied from probe_mask option */
405 /* CORB/RIRB and position buffers */
406 struct snd_dma_buffer rb;
407 struct snd_dma_buffer posbuf;
411 unsigned int running :1;
412 unsigned int initialized :1;
413 unsigned int single_cmd :1;
414 unsigned int polling_mode :1;
416 unsigned int irq_pending_warned :1;
417 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
418 unsigned int probing :1; /* codec probing phase */
421 unsigned int last_cmd; /* last issued command (to sync) */
423 /* for pending irqs */
424 struct work_struct irq_pending_work;
426 /* reboot notifier (for mysterious hangup problem at power-down) */
427 struct notifier_block reboot_notifier;
442 AZX_NUM_DRIVERS, /* keep this as last entry */
445 static char *driver_short_names[] __devinitdata = {
446 [AZX_DRIVER_ICH] = "HDA Intel",
447 [AZX_DRIVER_SCH] = "HDA Intel MID",
448 [AZX_DRIVER_ATI] = "HDA ATI SB",
449 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
450 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
451 [AZX_DRIVER_SIS] = "HDA SIS966",
452 [AZX_DRIVER_ULI] = "HDA ULI M5461",
453 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
454 [AZX_DRIVER_TERA] = "HDA Teradici",
455 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
459 * macros for easy use
461 #define azx_writel(chip,reg,value) \
462 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
463 #define azx_readl(chip,reg) \
464 readl((chip)->remap_addr + ICH6_REG_##reg)
465 #define azx_writew(chip,reg,value) \
466 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
467 #define azx_readw(chip,reg) \
468 readw((chip)->remap_addr + ICH6_REG_##reg)
469 #define azx_writeb(chip,reg,value) \
470 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
471 #define azx_readb(chip,reg) \
472 readb((chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_sd_writel(dev,reg,value) \
475 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
476 #define azx_sd_readl(dev,reg) \
477 readl((dev)->sd_addr + ICH6_REG_##reg)
478 #define azx_sd_writew(dev,reg,value) \
479 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
480 #define azx_sd_readw(dev,reg) \
481 readw((dev)->sd_addr + ICH6_REG_##reg)
482 #define azx_sd_writeb(dev,reg,value) \
483 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
484 #define azx_sd_readb(dev,reg) \
485 readb((dev)->sd_addr + ICH6_REG_##reg)
487 /* for pcm support */
488 #define get_azx_dev(substream) (substream->runtime->private_data)
490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
493 * Interface for HD codec
497 * CORB / RIRB interface
499 static int azx_alloc_cmd_io(struct azx *chip)
503 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
504 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
505 snd_dma_pci_data(chip->pci),
506 PAGE_SIZE, &chip->rb);
508 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
514 static void azx_init_cmd_io(struct azx *chip)
517 chip->corb.addr = chip->rb.addr;
518 chip->corb.buf = (u32 *)chip->rb.area;
519 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
520 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
522 /* set the corb size to 256 entries (ULI requires explicitly) */
523 azx_writeb(chip, CORBSIZE, 0x02);
524 /* set the corb write pointer to 0 */
525 azx_writew(chip, CORBWP, 0);
526 /* reset the corb hw read pointer */
527 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
528 /* enable corb dma */
529 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
532 chip->rirb.addr = chip->rb.addr + 2048;
533 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
534 chip->rirb.wp = chip->rirb.rp = 0;
535 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
536 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
537 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
539 /* set the rirb size to 256 entries (ULI requires explicitly) */
540 azx_writeb(chip, RIRBSIZE, 0x02);
541 /* reset the rirb hw write pointer */
542 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
543 /* set N=1, get RIRB response interrupt for new entry */
544 azx_writew(chip, RINTCNT, 1);
545 /* enable rirb dma and response irq */
546 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
549 static void azx_free_cmd_io(struct azx *chip)
551 /* disable ringbuffer DMAs */
552 azx_writeb(chip, RIRBCTL, 0);
553 azx_writeb(chip, CORBCTL, 0);
556 static unsigned int azx_command_addr(u32 cmd)
558 unsigned int addr = cmd >> 28;
560 if (addr >= AZX_MAX_CODECS) {
568 static unsigned int azx_response_addr(u32 res)
570 unsigned int addr = res & 0xf;
572 if (addr >= AZX_MAX_CODECS) {
581 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
583 struct azx *chip = bus->private_data;
584 unsigned int addr = azx_command_addr(val);
587 /* add command to corb */
588 wp = azx_readb(chip, CORBWP);
590 wp %= ICH6_MAX_CORB_ENTRIES;
592 spin_lock_irq(&chip->reg_lock);
593 chip->rirb.cmds[addr]++;
594 chip->corb.buf[wp] = cpu_to_le32(val);
595 azx_writel(chip, CORBWP, wp);
596 spin_unlock_irq(&chip->reg_lock);
601 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
603 /* retrieve RIRB entry - called from interrupt handler */
604 static void azx_update_rirb(struct azx *chip)
610 wp = azx_readb(chip, RIRBWP);
611 if (wp == chip->rirb.wp)
615 while (chip->rirb.rp != wp) {
617 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
619 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
620 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
621 res = le32_to_cpu(chip->rirb.buf[rp]);
622 addr = azx_response_addr(res_ex);
623 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
624 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
625 else if (chip->rirb.cmds[addr]) {
626 chip->rirb.res[addr] = res;
628 chip->rirb.cmds[addr]--;
633 /* receive a response */
634 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
637 struct azx *chip = bus->private_data;
638 unsigned long timeout;
641 timeout = jiffies + msecs_to_jiffies(1000);
643 if (chip->polling_mode) {
644 spin_lock_irq(&chip->reg_lock);
645 azx_update_rirb(chip);
646 spin_unlock_irq(&chip->reg_lock);
648 if (!chip->rirb.cmds[addr]) {
651 return chip->rirb.res[addr]; /* the last value */
653 if (time_after(jiffies, timeout))
655 if (bus->needs_damn_long_delay)
656 msleep(2); /* temporary workaround */
664 snd_printk(KERN_WARNING SFX "No response from codec, "
665 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
666 free_irq(chip->irq, chip);
668 pci_disable_msi(chip->pci);
670 if (azx_acquire_irq(chip, 1) < 0) {
677 if (!chip->polling_mode) {
678 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
679 "switching to polling mode: last cmd=0x%08x\n",
681 chip->polling_mode = 1;
686 /* If this critical timeout happens during the codec probing
687 * phase, this is likely an access to a non-existing codec
688 * slot. Better to return an error and reset the system.
693 /* a fatal communication error; need either to reset or to fallback
694 * to the single_cmd mode
697 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
698 bus->response_reset = 1;
699 return -1; /* give a chance to retry */
702 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
703 "switching to single_cmd mode: last cmd=0x%08x\n",
705 chip->single_cmd = 1;
706 bus->response_reset = 0;
707 /* re-initialize CORB/RIRB */
708 azx_free_cmd_io(chip);
709 azx_init_cmd_io(chip);
714 * Use the single immediate command instead of CORB/RIRB for simplicity
716 * Note: according to Intel, this is not preferred use. The command was
717 * intended for the BIOS only, and may get confused with unsolicited
718 * responses. So, we shouldn't use it for normal operation from the
720 * I left the codes, however, for debugging/testing purposes.
723 /* receive a response */
724 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
729 /* check IRV busy bit */
730 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
731 /* reuse rirb.res as the response return value */
732 chip->rirb.res[addr] = azx_readl(chip, IR);
737 if (printk_ratelimit())
738 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
739 azx_readw(chip, IRS));
740 chip->rirb.res[addr] = -1;
745 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
747 struct azx *chip = bus->private_data;
748 unsigned int addr = azx_command_addr(val);
753 /* check ICB busy bit */
754 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
755 /* Clear IRV valid bit */
756 azx_writew(chip, IRS, azx_readw(chip, IRS) |
758 azx_writel(chip, IC, val);
759 azx_writew(chip, IRS, azx_readw(chip, IRS) |
761 return azx_single_wait_for_response(chip, addr);
765 if (printk_ratelimit())
766 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
767 azx_readw(chip, IRS), val);
771 /* receive a response */
772 static unsigned int azx_single_get_response(struct hda_bus *bus,
775 struct azx *chip = bus->private_data;
776 return chip->rirb.res[addr];
780 * The below are the main callbacks from hda_codec.
782 * They are just the skeleton to call sub-callbacks according to the
783 * current setting of chip->single_cmd.
787 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
789 struct azx *chip = bus->private_data;
791 chip->last_cmd = val;
792 if (chip->single_cmd)
793 return azx_single_send_cmd(bus, val);
795 return azx_corb_send_cmd(bus, val);
799 static unsigned int azx_get_response(struct hda_bus *bus,
802 struct azx *chip = bus->private_data;
803 if (chip->single_cmd)
804 return azx_single_get_response(bus, addr);
806 return azx_rirb_get_response(bus, addr);
809 #ifdef CONFIG_SND_HDA_POWER_SAVE
810 static void azx_power_notify(struct hda_bus *bus);
813 /* reset codec link */
814 static int azx_reset(struct azx *chip)
819 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
821 /* reset controller */
822 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
825 while (azx_readb(chip, GCTL) && --count)
828 /* delay for >= 100us for codec PLL to settle per spec
829 * Rev 0.9 section 5.5.1
833 /* Bring controller out of reset */
834 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
837 while (!azx_readb(chip, GCTL) && --count)
840 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
843 /* check to see if controller is ready */
844 if (!azx_readb(chip, GCTL)) {
845 snd_printd(SFX "azx_reset: controller not ready!\n");
849 /* Accept unsolicited responses */
850 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
853 if (!chip->codec_mask) {
854 chip->codec_mask = azx_readw(chip, STATESTS);
855 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
866 /* enable interrupts */
867 static void azx_int_enable(struct azx *chip)
869 /* enable controller CIE and GIE */
870 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
871 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
874 /* disable interrupts */
875 static void azx_int_disable(struct azx *chip)
879 /* disable interrupts in stream descriptor */
880 for (i = 0; i < chip->num_streams; i++) {
881 struct azx_dev *azx_dev = &chip->azx_dev[i];
882 azx_sd_writeb(azx_dev, SD_CTL,
883 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
886 /* disable SIE for all streams */
887 azx_writeb(chip, INTCTL, 0);
889 /* disable controller CIE and GIE */
890 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
891 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
894 /* clear interrupts */
895 static void azx_int_clear(struct azx *chip)
899 /* clear stream status */
900 for (i = 0; i < chip->num_streams; i++) {
901 struct azx_dev *azx_dev = &chip->azx_dev[i];
902 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
906 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
908 /* clear rirb status */
909 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
911 /* clear int status */
912 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
916 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
919 * Before stream start, initialize parameter
921 azx_dev->insufficient = 1;
924 azx_writeb(chip, INTCTL,
925 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
926 /* set DMA start and interrupt mask */
927 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
928 SD_CTL_DMA_START | SD_INT_MASK);
932 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
934 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
935 ~(SD_CTL_DMA_START | SD_INT_MASK));
936 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
940 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
942 azx_stream_clear(chip, azx_dev);
944 azx_writeb(chip, INTCTL,
945 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
950 * reset and start the controller registers
952 static void azx_init_chip(struct azx *chip)
954 if (chip->initialized)
957 /* reset controller */
960 /* initialize interrupts */
962 azx_int_enable(chip);
964 /* initialize the codec command I/O */
965 azx_init_cmd_io(chip);
967 /* program the position buffer */
968 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
969 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
971 chip->initialized = 1;
975 * initialize the PCI registers
977 /* update bits in a PCI register byte */
978 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
979 unsigned char mask, unsigned char val)
983 pci_read_config_byte(pci, reg, &data);
985 data |= (val & mask);
986 pci_write_config_byte(pci, reg, data);
989 static void azx_init_pci(struct azx *chip)
991 unsigned short snoop;
993 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
994 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
995 * Ensuring these bits are 0 clears playback static on some HD Audio
998 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1000 switch (chip->driver_type) {
1001 case AZX_DRIVER_ATI:
1002 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1003 update_pci_byte(chip->pci,
1004 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1005 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1007 case AZX_DRIVER_NVIDIA:
1008 /* For NVIDIA HDA, enable snoop */
1009 update_pci_byte(chip->pci,
1010 NVIDIA_HDA_TRANSREG_ADDR,
1011 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1012 update_pci_byte(chip->pci,
1013 NVIDIA_HDA_ISTRM_COH,
1014 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1015 update_pci_byte(chip->pci,
1016 NVIDIA_HDA_OSTRM_COH,
1017 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1019 case AZX_DRIVER_SCH:
1020 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1021 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1022 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1023 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1024 pci_read_config_word(chip->pci,
1025 INTEL_SCH_HDA_DEVC, &snoop);
1026 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1027 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1036 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1041 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1043 struct azx *chip = dev_id;
1044 struct azx_dev *azx_dev;
1048 spin_lock(&chip->reg_lock);
1050 status = azx_readl(chip, INTSTS);
1052 spin_unlock(&chip->reg_lock);
1056 for (i = 0; i < chip->num_streams; i++) {
1057 azx_dev = &chip->azx_dev[i];
1058 if (status & azx_dev->sd_int_sta_mask) {
1059 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1060 if (!azx_dev->substream || !azx_dev->running)
1062 /* check whether this IRQ is really acceptable */
1063 ok = azx_position_ok(chip, azx_dev);
1065 azx_dev->irq_pending = 0;
1066 spin_unlock(&chip->reg_lock);
1067 snd_pcm_period_elapsed(azx_dev->substream);
1068 spin_lock(&chip->reg_lock);
1069 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1070 /* bogus IRQ, process it later */
1071 azx_dev->irq_pending = 1;
1072 queue_work(chip->bus->workq,
1073 &chip->irq_pending_work);
1078 /* clear rirb int */
1079 status = azx_readb(chip, RIRBSTS);
1080 if (status & RIRB_INT_MASK) {
1081 if (status & RIRB_INT_RESPONSE)
1082 azx_update_rirb(chip);
1083 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1087 /* clear state status int */
1088 if (azx_readb(chip, STATESTS) & 0x04)
1089 azx_writeb(chip, STATESTS, 0x04);
1091 spin_unlock(&chip->reg_lock);
1098 * set up a BDL entry
1100 static int setup_bdle(struct snd_pcm_substream *substream,
1101 struct azx_dev *azx_dev, u32 **bdlp,
1102 int ofs, int size, int with_ioc)
1110 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1113 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1114 /* program the address field of the BDL entry */
1115 bdl[0] = cpu_to_le32((u32)addr);
1116 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1117 /* program the size field of the BDL entry */
1118 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1119 bdl[2] = cpu_to_le32(chunk);
1120 /* program the IOC to enable interrupt
1121 * only when the whole fragment is processed
1124 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1134 * set up BDL entries
1136 static int azx_setup_periods(struct azx *chip,
1137 struct snd_pcm_substream *substream,
1138 struct azx_dev *azx_dev)
1141 int i, ofs, periods, period_bytes;
1144 /* reset BDL address */
1145 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1146 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1148 period_bytes = azx_dev->period_bytes;
1149 periods = azx_dev->bufsize / period_bytes;
1151 /* program the initial BDL entries */
1152 bdl = (u32 *)azx_dev->bdl.area;
1155 pos_adj = bdl_pos_adj[chip->dev_index];
1157 struct snd_pcm_runtime *runtime = substream->runtime;
1158 int pos_align = pos_adj;
1159 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1161 pos_adj = pos_align;
1163 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1165 pos_adj = frames_to_bytes(runtime, pos_adj);
1166 if (pos_adj >= period_bytes) {
1167 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1168 bdl_pos_adj[chip->dev_index]);
1171 ofs = setup_bdle(substream, azx_dev,
1172 &bdl, ofs, pos_adj, 1);
1178 for (i = 0; i < periods; i++) {
1179 if (i == periods - 1 && pos_adj)
1180 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1181 period_bytes - pos_adj, 0);
1183 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1191 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1192 azx_dev->bufsize, period_bytes);
1197 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1202 azx_stream_clear(chip, azx_dev);
1204 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1205 SD_CTL_STREAM_RESET);
1208 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1211 val &= ~SD_CTL_STREAM_RESET;
1212 azx_sd_writeb(azx_dev, SD_CTL, val);
1216 /* waiting for hardware to report that the stream is out of reset */
1217 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1221 /* reset first position - may not be synced with hw at this time */
1222 *azx_dev->posbuf = 0;
1226 * set up the SD for streaming
1228 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1230 /* make sure the run bit is zero for SD */
1231 azx_stream_clear(chip, azx_dev);
1232 /* program the stream_tag */
1233 azx_sd_writel(azx_dev, SD_CTL,
1234 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1235 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1237 /* program the length of samples in cyclic buffer */
1238 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1240 /* program the stream format */
1241 /* this value needs to be the same as the one programmed */
1242 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1244 /* program the stream LVI (last valid index) of the BDL */
1245 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1247 /* program the BDL address */
1248 /* lower BDL address */
1249 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1250 /* upper BDL address */
1251 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1253 /* enable the position buffer */
1254 if (chip->position_fix == POS_FIX_POSBUF ||
1255 chip->position_fix == POS_FIX_AUTO ||
1256 chip->via_dmapos_patch) {
1257 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1258 azx_writel(chip, DPLBASE,
1259 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1262 /* set the interrupt enable bits in the descriptor control register */
1263 azx_sd_writel(azx_dev, SD_CTL,
1264 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1270 * Probe the given codec address
1272 static int probe_codec(struct azx *chip, int addr)
1274 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1275 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1279 azx_send_cmd(chip->bus, cmd);
1280 res = azx_get_response(chip->bus, addr);
1284 snd_printdd(SFX "codec #%d probed OK\n", addr);
1288 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1289 struct hda_pcm *cpcm);
1290 static void azx_stop_chip(struct azx *chip);
1292 static void azx_bus_reset(struct hda_bus *bus)
1294 struct azx *chip = bus->private_data;
1297 azx_stop_chip(chip);
1298 azx_init_chip(chip);
1300 if (chip->initialized) {
1303 for (i = 0; i < AZX_MAX_PCMS; i++)
1304 snd_pcm_suspend_all(chip->pcm[i]);
1305 snd_hda_suspend(chip->bus);
1306 snd_hda_resume(chip->bus);
1313 * Codec initialization
1316 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1317 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1318 [AZX_DRIVER_TERA] = 1,
1321 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1324 struct hda_bus_template bus_temp;
1328 memset(&bus_temp, 0, sizeof(bus_temp));
1329 bus_temp.private_data = chip;
1330 bus_temp.modelname = model;
1331 bus_temp.pci = chip->pci;
1332 bus_temp.ops.command = azx_send_cmd;
1333 bus_temp.ops.get_response = azx_get_response;
1334 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1335 bus_temp.ops.bus_reset = azx_bus_reset;
1336 #ifdef CONFIG_SND_HDA_POWER_SAVE
1337 bus_temp.power_save = &power_save;
1338 bus_temp.ops.pm_notify = azx_power_notify;
1341 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1345 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1346 chip->bus->needs_damn_long_delay = 1;
1349 max_slots = azx_max_codecs[chip->driver_type];
1351 max_slots = AZX_MAX_CODECS;
1353 /* First try to probe all given codec slots */
1354 for (c = 0; c < max_slots; c++) {
1355 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1356 if (probe_codec(chip, c) < 0) {
1357 /* Some BIOSen give you wrong codec addresses
1360 snd_printk(KERN_WARNING SFX
1361 "Codec #%d probe error; "
1362 "disabling it...\n", c);
1363 chip->codec_mask &= ~(1 << c);
1364 /* More badly, accessing to a non-existing
1365 * codec often screws up the controller chip,
1366 * and distrubs the further communications.
1367 * Thus if an error occurs during probing,
1368 * better to reset the controller chip to
1369 * get back to the sanity state.
1371 azx_stop_chip(chip);
1372 azx_init_chip(chip);
1377 /* Then create codec instances */
1378 for (c = 0; c < max_slots; c++) {
1379 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1380 struct hda_codec *codec;
1381 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1388 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1400 /* assign a stream for the PCM */
1401 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1404 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1405 dev = chip->playback_index_offset;
1406 nums = chip->playback_streams;
1408 dev = chip->capture_index_offset;
1409 nums = chip->capture_streams;
1411 for (i = 0; i < nums; i++, dev++)
1412 if (!chip->azx_dev[dev].opened) {
1413 chip->azx_dev[dev].opened = 1;
1414 return &chip->azx_dev[dev];
1419 /* release the assigned stream */
1420 static inline void azx_release_device(struct azx_dev *azx_dev)
1422 azx_dev->opened = 0;
1425 static struct snd_pcm_hardware azx_pcm_hw = {
1426 .info = (SNDRV_PCM_INFO_MMAP |
1427 SNDRV_PCM_INFO_INTERLEAVED |
1428 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1429 SNDRV_PCM_INFO_MMAP_VALID |
1430 /* No full-resume yet implemented */
1431 /* SNDRV_PCM_INFO_RESUME |*/
1432 SNDRV_PCM_INFO_PAUSE |
1433 SNDRV_PCM_INFO_SYNC_START),
1434 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1435 .rates = SNDRV_PCM_RATE_48000,
1440 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1441 .period_bytes_min = 128,
1442 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1444 .periods_max = AZX_MAX_FRAG,
1450 struct hda_codec *codec;
1451 struct hda_pcm_stream *hinfo[2];
1454 static int azx_pcm_open(struct snd_pcm_substream *substream)
1456 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1457 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1458 struct azx *chip = apcm->chip;
1459 struct azx_dev *azx_dev;
1460 struct snd_pcm_runtime *runtime = substream->runtime;
1461 unsigned long flags;
1464 mutex_lock(&chip->open_mutex);
1465 azx_dev = azx_assign_device(chip, substream->stream);
1466 if (azx_dev == NULL) {
1467 mutex_unlock(&chip->open_mutex);
1470 runtime->hw = azx_pcm_hw;
1471 runtime->hw.channels_min = hinfo->channels_min;
1472 runtime->hw.channels_max = hinfo->channels_max;
1473 runtime->hw.formats = hinfo->formats;
1474 runtime->hw.rates = hinfo->rates;
1475 snd_pcm_limit_hw_rates(runtime);
1476 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1477 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1479 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1481 snd_hda_power_up(apcm->codec);
1482 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1484 azx_release_device(azx_dev);
1485 snd_hda_power_down(apcm->codec);
1486 mutex_unlock(&chip->open_mutex);
1489 snd_pcm_limit_hw_rates(runtime);
1491 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1492 snd_BUG_ON(!runtime->hw.channels_max) ||
1493 snd_BUG_ON(!runtime->hw.formats) ||
1494 snd_BUG_ON(!runtime->hw.rates)) {
1495 azx_release_device(azx_dev);
1496 hinfo->ops.close(hinfo, apcm->codec, substream);
1497 snd_hda_power_down(apcm->codec);
1498 mutex_unlock(&chip->open_mutex);
1501 spin_lock_irqsave(&chip->reg_lock, flags);
1502 azx_dev->substream = substream;
1503 azx_dev->running = 0;
1504 spin_unlock_irqrestore(&chip->reg_lock, flags);
1506 runtime->private_data = azx_dev;
1507 snd_pcm_set_sync(substream);
1508 mutex_unlock(&chip->open_mutex);
1512 static int azx_pcm_close(struct snd_pcm_substream *substream)
1514 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1515 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1516 struct azx *chip = apcm->chip;
1517 struct azx_dev *azx_dev = get_azx_dev(substream);
1518 unsigned long flags;
1520 mutex_lock(&chip->open_mutex);
1521 spin_lock_irqsave(&chip->reg_lock, flags);
1522 azx_dev->substream = NULL;
1523 azx_dev->running = 0;
1524 spin_unlock_irqrestore(&chip->reg_lock, flags);
1525 azx_release_device(azx_dev);
1526 hinfo->ops.close(hinfo, apcm->codec, substream);
1527 snd_hda_power_down(apcm->codec);
1528 mutex_unlock(&chip->open_mutex);
1532 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1533 struct snd_pcm_hw_params *hw_params)
1535 struct azx_dev *azx_dev = get_azx_dev(substream);
1537 azx_dev->bufsize = 0;
1538 azx_dev->period_bytes = 0;
1539 azx_dev->format_val = 0;
1540 return snd_pcm_lib_malloc_pages(substream,
1541 params_buffer_bytes(hw_params));
1544 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1546 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1547 struct azx_dev *azx_dev = get_azx_dev(substream);
1548 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1550 /* reset BDL address */
1551 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1552 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1553 azx_sd_writel(azx_dev, SD_CTL, 0);
1554 azx_dev->bufsize = 0;
1555 azx_dev->period_bytes = 0;
1556 azx_dev->format_val = 0;
1558 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1560 return snd_pcm_lib_free_pages(substream);
1563 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1565 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1566 struct azx *chip = apcm->chip;
1567 struct azx_dev *azx_dev = get_azx_dev(substream);
1568 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1569 struct snd_pcm_runtime *runtime = substream->runtime;
1570 unsigned int bufsize, period_bytes, format_val;
1573 azx_stream_reset(chip, azx_dev);
1574 format_val = snd_hda_calc_stream_format(runtime->rate,
1579 snd_printk(KERN_ERR SFX
1580 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1581 runtime->rate, runtime->channels, runtime->format);
1585 bufsize = snd_pcm_lib_buffer_bytes(substream);
1586 period_bytes = snd_pcm_lib_period_bytes(substream);
1588 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1589 bufsize, format_val);
1591 if (bufsize != azx_dev->bufsize ||
1592 period_bytes != azx_dev->period_bytes ||
1593 format_val != azx_dev->format_val) {
1594 azx_dev->bufsize = bufsize;
1595 azx_dev->period_bytes = period_bytes;
1596 azx_dev->format_val = format_val;
1597 err = azx_setup_periods(chip, substream, azx_dev);
1602 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1603 (runtime->rate * 2);
1604 azx_setup_controller(chip, azx_dev);
1605 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1606 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1608 azx_dev->fifo_size = 0;
1610 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1611 azx_dev->format_val, substream);
1614 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1616 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1617 struct azx *chip = apcm->chip;
1618 struct azx_dev *azx_dev;
1619 struct snd_pcm_substream *s;
1620 int rstart = 0, start, nsync = 0, sbits = 0;
1624 case SNDRV_PCM_TRIGGER_START:
1626 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1627 case SNDRV_PCM_TRIGGER_RESUME:
1630 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1631 case SNDRV_PCM_TRIGGER_SUSPEND:
1632 case SNDRV_PCM_TRIGGER_STOP:
1639 snd_pcm_group_for_each_entry(s, substream) {
1640 if (s->pcm->card != substream->pcm->card)
1642 azx_dev = get_azx_dev(s);
1643 sbits |= 1 << azx_dev->index;
1645 snd_pcm_trigger_done(s, substream);
1648 spin_lock(&chip->reg_lock);
1650 /* first, set SYNC bits of corresponding streams */
1651 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1653 snd_pcm_group_for_each_entry(s, substream) {
1654 if (s->pcm->card != substream->pcm->card)
1656 azx_dev = get_azx_dev(s);
1658 azx_dev->start_flag = 1;
1659 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1662 azx_stream_start(chip, azx_dev);
1664 azx_stream_stop(chip, azx_dev);
1665 azx_dev->running = start;
1667 spin_unlock(&chip->reg_lock);
1671 /* wait until all FIFOs get ready */
1672 for (timeout = 5000; timeout; timeout--) {
1674 snd_pcm_group_for_each_entry(s, substream) {
1675 if (s->pcm->card != substream->pcm->card)
1677 azx_dev = get_azx_dev(s);
1678 if (!(azx_sd_readb(azx_dev, SD_STS) &
1687 /* wait until all RUN bits are cleared */
1688 for (timeout = 5000; timeout; timeout--) {
1690 snd_pcm_group_for_each_entry(s, substream) {
1691 if (s->pcm->card != substream->pcm->card)
1693 azx_dev = get_azx_dev(s);
1694 if (azx_sd_readb(azx_dev, SD_CTL) &
1704 spin_lock(&chip->reg_lock);
1705 /* reset SYNC bits */
1706 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1707 spin_unlock(&chip->reg_lock);
1712 /* get the current DMA position with correction on VIA chips */
1713 static unsigned int azx_via_get_position(struct azx *chip,
1714 struct azx_dev *azx_dev)
1716 unsigned int link_pos, mini_pos, bound_pos;
1717 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1718 unsigned int fifo_size;
1720 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1721 if (azx_dev->index >= 4) {
1722 /* Playback, no problem using link position */
1728 * use mod to get the DMA position just like old chipset
1730 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1731 mod_dma_pos %= azx_dev->period_bytes;
1733 /* azx_dev->fifo_size can't get FIFO size of in stream.
1734 * Get from base address + offset.
1736 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1738 if (azx_dev->insufficient) {
1739 /* Link position never gather than FIFO size */
1740 if (link_pos <= fifo_size)
1743 azx_dev->insufficient = 0;
1746 if (link_pos <= fifo_size)
1747 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1749 mini_pos = link_pos - fifo_size;
1751 /* Find nearest previous boudary */
1752 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1753 mod_link_pos = link_pos % azx_dev->period_bytes;
1754 if (mod_link_pos >= fifo_size)
1755 bound_pos = link_pos - mod_link_pos;
1756 else if (mod_dma_pos >= mod_mini_pos)
1757 bound_pos = mini_pos - mod_mini_pos;
1759 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1760 if (bound_pos >= azx_dev->bufsize)
1764 /* Calculate real DMA position we want */
1765 return bound_pos + mod_dma_pos;
1768 static unsigned int azx_get_position(struct azx *chip,
1769 struct azx_dev *azx_dev)
1773 if (chip->via_dmapos_patch)
1774 pos = azx_via_get_position(chip, azx_dev);
1775 else if (chip->position_fix == POS_FIX_POSBUF ||
1776 chip->position_fix == POS_FIX_AUTO) {
1777 /* use the position buffer */
1778 pos = le32_to_cpu(*azx_dev->posbuf);
1781 pos = azx_sd_readl(azx_dev, SD_LPIB);
1783 if (pos >= azx_dev->bufsize)
1788 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1790 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1791 struct azx *chip = apcm->chip;
1792 struct azx_dev *azx_dev = get_azx_dev(substream);
1793 return bytes_to_frames(substream->runtime,
1794 azx_get_position(chip, azx_dev));
1798 * Check whether the current DMA position is acceptable for updating
1799 * periods. Returns non-zero if it's OK.
1801 * Many HD-audio controllers appear pretty inaccurate about
1802 * the update-IRQ timing. The IRQ is issued before actually the
1803 * data is processed. So, we need to process it afterwords in a
1806 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1810 if (azx_dev->start_flag &&
1811 time_before_eq(jiffies, azx_dev->start_jiffies))
1812 return -1; /* bogus (too early) interrupt */
1813 azx_dev->start_flag = 0;
1815 pos = azx_get_position(chip, azx_dev);
1816 if (chip->position_fix == POS_FIX_AUTO) {
1819 "hda-intel: Invalid position buffer, "
1820 "using LPIB read method instead.\n");
1821 chip->position_fix = POS_FIX_LPIB;
1822 pos = azx_get_position(chip, azx_dev);
1824 chip->position_fix = POS_FIX_POSBUF;
1827 if (!bdl_pos_adj[chip->dev_index])
1828 return 1; /* no delayed ack */
1829 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1830 return 0; /* NG - it's below the period boundary */
1831 return 1; /* OK, it's fine */
1835 * The work for pending PCM period updates.
1837 static void azx_irq_pending_work(struct work_struct *work)
1839 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1842 if (!chip->irq_pending_warned) {
1844 "hda-intel: IRQ timing workaround is activated "
1845 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1846 chip->card->number);
1847 chip->irq_pending_warned = 1;
1852 spin_lock_irq(&chip->reg_lock);
1853 for (i = 0; i < chip->num_streams; i++) {
1854 struct azx_dev *azx_dev = &chip->azx_dev[i];
1855 if (!azx_dev->irq_pending ||
1856 !azx_dev->substream ||
1859 if (azx_position_ok(chip, azx_dev)) {
1860 azx_dev->irq_pending = 0;
1861 spin_unlock(&chip->reg_lock);
1862 snd_pcm_period_elapsed(azx_dev->substream);
1863 spin_lock(&chip->reg_lock);
1867 spin_unlock_irq(&chip->reg_lock);
1874 /* clear irq_pending flags and assure no on-going workq */
1875 static void azx_clear_irq_pending(struct azx *chip)
1879 spin_lock_irq(&chip->reg_lock);
1880 for (i = 0; i < chip->num_streams; i++)
1881 chip->azx_dev[i].irq_pending = 0;
1882 spin_unlock_irq(&chip->reg_lock);
1885 static struct snd_pcm_ops azx_pcm_ops = {
1886 .open = azx_pcm_open,
1887 .close = azx_pcm_close,
1888 .ioctl = snd_pcm_lib_ioctl,
1889 .hw_params = azx_pcm_hw_params,
1890 .hw_free = azx_pcm_hw_free,
1891 .prepare = azx_pcm_prepare,
1892 .trigger = azx_pcm_trigger,
1893 .pointer = azx_pcm_pointer,
1894 .page = snd_pcm_sgbuf_ops_page,
1897 static void azx_pcm_free(struct snd_pcm *pcm)
1899 struct azx_pcm *apcm = pcm->private_data;
1901 apcm->chip->pcm[pcm->device] = NULL;
1907 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1908 struct hda_pcm *cpcm)
1910 struct azx *chip = bus->private_data;
1911 struct snd_pcm *pcm;
1912 struct azx_pcm *apcm;
1913 int pcm_dev = cpcm->device;
1916 if (pcm_dev >= AZX_MAX_PCMS) {
1917 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1921 if (chip->pcm[pcm_dev]) {
1922 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1925 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1926 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1927 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1931 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1932 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1936 apcm->codec = codec;
1937 pcm->private_data = apcm;
1938 pcm->private_free = azx_pcm_free;
1939 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1940 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1941 chip->pcm[pcm_dev] = pcm;
1943 for (s = 0; s < 2; s++) {
1944 apcm->hinfo[s] = &cpcm->stream[s];
1945 if (cpcm->stream[s].substreams)
1946 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1948 /* buffer pre-allocation */
1949 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1950 snd_dma_pci_data(chip->pci),
1951 1024 * 64, 32 * 1024 * 1024);
1956 * mixer creation - all stuff is implemented in hda module
1958 static int __devinit azx_mixer_create(struct azx *chip)
1960 return snd_hda_build_controls(chip->bus);
1965 * initialize SD streams
1967 static int __devinit azx_init_stream(struct azx *chip)
1971 /* initialize each stream (aka device)
1972 * assign the starting bdl address to each stream (device)
1975 for (i = 0; i < chip->num_streams; i++) {
1976 struct azx_dev *azx_dev = &chip->azx_dev[i];
1977 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1978 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1979 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1980 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1981 azx_dev->sd_int_sta_mask = 1 << i;
1982 /* stream tag: must be non-zero and unique */
1984 azx_dev->stream_tag = i + 1;
1990 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1992 if (request_irq(chip->pci->irq, azx_interrupt,
1993 chip->msi ? 0 : IRQF_SHARED,
1994 "HDA Intel", chip)) {
1995 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1996 "disabling device\n", chip->pci->irq);
1998 snd_card_disconnect(chip->card);
2001 chip->irq = chip->pci->irq;
2002 pci_intx(chip->pci, !chip->msi);
2007 static void azx_stop_chip(struct azx *chip)
2009 if (!chip->initialized)
2012 /* disable interrupts */
2013 azx_int_disable(chip);
2014 azx_int_clear(chip);
2016 /* disable CORB/RIRB */
2017 azx_free_cmd_io(chip);
2019 /* disable position buffer */
2020 azx_writel(chip, DPLBASE, 0);
2021 azx_writel(chip, DPUBASE, 0);
2023 chip->initialized = 0;
2026 #ifdef CONFIG_SND_HDA_POWER_SAVE
2027 /* power-up/down the controller */
2028 static void azx_power_notify(struct hda_bus *bus)
2030 struct azx *chip = bus->private_data;
2031 struct hda_codec *c;
2034 list_for_each_entry(c, &bus->codec_list, list) {
2041 azx_init_chip(chip);
2042 else if (chip->running && power_save_controller)
2043 azx_stop_chip(chip);
2045 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2052 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2054 struct hda_codec *codec;
2056 list_for_each_entry(codec, &bus->codec_list, list) {
2057 if (snd_hda_codec_needs_resume(codec))
2063 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2065 struct snd_card *card = pci_get_drvdata(pci);
2066 struct azx *chip = card->private_data;
2069 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2070 azx_clear_irq_pending(chip);
2071 for (i = 0; i < AZX_MAX_PCMS; i++)
2072 snd_pcm_suspend_all(chip->pcm[i]);
2073 if (chip->initialized)
2074 snd_hda_suspend(chip->bus);
2075 azx_stop_chip(chip);
2076 if (chip->irq >= 0) {
2077 free_irq(chip->irq, chip);
2081 pci_disable_msi(chip->pci);
2082 pci_disable_device(pci);
2083 pci_save_state(pci);
2084 pci_set_power_state(pci, pci_choose_state(pci, state));
2088 static int azx_resume(struct pci_dev *pci)
2090 struct snd_card *card = pci_get_drvdata(pci);
2091 struct azx *chip = card->private_data;
2093 pci_set_power_state(pci, PCI_D0);
2094 pci_restore_state(pci);
2095 if (pci_enable_device(pci) < 0) {
2096 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2097 "disabling device\n");
2098 snd_card_disconnect(card);
2101 pci_set_master(pci);
2103 if (pci_enable_msi(pci) < 0)
2105 if (azx_acquire_irq(chip, 1) < 0)
2109 if (snd_hda_codecs_inuse(chip->bus))
2110 azx_init_chip(chip);
2112 snd_hda_resume(chip->bus);
2113 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2116 #endif /* CONFIG_PM */
2120 * reboot notifier for hang-up problem at power-down
2122 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2124 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2125 azx_stop_chip(chip);
2129 static void azx_notifier_register(struct azx *chip)
2131 chip->reboot_notifier.notifier_call = azx_halt;
2132 register_reboot_notifier(&chip->reboot_notifier);
2135 static void azx_notifier_unregister(struct azx *chip)
2137 if (chip->reboot_notifier.notifier_call)
2138 unregister_reboot_notifier(&chip->reboot_notifier);
2144 static int azx_free(struct azx *chip)
2148 azx_notifier_unregister(chip);
2150 if (chip->initialized) {
2151 azx_clear_irq_pending(chip);
2152 for (i = 0; i < chip->num_streams; i++)
2153 azx_stream_stop(chip, &chip->azx_dev[i]);
2154 azx_stop_chip(chip);
2158 free_irq(chip->irq, (void*)chip);
2160 pci_disable_msi(chip->pci);
2161 if (chip->remap_addr)
2162 iounmap(chip->remap_addr);
2164 if (chip->azx_dev) {
2165 for (i = 0; i < chip->num_streams; i++)
2166 if (chip->azx_dev[i].bdl.area)
2167 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2170 snd_dma_free_pages(&chip->rb);
2171 if (chip->posbuf.area)
2172 snd_dma_free_pages(&chip->posbuf);
2173 pci_release_regions(chip->pci);
2174 pci_disable_device(chip->pci);
2175 kfree(chip->azx_dev);
2181 static int azx_dev_free(struct snd_device *device)
2183 return azx_free(device->device_data);
2187 * white/black-listing for position_fix
2189 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2190 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2191 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2192 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2196 static int __devinit check_position_fix(struct azx *chip, int fix)
2198 const struct snd_pci_quirk *q;
2202 case POS_FIX_POSBUF:
2206 /* Check VIA/ATI HD Audio Controller exist */
2207 switch (chip->driver_type) {
2208 case AZX_DRIVER_VIA:
2209 case AZX_DRIVER_ATI:
2210 chip->via_dmapos_patch = 1;
2211 /* Use link position directly, avoid any transfer problem. */
2212 return POS_FIX_LPIB;
2214 chip->via_dmapos_patch = 0;
2216 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2219 "hda_intel: position_fix set to %d "
2220 "for device %04x:%04x\n",
2221 q->value, q->subvendor, q->subdevice);
2224 return POS_FIX_AUTO;
2228 * black-lists for probe_mask
2230 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2231 /* Thinkpad often breaks the controller communication when accessing
2232 * to the non-working (or non-existing) modem codec slot.
2234 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2235 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2236 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2238 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2239 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2240 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2241 /* forced codec slots */
2242 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2243 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2247 #define AZX_FORCE_CODEC_MASK 0x100
2249 static void __devinit check_probe_mask(struct azx *chip, int dev)
2251 const struct snd_pci_quirk *q;
2253 chip->codec_probe_mask = probe_mask[dev];
2254 if (chip->codec_probe_mask == -1) {
2255 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2258 "hda_intel: probe_mask set to 0x%x "
2259 "for device %04x:%04x\n",
2260 q->value, q->subvendor, q->subdevice);
2261 chip->codec_probe_mask = q->value;
2265 /* check forced option */
2266 if (chip->codec_probe_mask != -1 &&
2267 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2268 chip->codec_mask = chip->codec_probe_mask & 0xff;
2269 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2278 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2279 int dev, int driver_type,
2284 unsigned short gcap;
2285 static struct snd_device_ops ops = {
2286 .dev_free = azx_dev_free,
2291 err = pci_enable_device(pci);
2295 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2297 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2298 pci_disable_device(pci);
2302 spin_lock_init(&chip->reg_lock);
2303 mutex_init(&chip->open_mutex);
2307 chip->driver_type = driver_type;
2308 chip->msi = enable_msi;
2309 chip->dev_index = dev;
2310 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2312 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2313 check_probe_mask(chip, dev);
2315 chip->single_cmd = single_cmd;
2317 if (bdl_pos_adj[dev] < 0) {
2318 switch (chip->driver_type) {
2319 case AZX_DRIVER_ICH:
2320 bdl_pos_adj[dev] = 1;
2323 bdl_pos_adj[dev] = 32;
2328 #if BITS_PER_LONG != 64
2329 /* Fix up base address on ULI M5461 */
2330 if (chip->driver_type == AZX_DRIVER_ULI) {
2332 pci_read_config_word(pci, 0x40, &tmp3);
2333 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2334 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2338 err = pci_request_regions(pci, "ICH HD audio");
2341 pci_disable_device(pci);
2345 chip->addr = pci_resource_start(pci, 0);
2346 chip->remap_addr = pci_ioremap_bar(pci, 0);
2347 if (chip->remap_addr == NULL) {
2348 snd_printk(KERN_ERR SFX "ioremap error\n");
2354 if (pci_enable_msi(pci) < 0)
2357 if (azx_acquire_irq(chip, 0) < 0) {
2362 pci_set_master(pci);
2363 synchronize_irq(chip->irq);
2365 gcap = azx_readw(chip, GCAP);
2366 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2368 /* disable SB600 64bit support for safety */
2369 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2370 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2371 struct pci_dev *p_smbus;
2372 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2373 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2376 if (p_smbus->revision < 0x30)
2377 gcap &= ~ICH6_GCAP_64OK;
2378 pci_dev_put(p_smbus);
2382 /* allow 64bit DMA address if supported by H/W */
2383 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2384 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2386 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2387 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2390 /* read number of streams from GCAP register instead of using
2393 chip->capture_streams = (gcap >> 8) & 0x0f;
2394 chip->playback_streams = (gcap >> 12) & 0x0f;
2395 if (!chip->playback_streams && !chip->capture_streams) {
2396 /* gcap didn't give any info, switching to old method */
2398 switch (chip->driver_type) {
2399 case AZX_DRIVER_ULI:
2400 chip->playback_streams = ULI_NUM_PLAYBACK;
2401 chip->capture_streams = ULI_NUM_CAPTURE;
2403 case AZX_DRIVER_ATIHDMI:
2404 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2405 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2407 case AZX_DRIVER_GENERIC:
2409 chip->playback_streams = ICH6_NUM_PLAYBACK;
2410 chip->capture_streams = ICH6_NUM_CAPTURE;
2414 chip->capture_index_offset = 0;
2415 chip->playback_index_offset = chip->capture_streams;
2416 chip->num_streams = chip->playback_streams + chip->capture_streams;
2417 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2419 if (!chip->azx_dev) {
2420 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2424 for (i = 0; i < chip->num_streams; i++) {
2425 /* allocate memory for the BDL for each stream */
2426 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2427 snd_dma_pci_data(chip->pci),
2428 BDL_SIZE, &chip->azx_dev[i].bdl);
2430 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2434 /* allocate memory for the position buffer */
2435 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2436 snd_dma_pci_data(chip->pci),
2437 chip->num_streams * 8, &chip->posbuf);
2439 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2442 /* allocate CORB/RIRB */
2443 err = azx_alloc_cmd_io(chip);
2447 /* initialize streams */
2448 azx_init_stream(chip);
2450 /* initialize chip */
2452 azx_init_chip(chip);
2454 /* codec detection */
2455 if (!chip->codec_mask) {
2456 snd_printk(KERN_ERR SFX "no codecs found!\n");
2461 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2463 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2467 strcpy(card->driver, "HDA-Intel");
2468 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2469 sizeof(card->shortname));
2470 snprintf(card->longname, sizeof(card->longname),
2471 "%s at 0x%lx irq %i",
2472 card->shortname, chip->addr, chip->irq);
2482 static void power_down_all_codecs(struct azx *chip)
2484 #ifdef CONFIG_SND_HDA_POWER_SAVE
2485 /* The codecs were powered up in snd_hda_codec_new().
2486 * Now all initialization done, so turn them down if possible
2488 struct hda_codec *codec;
2489 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2490 snd_hda_power_down(codec);
2495 static int __devinit azx_probe(struct pci_dev *pci,
2496 const struct pci_device_id *pci_id)
2499 struct snd_card *card;
2503 if (dev >= SNDRV_CARDS)
2510 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2512 snd_printk(KERN_ERR SFX "Error creating card!\n");
2516 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2519 card->private_data = chip;
2521 /* create codec instances */
2522 err = azx_codec_create(chip, model[dev], probe_only[dev]);
2526 /* create PCM streams */
2527 err = snd_hda_build_pcms(chip->bus);
2531 /* create mixer controls */
2532 err = azx_mixer_create(chip);
2536 snd_card_set_dev(card, &pci->dev);
2538 err = snd_card_register(card);
2542 pci_set_drvdata(pci, card);
2544 power_down_all_codecs(chip);
2545 azx_notifier_register(chip);
2550 snd_card_free(card);
2554 static void __devexit azx_remove(struct pci_dev *pci)
2556 snd_card_free(pci_get_drvdata(pci));
2557 pci_set_drvdata(pci, NULL);
2561 static struct pci_device_id azx_ids[] = {
2563 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2564 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2565 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2566 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2567 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2568 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2569 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2570 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2571 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2573 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2575 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2576 /* ATI SB 450/600 */
2577 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2578 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2580 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2581 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2582 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2583 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2584 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2585 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2586 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2587 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2588 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2589 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2590 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2591 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2592 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2593 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2594 /* VIA VT8251/VT8237A */
2595 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2597 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2599 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2601 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2602 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2603 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2604 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2605 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2606 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2607 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2608 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2609 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2610 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2611 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2612 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2613 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2614 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2615 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2616 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2617 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2618 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2619 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2620 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2621 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2622 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2624 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2625 /* Creative X-Fi (CA0110-IBG) */
2626 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2627 /* the following entry conflicts with snd-ctxfi driver,
2628 * as ctxfi driver mutates from HD-audio to native mode with
2629 * a special command sequence.
2631 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2632 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2633 .class_mask = 0xffffff,
2634 .driver_data = AZX_DRIVER_GENERIC },
2636 /* this entry seems still valid -- i.e. without emu20kx chip */
2637 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2639 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2640 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2641 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2642 .class_mask = 0xffffff,
2643 .driver_data = AZX_DRIVER_GENERIC },
2646 MODULE_DEVICE_TABLE(pci, azx_ids);
2648 /* pci_driver definition */
2649 static struct pci_driver driver = {
2650 .name = "HDA Intel",
2651 .id_table = azx_ids,
2653 .remove = __devexit_p(azx_remove),
2655 .suspend = azx_suspend,
2656 .resume = azx_resume,
2660 static int __init alsa_card_azx_init(void)
2662 return pci_register_driver(&driver);
2665 static void __exit alsa_card_azx_exit(void)
2667 pci_unregister_driver(&driver);
2670 module_init(alsa_card_azx_init)
2671 module_exit(alsa_card_azx_exit)