2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
40 #include <plat/sram.h>
41 #include <plat/clock.h>
43 #include <video/omapdss.h>
46 #include "dss_features.h"
50 #define DISPC_SZ_REGS SZ_4K
52 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
59 #define DISPC_MAX_NR_ISRS 8
61 #define TABLE_SIZE (256 * 4)
63 struct omap_dispc_isr_data {
85 enum omap_burst_size {
91 #define REG_GET(idx, start, end) \
92 FLD_GET(dispc_read_reg(idx), start, end)
94 #define REG_FLD_MOD(idx, val, start, end) \
95 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
97 struct dispc_irq_stats {
98 unsigned long last_reset;
104 struct platform_device *pdev;
112 u32 fifo_size[MAX_DSS_OVERLAYS];
116 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
118 struct work_struct error_work;
122 bool fc_isr_registered;
123 struct completion *fc_complete[4];
126 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
128 /* palette/gamma table */
130 dma_addr_t table_phys;
132 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
133 spinlock_t irq_stats_lock;
134 struct dispc_irq_stats irq_stats;
138 enum omap_color_component {
139 /* used for all color formats for OMAP3 and earlier
140 * and for RGB and Y color component on OMAP4
142 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
143 /* used for UV component for
144 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
145 * color formats on OMAP4
147 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150 static void _omap_dispc_set_irqs(void);
152 static inline void dispc_write_reg(const u16 idx, u32 val)
154 __raw_writel(val, dispc.base + idx);
157 static inline u32 dispc_read_reg(const u16 idx)
159 return __raw_readl(dispc.base + idx);
162 static int dispc_get_ctx_loss_count(void)
164 struct device *dev = &dispc.pdev->dev;
165 struct omap_display_platform_data *pdata = dev->platform_data;
166 struct omap_dss_board_info *board_data = pdata->board_data;
169 if (!board_data->get_context_loss_count)
172 cnt = board_data->get_context_loss_count(dev);
174 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
180 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
182 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
184 static void dispc_save_context(void)
188 DSSDBG("dispc_save_context\n");
194 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
195 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
197 if (dss_has_feature(FEAT_MGR_LCD2)) {
202 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
203 SR(DEFAULT_COLOR(i));
206 if (i == OMAP_DSS_CHANNEL_DIGIT)
217 if (dss_has_feature(FEAT_CPR)) {
224 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
229 SR(OVL_ATTRIBUTES(i));
230 SR(OVL_FIFO_THRESHOLD(i));
232 SR(OVL_PIXEL_INC(i));
233 if (dss_has_feature(FEAT_PRELOAD))
235 if (i == OMAP_DSS_GFX) {
236 SR(OVL_WINDOW_SKIP(i));
241 SR(OVL_PICTURE_SIZE(i));
245 for (j = 0; j < 8; j++)
246 SR(OVL_FIR_COEF_H(i, j));
248 for (j = 0; j < 8; j++)
249 SR(OVL_FIR_COEF_HV(i, j));
251 for (j = 0; j < 5; j++)
252 SR(OVL_CONV_COEF(i, j));
254 if (dss_has_feature(FEAT_FIR_COEF_V)) {
255 for (j = 0; j < 8; j++)
256 SR(OVL_FIR_COEF_V(i, j));
259 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
266 for (j = 0; j < 8; j++)
267 SR(OVL_FIR_COEF_H2(i, j));
269 for (j = 0; j < 8; j++)
270 SR(OVL_FIR_COEF_HV2(i, j));
272 for (j = 0; j < 8; j++)
273 SR(OVL_FIR_COEF_V2(i, j));
275 if (dss_has_feature(FEAT_ATTR2))
276 SR(OVL_ATTRIBUTES2(i));
279 if (dss_has_feature(FEAT_CORE_CLK_DIV))
282 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
283 dispc.ctx_valid = true;
285 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
288 static void dispc_restore_context(void)
292 DSSDBG("dispc_restore_context\n");
294 if (!dispc.ctx_valid)
297 ctx = dispc_get_ctx_loss_count();
299 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
302 DSSDBG("ctx_loss_count: saved %d, current %d\n",
303 dispc.ctx_loss_cnt, ctx);
309 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
310 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
312 if (dss_has_feature(FEAT_MGR_LCD2))
315 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
316 RR(DEFAULT_COLOR(i));
319 if (i == OMAP_DSS_CHANNEL_DIGIT)
330 if (dss_has_feature(FEAT_CPR)) {
337 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
342 RR(OVL_ATTRIBUTES(i));
343 RR(OVL_FIFO_THRESHOLD(i));
345 RR(OVL_PIXEL_INC(i));
346 if (dss_has_feature(FEAT_PRELOAD))
348 if (i == OMAP_DSS_GFX) {
349 RR(OVL_WINDOW_SKIP(i));
354 RR(OVL_PICTURE_SIZE(i));
358 for (j = 0; j < 8; j++)
359 RR(OVL_FIR_COEF_H(i, j));
361 for (j = 0; j < 8; j++)
362 RR(OVL_FIR_COEF_HV(i, j));
364 for (j = 0; j < 5; j++)
365 RR(OVL_CONV_COEF(i, j));
367 if (dss_has_feature(FEAT_FIR_COEF_V)) {
368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_V(i, j));
372 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
379 for (j = 0; j < 8; j++)
380 RR(OVL_FIR_COEF_H2(i, j));
382 for (j = 0; j < 8; j++)
383 RR(OVL_FIR_COEF_HV2(i, j));
385 for (j = 0; j < 8; j++)
386 RR(OVL_FIR_COEF_V2(i, j));
388 if (dss_has_feature(FEAT_ATTR2))
389 RR(OVL_ATTRIBUTES2(i));
392 if (dss_has_feature(FEAT_CORE_CLK_DIV))
395 /* enable last, because LCD & DIGIT enable are here */
397 if (dss_has_feature(FEAT_MGR_LCD2))
399 /* clear spurious SYNC_LOST_DIGIT interrupts */
400 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
403 * enable last so IRQs won't trigger before
404 * the context is fully restored
408 DSSDBG("context restored\n");
414 int dispc_runtime_get(void)
418 DSSDBG("dispc_runtime_get\n");
420 r = pm_runtime_get_sync(&dispc.pdev->dev);
422 return r < 0 ? r : 0;
424 EXPORT_SYMBOL(dispc_runtime_get);
426 void dispc_runtime_put(void)
430 DSSDBG("dispc_runtime_put\n");
432 r = pm_runtime_put_sync(&dispc.pdev->dev);
435 EXPORT_SYMBOL(dispc_runtime_put);
437 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
439 if (channel == OMAP_DSS_CHANNEL_LCD ||
440 channel == OMAP_DSS_CHANNEL_LCD2)
446 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
448 struct omap_overlay_manager *mgr =
449 omap_dss_get_overlay_manager(channel);
451 return mgr ? mgr->device : NULL;
454 bool dispc_mgr_go_busy(enum omap_channel channel)
458 if (dispc_mgr_is_lcd(channel))
461 bit = 6; /* GODIGIT */
463 if (channel == OMAP_DSS_CHANNEL_LCD2)
464 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
466 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
469 void dispc_mgr_go(enum omap_channel channel)
472 bool enable_bit, go_bit;
474 if (dispc_mgr_is_lcd(channel))
475 bit = 0; /* LCDENABLE */
477 bit = 1; /* DIGITALENABLE */
479 /* if the channel is not enabled, we don't need GO */
480 if (channel == OMAP_DSS_CHANNEL_LCD2)
481 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
483 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
488 if (dispc_mgr_is_lcd(channel))
491 bit = 6; /* GODIGIT */
493 if (channel == OMAP_DSS_CHANNEL_LCD2)
494 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
496 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
499 #if 0 /* pandora hack */
500 DSSERR("GO bit not down for channel %d\n", channel);
505 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
506 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
508 if (channel == OMAP_DSS_CHANNEL_LCD2)
509 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
511 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
514 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
516 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
519 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
521 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
524 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
526 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
529 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
531 BUG_ON(plane == OMAP_DSS_GFX);
533 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
536 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
539 BUG_ON(plane == OMAP_DSS_GFX);
541 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
544 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
546 BUG_ON(plane == OMAP_DSS_GFX);
548 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
551 /* Coefficients for horizontal up-sampling */
552 static struct dispc_h_coef coef_hup[8] = {
554 { -1, 13, 124, -8, 0 },
555 { -2, 30, 112, -11, -1 },
556 { -5, 51, 95, -11, -2 },
557 { 0, -9, 73, 73, -9 },
558 { -2, -11, 95, 51, -5 },
559 { -1, -11, 112, 30, -2 },
560 { 0, -8, 124, 13, -1 },
563 /* Coefficients for vertical up-sampling */
564 static struct dispc_v_coef coef_vup_3tap[8] = {
567 { 0, 12, 111, 5, 0 },
571 { 0, 5, 111, 12, 0 },
575 static struct dispc_v_coef coef_vup_5tap[8] = {
577 { -1, 13, 124, -8, 0 },
578 { -2, 30, 112, -11, -1 },
579 { -5, 51, 95, -11, -2 },
580 { 0, -9, 73, 73, -9 },
581 { -2, -11, 95, 51, -5 },
582 { -1, -11, 112, 30, -2 },
583 { 0, -8, 124, 13, -1 },
586 /* Coefficients for horizontal down-sampling */
587 static struct dispc_h_coef coef_hdown[8] = {
588 { 0, 36, 56, 36, 0 },
589 { 4, 40, 55, 31, -2 },
590 { 8, 44, 54, 27, -5 },
591 { 12, 48, 53, 22, -7 },
592 { -9, 17, 52, 51, 17 },
593 { -7, 22, 53, 48, 12 },
594 { -5, 27, 54, 44, 8 },
595 { -2, 31, 55, 40, 4 },
598 /* Coefficients for vertical down-sampling */
599 static struct dispc_v_coef coef_vdown_3tap[8] = {
600 { 0, 36, 56, 36, 0 },
601 { 0, 40, 57, 31, 0 },
602 { 0, 45, 56, 27, 0 },
603 { 0, 50, 55, 23, 0 },
604 { 0, 18, 55, 55, 0 },
605 { 0, 23, 55, 50, 0 },
606 { 0, 27, 56, 45, 0 },
607 { 0, 31, 57, 40, 0 },
610 static struct dispc_v_coef coef_vdown_5tap[8] = {
611 { 0, 36, 56, 36, 0 },
612 { 4, 40, 55, 31, -2 },
613 { 8, 44, 54, 27, -5 },
614 { 12, 48, 53, 22, -7 },
615 { -9, 17, 52, 51, 17 },
616 { -7, 22, 53, 48, 12 },
617 { -5, 27, 54, 44, 8 },
618 { -2, 31, 55, 40, 4 },
621 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
622 int vscaleup, int five_taps,
623 enum omap_color_component color_comp)
625 const struct dispc_h_coef *h_coef;
626 const struct dispc_v_coef *v_coef;
635 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
637 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
639 for (i = 0; i < 8; i++) {
642 h = FLD_VAL(h_coef[i].hc0, 7, 0)
643 | FLD_VAL(h_coef[i].hc1, 15, 8)
644 | FLD_VAL(h_coef[i].hc2, 23, 16)
645 | FLD_VAL(h_coef[i].hc3, 31, 24);
646 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
647 | FLD_VAL(v_coef[i].vc0, 15, 8)
648 | FLD_VAL(v_coef[i].vc1, 23, 16)
649 | FLD_VAL(v_coef[i].vc2, 31, 24);
651 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
652 dispc_ovl_write_firh_reg(plane, i, h);
653 dispc_ovl_write_firhv_reg(plane, i, hv);
655 dispc_ovl_write_firh2_reg(plane, i, h);
656 dispc_ovl_write_firhv2_reg(plane, i, hv);
662 for (i = 0; i < 8; i++) {
664 v = FLD_VAL(v_coef[i].vc00, 7, 0)
665 | FLD_VAL(v_coef[i].vc22, 15, 8);
666 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
667 dispc_ovl_write_firv_reg(plane, i, v);
669 dispc_ovl_write_firv2_reg(plane, i, v);
674 static struct dispc_h_coef *dispc_get_scale_coef_table(enum omap_plane plane,
675 enum omap_filter filter)
678 case OMAP_DSS_FILTER_UP_H:
680 case OMAP_DSS_FILTER_UP_V3:
681 /* XXX: relying on fact that h and v tables have same layout */
682 return (void *)coef_vup_3tap;
683 case OMAP_DSS_FILTER_UP_V5:
684 return (void *)coef_vup_5tap;
685 case OMAP_DSS_FILTER_DOWN_H:
687 case OMAP_DSS_FILTER_DOWN_V3:
688 return (void *)coef_vdown_3tap;
689 case OMAP_DSS_FILTER_DOWN_V5:
690 return (void *)coef_vdown_5tap;
696 void dispc_get_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
697 int phase, int *vals)
699 const struct dispc_h_coef *table;
701 if (phase < 0 || phase >= 8)
704 table = dispc_get_scale_coef_table(plane, filter);
709 vals[0] = table->hc4;
710 vals[1] = table->hc3;
711 vals[2] = table->hc2;
712 vals[3] = table->hc1;
713 vals[4] = table->hc0;
716 void dispc_set_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
717 int phase, const int *vals)
719 struct dispc_h_coef *table;
721 if (phase < 0 || phase >= 8)
724 table = dispc_get_scale_coef_table(plane, filter);
729 table->hc4 = vals[0];
730 table->hc3 = vals[1];
731 table->hc2 = vals[2];
732 table->hc1 = vals[3];
733 table->hc0 = vals[4];
736 static void _dispc_setup_color_conv_coef(void)
739 const struct color_conv_coef {
740 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
743 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
746 const struct color_conv_coef *ct;
748 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
752 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
753 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
754 CVAL(ct->rcr, ct->ry));
755 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
756 CVAL(ct->gy, ct->rcb));
757 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
758 CVAL(ct->gcb, ct->gcr));
759 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
760 CVAL(ct->bcr, ct->by));
761 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
764 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
772 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
774 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
777 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
779 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
782 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
784 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
787 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
789 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
792 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
794 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
796 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
799 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
801 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
803 if (plane == OMAP_DSS_GFX)
804 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
806 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
809 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
813 BUG_ON(plane == OMAP_DSS_GFX);
815 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
817 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
820 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
822 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
824 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
827 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
830 static void dispc_ovl_enable_zorder_planes(void)
834 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
837 for (i = 0; i < dss_feat_get_num_ovls(); i++)
838 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
841 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
843 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
845 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
848 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
851 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
853 static const unsigned shifts[] = { 0, 8, 16, 24, };
855 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
857 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
860 shift = shifts[plane];
861 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
864 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
866 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
869 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
871 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
874 static void dispc_ovl_set_color_mode(enum omap_plane plane,
875 enum omap_color_mode color_mode)
878 if (plane != OMAP_DSS_GFX) {
879 switch (color_mode) {
880 case OMAP_DSS_COLOR_NV12:
882 case OMAP_DSS_COLOR_RGB12U:
884 case OMAP_DSS_COLOR_RGBA16:
886 case OMAP_DSS_COLOR_RGBX16:
888 case OMAP_DSS_COLOR_ARGB16:
890 case OMAP_DSS_COLOR_RGB16:
892 case OMAP_DSS_COLOR_ARGB16_1555:
894 case OMAP_DSS_COLOR_RGB24U:
896 case OMAP_DSS_COLOR_RGB24P:
898 case OMAP_DSS_COLOR_YUV2:
900 case OMAP_DSS_COLOR_UYVY:
902 case OMAP_DSS_COLOR_ARGB32:
904 case OMAP_DSS_COLOR_RGBA32:
906 case OMAP_DSS_COLOR_RGBX32:
908 case OMAP_DSS_COLOR_XRGB16_1555:
914 switch (color_mode) {
915 case OMAP_DSS_COLOR_CLUT1:
917 case OMAP_DSS_COLOR_CLUT2:
919 case OMAP_DSS_COLOR_CLUT4:
921 case OMAP_DSS_COLOR_CLUT8:
923 case OMAP_DSS_COLOR_RGB12U:
925 case OMAP_DSS_COLOR_ARGB16:
927 case OMAP_DSS_COLOR_RGB16:
929 case OMAP_DSS_COLOR_ARGB16_1555:
931 case OMAP_DSS_COLOR_RGB24U:
933 case OMAP_DSS_COLOR_RGB24P:
935 case OMAP_DSS_COLOR_YUV2:
937 case OMAP_DSS_COLOR_UYVY:
939 case OMAP_DSS_COLOR_ARGB32:
941 case OMAP_DSS_COLOR_RGBA32:
943 case OMAP_DSS_COLOR_RGBX32:
945 case OMAP_DSS_COLOR_XRGB16_1555:
952 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
955 static void dispc_ovl_set_channel_out(enum omap_plane plane,
956 enum omap_channel channel)
960 int chan = 0, chan2 = 0;
966 case OMAP_DSS_VIDEO1:
967 case OMAP_DSS_VIDEO2:
968 case OMAP_DSS_VIDEO3:
976 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
977 if (dss_has_feature(FEAT_MGR_LCD2)) {
979 case OMAP_DSS_CHANNEL_LCD:
983 case OMAP_DSS_CHANNEL_DIGIT:
987 case OMAP_DSS_CHANNEL_LCD2:
995 val = FLD_MOD(val, chan, shift, shift);
996 val = FLD_MOD(val, chan2, 31, 30);
998 val = FLD_MOD(val, channel, shift, shift);
1000 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1003 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1004 enum omap_burst_size burst_size)
1006 static const unsigned shifts[] = { 6, 14, 14, 14, };
1009 shift = shifts[plane];
1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1013 static void dispc_configure_burst_sizes(void)
1016 const int burst_size = BURST_SIZE_X8;
1018 /* Configure burst size always to maximum size */
1019 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1020 dispc_ovl_set_burst_size(i, burst_size);
1023 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1025 unsigned unit = dss_feat_get_burst_size_unit();
1026 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1030 void dispc_enable_gamma_table(bool enable)
1033 * This is partially implemented to support only disabling of
1037 DSSWARN("Gamma table enabling for TV not yet supported");
1041 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1044 void dispc_set_gamma_table(void *table, u32 size)
1046 if (table == NULL || size == 0 || size > TABLE_SIZE) {
1047 REG_FLD_MOD(DISPC_CONFIG, 0, 3, 3);
1051 memcpy(dispc.table_virt, table, size);
1053 dispc_write_reg(DISPC_OVL_TABLE_BA(0), dispc.table_phys);
1054 dispc_set_loadmode(OMAP_DSS_LOAD_CLUT_ONCE_FRAME);
1055 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
1058 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1062 if (channel == OMAP_DSS_CHANNEL_LCD)
1064 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1065 reg = DISPC_CONFIG2;
1069 REG_FLD_MOD(reg, enable, 15, 15);
1072 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1073 struct omap_dss_cpr_coefs *coefs)
1075 u32 coef_r, coef_g, coef_b;
1077 if (!dispc_mgr_is_lcd(channel))
1080 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1081 FLD_VAL(coefs->rb, 9, 0);
1082 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1083 FLD_VAL(coefs->gb, 9, 0);
1084 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1085 FLD_VAL(coefs->bb, 9, 0);
1087 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1088 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1089 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1092 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1096 BUG_ON(plane == OMAP_DSS_GFX);
1098 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1099 val = FLD_MOD(val, enable, 9, 9);
1100 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1103 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1105 static const unsigned shifts[] = { 5, 10, 10, 10 };
1108 shift = shifts[plane];
1109 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1112 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1115 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1116 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1117 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1120 void dispc_set_digit_size(u16 width, u16 height)
1123 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1124 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1125 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1128 static void dispc_read_plane_fifo_sizes(void)
1135 unit = dss_feat_get_buffer_size_unit();
1137 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1139 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1140 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1142 dispc.fifo_size[plane] = size;
1146 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1148 return dispc.fifo_size[plane];
1151 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1154 u8 hi_start, hi_end, lo_start, lo_end;
1157 unit = dss_feat_get_buffer_size_unit();
1159 WARN_ON(low % unit != 0);
1160 WARN_ON(high % unit != 0);
1165 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1166 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1168 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1170 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1172 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1176 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1177 FLD_VAL(high, hi_start, hi_end) |
1178 FLD_VAL(low, lo_start, lo_end));
1181 void dispc_enable_fifomerge(bool enable)
1183 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1184 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1187 static void dispc_ovl_set_fir(enum omap_plane plane,
1189 enum omap_color_component color_comp)
1193 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1194 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1196 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1197 &hinc_start, &hinc_end);
1198 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1199 &vinc_start, &vinc_end);
1200 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1201 FLD_VAL(hinc, hinc_start, hinc_end);
1203 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1205 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1206 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1210 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1213 u8 hor_start, hor_end, vert_start, vert_end;
1215 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1216 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1218 val = FLD_VAL(vaccu, vert_start, vert_end) |
1219 FLD_VAL(haccu, hor_start, hor_end);
1221 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1224 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1227 u8 hor_start, hor_end, vert_start, vert_end;
1229 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1230 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1232 val = FLD_VAL(vaccu, vert_start, vert_end) |
1233 FLD_VAL(haccu, hor_start, hor_end);
1235 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1238 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1243 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1244 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1247 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1252 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1253 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1256 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1257 u16 orig_width, u16 orig_height,
1258 u16 out_width, u16 out_height,
1259 bool five_taps, u8 rotation,
1260 enum omap_color_component color_comp)
1262 int fir_hinc, fir_vinc;
1263 int hscaleup, vscaleup;
1265 hscaleup = orig_width <= out_width;
1266 vscaleup = orig_height <= out_height;
1268 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1271 fir_hinc = 1024 * orig_width / out_width;
1272 fir_vinc = 1024 * orig_height / out_height;
1274 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1277 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1278 u16 orig_width, u16 orig_height,
1279 u16 out_width, u16 out_height,
1280 bool ilace, bool five_taps,
1281 bool fieldmode, enum omap_color_mode color_mode,
1288 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1289 out_width, out_height, five_taps,
1290 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1291 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1293 /* RESIZEENABLE and VERTICALTAPS */
1294 l &= ~((0x3 << 5) | (0x1 << 21));
1295 l |= (orig_width != out_width) ? (1 << 5) : 0;
1296 l |= (orig_height != out_height) ? (1 << 6) : 0;
1297 l |= five_taps ? (1 << 21) : 0;
1299 /* VRESIZECONF and HRESIZECONF */
1300 if (dss_has_feature(FEAT_RESIZECONF)) {
1302 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1303 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1306 /* LINEBUFFERSPLIT */
1307 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1309 l |= five_taps ? (1 << 22) : 0;
1312 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1315 * field 0 = even field = bottom field
1316 * field 1 = odd field = top field
1318 if (ilace && !fieldmode) {
1320 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1321 if (accu0 >= 1024/2) {
1327 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1328 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1331 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1332 u16 orig_width, u16 orig_height,
1333 u16 out_width, u16 out_height,
1334 bool ilace, bool five_taps,
1335 bool fieldmode, enum omap_color_mode color_mode,
1338 int scale_x = out_width != orig_width;
1339 int scale_y = out_height != orig_height;
1341 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1343 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1344 color_mode != OMAP_DSS_COLOR_UYVY &&
1345 color_mode != OMAP_DSS_COLOR_NV12)) {
1346 /* reset chroma resampling for RGB formats */
1347 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1350 switch (color_mode) {
1351 case OMAP_DSS_COLOR_NV12:
1352 /* UV is subsampled by 2 vertically*/
1354 /* UV is subsampled by 2 horz.*/
1357 case OMAP_DSS_COLOR_YUV2:
1358 case OMAP_DSS_COLOR_UYVY:
1359 /*For YUV422 with 90/270 rotation,
1360 *we don't upsample chroma
1362 if (rotation == OMAP_DSS_ROT_0 ||
1363 rotation == OMAP_DSS_ROT_180)
1364 /* UV is subsampled by 2 hrz*/
1366 /* must use FIR for YUV422 if rotated */
1367 if (rotation != OMAP_DSS_ROT_0)
1368 scale_x = scale_y = true;
1374 if (out_width != orig_width)
1376 if (out_height != orig_height)
1379 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1380 out_width, out_height, five_taps,
1381 rotation, DISPC_COLOR_COMPONENT_UV);
1383 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1384 (scale_x || scale_y) ? 1 : 0, 8, 8);
1386 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1388 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1390 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1391 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1394 static void dispc_ovl_set_scaling(enum omap_plane plane,
1395 u16 orig_width, u16 orig_height,
1396 u16 out_width, u16 out_height,
1397 bool ilace, bool five_taps,
1398 bool fieldmode, enum omap_color_mode color_mode,
1401 BUG_ON(plane == OMAP_DSS_GFX);
1403 dispc_ovl_set_scaling_common(plane,
1404 orig_width, orig_height,
1405 out_width, out_height,
1407 fieldmode, color_mode,
1410 dispc_ovl_set_scaling_uv(plane,
1411 orig_width, orig_height,
1412 out_width, out_height,
1414 fieldmode, color_mode,
1418 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1419 bool mirroring, enum omap_color_mode color_mode)
1421 bool row_repeat = false;
1424 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1425 color_mode == OMAP_DSS_COLOR_UYVY) {
1429 case OMAP_DSS_ROT_0:
1432 case OMAP_DSS_ROT_90:
1435 case OMAP_DSS_ROT_180:
1438 case OMAP_DSS_ROT_270:
1444 case OMAP_DSS_ROT_0:
1447 case OMAP_DSS_ROT_90:
1450 case OMAP_DSS_ROT_180:
1453 case OMAP_DSS_ROT_270:
1459 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1465 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1466 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1467 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1468 row_repeat ? 1 : 0, 18, 18);
1471 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1473 switch (color_mode) {
1474 case OMAP_DSS_COLOR_CLUT1:
1476 case OMAP_DSS_COLOR_CLUT2:
1478 case OMAP_DSS_COLOR_CLUT4:
1480 case OMAP_DSS_COLOR_CLUT8:
1481 case OMAP_DSS_COLOR_NV12:
1483 case OMAP_DSS_COLOR_RGB12U:
1484 case OMAP_DSS_COLOR_RGB16:
1485 case OMAP_DSS_COLOR_ARGB16:
1486 case OMAP_DSS_COLOR_YUV2:
1487 case OMAP_DSS_COLOR_UYVY:
1488 case OMAP_DSS_COLOR_RGBA16:
1489 case OMAP_DSS_COLOR_RGBX16:
1490 case OMAP_DSS_COLOR_ARGB16_1555:
1491 case OMAP_DSS_COLOR_XRGB16_1555:
1493 case OMAP_DSS_COLOR_RGB24P:
1495 case OMAP_DSS_COLOR_RGB24U:
1496 case OMAP_DSS_COLOR_ARGB32:
1497 case OMAP_DSS_COLOR_RGBA32:
1498 case OMAP_DSS_COLOR_RGBX32:
1505 static s32 pixinc(int pixels, u8 ps)
1509 else if (pixels > 1)
1510 return 1 + (pixels - 1) * ps;
1511 else if (pixels < 0)
1512 return 1 - (-pixels + 1) * ps;
1517 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1519 u16 width, u16 height,
1520 enum omap_color_mode color_mode, bool fieldmode,
1521 unsigned int field_offset,
1522 unsigned *offset0, unsigned *offset1,
1523 s32 *row_inc, s32 *pix_inc)
1527 /* FIXME CLUT formats */
1528 switch (color_mode) {
1529 case OMAP_DSS_COLOR_CLUT1:
1530 case OMAP_DSS_COLOR_CLUT2:
1531 case OMAP_DSS_COLOR_CLUT4:
1532 case OMAP_DSS_COLOR_CLUT8:
1535 case OMAP_DSS_COLOR_YUV2:
1536 case OMAP_DSS_COLOR_UYVY:
1540 ps = color_mode_to_bpp(color_mode) / 8;
1544 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1548 * field 0 = even field = bottom field
1549 * field 1 = odd field = top field
1551 switch (rotation + mirror * 4) {
1552 case OMAP_DSS_ROT_0:
1553 case OMAP_DSS_ROT_180:
1555 * If the pixel format is YUV or UYVY divide the width
1556 * of the image by 2 for 0 and 180 degree rotation.
1558 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1559 color_mode == OMAP_DSS_COLOR_UYVY)
1561 case OMAP_DSS_ROT_90:
1562 case OMAP_DSS_ROT_270:
1565 *offset0 = field_offset * screen_width * ps;
1569 *row_inc = pixinc(1 + (screen_width - width) +
1570 (fieldmode ? screen_width : 0),
1572 *pix_inc = pixinc(1, ps);
1575 case OMAP_DSS_ROT_0 + 4:
1576 case OMAP_DSS_ROT_180 + 4:
1577 /* If the pixel format is YUV or UYVY divide the width
1578 * of the image by 2 for 0 degree and 180 degree
1580 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1581 color_mode == OMAP_DSS_COLOR_UYVY)
1583 case OMAP_DSS_ROT_90 + 4:
1584 case OMAP_DSS_ROT_270 + 4:
1587 *offset0 = field_offset * screen_width * ps;
1590 *row_inc = pixinc(1 - (screen_width + width) -
1591 (fieldmode ? screen_width : 0),
1593 *pix_inc = pixinc(1, ps);
1601 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1603 u16 width, u16 height,
1604 enum omap_color_mode color_mode, bool fieldmode,
1605 unsigned int field_offset,
1606 unsigned *offset0, unsigned *offset1,
1607 s32 *row_inc, s32 *pix_inc)
1612 /* FIXME CLUT formats */
1613 switch (color_mode) {
1614 case OMAP_DSS_COLOR_CLUT1:
1615 case OMAP_DSS_COLOR_CLUT2:
1616 case OMAP_DSS_COLOR_CLUT4:
1617 case OMAP_DSS_COLOR_CLUT8:
1621 ps = color_mode_to_bpp(color_mode) / 8;
1625 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1628 /* width & height are overlay sizes, convert to fb sizes */
1630 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1639 * field 0 = even field = bottom field
1640 * field 1 = odd field = top field
1642 switch (rotation + mirror * 4) {
1643 case OMAP_DSS_ROT_0:
1646 *offset0 = *offset1 + field_offset * screen_width * ps;
1648 *offset0 = *offset1;
1649 *row_inc = pixinc(1 + (screen_width - fbw) +
1650 (fieldmode ? screen_width : 0),
1652 *pix_inc = pixinc(1, ps);
1654 case OMAP_DSS_ROT_90:
1655 *offset1 = screen_width * (fbh - 1) * ps;
1657 *offset0 = *offset1 + field_offset * ps;
1659 *offset0 = *offset1;
1660 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1661 (fieldmode ? 1 : 0), ps);
1662 *pix_inc = pixinc(-screen_width, ps);
1664 case OMAP_DSS_ROT_180:
1665 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1667 *offset0 = *offset1 - field_offset * screen_width * ps;
1669 *offset0 = *offset1;
1670 *row_inc = pixinc(-1 -
1671 (screen_width - fbw) -
1672 (fieldmode ? screen_width : 0),
1674 *pix_inc = pixinc(-1, ps);
1676 case OMAP_DSS_ROT_270:
1677 *offset1 = (fbw - 1) * ps;
1679 *offset0 = *offset1 - field_offset * ps;
1681 *offset0 = *offset1;
1682 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1683 (fieldmode ? 1 : 0), ps);
1684 *pix_inc = pixinc(screen_width, ps);
1688 case OMAP_DSS_ROT_0 + 4:
1689 *offset1 = (fbw - 1) * ps;
1691 *offset0 = *offset1 + field_offset * screen_width * ps;
1693 *offset0 = *offset1;
1694 *row_inc = pixinc(screen_width * 2 - 1 +
1695 (fieldmode ? screen_width : 0),
1697 *pix_inc = pixinc(-1, ps);
1700 case OMAP_DSS_ROT_90 + 4:
1703 *offset0 = *offset1 + field_offset * ps;
1705 *offset0 = *offset1;
1706 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1707 (fieldmode ? 1 : 0),
1709 *pix_inc = pixinc(screen_width, ps);
1712 case OMAP_DSS_ROT_180 + 4:
1713 *offset1 = screen_width * (fbh - 1) * ps;
1715 *offset0 = *offset1 - field_offset * screen_width * ps;
1717 *offset0 = *offset1;
1718 *row_inc = pixinc(1 - screen_width * 2 -
1719 (fieldmode ? screen_width : 0),
1721 *pix_inc = pixinc(1, ps);
1724 case OMAP_DSS_ROT_270 + 4:
1725 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1727 *offset0 = *offset1 - field_offset * ps;
1729 *offset0 = *offset1;
1730 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1731 (fieldmode ? 1 : 0),
1733 *pix_inc = pixinc(-screen_width, ps);
1741 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1742 u16 height, u16 out_width, u16 out_height,
1743 enum omap_color_mode color_mode)
1746 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1748 if (height > out_height) {
1749 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1750 unsigned int ppl = dssdev->panel.timings.x_res;
1752 tmp = pclk * height * out_width;
1753 do_div(tmp, 2 * out_height * ppl);
1756 if (height > 2 * out_height) {
1757 if (ppl == out_width)
1760 tmp = pclk * (height - 2 * out_height) * out_width;
1761 do_div(tmp, 2 * out_height * (ppl - out_width));
1762 fclk = max(fclk, (u32) tmp);
1766 if (width > out_width) {
1768 do_div(tmp, out_width);
1769 fclk = max(fclk, (u32) tmp);
1771 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1778 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1779 u16 height, u16 out_width, u16 out_height)
1781 unsigned int hf, vf;
1784 * FIXME how to determine the 'A' factor
1785 * for the no downscaling case ?
1788 if (width > 3 * out_width)
1790 else if (width > 2 * out_width)
1792 else if (width > out_width)
1797 if (height > out_height)
1802 return dispc_mgr_pclk_rate(channel) * vf * hf;
1805 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1806 enum omap_channel channel, u16 width, u16 height,
1807 u16 out_width, u16 out_height,
1808 enum omap_color_mode color_mode, bool *five_taps)
1810 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1811 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1812 unsigned long fclk = 0;
1814 if (width == out_width && height == out_height)
1817 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1820 if (out_width < width / maxdownscale ||
1821 out_width > width * 8)
1824 if (out_height < height / maxdownscale ||
1825 out_height > height * 8)
1828 /* Must use 5-tap filter? */
1829 *five_taps = height > out_height * 2;
1832 fclk = calc_fclk(channel, width, height, out_width,
1835 /* Try 5-tap filter if 3-tap fclk is too high */
1836 if (cpu_is_omap34xx() && height > out_height &&
1837 fclk > dispc_fclk_rate())
1841 if (width > (2048 >> *five_taps)) {
1842 DSSERR("failed to set up scaling, fclk too low\n");
1847 fclk = calc_fclk_five_taps(channel, width, height,
1848 out_width, out_height, color_mode);
1850 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1851 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1853 if (!fclk || fclk > dispc_fclk_rate()) {
1854 DSSERR("failed to set up scaling, "
1855 "required fclk rate = %lu Hz, "
1856 "current fclk rate = %lu Hz\n",
1857 fclk, dispc_fclk_rate());
1864 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1865 bool ilace, enum omap_channel channel, bool replication,
1866 u32 fifo_low, u32 fifo_high)
1868 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1869 bool five_taps = false;
1872 unsigned offset0, offset1;
1875 u16 frame_height = oi->height;
1876 unsigned int field_offset = 0;
1878 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1879 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1880 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1881 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1882 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1883 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1888 if (ilace && oi->height == oi->out_height)
1895 oi->out_height /= 2;
1897 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1899 oi->height, oi->pos_y, oi->out_height);
1902 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1905 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1906 oi->out_width, oi->out_height, oi->color_mode,
1911 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1912 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1913 oi->color_mode == OMAP_DSS_COLOR_NV12)
1916 if (ilace && !fieldmode) {
1918 * when downscaling the bottom field may have to start several
1919 * source lines below the top field. Unfortunately ACCUI
1920 * registers will only hold the fractional part of the offset
1921 * so the integer part must be added to the base address of the
1924 if (!oi->height || oi->height == oi->out_height)
1927 field_offset = oi->height / oi->out_height / 2;
1930 /* Fields are independent but interleaved in memory. */
1934 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1935 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1936 oi->screen_width, oi->width, frame_height,
1937 oi->color_mode, fieldmode, field_offset,
1938 &offset0, &offset1, &row_inc, &pix_inc);
1940 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1941 oi->screen_width, oi->width, frame_height,
1942 oi->color_mode, fieldmode, field_offset,
1943 &offset0, &offset1, &row_inc, &pix_inc);
1945 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1946 offset0, offset1, row_inc, pix_inc);
1948 dispc_ovl_set_color_mode(plane, oi->color_mode);
1950 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1951 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1953 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1954 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1955 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1959 dispc_ovl_set_row_inc(plane, row_inc);
1960 dispc_ovl_set_pix_inc(plane, pix_inc);
1962 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1963 oi->height, oi->out_width, oi->out_height);
1965 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1967 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1969 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1970 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1971 oi->out_width, oi->out_height,
1972 ilace, five_taps, fieldmode,
1973 oi->color_mode, oi->rotation);
1974 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1975 dispc_ovl_set_vid_color_conv(plane, cconv);
1978 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1981 dispc_ovl_set_zorder(plane, oi->zorder);
1982 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1983 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1985 dispc_ovl_set_channel_out(plane, channel);
1987 dispc_ovl_enable_replication(plane, replication);
1988 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1993 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1995 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1997 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2002 static void dispc_disable_isr(void *data, u32 mask)
2004 struct completion *compl = data;
2008 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2010 if (channel == OMAP_DSS_CHANNEL_LCD2)
2011 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2013 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
2016 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2018 struct completion frame_done_completion;
2023 /* When we disable LCD output, we need to wait until frame is done.
2024 * Otherwise the DSS is still working, and turning off the clocks
2025 * prevents DSS from going to OFF mode */
2026 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2027 REG_GET(DISPC_CONTROL2, 0, 0) :
2028 REG_GET(DISPC_CONTROL, 0, 0);
2030 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2031 DISPC_IRQ_FRAMEDONE;
2033 if (!enable && is_on) {
2034 init_completion(&frame_done_completion);
2036 r = omap_dispc_register_isr(dispc_disable_isr,
2037 &frame_done_completion, irq);
2040 DSSERR("failed to register FRAMEDONE isr\n");
2043 _enable_lcd_out(channel, enable);
2045 if (!enable && is_on) {
2046 if (!wait_for_completion_timeout(&frame_done_completion,
2047 msecs_to_jiffies(100)))
2048 DSSERR("timeout waiting for FRAME DONE\n");
2050 r = omap_dispc_unregister_isr(dispc_disable_isr,
2051 &frame_done_completion, irq);
2054 DSSERR("failed to unregister FRAMEDONE isr\n");
2058 static void _enable_digit_out(bool enable)
2060 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2063 static void dispc_mgr_enable_digit_out(bool enable)
2065 struct completion frame_done_completion;
2066 enum dss_hdmi_venc_clk_source_select src;
2071 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2074 src = dss_get_hdmi_venc_clk_source();
2077 unsigned long flags;
2078 /* When we enable digit output, we'll get an extra digit
2079 * sync lost interrupt, that we need to ignore */
2080 spin_lock_irqsave(&dispc.irq_lock, flags);
2081 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2082 _omap_dispc_set_irqs();
2083 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2086 /* When we disable digit output, we need to wait until fields are done.
2087 * Otherwise the DSS is still working, and turning off the clocks
2088 * prevents DSS from going to OFF mode. And when enabling, we need to
2089 * wait for the extra sync losts */
2090 init_completion(&frame_done_completion);
2092 if (src == DSS_HDMI_M_PCLK && enable == false) {
2093 irq_mask = DISPC_IRQ_FRAMEDONETV;
2096 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2097 /* XXX I understand from TRM that we should only wait for the
2098 * current field to complete. But it seems we have to wait for
2103 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2106 DSSERR("failed to register %x isr\n", irq_mask);
2108 _enable_digit_out(enable);
2110 for (i = 0; i < num_irqs; ++i) {
2111 if (!wait_for_completion_timeout(&frame_done_completion,
2112 msecs_to_jiffies(100)))
2113 DSSERR("timeout waiting for digit out to %s\n",
2114 enable ? "start" : "stop");
2117 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2120 DSSERR("failed to unregister %x isr\n", irq_mask);
2123 unsigned long flags;
2124 spin_lock_irqsave(&dispc.irq_lock, flags);
2125 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2126 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2127 _omap_dispc_set_irqs();
2128 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2132 bool dispc_mgr_is_enabled(enum omap_channel channel)
2134 if (channel == OMAP_DSS_CHANNEL_LCD)
2135 return !!REG_GET(DISPC_CONTROL, 0, 0);
2136 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2137 return !!REG_GET(DISPC_CONTROL, 1, 1);
2138 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2139 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2144 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2146 if (dispc_mgr_is_lcd(channel))
2147 dispc_mgr_enable_lcd_out(channel, enable);
2148 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2149 dispc_mgr_enable_digit_out(enable);
2154 void dispc_lcd_enable_signal_polarity(bool act_high)
2156 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2159 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2162 void dispc_lcd_enable_signal(bool enable)
2164 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2167 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2170 void dispc_pck_free_enable(bool enable)
2172 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2175 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2178 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2180 if (channel == OMAP_DSS_CHANNEL_LCD2)
2181 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2183 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2187 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2188 enum omap_lcd_display_type type)
2193 case OMAP_DSS_LCD_DISPLAY_STN:
2197 case OMAP_DSS_LCD_DISPLAY_TFT:
2206 if (channel == OMAP_DSS_CHANNEL_LCD2)
2207 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2209 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2212 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2214 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2218 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2220 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2223 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2227 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2228 channel != OMAP_DSS_CHANNEL_LCD &&
2229 channel != OMAP_DSS_CHANNEL_LCD2);
2231 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2236 void dispc_mgr_set_trans_key(enum omap_channel ch,
2237 enum omap_dss_trans_key_type type,
2240 if (ch == OMAP_DSS_CHANNEL_LCD)
2241 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2242 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2243 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2244 else /* OMAP_DSS_CHANNEL_LCD2 */
2245 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2247 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2250 void dispc_mgr_get_trans_key(enum omap_channel ch,
2251 enum omap_dss_trans_key_type *type,
2255 if (ch == OMAP_DSS_CHANNEL_LCD)
2256 *type = REG_GET(DISPC_CONFIG, 11, 11);
2257 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2258 *type = REG_GET(DISPC_CONFIG, 13, 13);
2259 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2260 *type = REG_GET(DISPC_CONFIG2, 11, 11);
2266 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2269 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2271 if (ch == OMAP_DSS_CHANNEL_LCD)
2272 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2273 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2274 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2275 else /* OMAP_DSS_CHANNEL_LCD2 */
2276 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2279 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2281 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2284 if (ch == OMAP_DSS_CHANNEL_LCD)
2285 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2286 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2287 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2290 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2294 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2297 if (ch == OMAP_DSS_CHANNEL_LCD)
2298 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2299 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2300 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2307 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2311 if (ch == OMAP_DSS_CHANNEL_LCD)
2312 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2313 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2314 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2315 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2316 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2324 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2328 switch (data_lines) {
2346 if (channel == OMAP_DSS_CHANNEL_LCD2)
2347 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2349 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2352 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2358 case DSS_IO_PAD_MODE_RESET:
2362 case DSS_IO_PAD_MODE_RFBI:
2366 case DSS_IO_PAD_MODE_BYPASS:
2375 l = dispc_read_reg(DISPC_CONTROL);
2376 l = FLD_MOD(l, gpout0, 15, 15);
2377 l = FLD_MOD(l, gpout1, 16, 16);
2378 dispc_write_reg(DISPC_CONTROL, l);
2381 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2383 if (channel == OMAP_DSS_CHANNEL_LCD2)
2384 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2386 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2389 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2390 int vsw, int vfp, int vbp)
2392 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2393 if (hsw < 1 || hsw > 64 ||
2394 hfp < 1 || hfp > 256 ||
2395 hbp < 1 || hbp > 256 ||
2396 vsw < 1 || vsw > 64 ||
2397 vfp < 0 || vfp > 255 ||
2398 vbp < 0 || vbp > 255)
2401 if (hsw < 1 || hsw > 256 ||
2402 hfp < 1 || hfp > 4096 ||
2403 hbp < 1 || hbp > 4096 ||
2404 vsw < 1 || vsw > 256 ||
2405 vfp < 0 || vfp > 4095 ||
2406 vbp < 0 || vbp > 4095)
2413 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2415 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2416 timings->hbp, timings->vsw,
2417 timings->vfp, timings->vbp);
2420 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2421 int hfp, int hbp, int vsw, int vfp, int vbp)
2423 u32 timing_h, timing_v;
2425 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2426 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2427 FLD_VAL(hbp-1, 27, 20);
2429 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2430 FLD_VAL(vbp, 27, 20);
2432 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2433 FLD_VAL(hbp-1, 31, 20);
2435 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2436 FLD_VAL(vbp, 31, 20);
2439 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2440 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2443 /* change name to mode? */
2444 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2445 struct omap_video_timings *timings)
2447 unsigned xtot, ytot;
2448 unsigned long ht, vt;
2450 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2451 timings->hbp, timings->vsw,
2452 timings->vfp, timings->vbp))
2455 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2456 timings->hbp, timings->vsw, timings->vfp,
2459 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2461 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2462 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2464 ht = (timings->pixel_clock * 1000) / xtot;
2465 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2467 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2469 DSSDBG("pck %u\n", timings->pixel_clock);
2470 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2471 timings->hsw, timings->hfp, timings->hbp,
2472 timings->vsw, timings->vfp, timings->vbp);
2474 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2477 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2480 BUG_ON(lck_div < 1);
2481 BUG_ON(pck_div < 1);
2483 dispc_write_reg(DISPC_DIVISORo(channel),
2484 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2487 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2491 l = dispc_read_reg(DISPC_DIVISORo(channel));
2492 *lck_div = FLD_GET(l, 23, 16);
2493 *pck_div = FLD_GET(l, 7, 0);
2496 unsigned long dispc_fclk_rate(void)
2498 struct platform_device *dsidev;
2499 unsigned long r = 0;
2501 switch (dss_get_dispc_clk_source()) {
2502 case OMAP_DSS_CLK_SRC_FCK:
2503 r = clk_get_rate(dispc.dss_clk);
2505 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2506 dsidev = dsi_get_dsidev_from_id(0);
2507 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2509 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2510 dsidev = dsi_get_dsidev_from_id(1);
2511 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2520 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2522 struct platform_device *dsidev;
2527 l = dispc_read_reg(DISPC_DIVISORo(channel));
2529 lcd = FLD_GET(l, 23, 16);
2531 switch (dss_get_lcd_clk_source(channel)) {
2532 case OMAP_DSS_CLK_SRC_FCK:
2533 r = clk_get_rate(dispc.dss_clk);
2535 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2536 dsidev = dsi_get_dsidev_from_id(0);
2537 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2539 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2540 dsidev = dsi_get_dsidev_from_id(1);
2541 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2550 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2554 if (dispc_mgr_is_lcd(channel)) {
2558 l = dispc_read_reg(DISPC_DIVISORo(channel));
2560 pcd = FLD_GET(l, 7, 0);
2562 r = dispc_mgr_lclk_rate(channel);
2566 struct omap_dss_device *dssdev =
2567 dispc_mgr_get_device(channel);
2569 switch (dssdev->type) {
2570 case OMAP_DISPLAY_TYPE_VENC:
2571 return venc_get_pixel_clock();
2572 case OMAP_DISPLAY_TYPE_HDMI:
2573 return hdmi_get_pixel_clock();
2580 void dispc_dump_clocks(struct seq_file *s)
2584 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2585 enum omap_dss_clk_source lcd_clk_src;
2587 if (dispc_runtime_get())
2590 seq_printf(s, "- DISPC -\n");
2592 seq_printf(s, "dispc fclk source = %s (%s)\n",
2593 dss_get_generic_clk_source_name(dispc_clk_src),
2594 dss_feat_get_clk_source_name(dispc_clk_src));
2596 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2598 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2599 seq_printf(s, "- DISPC-CORE-CLK -\n");
2600 l = dispc_read_reg(DISPC_DIVISOR);
2601 lcd = FLD_GET(l, 23, 16);
2603 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2604 (dispc_fclk_rate()/lcd), lcd);
2606 seq_printf(s, "- LCD1 -\n");
2608 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2610 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2611 dss_get_generic_clk_source_name(lcd_clk_src),
2612 dss_feat_get_clk_source_name(lcd_clk_src));
2614 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2616 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2617 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2618 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2619 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2620 if (dss_has_feature(FEAT_MGR_LCD2)) {
2621 seq_printf(s, "- LCD2 -\n");
2623 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2625 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2626 dss_get_generic_clk_source_name(lcd_clk_src),
2627 dss_feat_get_clk_source_name(lcd_clk_src));
2629 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2631 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2632 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2633 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2634 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2637 dispc_runtime_put();
2640 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2641 void dispc_dump_irqs(struct seq_file *s)
2643 unsigned long flags;
2644 struct dispc_irq_stats stats;
2646 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2648 stats = dispc.irq_stats;
2649 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2650 dispc.irq_stats.last_reset = jiffies;
2652 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2654 seq_printf(s, "period %u ms\n",
2655 jiffies_to_msecs(jiffies - stats.last_reset));
2657 seq_printf(s, "irqs %d\n", stats.irq_count);
2659 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2665 PIS(ACBIAS_COUNT_STAT);
2667 PIS(GFX_FIFO_UNDERFLOW);
2669 PIS(PAL_GAMMA_MASK);
2671 PIS(VID1_FIFO_UNDERFLOW);
2673 PIS(VID2_FIFO_UNDERFLOW);
2675 if (dss_feat_get_num_ovls() > 3) {
2676 PIS(VID3_FIFO_UNDERFLOW);
2680 PIS(SYNC_LOST_DIGIT);
2682 if (dss_has_feature(FEAT_MGR_LCD2)) {
2685 PIS(ACBIAS_COUNT_STAT2);
2692 void dispc_dump_regs(struct seq_file *s)
2695 const char *mgr_names[] = {
2696 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2697 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2698 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2700 const char *ovl_names[] = {
2701 [OMAP_DSS_GFX] = "GFX",
2702 [OMAP_DSS_VIDEO1] = "VID1",
2703 [OMAP_DSS_VIDEO2] = "VID2",
2704 [OMAP_DSS_VIDEO3] = "VID3",
2706 const char **p_names;
2708 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2710 if (dispc_runtime_get())
2713 /* DISPC common registers */
2714 DUMPREG(DISPC_REVISION);
2715 DUMPREG(DISPC_SYSCONFIG);
2716 DUMPREG(DISPC_SYSSTATUS);
2717 DUMPREG(DISPC_IRQSTATUS);
2718 DUMPREG(DISPC_IRQENABLE);
2719 DUMPREG(DISPC_CONTROL);
2720 DUMPREG(DISPC_CONFIG);
2721 DUMPREG(DISPC_CAPABLE);
2722 DUMPREG(DISPC_LINE_STATUS);
2723 DUMPREG(DISPC_LINE_NUMBER);
2724 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2725 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2726 DUMPREG(DISPC_GLOBAL_ALPHA);
2727 if (dss_has_feature(FEAT_MGR_LCD2)) {
2728 DUMPREG(DISPC_CONTROL2);
2729 DUMPREG(DISPC_CONFIG2);
2734 #define DISPC_REG(i, name) name(i)
2735 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2736 48 - strlen(#r) - strlen(p_names[i]), " ", \
2737 dispc_read_reg(DISPC_REG(i, r)))
2739 p_names = mgr_names;
2741 /* DISPC channel specific registers */
2742 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2743 DUMPREG(i, DISPC_DEFAULT_COLOR);
2744 DUMPREG(i, DISPC_TRANS_COLOR);
2745 DUMPREG(i, DISPC_SIZE_MGR);
2747 if (i == OMAP_DSS_CHANNEL_DIGIT)
2750 DUMPREG(i, DISPC_DEFAULT_COLOR);
2751 DUMPREG(i, DISPC_TRANS_COLOR);
2752 DUMPREG(i, DISPC_TIMING_H);
2753 DUMPREG(i, DISPC_TIMING_V);
2754 DUMPREG(i, DISPC_POL_FREQ);
2755 DUMPREG(i, DISPC_DIVISORo);
2756 DUMPREG(i, DISPC_SIZE_MGR);
2758 DUMPREG(i, DISPC_DATA_CYCLE1);
2759 DUMPREG(i, DISPC_DATA_CYCLE2);
2760 DUMPREG(i, DISPC_DATA_CYCLE3);
2762 if (dss_has_feature(FEAT_CPR)) {
2763 DUMPREG(i, DISPC_CPR_COEF_R);
2764 DUMPREG(i, DISPC_CPR_COEF_G);
2765 DUMPREG(i, DISPC_CPR_COEF_B);
2769 p_names = ovl_names;
2771 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2772 DUMPREG(i, DISPC_OVL_BA0);
2773 DUMPREG(i, DISPC_OVL_BA1);
2774 DUMPREG(i, DISPC_OVL_POSITION);
2775 DUMPREG(i, DISPC_OVL_SIZE);
2776 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2777 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2778 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2779 DUMPREG(i, DISPC_OVL_ROW_INC);
2780 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2781 if (dss_has_feature(FEAT_PRELOAD))
2782 DUMPREG(i, DISPC_OVL_PRELOAD);
2784 if (i == OMAP_DSS_GFX) {
2785 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2786 DUMPREG(i, DISPC_OVL_TABLE_BA);
2790 DUMPREG(i, DISPC_OVL_FIR);
2791 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2792 DUMPREG(i, DISPC_OVL_ACCU0);
2793 DUMPREG(i, DISPC_OVL_ACCU1);
2794 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2795 DUMPREG(i, DISPC_OVL_BA0_UV);
2796 DUMPREG(i, DISPC_OVL_BA1_UV);
2797 DUMPREG(i, DISPC_OVL_FIR2);
2798 DUMPREG(i, DISPC_OVL_ACCU2_0);
2799 DUMPREG(i, DISPC_OVL_ACCU2_1);
2801 if (dss_has_feature(FEAT_ATTR2))
2802 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2803 if (dss_has_feature(FEAT_PRELOAD))
2804 DUMPREG(i, DISPC_OVL_PRELOAD);
2810 #define DISPC_REG(plane, name, i) name(plane, i)
2811 #define DUMPREG(plane, name, i) \
2812 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2813 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2814 dispc_read_reg(DISPC_REG(plane, name, i)))
2816 /* Video pipeline coefficient registers */
2818 /* start from OMAP_DSS_VIDEO1 */
2819 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2820 for (j = 0; j < 8; j++)
2821 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2823 for (j = 0; j < 8; j++)
2824 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2826 for (j = 0; j < 5; j++)
2827 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2829 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2830 for (j = 0; j < 8; j++)
2831 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2834 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2835 for (j = 0; j < 8; j++)
2836 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2838 for (j = 0; j < 8; j++)
2839 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2841 for (j = 0; j < 8; j++)
2842 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2846 dispc_runtime_put();
2852 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2853 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2858 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2859 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2861 l |= FLD_VAL(onoff, 17, 17);
2862 l |= FLD_VAL(rf, 16, 16);
2863 l |= FLD_VAL(ieo, 15, 15);
2864 l |= FLD_VAL(ipc, 14, 14);
2865 l |= FLD_VAL(ihs, 13, 13);
2866 l |= FLD_VAL(ivs, 12, 12);
2867 l |= FLD_VAL(acbi, 11, 8);
2868 l |= FLD_VAL(acb, 7, 0);
2870 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2873 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2874 enum omap_panel_config config, u8 acbi, u8 acb)
2876 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2877 (config & OMAP_DSS_LCD_RF) != 0,
2878 (config & OMAP_DSS_LCD_IEO) != 0,
2879 (config & OMAP_DSS_LCD_IPC) != 0,
2880 (config & OMAP_DSS_LCD_IHS) != 0,
2881 (config & OMAP_DSS_LCD_IVS) != 0,
2885 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2886 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2887 struct dispc_clock_info *cinfo)
2889 u16 pcd_min, pcd_max;
2890 unsigned long best_pck;
2891 u16 best_ld, cur_ld;
2892 u16 best_pd, cur_pd;
2894 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2895 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2904 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2905 unsigned long lck = fck / cur_ld;
2907 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2908 unsigned long pck = lck / cur_pd;
2909 long old_delta = abs(best_pck - req_pck);
2910 long new_delta = abs(pck - req_pck);
2912 if (best_pck == 0 || new_delta < old_delta) {
2925 if (lck / pcd_min < req_pck)
2930 cinfo->lck_div = best_ld;
2931 cinfo->pck_div = best_pd;
2932 cinfo->lck = fck / cinfo->lck_div;
2933 cinfo->pck = cinfo->lck / cinfo->pck_div;
2936 /* calculate clock rates using dividers in cinfo */
2937 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2938 struct dispc_clock_info *cinfo)
2940 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2942 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2945 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2946 cinfo->pck = cinfo->lck / cinfo->pck_div;
2951 int dispc_mgr_set_clock_div(enum omap_channel channel,
2952 struct dispc_clock_info *cinfo)
2954 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2955 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2957 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2962 int dispc_mgr_get_clock_div(enum omap_channel channel,
2963 struct dispc_clock_info *cinfo)
2967 fck = dispc_fclk_rate();
2969 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2970 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2972 cinfo->lck = fck / cinfo->lck_div;
2973 cinfo->pck = cinfo->lck / cinfo->pck_div;
2978 /* dispc.irq_lock has to be locked by the caller */
2979 static void _omap_dispc_set_irqs(void)
2984 struct omap_dispc_isr_data *isr_data;
2986 mask = dispc.irq_error_mask;
2988 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2989 isr_data = &dispc.registered_isr[i];
2991 if (isr_data->isr == NULL)
2994 mask |= isr_data->mask;
2997 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2998 /* clear the irqstatus for newly enabled irqs */
2999 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3001 dispc_write_reg(DISPC_IRQENABLE, mask);
3002 /* flush posted write */
3003 dispc_read_reg(DISPC_IRQENABLE);
3006 static int omap_dispc_register_isr_unlocked(omap_dispc_isr_t isr,
3007 void *arg, u32 mask)
3011 struct omap_dispc_isr_data *isr_data;
3016 /* check for duplicate entry */
3017 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3018 isr_data = &dispc.registered_isr[i];
3019 if (isr_data->isr == isr && isr_data->arg == arg &&
3020 isr_data->mask == mask) {
3029 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3030 isr_data = &dispc.registered_isr[i];
3032 if (isr_data->isr != NULL)
3035 isr_data->isr = isr;
3036 isr_data->arg = arg;
3037 isr_data->mask = mask;
3046 _omap_dispc_set_irqs();
3052 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3054 unsigned long flags;
3057 spin_lock_irqsave(&dispc.irq_lock, flags);
3058 ret = omap_dispc_register_isr_unlocked(isr, arg, mask);
3059 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3063 EXPORT_SYMBOL(omap_dispc_register_isr);
3065 static int omap_dispc_unregister_isr_unlocked(omap_dispc_isr_t isr,
3066 void *arg, u32 mask)
3070 struct omap_dispc_isr_data *isr_data;
3072 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3073 isr_data = &dispc.registered_isr[i];
3074 if (isr_data->isr != isr || isr_data->arg != arg ||
3075 isr_data->mask != mask)
3078 /* found the correct isr */
3080 isr_data->isr = NULL;
3081 isr_data->arg = NULL;
3089 _omap_dispc_set_irqs();
3094 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3096 unsigned long flags;
3099 spin_lock_irqsave(&dispc.irq_lock, flags);
3100 ret = omap_dispc_unregister_isr_unlocked(isr, arg, mask);
3101 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3105 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3108 static void print_irq_status(u32 status)
3110 if ((status & dispc.irq_error_mask) == 0)
3113 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3116 if (status & DISPC_IRQ_##x) \
3118 PIS(GFX_FIFO_UNDERFLOW);
3120 PIS(VID1_FIFO_UNDERFLOW);
3121 PIS(VID2_FIFO_UNDERFLOW);
3122 if (dss_feat_get_num_ovls() > 3)
3123 PIS(VID3_FIFO_UNDERFLOW);
3125 PIS(SYNC_LOST_DIGIT);
3126 if (dss_has_feature(FEAT_MGR_LCD2))
3134 /* Called from dss.c. Note that we don't touch clocks here,
3135 * but we presume they are on because we got an IRQ. However,
3136 * an irq handler may turn the clocks off, so we may not have
3137 * clock later in the function. */
3138 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3141 u32 irqstatus, irqenable;
3142 u32 handledirqs = 0;
3143 u32 unhandled_errors;
3144 struct omap_dispc_isr_data *isr_data;
3145 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3147 spin_lock(&dispc.irq_lock);
3149 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3150 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3152 /* IRQ is not for us */
3153 if (!(irqstatus & irqenable)) {
3154 spin_unlock(&dispc.irq_lock);
3158 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3159 spin_lock(&dispc.irq_stats_lock);
3160 dispc.irq_stats.irq_count++;
3161 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3162 spin_unlock(&dispc.irq_stats_lock);
3167 print_irq_status(irqstatus);
3169 /* Ack the interrupt. Do it here before clocks are possibly turned
3171 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3172 /* flush posted write */
3173 dispc_read_reg(DISPC_IRQSTATUS);
3175 /* make a copy and unlock, so that isrs can unregister
3177 memcpy(registered_isr, dispc.registered_isr,
3178 sizeof(registered_isr));
3180 spin_unlock(&dispc.irq_lock);
3182 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3183 isr_data = ®istered_isr[i];
3188 if (isr_data->mask & irqstatus) {
3189 isr_data->isr(isr_data->arg, irqstatus);
3190 handledirqs |= isr_data->mask;
3194 spin_lock(&dispc.irq_lock);
3196 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3198 if (unhandled_errors) {
3199 dispc.error_irqs |= unhandled_errors;
3201 dispc.irq_error_mask &= ~unhandled_errors;
3202 _omap_dispc_set_irqs();
3204 schedule_work(&dispc.error_work);
3207 spin_unlock(&dispc.irq_lock);
3212 static void dispc_error_worker(struct work_struct *work)
3216 unsigned long flags;
3217 static const unsigned fifo_underflow_bits[] = {
3218 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3219 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3220 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3221 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3224 static const unsigned sync_lost_bits[] = {
3225 DISPC_IRQ_SYNC_LOST,
3226 DISPC_IRQ_SYNC_LOST_DIGIT,
3227 DISPC_IRQ_SYNC_LOST2,
3230 spin_lock_irqsave(&dispc.irq_lock, flags);
3231 errors = dispc.error_irqs;
3232 dispc.error_irqs = 0;
3233 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3235 dispc_runtime_get();
3237 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3238 struct omap_overlay *ovl;
3241 ovl = omap_dss_get_overlay(i);
3242 bit = fifo_underflow_bits[i];
3245 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3247 dispc_ovl_enable(ovl->id, false);
3248 dispc_mgr_go(ovl->manager->id);
3253 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3254 struct omap_overlay_manager *mgr;
3257 mgr = omap_dss_get_overlay_manager(i);
3258 bit = sync_lost_bits[i];
3261 struct omap_dss_device *dssdev = mgr->device;
3264 DSSERR("SYNC_LOST on channel %s, restarting the output "
3265 "with video overlays disabled\n",
3268 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3269 dssdev->driver->disable(dssdev);
3271 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3272 struct omap_overlay *ovl;
3273 ovl = omap_dss_get_overlay(i);
3275 if (ovl->id != OMAP_DSS_GFX &&
3276 ovl->manager == mgr)
3277 dispc_ovl_enable(ovl->id, false);
3280 dispc_mgr_go(mgr->id);
3284 dssdev->driver->enable(dssdev);
3288 if (errors & DISPC_IRQ_OCP_ERR) {
3289 DSSERR("OCP_ERR\n");
3290 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3291 struct omap_overlay_manager *mgr;
3292 mgr = omap_dss_get_overlay_manager(i);
3293 mgr->device->driver->disable(mgr->device);
3297 spin_lock_irqsave(&dispc.irq_lock, flags);
3298 dispc.irq_error_mask |= errors;
3299 _omap_dispc_set_irqs();
3300 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3302 dispc_runtime_put();
3305 static void dispc_irq_wait_handler(void *data, u32 mask)
3307 complete((struct completion *)data);
3310 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3313 DECLARE_COMPLETION_ONSTACK(completion);
3315 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3321 timeout = wait_for_completion_timeout(&completion, timeout);
3323 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3328 if (timeout == -ERESTARTSYS)
3329 return -ERESTARTSYS;
3334 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3335 unsigned long timeout)
3338 DECLARE_COMPLETION_ONSTACK(completion);
3340 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3346 timeout = wait_for_completion_interruptible_timeout(&completion,
3349 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3354 if (timeout == -ERESTARTSYS)
3355 return -ERESTARTSYS;
3360 static void dispc_irq_vsync_on_frame_handler(void *data, u32 mask)
3362 struct completion *completion;
3367 spin_lock(&dispc.irq_lock);
3369 dispc.frame_counter++;
3371 diff = dispc.frame_counter - dispc.fc_last_use;
3372 if (diff > 5 * 60 && dispc.fc_isr_registered) {
3373 ret = omap_dispc_unregister_isr_unlocked(
3374 dispc_irq_vsync_on_frame_handler,
3375 data, DISPC_IRQ_VSYNC);
3377 dispc.fc_isr_registered = false;
3380 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3381 completion = xchg(&dispc.fc_complete[i], NULL);
3382 if (completion != NULL)
3383 complete(completion);
3386 spin_unlock(&dispc.irq_lock);
3389 int omap_dispc_wait_for_vsync_on_frame(u32 *frame,
3390 unsigned long timeout, bool force)
3392 DECLARE_COMPLETION_ONSTACK(completion);
3393 bool need_to_wait = force;
3394 unsigned long flags;
3399 spin_lock_irqsave(&dispc.irq_lock, flags);
3401 if (!dispc.fc_isr_registered) {
3402 ret = omap_dispc_register_isr_unlocked(
3403 dispc_irq_vsync_on_frame_handler,
3404 NULL, DISPC_IRQ_VSYNC);
3407 dispc.fc_isr_registered = true;
3410 need_to_wait |= *frame == dispc.frame_counter;
3412 dispc.fc_last_use = dispc.frame_counter;
3415 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3416 if (dispc.fc_complete[i] == NULL) {
3417 dispc.fc_complete[i] = &completion;
3421 if (i == ARRAY_SIZE(dispc.fc_complete)) {
3427 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3431 time = wait_for_completion_interruptible_timeout(
3432 &completion, msecs_to_jiffies(17 * 2));
3439 spin_lock(&dispc.irq_lock);
3441 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3442 if (dispc.fc_complete[i] == &completion) {
3443 dispc.fc_complete[i] = NULL;
3448 spin_unlock(&dispc.irq_lock);
3451 *frame = dispc.frame_counter;
3455 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3459 int omap_dispc_get_line_status(void)
3463 r = dispc_runtime_get();
3467 r = dispc_read_reg(DISPC_LINE_STATUS);
3469 dispc_runtime_put();
3474 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3475 void dispc_fake_vsync_irq(void)
3477 u32 irqstatus = DISPC_IRQ_VSYNC;
3480 WARN_ON(!in_interrupt());
3482 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3483 struct omap_dispc_isr_data *isr_data;
3484 isr_data = &dispc.registered_isr[i];
3489 if (isr_data->mask & irqstatus)
3490 isr_data->isr(isr_data->arg, irqstatus);
3495 static void _omap_dispc_initialize_irq(void)
3497 unsigned long flags;
3499 spin_lock_irqsave(&dispc.irq_lock, flags);
3501 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3503 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3504 if (dss_has_feature(FEAT_MGR_LCD2))
3505 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3506 if (dss_feat_get_num_ovls() > 3)
3507 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3509 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3511 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3513 _omap_dispc_set_irqs();
3515 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3518 void dispc_enable_sidle(void)
3520 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3523 void dispc_disable_sidle(void)
3525 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3528 static void _omap_dispc_initial_config(void)
3532 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3533 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3534 l = dispc_read_reg(DISPC_DIVISOR);
3535 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3536 l = FLD_MOD(l, 1, 0, 0);
3537 l = FLD_MOD(l, 1, 23, 16);
3538 dispc_write_reg(DISPC_DIVISOR, l);
3542 if (dss_has_feature(FEAT_FUNCGATED))
3543 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3545 /* L3 firewall setting: enable access to OCM RAM */
3546 /* XXX this should be somewhere in plat-omap */
3547 if (cpu_is_omap24xx())
3548 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3550 _dispc_setup_color_conv_coef();
3552 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3554 dispc_read_plane_fifo_sizes();
3556 dispc_configure_burst_sizes();
3558 dispc_ovl_enable_zorder_planes();
3561 /* DISPC HW IP initialisation */
3562 static int omap_dispchw_probe(struct platform_device *pdev)
3566 struct resource *dispc_mem;
3571 clk = clk_get(&pdev->dev, "fck");
3573 DSSERR("can't get fck\n");
3578 dispc.dss_clk = clk;
3580 spin_lock_init(&dispc.irq_lock);
3582 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3583 spin_lock_init(&dispc.irq_stats_lock);
3584 dispc.irq_stats.last_reset = jiffies;
3587 INIT_WORK(&dispc.error_work, dispc_error_worker);
3589 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3591 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3595 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3597 DSSERR("can't ioremap DISPC\n");
3601 dispc.irq = platform_get_irq(dispc.pdev, 0);
3602 if (dispc.irq < 0) {
3603 DSSERR("platform_get_irq failed\n");
3608 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3609 "OMAP DISPC", dispc.pdev);
3611 DSSERR("request_irq failed\n");
3615 pdev->dev.coherent_dma_mask = ~0;
3616 dispc.table_virt = dma_alloc_writecombine(&pdev->dev,
3617 TABLE_SIZE, &dispc.table_phys, GFP_KERNEL);
3618 if (dispc.table_virt == NULL) {
3619 dev_err(&pdev->dev, "failed to alloc palette memory\n");
3622 memset(dispc.table_virt, 0, TABLE_SIZE);
3624 pm_runtime_enable(&pdev->dev);
3626 r = dispc_runtime_get();
3628 goto err_runtime_get;
3630 _omap_dispc_initial_config();
3632 _omap_dispc_initialize_irq();
3634 rev = dispc_read_reg(DISPC_REVISION);
3635 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3636 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3638 dispc_runtime_put();
3643 pm_runtime_disable(&pdev->dev);
3644 dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3645 dispc.table_virt, dispc.table_phys);
3647 free_irq(dispc.irq, dispc.pdev);
3649 iounmap(dispc.base);
3651 clk_put(dispc.dss_clk);
3656 static int omap_dispchw_remove(struct platform_device *pdev)
3658 pm_runtime_disable(&pdev->dev);
3660 dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3661 dispc.table_virt, dispc.table_phys);
3663 clk_put(dispc.dss_clk);
3665 free_irq(dispc.irq, dispc.pdev);
3666 iounmap(dispc.base);
3670 static int dispc_runtime_suspend(struct device *dev)
3672 dispc_save_context();
3678 static int dispc_runtime_resume(struct device *dev)
3682 r = dss_runtime_get();
3686 dispc_restore_context();
3691 static const struct dev_pm_ops dispc_pm_ops = {
3692 .runtime_suspend = dispc_runtime_suspend,
3693 .runtime_resume = dispc_runtime_resume,
3696 static struct platform_driver omap_dispchw_driver = {
3697 .remove = omap_dispchw_remove,
3699 .name = "omapdss_dispc",
3700 .owner = THIS_MODULE,
3701 .pm = &dispc_pm_ops,
3705 int dispc_init_platform_driver(void)
3707 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3710 void dispc_uninit_platform_driver(void)
3712 return platform_driver_unregister(&omap_dispchw_driver);