drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <plat/sram.h>
  41 #include <plat/clock.h>
  42
  43 #include <video/omapdss.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47 #include "dispc.h"
  48
  49 /* DISPC */
  50 #define DISPC_SZ_REGS                   SZ_4K
  51
  52 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  53                                          DISPC_IRQ_OCP_ERR | \
  54                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  56                                          DISPC_IRQ_SYNC_LOST | \
  57                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  58
  59 #define DISPC_MAX_NR_ISRS               8
  60
  61 #define TABLE_SIZE (256 * 4)
  62
  63 struct omap_dispc_isr_data {
  64         omap_dispc_isr_t        isr;
  65         void                    *arg;
  66         u32                     mask;
  67 };
  68
  69 struct dispc_h_coef {
  70         s8 hc4;
  71         s8 hc3;
  72         u8 hc2;
  73         s8 hc1;
  74         s8 hc0;
  75 };
  76
  77 struct dispc_v_coef {
  78         s8 vc22;
  79         s8 vc2;
  80         u8 vc1;
  81         s8 vc0;
  82         s8 vc00;
  83 };
  84
  85 enum omap_burst_size {
  86         BURST_SIZE_X2 = 0,
  87         BURST_SIZE_X4 = 1,
  88         BURST_SIZE_X8 = 2,
  89 };
  90
  91 #define REG_GET(idx, start, end) \
  92         FLD_GET(dispc_read_reg(idx), start, end)
  93
  94 #define REG_FLD_MOD(idx, val, start, end)                               \
  95         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  96
  97 struct dispc_irq_stats {
  98         unsigned long last_reset;
  99         unsigned irq_count;
 100         unsigned irqs[32];
 101 };
 102
 103 static struct {
 104         struct platform_device *pdev;
 105         void __iomem    *base;
 106
 107         int             ctx_loss_cnt;
 108
 109         int irq;
 110         struct clk *dss_clk;
 111
 112         u32     fifo_size[MAX_DSS_OVERLAYS];
 113
 114         spinlock_t irq_lock;
 115         u32 irq_error_mask;
 116         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 117         u32 error_irqs;
 118         struct work_struct error_work;
 119
 120         u32 frame_counter;
 121         u32 fc_last_use;
 122         bool fc_isr_registered;
 123         struct completion *fc_complete[4];
 124
 125         bool            ctx_valid;
 126         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 127
 128         /* palette/gamma table */
 129         void            *table_virt;
 130         dma_addr_t      table_phys;
 131
 132 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 133         spinlock_t irq_stats_lock;
 134         struct dispc_irq_stats irq_stats;
 135 #endif
 136 } dispc;
 137
 138 enum omap_color_component {
 139         /* used for all color formats for OMAP3 and earlier
 140          * and for RGB and Y color component on OMAP4
 141          */
 142         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 143         /* used for UV component for
 144          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 145          * color formats on OMAP4
 146          */
 147         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 148 };
 149
 150 static void _omap_dispc_set_irqs(void);
 151
 152 static inline void dispc_write_reg(const u16 idx, u32 val)
 153 {
 154         __raw_writel(val, dispc.base + idx);
 155 }
 156
 157 static inline u32 dispc_read_reg(const u16 idx)
 158 {
 159         return __raw_readl(dispc.base + idx);
 160 }
 161
 162 static int dispc_get_ctx_loss_count(void)
 163 {
 164         struct device *dev = &dispc.pdev->dev;
 165         struct omap_display_platform_data *pdata = dev->platform_data;
 166         struct omap_dss_board_info *board_data = pdata->board_data;
 167         int cnt;
 168
 169         if (!board_data->get_context_loss_count)
 170                 return -ENOENT;
 171
 172         cnt = board_data->get_context_loss_count(dev);
 173
 174         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 175
 176         return cnt;
 177 }
 178
 179 #define SR(reg) \
 180         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 181 #define RR(reg) \
 182         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 183
 184 static void dispc_save_context(void)
 185 {
 186         int i, j;
 187
 188         DSSDBG("dispc_save_context\n");
 189
 190         SR(IRQENABLE);
 191         SR(CONTROL);
 192         SR(CONFIG);
 193         SR(LINE_NUMBER);
 194         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 195                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 196                 SR(GLOBAL_ALPHA);
 197         if (dss_has_feature(FEAT_MGR_LCD2)) {
 198                 SR(CONTROL2);
 199                 SR(CONFIG2);
 200         }
 201
 202         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 203                 SR(DEFAULT_COLOR(i));
 204                 SR(TRANS_COLOR(i));
 205                 SR(SIZE_MGR(i));
 206                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 207                         continue;
 208                 SR(TIMING_H(i));
 209                 SR(TIMING_V(i));
 210                 SR(POL_FREQ(i));
 211                 SR(DIVISORo(i));
 212
 213                 SR(DATA_CYCLE1(i));
 214                 SR(DATA_CYCLE2(i));
 215                 SR(DATA_CYCLE3(i));
 216
 217                 if (dss_has_feature(FEAT_CPR)) {
 218                         SR(CPR_COEF_R(i));
 219                         SR(CPR_COEF_G(i));
 220                         SR(CPR_COEF_B(i));
 221                 }
 222         }
 223
 224         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 225                 SR(OVL_BA0(i));
 226                 SR(OVL_BA1(i));
 227                 SR(OVL_POSITION(i));
 228                 SR(OVL_SIZE(i));
 229                 SR(OVL_ATTRIBUTES(i));
 230                 SR(OVL_FIFO_THRESHOLD(i));
 231                 SR(OVL_ROW_INC(i));
 232                 SR(OVL_PIXEL_INC(i));
 233                 if (dss_has_feature(FEAT_PRELOAD))
 234                         SR(OVL_PRELOAD(i));
 235                 if (i == OMAP_DSS_GFX) {
 236                         SR(OVL_WINDOW_SKIP(i));
 237                         SR(OVL_TABLE_BA(i));
 238                         continue;
 239                 }
 240                 SR(OVL_FIR(i));
 241                 SR(OVL_PICTURE_SIZE(i));
 242                 SR(OVL_ACCU0(i));
 243                 SR(OVL_ACCU1(i));
 244
 245                 for (j = 0; j < 8; j++)
 246                         SR(OVL_FIR_COEF_H(i, j));
 247
 248                 for (j = 0; j < 8; j++)
 249                         SR(OVL_FIR_COEF_HV(i, j));
 250
 251                 for (j = 0; j < 5; j++)
 252                         SR(OVL_CONV_COEF(i, j));
 253
 254                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 255                         for (j = 0; j < 8; j++)
 256                                 SR(OVL_FIR_COEF_V(i, j));
 257                 }
 258
 259                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 260                         SR(OVL_BA0_UV(i));
 261                         SR(OVL_BA1_UV(i));
 262                         SR(OVL_FIR2(i));
 263                         SR(OVL_ACCU2_0(i));
 264                         SR(OVL_ACCU2_1(i));
 265
 266                         for (j = 0; j < 8; j++)
 267                                 SR(OVL_FIR_COEF_H2(i, j));
 268
 269                         for (j = 0; j < 8; j++)
 270                                 SR(OVL_FIR_COEF_HV2(i, j));
 271
 272                         for (j = 0; j < 8; j++)
 273                                 SR(OVL_FIR_COEF_V2(i, j));
 274                 }
 275                 if (dss_has_feature(FEAT_ATTR2))
 276                         SR(OVL_ATTRIBUTES2(i));
 277         }
 278
 279         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 280                 SR(DIVISOR);
 281
 282         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 283         dispc.ctx_valid = true;
 284
 285         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 286 }
 287
 288 static void dispc_restore_context(void)
 289 {
 290         int i, j, ctx;
 291         u32 val;
 292
 293         DSSDBG("dispc_restore_context\n");
 294
 295         if (!dispc.ctx_valid)
 296                 return;
 297
 298         ctx = dispc_get_ctx_loss_count();
 299
 300         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 301                 return;
 302
 303         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 304                         dispc.ctx_loss_cnt, ctx);
 305
 306         /*RR(IRQENABLE);*/
 307         /*RR(CONTROL);*/
 308         RR(CONFIG);
 309         RR(LINE_NUMBER);
 310         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 311                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 312                 RR(GLOBAL_ALPHA);
 313         if (dss_has_feature(FEAT_MGR_LCD2))
 314                 RR(CONFIG2);
 315
 316         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 317                 RR(DEFAULT_COLOR(i));
 318                 RR(TRANS_COLOR(i));
 319                 RR(SIZE_MGR(i));
 320                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 321                         continue;
 322                 RR(TIMING_H(i));
 323                 RR(TIMING_V(i));
 324                 RR(POL_FREQ(i));
 325                 RR(DIVISORo(i));
 326
 327                 RR(DATA_CYCLE1(i));
 328                 RR(DATA_CYCLE2(i));
 329                 RR(DATA_CYCLE3(i));
 330
 331                 if (dss_has_feature(FEAT_CPR)) {
 332                         RR(CPR_COEF_R(i));
 333                         RR(CPR_COEF_G(i));
 334                         RR(CPR_COEF_B(i));
 335                 }
 336         }
 337
 338         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 339                 RR(OVL_BA0(i));
 340                 RR(OVL_BA1(i));
 341                 RR(OVL_POSITION(i));
 342                 RR(OVL_SIZE(i));
 343                 RR(OVL_ATTRIBUTES(i));
 344                 RR(OVL_FIFO_THRESHOLD(i));
 345                 RR(OVL_ROW_INC(i));
 346                 RR(OVL_PIXEL_INC(i));
 347                 if (dss_has_feature(FEAT_PRELOAD))
 348                         RR(OVL_PRELOAD(i));
 349                 if (i == OMAP_DSS_GFX) {
 350                         RR(OVL_WINDOW_SKIP(i));
 351                         RR(OVL_TABLE_BA(i));
 352                         continue;
 353                 }
 354                 RR(OVL_FIR(i));
 355                 RR(OVL_PICTURE_SIZE(i));
 356                 RR(OVL_ACCU0(i));
 357                 RR(OVL_ACCU1(i));
 358
 359                 for (j = 0; j < 8; j++)
 360                         RR(OVL_FIR_COEF_H(i, j));
 361
 362                 for (j = 0; j < 8; j++)
 363                         RR(OVL_FIR_COEF_HV(i, j));
 364
 365                 for (j = 0; j < 5; j++)
 366                         RR(OVL_CONV_COEF(i, j));
 367
 368                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 369                         for (j = 0; j < 8; j++)
 370                                 RR(OVL_FIR_COEF_V(i, j));
 371                 }
 372
 373                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 374                         RR(OVL_BA0_UV(i));
 375                         RR(OVL_BA1_UV(i));
 376                         RR(OVL_FIR2(i));
 377                         RR(OVL_ACCU2_0(i));
 378                         RR(OVL_ACCU2_1(i));
 379
 380                         for (j = 0; j < 8; j++)
 381                                 RR(OVL_FIR_COEF_H2(i, j));
 382
 383                         for (j = 0; j < 8; j++)
 384                                 RR(OVL_FIR_COEF_HV2(i, j));
 385
 386                         for (j = 0; j < 8; j++)
 387                                 RR(OVL_FIR_COEF_V2(i, j));
 388                 }
 389                 if (dss_has_feature(FEAT_ATTR2))
 390                         RR(OVL_ATTRIBUTES2(i));
 391         }
 392
 393         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 394                 RR(DIVISOR);
 395
 396         /* if gamma table is on, be sure to reload it */
 397         val = dispc_read_reg(DISPC_CONFIG);
 398         if (FLD_GET(val, 3, 3) &&
 399             FLD_GET(val, 2, 1) == OMAP_DSS_LOAD_FRAME_ONLY)
 400                 dispc_set_loadmode(OMAP_DSS_LOAD_CLUT_ONCE_FRAME);
 401
 402         /* enable last, because LCD & DIGIT enable are here */
 403         RR(CONTROL);
 404         if (dss_has_feature(FEAT_MGR_LCD2))
 405                 RR(CONTROL2);
 406         /* clear spurious SYNC_LOST_DIGIT interrupts */
 407         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 408
 409         /*
 410          * enable last so IRQs won't trigger before
 411          * the context is fully restored
 412          */
 413         RR(IRQENABLE);
 414
 415         /* flush posted write */
 416         dispc_read_reg(DISPC_IRQENABLE);
 417
 418         DSSDBG("context restored\n");
 419 }
 420
 421 #undef SR
 422 #undef RR
 423
 424 int dispc_runtime_get(void)
 425 {
 426         int r;
 427
 428         DSSDBG("dispc_runtime_get\n");
 429
 430         r = pm_runtime_get_sync(&dispc.pdev->dev);
 431         WARN_ON(r < 0);
 432         return r < 0 ? r : 0;
 433 }
 434 EXPORT_SYMBOL(dispc_runtime_get);
 435
 436 void dispc_runtime_put(void)
 437 {
 438         int r;
 439
 440         DSSDBG("dispc_runtime_put\n");
 441
 442         r = pm_runtime_put_sync(&dispc.pdev->dev);
 443         WARN_ON(r < 0);
 444 }
 445 EXPORT_SYMBOL(dispc_runtime_put);
 446
 447 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
 448 {
 449         if (channel == OMAP_DSS_CHANNEL_LCD ||
 450                         channel == OMAP_DSS_CHANNEL_LCD2)
 451                 return true;
 452         else
 453                 return false;
 454 }
 455
 456 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
 457 {
 458         struct omap_overlay_manager *mgr =
 459                 omap_dss_get_overlay_manager(channel);
 460
 461         return mgr ? mgr->device : NULL;
 462 }
 463
 464 bool dispc_mgr_go_busy(enum omap_channel channel)
 465 {
 466         int bit;
 467
 468         if (dispc_mgr_is_lcd(channel))
 469                 bit = 5; /* GOLCD */
 470         else
 471                 bit = 6; /* GODIGIT */
 472
 473         if (channel == OMAP_DSS_CHANNEL_LCD2)
 474                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 475         else
 476                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 477 }
 478
 479 void dispc_mgr_go(enum omap_channel channel)
 480 {
 481         int bit;
 482         bool enable_bit, go_bit;
 483
 484         if (dispc_mgr_is_lcd(channel))
 485                 bit = 0; /* LCDENABLE */
 486         else
 487                 bit = 1; /* DIGITALENABLE */
 488
 489         /* if the channel is not enabled, we don't need GO */
 490         if (channel == OMAP_DSS_CHANNEL_LCD2)
 491                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 492         else
 493                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 494
 495         if (!enable_bit)
 496                 return;
 497
 498         if (dispc_mgr_is_lcd(channel))
 499                 bit = 5; /* GOLCD */
 500         else
 501                 bit = 6; /* GODIGIT */
 502
 503         if (channel == OMAP_DSS_CHANNEL_LCD2)
 504                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 505         else
 506                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 507
 508         if (go_bit) {
 509 #if 0 /* pandora hack */
 510                 DSSERR("GO bit not down for channel %d\n", channel);
 511 #endif
 512                 return;
 513         }
 514
 515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 516                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 517
 518         if (channel == OMAP_DSS_CHANNEL_LCD2)
 519                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 520         else
 521                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 522 }
 523
 524 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 525 {
 526         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 527 }
 528
 529 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 532 }
 533
 534 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 535 {
 536         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 537 }
 538
 539 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 540 {
 541         BUG_ON(plane == OMAP_DSS_GFX);
 542
 543         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 544 }
 545
 546 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 547                 u32 value)
 548 {
 549         BUG_ON(plane == OMAP_DSS_GFX);
 550
 551         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 552 }
 553
 554 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 555 {
 556         BUG_ON(plane == OMAP_DSS_GFX);
 557
 558         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 559 }
 560
 561 /* Coefficients for horizontal up-sampling */
 562 static struct dispc_h_coef coef_hup[8] = {
 563         {  0,   0, 128,   0,  0 },
 564         { -1,  13, 124,  -8,  0 },
 565         { -2,  30, 112, -11, -1 },
 566         { -5,  51,  95, -11, -2 },
 567         {  0,  -9,  73,  73, -9 },
 568         { -2, -11,  95,  51, -5 },
 569         { -1, -11, 112,  30, -2 },
 570         {  0,  -8, 124,  13, -1 },
 571 };
 572
 573 /* Coefficients for vertical up-sampling */
 574 static struct dispc_v_coef coef_vup_3tap[8] = {
 575         { 0,  0, 128,  0, 0 },
 576         { 0,  3, 123,  2, 0 },
 577         { 0, 12, 111,  5, 0 },
 578         { 0, 32,  89,  7, 0 },
 579         { 0,  0,  64, 64, 0 },
 580         { 0,  7,  89, 32, 0 },
 581         { 0,  5, 111, 12, 0 },
 582         { 0,  2, 123,  3, 0 },
 583 };
 584
 585 static struct dispc_v_coef coef_vup_5tap[8] = {
 586         {  0,   0, 128,   0,  0 },
 587         { -1,  13, 124,  -8,  0 },
 588         { -2,  30, 112, -11, -1 },
 589         { -5,  51,  95, -11, -2 },
 590         {  0,  -9,  73,  73, -9 },
 591         { -2, -11,  95,  51, -5 },
 592         { -1, -11, 112,  30, -2 },
 593         {  0,  -8, 124,  13, -1 },
 594 };
 595
 596 /* Coefficients for horizontal down-sampling */
 597 static struct dispc_h_coef coef_hdown[8] = {
 598         {   0, 36, 56, 36,  0 },
 599         {   4, 40, 55, 31, -2 },
 600         {   8, 44, 54, 27, -5 },
 601         {  12, 48, 53, 22, -7 },
 602         {  -9, 17, 52, 51, 17 },
 603         {  -7, 22, 53, 48, 12 },
 604         {  -5, 27, 54, 44,  8 },
 605         {  -2, 31, 55, 40,  4 },
 606 };
 607
 608 /* Coefficients for vertical down-sampling */
 609 static struct dispc_v_coef coef_vdown_3tap[8] = {
 610         { 0, 36, 56, 36, 0 },
 611         { 0, 40, 57, 31, 0 },
 612         { 0, 45, 56, 27, 0 },
 613         { 0, 50, 55, 23, 0 },
 614         { 0, 18, 55, 55, 0 },
 615         { 0, 23, 55, 50, 0 },
 616         { 0, 27, 56, 45, 0 },
 617         { 0, 31, 57, 40, 0 },
 618 };
 619
 620 static struct dispc_v_coef coef_vdown_5tap[8] = {
 621         {   0, 36, 56, 36,  0 },
 622         {   4, 40, 55, 31, -2 },
 623         {   8, 44, 54, 27, -5 },
 624         {  12, 48, 53, 22, -7 },
 625         {  -9, 17, 52, 51, 17 },
 626         {  -7, 22, 53, 48, 12 },
 627         {  -5, 27, 54, 44,  8 },
 628         {  -2, 31, 55, 40,  4 },
 629 };
 630
 631 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
 632                                   int vscaleup, int five_taps,
 633                                   enum omap_color_component color_comp)
 634 {
 635         const struct dispc_h_coef *h_coef;
 636         const struct dispc_v_coef *v_coef;
 637         int i;
 638
 639         if (hscaleup)
 640                 h_coef = coef_hup;
 641         else
 642                 h_coef = coef_hdown;
 643
 644         if (vscaleup)
 645                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 646         else
 647                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 648
 649         for (i = 0; i < 8; i++) {
 650                 u32 h, hv;
 651
 652                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 653                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 654                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 655                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 656                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 657                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 658                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 659                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 660
 661                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 662                         dispc_ovl_write_firh_reg(plane, i, h);
 663                         dispc_ovl_write_firhv_reg(plane, i, hv);
 664                 } else {
 665                         dispc_ovl_write_firh2_reg(plane, i, h);
 666                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 667                 }
 668
 669         }
 670
 671         if (five_taps) {
 672                 for (i = 0; i < 8; i++) {
 673                         u32 v;
 674                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 675                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 676                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 677                                 dispc_ovl_write_firv_reg(plane, i, v);
 678                         else
 679                                 dispc_ovl_write_firv2_reg(plane, i, v);
 680                 }
 681         }
 682 }
 683
 684 static struct dispc_h_coef *dispc_get_scale_coef_table(enum omap_plane plane,
 685                 enum omap_filter filter)
 686 {
 687         switch (filter) {
 688         case OMAP_DSS_FILTER_UP_H:
 689                 return coef_hup;
 690         case OMAP_DSS_FILTER_UP_V3:
 691                 /* XXX: relying on fact that h and v tables have same layout */
 692                 return (void *)coef_vup_3tap;
 693         case OMAP_DSS_FILTER_UP_V5:
 694                 return (void *)coef_vup_5tap;
 695         case OMAP_DSS_FILTER_DOWN_H:
 696                 return coef_hdown;
 697         case OMAP_DSS_FILTER_DOWN_V3:
 698                 return (void *)coef_vdown_3tap;
 699         case OMAP_DSS_FILTER_DOWN_V5:
 700                 return (void *)coef_vdown_5tap;
 701         default:
 702                 return NULL;
 703         }
 704 }
 705
 706 void dispc_get_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
 707                 int phase, int *vals)
 708 {
 709         const struct dispc_h_coef *table;
 710
 711         if (phase < 0 || phase >= 8)
 712                 return;
 713
 714         table = dispc_get_scale_coef_table(plane, filter);
 715         if (table == NULL)
 716                 return;
 717
 718         table += phase;
 719         vals[0] = table->hc4;
 720         vals[1] = table->hc3;
 721         vals[2] = table->hc2;
 722         vals[3] = table->hc1;
 723         vals[4] = table->hc0;
 724 }
 725
 726 void dispc_set_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
 727                 int phase, const int *vals)
 728 {
 729         struct dispc_h_coef *table;
 730
 731         if (phase < 0 || phase >= 8)
 732                 return;
 733
 734         table = dispc_get_scale_coef_table(plane, filter);
 735         if (table == NULL)
 736                 return;
 737
 738         table += phase;
 739         table->hc4 = vals[0];
 740         table->hc3 = vals[1];
 741         table->hc2 = vals[2];
 742         table->hc1 = vals[3];
 743         table->hc0 = vals[4];
 744 }
 745
 746 static void _dispc_setup_color_conv_coef(void)
 747 {
 748         int i;
 749         const struct color_conv_coef {
 750                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 751                 int  full_range;
 752         }  ctbl_bt601_5 = {
 753                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 754         };
 755
 756         const struct color_conv_coef *ct;
 757
 758 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 759
 760         ct = &ctbl_bt601_5;
 761
 762         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 763                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 764                         CVAL(ct->rcr, ct->ry));
 765                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 766                         CVAL(ct->gy,  ct->rcb));
 767                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 768                         CVAL(ct->gcb, ct->gcr));
 769                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 770                         CVAL(ct->bcr, ct->by));
 771                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 772                         CVAL(0, ct->bcb));
 773
 774                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 775                         11, 11);
 776         }
 777
 778 #undef CVAL
 779 }
 780
 781
 782 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 783 {
 784         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 785 }
 786
 787 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 788 {
 789         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 790 }
 791
 792 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 793 {
 794         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 795 }
 796
 797 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 798 {
 799         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 800 }
 801
 802 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 803 {
 804         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 805
 806         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 807 }
 808
 809 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 810 {
 811         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 812
 813         if (plane == OMAP_DSS_GFX)
 814                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 815         else
 816                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 817 }
 818
 819 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 820 {
 821         u32 val;
 822
 823         BUG_ON(plane == OMAP_DSS_GFX);
 824
 825         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 826
 827         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 828 }
 829
 830 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
 831 {
 832         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 833
 834         if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 835                 return;
 836
 837         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 838 }
 839
 840 static void dispc_ovl_enable_zorder_planes(void)
 841 {
 842         int i;
 843
 844         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 845                 return;
 846
 847         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 848                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 849 }
 850
 851 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 852 {
 853         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 854
 855         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 856                 return;
 857
 858         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 859 }
 860
 861 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 862 {
 863         static const unsigned shifts[] = { 0, 8, 16, 24, };
 864         int shift;
 865         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 866
 867         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 868                 return;
 869
 870         shift = shifts[plane];
 871         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 872 }
 873
 874 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 875 {
 876         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 877 }
 878
 879 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 880 {
 881         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 882 }
 883
 884 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 885                 enum omap_color_mode color_mode)
 886 {
 887         u32 m = 0;
 888         if (plane != OMAP_DSS_GFX) {
 889                 switch (color_mode) {
 890                 case OMAP_DSS_COLOR_NV12:
 891                         m = 0x0; break;
 892                 case OMAP_DSS_COLOR_RGB12U:
 893                         m = 0x1; break;
 894                 case OMAP_DSS_COLOR_RGBA16:
 895                         m = 0x2; break;
 896                 case OMAP_DSS_COLOR_RGBX16:
 897                         m = 0x4; break;
 898                 case OMAP_DSS_COLOR_ARGB16:
 899                         m = 0x5; break;
 900                 case OMAP_DSS_COLOR_RGB16:
 901                         m = 0x6; break;
 902                 case OMAP_DSS_COLOR_ARGB16_1555:
 903                         m = 0x7; break;
 904                 case OMAP_DSS_COLOR_RGB24U:
 905                         m = 0x8; break;
 906                 case OMAP_DSS_COLOR_RGB24P:
 907                         m = 0x9; break;
 908                 case OMAP_DSS_COLOR_YUV2:
 909                         m = 0xa; break;
 910                 case OMAP_DSS_COLOR_UYVY:
 911                         m = 0xb; break;
 912                 case OMAP_DSS_COLOR_ARGB32:
 913                         m = 0xc; break;
 914                 case OMAP_DSS_COLOR_RGBA32:
 915                         m = 0xd; break;
 916                 case OMAP_DSS_COLOR_RGBX32:
 917                         m = 0xe; break;
 918                 case OMAP_DSS_COLOR_XRGB16_1555:
 919                         m = 0xf; break;
 920                 default:
 921                         BUG(); break;
 922                 }
 923         } else {
 924                 switch (color_mode) {
 925                 case OMAP_DSS_COLOR_CLUT1:
 926                         m = 0x0; break;
 927                 case OMAP_DSS_COLOR_CLUT2:
 928                         m = 0x1; break;
 929                 case OMAP_DSS_COLOR_CLUT4:
 930                         m = 0x2; break;
 931                 case OMAP_DSS_COLOR_CLUT8:
 932                         m = 0x3; break;
 933                 case OMAP_DSS_COLOR_RGB12U:
 934                         m = 0x4; break;
 935                 case OMAP_DSS_COLOR_ARGB16:
 936                         m = 0x5; break;
 937                 case OMAP_DSS_COLOR_RGB16:
 938                         m = 0x6; break;
 939                 case OMAP_DSS_COLOR_ARGB16_1555:
 940                         m = 0x7; break;
 941                 case OMAP_DSS_COLOR_RGB24U:
 942                         m = 0x8; break;
 943                 case OMAP_DSS_COLOR_RGB24P:
 944                         m = 0x9; break;
 945                 case OMAP_DSS_COLOR_YUV2:
 946                         m = 0xa; break;
 947                 case OMAP_DSS_COLOR_UYVY:
 948                         m = 0xb; break;
 949                 case OMAP_DSS_COLOR_ARGB32:
 950                         m = 0xc; break;
 951                 case OMAP_DSS_COLOR_RGBA32:
 952                         m = 0xd; break;
 953                 case OMAP_DSS_COLOR_RGBX32:
 954                         m = 0xe; break;
 955                 case OMAP_DSS_COLOR_XRGB16_1555:
 956                         m = 0xf; break;
 957                 default:
 958                         BUG(); break;
 959                 }
 960         }
 961
 962         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 963 }
 964
 965 static void dispc_ovl_set_channel_out(enum omap_plane plane,
 966                 enum omap_channel channel)
 967 {
 968         int shift;
 969         u32 val;
 970         int chan = 0, chan2 = 0;
 971
 972         switch (plane) {
 973         case OMAP_DSS_GFX:
 974                 shift = 8;
 975                 break;
 976         case OMAP_DSS_VIDEO1:
 977         case OMAP_DSS_VIDEO2:
 978         case OMAP_DSS_VIDEO3:
 979                 shift = 16;
 980                 break;
 981         default:
 982                 BUG();
 983                 return;
 984         }
 985
 986         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 987         if (dss_has_feature(FEAT_MGR_LCD2)) {
 988                 switch (channel) {
 989                 case OMAP_DSS_CHANNEL_LCD:
 990                         chan = 0;
 991                         chan2 = 0;
 992                         break;
 993                 case OMAP_DSS_CHANNEL_DIGIT:
 994                         chan = 1;
 995                         chan2 = 0;
 996                         break;
 997                 case OMAP_DSS_CHANNEL_LCD2:
 998                         chan = 0;
 999                         chan2 = 1;
1000                         break;
1001                 default:
1002                         BUG();
1003                 }
1004
1005                 val = FLD_MOD(val, chan, shift, shift);
1006                 val = FLD_MOD(val, chan2, 31, 30);
1007         } else {
1008                 val = FLD_MOD(val, channel, shift, shift);
1009         }
1010         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1011 }
1012
1013 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1014                 enum omap_burst_size burst_size)
1015 {
1016         static const unsigned shifts[] = { 6, 14, 14, 14, };
1017         int shift;
1018
1019         shift = shifts[plane];
1020         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1021 }
1022
1023 static void dispc_configure_burst_sizes(void)
1024 {
1025         int i;
1026         const int burst_size = BURST_SIZE_X8;
1027
1028         /* Configure burst size always to maximum size */
1029         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1030                 dispc_ovl_set_burst_size(i, burst_size);
1031 }
1032
1033 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1034 {
1035         unsigned unit = dss_feat_get_burst_size_unit();
1036         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1037         return unit * 8;
1038 }
1039
1040 void dispc_enable_gamma_table(bool enable)
1041 {
1042         /*
1043          * This is partially implemented to support only disabling of
1044          * the gamma table.
1045          */
1046         if (enable) {
1047                 DSSWARN("Gamma table enabling for TV not yet supported");
1048                 return;
1049         }
1050
1051         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1052 }
1053
1054 void dispc_set_gamma_table(void *table, u32 size)
1055 {
1056         if (table == NULL || size == 0 || size > TABLE_SIZE) {
1057                 REG_FLD_MOD(DISPC_CONFIG, 0, 3, 3);
1058                 return;
1059         }
1060
1061         memcpy(dispc.table_virt, table, size);
1062
1063         dispc_write_reg(DISPC_OVL_TABLE_BA(0), dispc.table_phys);
1064         dispc_set_loadmode(OMAP_DSS_LOAD_CLUT_ONCE_FRAME);
1065         REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
1066 }
1067
1068 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1069 {
1070         u16 reg;
1071
1072         if (channel == OMAP_DSS_CHANNEL_LCD)
1073                 reg = DISPC_CONFIG;
1074         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1075                 reg = DISPC_CONFIG2;
1076         else
1077                 return;
1078
1079         REG_FLD_MOD(reg, enable, 15, 15);
1080 }
1081
1082 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1083                 struct omap_dss_cpr_coefs *coefs)
1084 {
1085         u32 coef_r, coef_g, coef_b;
1086
1087         if (!dispc_mgr_is_lcd(channel))
1088                 return;
1089
1090         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1091                 FLD_VAL(coefs->rb, 9, 0);
1092         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1093                 FLD_VAL(coefs->gb, 9, 0);
1094         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1095                 FLD_VAL(coefs->bb, 9, 0);
1096
1097         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1098         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1099         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1100 }
1101
1102 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1103 {
1104         u32 val;
1105
1106         BUG_ON(plane == OMAP_DSS_GFX);
1107
1108         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1109         val = FLD_MOD(val, enable, 9, 9);
1110         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1111 }
1112
1113 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1114 {
1115         static const unsigned shifts[] = { 5, 10, 10, 10 };
1116         int shift;
1117
1118         shift = shifts[plane];
1119         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1120 }
1121
1122 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1123 {
1124         u32 val;
1125         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1126         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1127         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1128 }
1129
1130 void dispc_set_digit_size(u16 width, u16 height)
1131 {
1132         u32 val;
1133         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1134         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1135         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1136 }
1137
1138 static void dispc_read_plane_fifo_sizes(void)
1139 {
1140         u32 size;
1141         int plane;
1142         u8 start, end;
1143         u32 unit;
1144
1145         unit = dss_feat_get_buffer_size_unit();
1146
1147         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1148
1149         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1150                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1151                 size *= unit;
1152                 dispc.fifo_size[plane] = size;
1153         }
1154 }
1155
1156 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1157 {
1158         return dispc.fifo_size[plane];
1159 }
1160
1161 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1162                 u32 high)
1163 {
1164         u8 hi_start, hi_end, lo_start, lo_end;
1165         u32 unit;
1166
1167         unit = dss_feat_get_buffer_size_unit();
1168
1169         WARN_ON(low % unit != 0);
1170         WARN_ON(high % unit != 0);
1171
1172         low /= unit;
1173         high /= unit;
1174
1175         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1176         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1177
1178         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1179                         plane,
1180                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1181                                 lo_start, lo_end),
1182                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1183                                 hi_start, hi_end),
1184                         low, high);
1185
1186         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1187                         FLD_VAL(high, hi_start, hi_end) |
1188                         FLD_VAL(low, lo_start, lo_end));
1189 }
1190
1191 void dispc_enable_fifomerge(bool enable)
1192 {
1193         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1194         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1195 }
1196
1197 static void dispc_ovl_set_fir(enum omap_plane plane,
1198                                 int hinc, int vinc,
1199                                 enum omap_color_component color_comp)
1200 {
1201         u32 val;
1202
1203         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1204                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1205
1206                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1207                                         &hinc_start, &hinc_end);
1208                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1209                                         &vinc_start, &vinc_end);
1210                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1211                                 FLD_VAL(hinc, hinc_start, hinc_end);
1212
1213                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1214         } else {
1215                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1216                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1217         }
1218 }
1219
1220 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1221 {
1222         u32 val;
1223         u8 hor_start, hor_end, vert_start, vert_end;
1224
1225         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1226         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1227
1228         val = FLD_VAL(vaccu, vert_start, vert_end) |
1229                         FLD_VAL(haccu, hor_start, hor_end);
1230
1231         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1232 }
1233
1234 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1235 {
1236         u32 val;
1237         u8 hor_start, hor_end, vert_start, vert_end;
1238
1239         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1240         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1241
1242         val = FLD_VAL(vaccu, vert_start, vert_end) |
1243                         FLD_VAL(haccu, hor_start, hor_end);
1244
1245         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1246 }
1247
1248 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1249                 int vaccu)
1250 {
1251         u32 val;
1252
1253         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1254         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1255 }
1256
1257 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1258                 int vaccu)
1259 {
1260         u32 val;
1261
1262         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1263         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1264 }
1265
1266 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1267                 u16 orig_width, u16 orig_height,
1268                 u16 out_width, u16 out_height,
1269                 bool five_taps, u8 rotation,
1270                 enum omap_color_component color_comp)
1271 {
1272         int fir_hinc, fir_vinc;
1273         int hscaleup, vscaleup;
1274
1275         hscaleup = orig_width <= out_width;
1276         vscaleup = orig_height <= out_height;
1277
1278         dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1279                         color_comp);
1280
1281         fir_hinc = 1024 * orig_width / out_width;
1282         fir_vinc = 1024 * orig_height / out_height;
1283
1284         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1285 }
1286
1287 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1288                 u16 orig_width, u16 orig_height,
1289                 u16 out_width, u16 out_height,
1290                 bool ilace, bool five_taps,
1291                 bool fieldmode, enum omap_color_mode color_mode,
1292                 u8 rotation)
1293 {
1294         int accu0 = 0;
1295         int accu1 = 0;
1296         u32 l;
1297
1298         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1299                                 out_width, out_height, five_taps,
1300                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1301         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1302
1303         /* RESIZEENABLE and VERTICALTAPS */
1304         l &= ~((0x3 << 5) | (0x1 << 21));
1305         l |= (orig_width != out_width) ? (1 << 5) : 0;
1306         l |= (orig_height != out_height) ? (1 << 6) : 0;
1307         l |= five_taps ? (1 << 21) : 0;
1308
1309         /* VRESIZECONF and HRESIZECONF */
1310         if (dss_has_feature(FEAT_RESIZECONF)) {
1311                 l &= ~(0x3 << 7);
1312                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1313                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1314         }
1315
1316         /* LINEBUFFERSPLIT */
1317         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1318                 l &= ~(0x1 << 22);
1319                 l |= five_taps ? (1 << 22) : 0;
1320         }
1321
1322         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1323
1324         /*
1325          * field 0 = even field = bottom field
1326          * field 1 = odd field = top field
1327          */
1328         if (ilace && !fieldmode) {
1329                 accu1 = 0;
1330                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1331                 if (accu0 >= 1024/2) {
1332                         accu1 = 1024/2;
1333                         accu0 -= accu1;
1334                 }
1335         }
1336
1337         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1338         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1339 }
1340
1341 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1342                 u16 orig_width, u16 orig_height,
1343                 u16 out_width, u16 out_height,
1344                 bool ilace, bool five_taps,
1345                 bool fieldmode, enum omap_color_mode color_mode,
1346                 u8 rotation)
1347 {
1348         int scale_x = out_width != orig_width;
1349         int scale_y = out_height != orig_height;
1350
1351         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1352                 return;
1353         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1354                         color_mode != OMAP_DSS_COLOR_UYVY &&
1355                         color_mode != OMAP_DSS_COLOR_NV12)) {
1356                 /* reset chroma resampling for RGB formats  */
1357                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1358                 return;
1359         }
1360         switch (color_mode) {
1361         case OMAP_DSS_COLOR_NV12:
1362                 /* UV is subsampled by 2 vertically*/
1363                 orig_height >>= 1;
1364                 /* UV is subsampled by 2 horz.*/
1365                 orig_width >>= 1;
1366                 break;
1367         case OMAP_DSS_COLOR_YUV2:
1368         case OMAP_DSS_COLOR_UYVY:
1369                 /*For YUV422 with 90/270 rotation,
1370                  *we don't upsample chroma
1371                  */
1372                 if (rotation == OMAP_DSS_ROT_0 ||
1373                         rotation == OMAP_DSS_ROT_180)
1374                         /* UV is subsampled by 2 hrz*/
1375                         orig_width >>= 1;
1376                 /* must use FIR for YUV422 if rotated */
1377                 if (rotation != OMAP_DSS_ROT_0)
1378                         scale_x = scale_y = true;
1379                 break;
1380         default:
1381                 BUG();
1382         }
1383
1384         if (out_width != orig_width)
1385                 scale_x = true;
1386         if (out_height != orig_height)
1387                 scale_y = true;
1388
1389         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1390                         out_width, out_height, five_taps,
1391                                 rotation, DISPC_COLOR_COMPONENT_UV);
1392
1393         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1394                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1395         /* set H scaling */
1396         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1397         /* set V scaling */
1398         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1399
1400         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1401         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1402 }
1403
1404 static void dispc_ovl_set_scaling(enum omap_plane plane,
1405                 u16 orig_width, u16 orig_height,
1406                 u16 out_width, u16 out_height,
1407                 bool ilace, bool five_taps,
1408                 bool fieldmode, enum omap_color_mode color_mode,
1409                 u8 rotation)
1410 {
1411         BUG_ON(plane == OMAP_DSS_GFX);
1412
1413         dispc_ovl_set_scaling_common(plane,
1414                         orig_width, orig_height,
1415                         out_width, out_height,
1416                         ilace, five_taps,
1417                         fieldmode, color_mode,
1418                         rotation);
1419
1420         dispc_ovl_set_scaling_uv(plane,
1421                 orig_width, orig_height,
1422                 out_width, out_height,
1423                 ilace, five_taps,
1424                 fieldmode, color_mode,
1425                 rotation);
1426 }
1427
1428 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1429                 bool mirroring, enum omap_color_mode color_mode)
1430 {
1431         bool row_repeat = false;
1432         int vidrot = 0;
1433
1434         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1435                         color_mode == OMAP_DSS_COLOR_UYVY) {
1436
1437                 if (mirroring) {
1438                         switch (rotation) {
1439                         case OMAP_DSS_ROT_0:
1440                                 vidrot = 2;
1441                                 break;
1442                         case OMAP_DSS_ROT_90:
1443                                 vidrot = 1;
1444                                 break;
1445                         case OMAP_DSS_ROT_180:
1446                                 vidrot = 0;
1447                                 break;
1448                         case OMAP_DSS_ROT_270:
1449                                 vidrot = 3;
1450                                 break;
1451                         }
1452                 } else {
1453                         switch (rotation) {
1454                         case OMAP_DSS_ROT_0:
1455                                 vidrot = 0;
1456                                 break;
1457                         case OMAP_DSS_ROT_90:
1458                                 vidrot = 1;
1459                                 break;
1460                         case OMAP_DSS_ROT_180:
1461                                 vidrot = 2;
1462                                 break;
1463                         case OMAP_DSS_ROT_270:
1464                                 vidrot = 3;
1465                                 break;
1466                         }
1467                 }
1468
1469                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1470                         row_repeat = true;
1471                 else
1472                         row_repeat = false;
1473         }
1474
1475         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1476         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1477                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1478                         row_repeat ? 1 : 0, 18, 18);
1479 }
1480
1481 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1482 {
1483         switch (color_mode) {
1484         case OMAP_DSS_COLOR_CLUT1:
1485                 return 1;
1486         case OMAP_DSS_COLOR_CLUT2:
1487                 return 2;
1488         case OMAP_DSS_COLOR_CLUT4:
1489                 return 4;
1490         case OMAP_DSS_COLOR_CLUT8:
1491         case OMAP_DSS_COLOR_NV12:
1492                 return 8;
1493         case OMAP_DSS_COLOR_RGB12U:
1494         case OMAP_DSS_COLOR_RGB16:
1495         case OMAP_DSS_COLOR_ARGB16:
1496         case OMAP_DSS_COLOR_YUV2:
1497         case OMAP_DSS_COLOR_UYVY:
1498         case OMAP_DSS_COLOR_RGBA16:
1499         case OMAP_DSS_COLOR_RGBX16:
1500         case OMAP_DSS_COLOR_ARGB16_1555:
1501         case OMAP_DSS_COLOR_XRGB16_1555:
1502                 return 16;
1503         case OMAP_DSS_COLOR_RGB24P:
1504                 return 24;
1505         case OMAP_DSS_COLOR_RGB24U:
1506         case OMAP_DSS_COLOR_ARGB32:
1507         case OMAP_DSS_COLOR_RGBA32:
1508         case OMAP_DSS_COLOR_RGBX32:
1509                 return 32;
1510         default:
1511                 BUG();
1512         }
1513 }
1514
1515 static s32 pixinc(int pixels, u8 ps)
1516 {
1517         if (pixels == 1)
1518                 return 1;
1519         else if (pixels > 1)
1520                 return 1 + (pixels - 1) * ps;
1521         else if (pixels < 0)
1522                 return 1 - (-pixels + 1) * ps;
1523         else
1524                 BUG();
1525 }
1526
1527 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1528                 u16 screen_width,
1529                 u16 width, u16 height,
1530                 enum omap_color_mode color_mode, bool fieldmode,
1531                 unsigned int field_offset,
1532                 unsigned *offset0, unsigned *offset1,
1533                 s32 *row_inc, s32 *pix_inc)
1534 {
1535         u8 ps;
1536
1537         /* FIXME CLUT formats */
1538         switch (color_mode) {
1539         case OMAP_DSS_COLOR_CLUT1:
1540         case OMAP_DSS_COLOR_CLUT2:
1541         case OMAP_DSS_COLOR_CLUT4:
1542         case OMAP_DSS_COLOR_CLUT8:
1543                 BUG();
1544                 return;
1545         case OMAP_DSS_COLOR_YUV2:
1546         case OMAP_DSS_COLOR_UYVY:
1547                 ps = 4;
1548                 break;
1549         default:
1550                 ps = color_mode_to_bpp(color_mode) / 8;
1551                 break;
1552         }
1553
1554         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1555                         width, height);
1556
1557         /*
1558          * field 0 = even field = bottom field
1559          * field 1 = odd field = top field
1560          */
1561         switch (rotation + mirror * 4) {
1562         case OMAP_DSS_ROT_0:
1563         case OMAP_DSS_ROT_180:
1564                 /*
1565                  * If the pixel format is YUV or UYVY divide the width
1566                  * of the image by 2 for 0 and 180 degree rotation.
1567                  */
1568                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1569                         color_mode == OMAP_DSS_COLOR_UYVY)
1570                         width = width >> 1;
1571         case OMAP_DSS_ROT_90:
1572         case OMAP_DSS_ROT_270:
1573                 *offset1 = 0;
1574                 if (field_offset)
1575                         *offset0 = field_offset * screen_width * ps;
1576                 else
1577                         *offset0 = 0;
1578
1579                 *row_inc = pixinc(1 + (screen_width - width) +
1580                                 (fieldmode ? screen_width : 0),
1581                                 ps);
1582                 *pix_inc = pixinc(1, ps);
1583                 break;
1584
1585         case OMAP_DSS_ROT_0 + 4:
1586         case OMAP_DSS_ROT_180 + 4:
1587                 /* If the pixel format is YUV or UYVY divide the width
1588                  * of the image by 2  for 0 degree and 180 degree
1589                  */
1590                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1591                         color_mode == OMAP_DSS_COLOR_UYVY)
1592                         width = width >> 1;
1593         case OMAP_DSS_ROT_90 + 4:
1594         case OMAP_DSS_ROT_270 + 4:
1595                 *offset1 = 0;
1596                 if (field_offset)
1597                         *offset0 = field_offset * screen_width * ps;
1598                 else
1599                         *offset0 = 0;
1600                 *row_inc = pixinc(1 - (screen_width + width) -
1601                                 (fieldmode ? screen_width : 0),
1602                                 ps);
1603                 *pix_inc = pixinc(1, ps);
1604                 break;
1605
1606         default:
1607                 BUG();
1608         }
1609 }
1610
1611 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1612                 u16 screen_width,
1613                 u16 width, u16 height,
1614                 enum omap_color_mode color_mode, bool fieldmode,
1615                 unsigned int field_offset,
1616                 unsigned *offset0, unsigned *offset1,
1617                 s32 *row_inc, s32 *pix_inc)
1618 {
1619         u8 ps;
1620         u16 fbw, fbh;
1621
1622         /* FIXME CLUT formats */
1623         switch (color_mode) {
1624         case OMAP_DSS_COLOR_CLUT1:
1625         case OMAP_DSS_COLOR_CLUT2:
1626         case OMAP_DSS_COLOR_CLUT4:
1627         case OMAP_DSS_COLOR_CLUT8:
1628                 BUG();
1629                 return;
1630         default:
1631                 ps = color_mode_to_bpp(color_mode) / 8;
1632                 break;
1633         }
1634
1635         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1636                         width, height);
1637
1638         /* width & height are overlay sizes, convert to fb sizes */
1639
1640         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1641                 fbw = width;
1642                 fbh = height;
1643         } else {
1644                 fbw = height;
1645                 fbh = width;
1646         }
1647
1648         /*
1649          * field 0 = even field = bottom field
1650          * field 1 = odd field = top field
1651          */
1652         switch (rotation + mirror * 4) {
1653         case OMAP_DSS_ROT_0:
1654                 *offset1 = 0;
1655                 if (field_offset)
1656                         *offset0 = *offset1 + field_offset * screen_width * ps;
1657                 else
1658                         *offset0 = *offset1;
1659                 *row_inc = pixinc(1 + (screen_width - fbw) +
1660                                 (fieldmode ? screen_width : 0),
1661                                 ps);
1662                 *pix_inc = pixinc(1, ps);
1663                 break;
1664         case OMAP_DSS_ROT_90:
1665                 *offset1 = screen_width * (fbh - 1) * ps;
1666                 if (field_offset)
1667                         *offset0 = *offset1 + field_offset * ps;
1668                 else
1669                         *offset0 = *offset1;
1670                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1671                                 (fieldmode ? 1 : 0), ps);
1672                 *pix_inc = pixinc(-screen_width, ps);
1673                 break;
1674         case OMAP_DSS_ROT_180:
1675                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1676                 if (field_offset)
1677                         *offset0 = *offset1 - field_offset * screen_width * ps;
1678                 else
1679                         *offset0 = *offset1;
1680                 *row_inc = pixinc(-1 -
1681                                 (screen_width - fbw) -
1682                                 (fieldmode ? screen_width : 0),
1683                                 ps);
1684                 *pix_inc = pixinc(-1, ps);
1685                 break;
1686         case OMAP_DSS_ROT_270:
1687                 *offset1 = (fbw - 1) * ps;
1688                 if (field_offset)
1689                         *offset0 = *offset1 - field_offset * ps;
1690                 else
1691                         *offset0 = *offset1;
1692                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1693                                 (fieldmode ? 1 : 0), ps);
1694                 *pix_inc = pixinc(screen_width, ps);
1695                 break;
1696
1697         /* mirroring */
1698         case OMAP_DSS_ROT_0 + 4:
1699                 *offset1 = (fbw - 1) * ps;
1700                 if (field_offset)
1701                         *offset0 = *offset1 + field_offset * screen_width * ps;
1702                 else
1703                         *offset0 = *offset1;
1704                 *row_inc = pixinc(screen_width * 2 - 1 +
1705                                 (fieldmode ? screen_width : 0),
1706                                 ps);
1707                 *pix_inc = pixinc(-1, ps);
1708                 break;
1709
1710         case OMAP_DSS_ROT_90 + 4:
1711                 *offset1 = 0;
1712                 if (field_offset)
1713                         *offset0 = *offset1 + field_offset * ps;
1714                 else
1715                         *offset0 = *offset1;
1716                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1717                                 (fieldmode ? 1 : 0),
1718                                 ps);
1719                 *pix_inc = pixinc(screen_width, ps);
1720                 break;
1721
1722         case OMAP_DSS_ROT_180 + 4:
1723                 *offset1 = screen_width * (fbh - 1) * ps;
1724                 if (field_offset)
1725                         *offset0 = *offset1 - field_offset * screen_width * ps;
1726                 else
1727                         *offset0 = *offset1;
1728                 *row_inc = pixinc(1 - screen_width * 2 -
1729                                 (fieldmode ? screen_width : 0),
1730                                 ps);
1731                 *pix_inc = pixinc(1, ps);
1732                 break;
1733
1734         case OMAP_DSS_ROT_270 + 4:
1735                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1736                 if (field_offset)
1737                         *offset0 = *offset1 - field_offset * ps;
1738                 else
1739                         *offset0 = *offset1;
1740                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1741                                 (fieldmode ? 1 : 0),
1742                                 ps);
1743                 *pix_inc = pixinc(-screen_width, ps);
1744                 break;
1745
1746         default:
1747                 BUG();
1748         }
1749 }
1750
1751 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1752                 u16 height, u16 out_width, u16 out_height,
1753                 enum omap_color_mode color_mode)
1754 {
1755         u32 fclk = 0;
1756         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1757
1758         if (height > out_height) {
1759                 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1760                 unsigned int ppl = dssdev->panel.timings.x_res;
1761
1762                 tmp = pclk * height * out_width;
1763                 do_div(tmp, 2 * out_height * ppl);
1764                 fclk = tmp;
1765
1766                 if (height > 2 * out_height) {
1767                         if (ppl == out_width)
1768                                 return 0;
1769
1770                         tmp = pclk * (height - 2 * out_height) * out_width;
1771                         do_div(tmp, 2 * out_height * (ppl - out_width));
1772                         fclk = max(fclk, (u32) tmp);
1773                 }
1774         }
1775
1776         if (width > out_width) {
1777                 tmp = pclk * width;
1778                 do_div(tmp, out_width);
1779                 fclk = max(fclk, (u32) tmp);
1780
1781                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1782                         fclk <<= 1;
1783         }
1784
1785         return fclk;
1786 }
1787
1788 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1789                 u16 height, u16 out_width, u16 out_height)
1790 {
1791         unsigned int hf, vf;
1792
1793         /*
1794          * FIXME how to determine the 'A' factor
1795          * for the no downscaling case ?
1796          */
1797
1798         if (width > 3 * out_width)
1799                 hf = 4;
1800         else if (width > 2 * out_width)
1801                 hf = 3;
1802         else if (width > out_width)
1803                 hf = 2;
1804         else
1805                 hf = 1;
1806
1807         if (height > out_height)
1808                 vf = 2;
1809         else
1810                 vf = 1;
1811
1812         return dispc_mgr_pclk_rate(channel) * vf * hf;
1813 }
1814
1815 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1816                 enum omap_channel channel, u16 width, u16 height,
1817                 u16 out_width, u16 out_height,
1818                 enum omap_color_mode color_mode, bool *five_taps)
1819 {
1820         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1821         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1822         unsigned long fclk = 0;
1823
1824         if (width == out_width && height == out_height)
1825                 return 0;
1826
1827         if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1828                 return -EINVAL;
1829
1830         if (out_width < width / maxdownscale ||
1831                         out_width > width * 8)
1832                 return -EINVAL;
1833
1834         if (out_height < height / maxdownscale ||
1835                         out_height > height * 8)
1836                 return -EINVAL;
1837
1838         /* Must use 5-tap filter? */
1839         *five_taps = height > out_height * 2;
1840
1841         if (!*five_taps) {
1842                 fclk = calc_fclk(channel, width, height, out_width,
1843                                 out_height);
1844
1845                 /* Try 5-tap filter if 3-tap fclk is too high */
1846                 if (cpu_is_omap34xx() && height > out_height &&
1847                                 fclk > dispc_fclk_rate())
1848                         *five_taps = true;
1849         }
1850
1851         if (width > (2048 >> *five_taps)) {
1852                 DSSERR("failed to set up scaling, fclk too low\n");
1853                 return -EINVAL;
1854         }
1855
1856         if (*five_taps)
1857                 fclk = calc_fclk_five_taps(channel, width, height,
1858                                 out_width, out_height, color_mode);
1859
1860         DSSDBG("required fclk rate = %lu Hz\n", fclk);
1861         DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1862
1863         if (!fclk || fclk > dispc_fclk_rate()) {
1864                 DSSERR("failed to set up scaling, "
1865                         "required fclk rate = %lu Hz, "
1866                         "current fclk rate = %lu Hz\n",
1867                         fclk, dispc_fclk_rate());
1868                 return -EINVAL;
1869         }
1870
1871         return 0;
1872 }
1873
1874 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1875                 bool ilace, enum omap_channel channel, bool replication,
1876                 u32 fifo_low, u32 fifo_high)
1877 {
1878         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1879         bool five_taps = false;
1880         bool fieldmode = 0;
1881         int r, cconv = 0;
1882         unsigned offset0, offset1;
1883         s32 row_inc;
1884         s32 pix_inc;
1885         u16 frame_height = oi->height;
1886         unsigned int field_offset = 0;
1887
1888         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1889                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1890                 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1891                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1892                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1893                 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1894
1895         if (oi->paddr == 0)
1896                 return -EINVAL;
1897
1898         if (ilace && oi->height == oi->out_height)
1899                 fieldmode = 1;
1900
1901         if (ilace) {
1902                 if (fieldmode)
1903                         oi->height /= 2;
1904                 oi->pos_y /= 2;
1905                 oi->out_height /= 2;
1906
1907                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1908                                 "out_height %d\n",
1909                                 oi->height, oi->pos_y, oi->out_height);
1910         }
1911
1912         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1913                 return -EINVAL;
1914
1915         r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1916                         oi->out_width, oi->out_height, oi->color_mode,
1917                         &five_taps);
1918         if (r)
1919                 return r;
1920
1921         if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1922                         oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1923                         oi->color_mode == OMAP_DSS_COLOR_NV12)
1924                 cconv = 1;
1925
1926         if (ilace && !fieldmode) {
1927                 /*
1928                  * when downscaling the bottom field may have to start several
1929                  * source lines below the top field. Unfortunately ACCUI
1930                  * registers will only hold the fractional part of the offset
1931                  * so the integer part must be added to the base address of the
1932                  * bottom field.
1933                  */
1934                 if (!oi->height || oi->height == oi->out_height)
1935                         field_offset = 0;
1936                 else
1937                         field_offset = oi->height / oi->out_height / 2;
1938         }
1939
1940         /* Fields are independent but interleaved in memory. */
1941         if (fieldmode)
1942                 field_offset = 1;
1943
1944         if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1945                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1946                                 oi->screen_width, oi->width, frame_height,
1947                                 oi->color_mode, fieldmode, field_offset,
1948                                 &offset0, &offset1, &row_inc, &pix_inc);
1949         else
1950                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1951                                 oi->screen_width, oi->width, frame_height,
1952                                 oi->color_mode, fieldmode, field_offset,
1953                                 &offset0, &offset1, &row_inc, &pix_inc);
1954
1955         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1956                         offset0, offset1, row_inc, pix_inc);
1957
1958         dispc_ovl_set_color_mode(plane, oi->color_mode);
1959
1960         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1961         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1962
1963         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1964                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1965                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1966         }
1967
1968
1969         dispc_ovl_set_row_inc(plane, row_inc);
1970         dispc_ovl_set_pix_inc(plane, pix_inc);
1971
1972         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1973                         oi->height, oi->out_width, oi->out_height);
1974
1975         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1976
1977         dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1978
1979         if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1980                 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1981                                    oi->out_width, oi->out_height,
1982                                    ilace, five_taps, fieldmode,
1983                                    oi->color_mode, oi->rotation);
1984                 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1985                 dispc_ovl_set_vid_color_conv(plane, cconv);
1986         }
1987
1988         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1989                         oi->color_mode);
1990
1991         dispc_ovl_set_zorder(plane, oi->zorder);
1992         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1993         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1994
1995         dispc_ovl_set_channel_out(plane, channel);
1996
1997         dispc_ovl_enable_replication(plane, replication);
1998         dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1999
2000         return 0;
2001 }
2002
2003 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2004 {
2005         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2006
2007         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2008
2009         return 0;
2010 }
2011
2012 static void dispc_disable_isr(void *data, u32 mask)
2013 {
2014         struct completion *compl = data;
2015         complete(compl);
2016 }
2017
2018 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2019 {
2020         if (channel == OMAP_DSS_CHANNEL_LCD2)
2021                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2022         else
2023                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
2024 }
2025
2026 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2027 {
2028         struct completion frame_done_completion;
2029         bool is_on;
2030         int r;
2031         u32 irq;
2032
2033         /* When we disable LCD output, we need to wait until frame is done.
2034          * Otherwise the DSS is still working, and turning off the clocks
2035          * prevents DSS from going to OFF mode */
2036         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2037                         REG_GET(DISPC_CONTROL2, 0, 0) :
2038                         REG_GET(DISPC_CONTROL, 0, 0);
2039
2040         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2041                         DISPC_IRQ_FRAMEDONE;
2042
2043         if (!enable && is_on) {
2044                 init_completion(&frame_done_completion);
2045
2046                 r = omap_dispc_register_isr(dispc_disable_isr,
2047                                 &frame_done_completion, irq);
2048
2049                 if (r)
2050                         DSSERR("failed to register FRAMEDONE isr\n");
2051         }
2052
2053         _enable_lcd_out(channel, enable);
2054
2055         if (!enable && is_on) {
2056                 if (!wait_for_completion_timeout(&frame_done_completion,
2057                                         msecs_to_jiffies(100)))
2058                         DSSERR("timeout waiting for FRAME DONE\n");
2059
2060                 r = omap_dispc_unregister_isr(dispc_disable_isr,
2061                                 &frame_done_completion, irq);
2062
2063                 if (r)
2064                         DSSERR("failed to unregister FRAMEDONE isr\n");
2065         }
2066 }
2067
2068 static void _enable_digit_out(bool enable)
2069 {
2070         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2071 }
2072
2073 static void dispc_mgr_enable_digit_out(bool enable)
2074 {
2075         struct completion frame_done_completion;
2076         enum dss_hdmi_venc_clk_source_select src;
2077         int r, i;
2078         u32 irq_mask;
2079         int num_irqs;
2080
2081         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2082                 return;
2083
2084         src = dss_get_hdmi_venc_clk_source();
2085
2086         if (enable) {
2087                 unsigned long flags;
2088                 /* When we enable digit output, we'll get an extra digit
2089                  * sync lost interrupt, that we need to ignore */
2090                 spin_lock_irqsave(&dispc.irq_lock, flags);
2091                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2092                 _omap_dispc_set_irqs();
2093                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2094         }
2095
2096         /* When we disable digit output, we need to wait until fields are done.
2097          * Otherwise the DSS is still working, and turning off the clocks
2098          * prevents DSS from going to OFF mode. And when enabling, we need to
2099          * wait for the extra sync losts */
2100         init_completion(&frame_done_completion);
2101
2102         if (src == DSS_HDMI_M_PCLK && enable == false) {
2103                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2104                 num_irqs = 1;
2105         } else {
2106                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2107                 /* XXX I understand from TRM that we should only wait for the
2108                  * current field to complete. But it seems we have to wait for
2109                  * both fields */
2110                 num_irqs = 2;
2111         }
2112
2113         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2114                         irq_mask);
2115         if (r)
2116                 DSSERR("failed to register %x isr\n", irq_mask);
2117
2118         _enable_digit_out(enable);
2119
2120         for (i = 0; i < num_irqs; ++i) {
2121                 if (!wait_for_completion_timeout(&frame_done_completion,
2122                                         msecs_to_jiffies(100)))
2123                         DSSERR("timeout waiting for digit out to %s\n",
2124                                         enable ? "start" : "stop");
2125         }
2126
2127         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2128                         irq_mask);
2129         if (r)
2130                 DSSERR("failed to unregister %x isr\n", irq_mask);
2131
2132         if (enable) {
2133                 unsigned long flags;
2134                 spin_lock_irqsave(&dispc.irq_lock, flags);
2135                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2136                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2137                 _omap_dispc_set_irqs();
2138                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2139         }
2140 }
2141
2142 bool dispc_mgr_is_enabled(enum omap_channel channel)
2143 {
2144         if (channel == OMAP_DSS_CHANNEL_LCD)
2145                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2146         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2147                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2148         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2149                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2150         else
2151                 BUG();
2152 }
2153
2154 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2155 {
2156         if (dispc_mgr_is_lcd(channel))
2157                 dispc_mgr_enable_lcd_out(channel, enable);
2158         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2159                 dispc_mgr_enable_digit_out(enable);
2160         else
2161                 BUG();
2162 }
2163
2164 void dispc_lcd_enable_signal_polarity(bool act_high)
2165 {
2166         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2167                 return;
2168
2169         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2170 }
2171
2172 void dispc_lcd_enable_signal(bool enable)
2173 {
2174         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2175                 return;
2176
2177         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2178 }
2179
2180 void dispc_pck_free_enable(bool enable)
2181 {
2182         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2183                 return;
2184
2185         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2186 }
2187
2188 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2189 {
2190         if (channel == OMAP_DSS_CHANNEL_LCD2)
2191                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2192         else
2193                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2194 }
2195
2196
2197 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2198                 enum omap_lcd_display_type type)
2199 {
2200         int mode;
2201
2202         switch (type) {
2203         case OMAP_DSS_LCD_DISPLAY_STN:
2204                 mode = 0;
2205                 break;
2206
2207         case OMAP_DSS_LCD_DISPLAY_TFT:
2208                 mode = 1;
2209                 break;
2210
2211         default:
2212                 BUG();
2213                 return;
2214         }
2215
2216         if (channel == OMAP_DSS_CHANNEL_LCD2)
2217                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2218         else
2219                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2220 }
2221
2222 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2223 {
2224         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2225 }
2226
2227
2228 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2229 {
2230         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2231 }
2232
2233 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2234 {
2235         u32 l;
2236
2237         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2238                 channel != OMAP_DSS_CHANNEL_LCD &&
2239                 channel != OMAP_DSS_CHANNEL_LCD2);
2240
2241         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2242
2243         return l;
2244 }
2245
2246 void dispc_mgr_set_trans_key(enum omap_channel ch,
2247                 enum omap_dss_trans_key_type type,
2248                 u32 trans_key)
2249 {
2250         if (ch == OMAP_DSS_CHANNEL_LCD)
2251                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2252         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2253                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2254         else /* OMAP_DSS_CHANNEL_LCD2 */
2255                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2256
2257         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2258 }
2259
2260 void dispc_mgr_get_trans_key(enum omap_channel ch,
2261                 enum omap_dss_trans_key_type *type,
2262                 u32 *trans_key)
2263 {
2264         if (type) {
2265                 if (ch == OMAP_DSS_CHANNEL_LCD)
2266                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2267                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2268                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2269                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2270                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2271                 else
2272                         BUG();
2273         }
2274
2275         if (trans_key)
2276                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2277 }
2278
2279 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2280 {
2281         if (ch == OMAP_DSS_CHANNEL_LCD)
2282                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2283         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2284                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2285         else /* OMAP_DSS_CHANNEL_LCD2 */
2286                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2287 }
2288
2289 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2290 {
2291         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2292                 return;
2293
2294         if (ch == OMAP_DSS_CHANNEL_LCD)
2295                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2296         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2297                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2298 }
2299
2300 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2301 {
2302         bool enabled;
2303
2304         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2305                 return false;
2306
2307         if (ch == OMAP_DSS_CHANNEL_LCD)
2308                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2309         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2310                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2311         else
2312                 BUG();
2313
2314         return enabled;
2315 }
2316
2317 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2318 {
2319         bool enabled;
2320
2321         if (ch == OMAP_DSS_CHANNEL_LCD)
2322                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2323         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2324                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2325         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2326                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2327         else
2328                 BUG();
2329
2330         return enabled;
2331 }
2332
2333
2334 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2335 {
2336         int code;
2337
2338         switch (data_lines) {
2339         case 12:
2340                 code = 0;
2341                 break;
2342         case 16:
2343                 code = 1;
2344                 break;
2345         case 18:
2346                 code = 2;
2347                 break;
2348         case 24:
2349                 code = 3;
2350                 break;
2351         default:
2352                 BUG();
2353                 return;
2354         }
2355
2356         if (channel == OMAP_DSS_CHANNEL_LCD2)
2357                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2358         else
2359                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2360 }
2361
2362 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2363 {
2364         u32 l;
2365         int gpout0, gpout1;
2366
2367         switch (mode) {
2368         case DSS_IO_PAD_MODE_RESET:
2369                 gpout0 = 0;
2370                 gpout1 = 0;
2371                 break;
2372         case DSS_IO_PAD_MODE_RFBI:
2373                 gpout0 = 1;
2374                 gpout1 = 0;
2375                 break;
2376         case DSS_IO_PAD_MODE_BYPASS:
2377                 gpout0 = 1;
2378                 gpout1 = 1;
2379                 break;
2380         default:
2381                 BUG();
2382                 return;
2383         }
2384
2385         l = dispc_read_reg(DISPC_CONTROL);
2386         l = FLD_MOD(l, gpout0, 15, 15);
2387         l = FLD_MOD(l, gpout1, 16, 16);
2388         dispc_write_reg(DISPC_CONTROL, l);
2389 }
2390
2391 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2392 {
2393         if (channel == OMAP_DSS_CHANNEL_LCD2)
2394                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2395         else
2396                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2397 }
2398
2399 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2400                 int vsw, int vfp, int vbp)
2401 {
2402         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2403                 if (hsw < 1 || hsw > 64 ||
2404                                 hfp < 1 || hfp > 256 ||
2405                                 hbp < 1 || hbp > 256 ||
2406                                 vsw < 1 || vsw > 64 ||
2407                                 vfp < 0 || vfp > 255 ||
2408                                 vbp < 0 || vbp > 255)
2409                         return false;
2410         } else {
2411                 if (hsw < 1 || hsw > 256 ||
2412                                 hfp < 1 || hfp > 4096 ||
2413                                 hbp < 1 || hbp > 4096 ||
2414                                 vsw < 1 || vsw > 256 ||
2415                                 vfp < 0 || vfp > 4095 ||
2416                                 vbp < 0 || vbp > 4095)
2417                         return false;
2418         }
2419
2420         return true;
2421 }
2422
2423 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2424 {
2425         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2426                         timings->hbp, timings->vsw,
2427                         timings->vfp, timings->vbp);
2428 }
2429
2430 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2431                 int hfp, int hbp, int vsw, int vfp, int vbp)
2432 {
2433         u32 timing_h, timing_v;
2434
2435         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2436                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2437                         FLD_VAL(hbp-1, 27, 20);
2438
2439                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2440                         FLD_VAL(vbp, 27, 20);
2441         } else {
2442                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2443                         FLD_VAL(hbp-1, 31, 20);
2444
2445                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2446                         FLD_VAL(vbp, 31, 20);
2447         }
2448
2449         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2450         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2451 }
2452
2453 /* change name to mode? */
2454 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2455                 struct omap_video_timings *timings)
2456 {
2457         unsigned xtot, ytot;
2458         unsigned long ht, vt;
2459
2460         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2461                                 timings->hbp, timings->vsw,
2462                                 timings->vfp, timings->vbp))
2463                 BUG();
2464
2465         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2466                         timings->hbp, timings->vsw, timings->vfp,
2467                         timings->vbp);
2468
2469         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2470
2471         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2472         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2473
2474         ht = (timings->pixel_clock * 1000) / xtot;
2475         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2476
2477         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2478                         timings->y_res);
2479         DSSDBG("pck %u\n", timings->pixel_clock);
2480         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2481                         timings->hsw, timings->hfp, timings->hbp,
2482                         timings->vsw, timings->vfp, timings->vbp);
2483
2484         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2485 }
2486
2487 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2488                 u16 pck_div)
2489 {
2490         BUG_ON(lck_div < 1);
2491         BUG_ON(pck_div < 1);
2492
2493         dispc_write_reg(DISPC_DIVISORo(channel),
2494                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2495 }
2496
2497 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2498                 int *pck_div)
2499 {
2500         u32 l;
2501         l = dispc_read_reg(DISPC_DIVISORo(channel));
2502         *lck_div = FLD_GET(l, 23, 16);
2503         *pck_div = FLD_GET(l, 7, 0);
2504 }
2505
2506 unsigned long dispc_fclk_rate(void)
2507 {
2508         struct platform_device *dsidev;
2509         unsigned long r = 0;
2510
2511         switch (dss_get_dispc_clk_source()) {
2512         case OMAP_DSS_CLK_SRC_FCK:
2513                 r = clk_get_rate(dispc.dss_clk);
2514                 break;
2515         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2516                 dsidev = dsi_get_dsidev_from_id(0);
2517                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2518                 break;
2519         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2520                 dsidev = dsi_get_dsidev_from_id(1);
2521                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2522                 break;
2523         default:
2524                 BUG();
2525         }
2526
2527         return r;
2528 }
2529
2530 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2531 {
2532         struct platform_device *dsidev;
2533         int lcd;
2534         unsigned long r;
2535         u32 l;
2536
2537         l = dispc_read_reg(DISPC_DIVISORo(channel));
2538
2539         lcd = FLD_GET(l, 23, 16);
2540
2541         switch (dss_get_lcd_clk_source(channel)) {
2542         case OMAP_DSS_CLK_SRC_FCK:
2543                 r = clk_get_rate(dispc.dss_clk);
2544                 break;
2545         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2546                 dsidev = dsi_get_dsidev_from_id(0);
2547                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2548                 break;
2549         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2550                 dsidev = dsi_get_dsidev_from_id(1);
2551                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2552                 break;
2553         default:
2554                 BUG();
2555         }
2556
2557         return r / lcd;
2558 }
2559
2560 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2561 {
2562         unsigned long r;
2563
2564         if (dispc_mgr_is_lcd(channel)) {
2565                 int pcd;
2566                 u32 l;
2567
2568                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2569
2570                 pcd = FLD_GET(l, 7, 0);
2571
2572                 r = dispc_mgr_lclk_rate(channel);
2573
2574                 return r / pcd;
2575         } else {
2576                 struct omap_dss_device *dssdev =
2577                         dispc_mgr_get_device(channel);
2578
2579                 switch (dssdev->type) {
2580                 case OMAP_DISPLAY_TYPE_VENC:
2581                         return venc_get_pixel_clock();
2582                 case OMAP_DISPLAY_TYPE_HDMI:
2583                         return hdmi_get_pixel_clock();
2584                 default:
2585                         BUG();
2586                 }
2587         }
2588 }
2589
2590 void dispc_dump_clocks(struct seq_file *s)
2591 {
2592         int lcd, pcd;
2593         u32 l;
2594         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2595         enum omap_dss_clk_source lcd_clk_src;
2596
2597         if (dispc_runtime_get())
2598                 return;
2599
2600         seq_printf(s, "- DISPC -\n");
2601
2602         seq_printf(s, "dispc fclk source = %s (%s)\n",
2603                         dss_get_generic_clk_source_name(dispc_clk_src),
2604                         dss_feat_get_clk_source_name(dispc_clk_src));
2605
2606         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2607
2608         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2609                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2610                 l = dispc_read_reg(DISPC_DIVISOR);
2611                 lcd = FLD_GET(l, 23, 16);
2612
2613                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2614                                 (dispc_fclk_rate()/lcd), lcd);
2615         }
2616         seq_printf(s, "- LCD1 -\n");
2617
2618         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2619
2620         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2621                 dss_get_generic_clk_source_name(lcd_clk_src),
2622                 dss_feat_get_clk_source_name(lcd_clk_src));
2623
2624         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2625
2626         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2627                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2628         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2629                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2630         if (dss_has_feature(FEAT_MGR_LCD2)) {
2631                 seq_printf(s, "- LCD2 -\n");
2632
2633                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2634
2635                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2636                         dss_get_generic_clk_source_name(lcd_clk_src),
2637                         dss_feat_get_clk_source_name(lcd_clk_src));
2638
2639                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2640
2641                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2642                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2643                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2644                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2645         }
2646
2647         dispc_runtime_put();
2648 }
2649
2650 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2651 void dispc_dump_irqs(struct seq_file *s)
2652 {
2653         unsigned long flags;
2654         struct dispc_irq_stats stats;
2655
2656         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2657
2658         stats = dispc.irq_stats;
2659         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2660         dispc.irq_stats.last_reset = jiffies;
2661
2662         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2663
2664         seq_printf(s, "period %u ms\n",
2665                         jiffies_to_msecs(jiffies - stats.last_reset));
2666
2667         seq_printf(s, "irqs %d\n", stats.irq_count);
2668 #define PIS(x) \
2669         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2670
2671         PIS(FRAMEDONE);
2672         PIS(VSYNC);
2673         PIS(EVSYNC_EVEN);
2674         PIS(EVSYNC_ODD);
2675         PIS(ACBIAS_COUNT_STAT);
2676         PIS(PROG_LINE_NUM);
2677         PIS(GFX_FIFO_UNDERFLOW);
2678         PIS(GFX_END_WIN);
2679         PIS(PAL_GAMMA_MASK);
2680         PIS(OCP_ERR);
2681         PIS(VID1_FIFO_UNDERFLOW);
2682         PIS(VID1_END_WIN);
2683         PIS(VID2_FIFO_UNDERFLOW);
2684         PIS(VID2_END_WIN);
2685         if (dss_feat_get_num_ovls() > 3) {
2686                 PIS(VID3_FIFO_UNDERFLOW);
2687                 PIS(VID3_END_WIN);
2688         }
2689         PIS(SYNC_LOST);
2690         PIS(SYNC_LOST_DIGIT);
2691         PIS(WAKEUP);
2692         if (dss_has_feature(FEAT_MGR_LCD2)) {
2693                 PIS(FRAMEDONE2);
2694                 PIS(VSYNC2);
2695                 PIS(ACBIAS_COUNT_STAT2);
2696                 PIS(SYNC_LOST2);
2697         }
2698 #undef PIS
2699 }
2700 #endif
2701
2702 void dispc_dump_regs(struct seq_file *s)
2703 {
2704         int i, j;
2705         const char *mgr_names[] = {
2706                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2707                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2708                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2709         };
2710         const char *ovl_names[] = {
2711                 [OMAP_DSS_GFX]          = "GFX",
2712                 [OMAP_DSS_VIDEO1]       = "VID1",
2713                 [OMAP_DSS_VIDEO2]       = "VID2",
2714                 [OMAP_DSS_VIDEO3]       = "VID3",
2715         };
2716         const char **p_names;
2717
2718 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2719
2720         if (dispc_runtime_get())
2721                 return;
2722
2723         /* DISPC common registers */
2724         DUMPREG(DISPC_REVISION);
2725         DUMPREG(DISPC_SYSCONFIG);
2726         DUMPREG(DISPC_SYSSTATUS);
2727         DUMPREG(DISPC_IRQSTATUS);
2728         DUMPREG(DISPC_IRQENABLE);
2729         DUMPREG(DISPC_CONTROL);
2730         DUMPREG(DISPC_CONFIG);
2731         DUMPREG(DISPC_CAPABLE);
2732         DUMPREG(DISPC_LINE_STATUS);
2733         DUMPREG(DISPC_LINE_NUMBER);
2734         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2735                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2736                 DUMPREG(DISPC_GLOBAL_ALPHA);
2737         if (dss_has_feature(FEAT_MGR_LCD2)) {
2738                 DUMPREG(DISPC_CONTROL2);
2739                 DUMPREG(DISPC_CONFIG2);
2740         }
2741
2742 #undef DUMPREG
2743
2744 #define DISPC_REG(i, name) name(i)
2745 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2746         48 - strlen(#r) - strlen(p_names[i]), " ", \
2747         dispc_read_reg(DISPC_REG(i, r)))
2748
2749         p_names = mgr_names;
2750
2751         /* DISPC channel specific registers */
2752         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2753                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2754                 DUMPREG(i, DISPC_TRANS_COLOR);
2755                 DUMPREG(i, DISPC_SIZE_MGR);
2756
2757                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2758                         continue;
2759
2760                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2761                 DUMPREG(i, DISPC_TRANS_COLOR);
2762                 DUMPREG(i, DISPC_TIMING_H);
2763                 DUMPREG(i, DISPC_TIMING_V);
2764                 DUMPREG(i, DISPC_POL_FREQ);
2765                 DUMPREG(i, DISPC_DIVISORo);
2766                 DUMPREG(i, DISPC_SIZE_MGR);
2767
2768                 DUMPREG(i, DISPC_DATA_CYCLE1);
2769                 DUMPREG(i, DISPC_DATA_CYCLE2);
2770                 DUMPREG(i, DISPC_DATA_CYCLE3);
2771
2772                 if (dss_has_feature(FEAT_CPR)) {
2773                         DUMPREG(i, DISPC_CPR_COEF_R);
2774                         DUMPREG(i, DISPC_CPR_COEF_G);
2775                         DUMPREG(i, DISPC_CPR_COEF_B);
2776                 }
2777         }
2778
2779         p_names = ovl_names;
2780
2781         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2782                 DUMPREG(i, DISPC_OVL_BA0);
2783                 DUMPREG(i, DISPC_OVL_BA1);
2784                 DUMPREG(i, DISPC_OVL_POSITION);
2785                 DUMPREG(i, DISPC_OVL_SIZE);
2786                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2787                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2788                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2789                 DUMPREG(i, DISPC_OVL_ROW_INC);
2790                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2791                 if (dss_has_feature(FEAT_PRELOAD))
2792                         DUMPREG(i, DISPC_OVL_PRELOAD);
2793
2794                 if (i == OMAP_DSS_GFX) {
2795                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2796                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2797                         continue;
2798                 }
2799
2800                 DUMPREG(i, DISPC_OVL_FIR);
2801                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2802                 DUMPREG(i, DISPC_OVL_ACCU0);
2803                 DUMPREG(i, DISPC_OVL_ACCU1);
2804                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2805                         DUMPREG(i, DISPC_OVL_BA0_UV);
2806                         DUMPREG(i, DISPC_OVL_BA1_UV);
2807                         DUMPREG(i, DISPC_OVL_FIR2);
2808                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2809                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2810                 }
2811                 if (dss_has_feature(FEAT_ATTR2))
2812                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2813                 if (dss_has_feature(FEAT_PRELOAD))
2814                         DUMPREG(i, DISPC_OVL_PRELOAD);
2815         }
2816
2817 #undef DISPC_REG
2818 #undef DUMPREG
2819
2820 #define DISPC_REG(plane, name, i) name(plane, i)
2821 #define DUMPREG(plane, name, i) \
2822         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2823         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2824         dispc_read_reg(DISPC_REG(plane, name, i)))
2825
2826         /* Video pipeline coefficient registers */
2827
2828         /* start from OMAP_DSS_VIDEO1 */
2829         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2830                 for (j = 0; j < 8; j++)
2831                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2832
2833                 for (j = 0; j < 8; j++)
2834                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2835
2836                 for (j = 0; j < 5; j++)
2837                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2838
2839                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2840                         for (j = 0; j < 8; j++)
2841                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2842                 }
2843
2844                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2845                         for (j = 0; j < 8; j++)
2846                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2847
2848                         for (j = 0; j < 8; j++)
2849                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2850
2851                         for (j = 0; j < 8; j++)
2852                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2853                 }
2854         }
2855
2856         dispc_runtime_put();
2857
2858 #undef DISPC_REG
2859 #undef DUMPREG
2860 }
2861
2862 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2863                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2864                 u8 acb)
2865 {
2866         u32 l = 0;
2867
2868         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2869                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2870
2871         l |= FLD_VAL(onoff, 17, 17);
2872         l |= FLD_VAL(rf, 16, 16);
2873         l |= FLD_VAL(ieo, 15, 15);
2874         l |= FLD_VAL(ipc, 14, 14);
2875         l |= FLD_VAL(ihs, 13, 13);
2876         l |= FLD_VAL(ivs, 12, 12);
2877         l |= FLD_VAL(acbi, 11, 8);
2878         l |= FLD_VAL(acb, 7, 0);
2879
2880         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2881 }
2882
2883 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2884                 enum omap_panel_config config, u8 acbi, u8 acb)
2885 {
2886         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2887                         (config & OMAP_DSS_LCD_RF) != 0,
2888                         (config & OMAP_DSS_LCD_IEO) != 0,
2889                         (config & OMAP_DSS_LCD_IPC) != 0,
2890                         (config & OMAP_DSS_LCD_IHS) != 0,
2891                         (config & OMAP_DSS_LCD_IVS) != 0,
2892                         acbi, acb);
2893 }
2894
2895 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2896 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2897                 struct dispc_clock_info *cinfo)
2898 {
2899         u16 pcd_min, pcd_max;
2900         unsigned long best_pck;
2901         u16 best_ld, cur_ld;
2902         u16 best_pd, cur_pd;
2903
2904         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2905         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2906
2907         if (!is_tft)
2908                 pcd_min = 3;
2909
2910         best_pck = 0;
2911         best_ld = 0;
2912         best_pd = 0;
2913
2914         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2915                 unsigned long lck = fck / cur_ld;
2916
2917                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2918                         unsigned long pck = lck / cur_pd;
2919                         long old_delta = abs(best_pck - req_pck);
2920                         long new_delta = abs(pck - req_pck);
2921
2922                         if (best_pck == 0 || new_delta < old_delta) {
2923                                 best_pck = pck;
2924                                 best_ld = cur_ld;
2925                                 best_pd = cur_pd;
2926
2927                                 if (pck == req_pck)
2928                                         goto found;
2929                         }
2930
2931                         if (pck < req_pck)
2932                                 break;
2933                 }
2934
2935                 if (lck / pcd_min < req_pck)
2936                         break;
2937         }
2938
2939 found:
2940         cinfo->lck_div = best_ld;
2941         cinfo->pck_div = best_pd;
2942         cinfo->lck = fck / cinfo->lck_div;
2943         cinfo->pck = cinfo->lck / cinfo->pck_div;
2944 }
2945
2946 /* calculate clock rates using dividers in cinfo */
2947 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2948                 struct dispc_clock_info *cinfo)
2949 {
2950         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2951                 return -EINVAL;
2952         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2953                 return -EINVAL;
2954
2955         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2956         cinfo->pck = cinfo->lck / cinfo->pck_div;
2957
2958         return 0;
2959 }
2960
2961 int dispc_mgr_set_clock_div(enum omap_channel channel,
2962                 struct dispc_clock_info *cinfo)
2963 {
2964         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2965         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2966
2967         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2968
2969         return 0;
2970 }
2971
2972 int dispc_mgr_get_clock_div(enum omap_channel channel,
2973                 struct dispc_clock_info *cinfo)
2974 {
2975         unsigned long fck;
2976
2977         fck = dispc_fclk_rate();
2978
2979         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2980         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2981
2982         cinfo->lck = fck / cinfo->lck_div;
2983         cinfo->pck = cinfo->lck / cinfo->pck_div;
2984
2985         return 0;
2986 }
2987
2988 /* dispc.irq_lock has to be locked by the caller */
2989 static void _omap_dispc_set_irqs(void)
2990 {
2991         u32 mask;
2992         u32 old_mask;
2993         int i;
2994         struct omap_dispc_isr_data *isr_data;
2995
2996         mask = dispc.irq_error_mask;
2997
2998         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2999                 isr_data = &dispc.registered_isr[i];
3000
3001                 if (isr_data->isr == NULL)
3002                         continue;
3003
3004                 mask |= isr_data->mask;
3005         }
3006
3007         old_mask = dispc_read_reg(DISPC_IRQENABLE);
3008         /* clear the irqstatus for newly enabled irqs */
3009         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3010
3011         dispc_write_reg(DISPC_IRQENABLE, mask);
3012         /* flush posted write */
3013         dispc_read_reg(DISPC_IRQENABLE);
3014 }
3015
3016 static int omap_dispc_register_isr_unlocked(omap_dispc_isr_t isr,
3017                 void *arg, u32 mask)
3018 {
3019         int i;
3020         int ret;
3021         struct omap_dispc_isr_data *isr_data;
3022
3023         if (isr == NULL)
3024                 return -EINVAL;
3025
3026         /* check for duplicate entry */
3027         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3028                 isr_data = &dispc.registered_isr[i];
3029                 if (isr_data->isr == isr && isr_data->arg == arg &&
3030                                 isr_data->mask == mask) {
3031                         ret = -EINVAL;
3032                         goto err;
3033                 }
3034         }
3035
3036         isr_data = NULL;
3037         ret = -EBUSY;
3038
3039         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3040                 isr_data = &dispc.registered_isr[i];
3041
3042                 if (isr_data->isr != NULL)
3043                         continue;
3044
3045                 isr_data->isr = isr;
3046                 isr_data->arg = arg;
3047                 isr_data->mask = mask;
3048                 ret = 0;
3049
3050                 break;
3051         }
3052
3053         if (ret)
3054                 goto err;
3055
3056         _omap_dispc_set_irqs();
3057
3058 err:
3059         return ret;
3060 }
3061
3062 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3063 {
3064         unsigned long flags;
3065         int ret;
3066
3067         spin_lock_irqsave(&dispc.irq_lock, flags);
3068         ret = omap_dispc_register_isr_unlocked(isr, arg, mask);
3069         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3070
3071         return ret;
3072 }
3073 EXPORT_SYMBOL(omap_dispc_register_isr);
3074
3075 static int omap_dispc_unregister_isr_unlocked(omap_dispc_isr_t isr,
3076                 void *arg, u32 mask)
3077 {
3078         int i;
3079         int ret = -EINVAL;
3080         struct omap_dispc_isr_data *isr_data;
3081
3082         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3083                 isr_data = &dispc.registered_isr[i];
3084                 if (isr_data->isr != isr || isr_data->arg != arg ||
3085                                 isr_data->mask != mask)
3086                         continue;
3087
3088                 /* found the correct isr */
3089
3090                 isr_data->isr = NULL;
3091                 isr_data->arg = NULL;
3092                 isr_data->mask = 0;
3093
3094                 ret = 0;
3095                 break;
3096         }
3097
3098         if (ret == 0)
3099                 _omap_dispc_set_irqs();
3100
3101         return ret;
3102 }
3103
3104 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3105 {
3106         unsigned long flags;
3107         int ret;
3108
3109         spin_lock_irqsave(&dispc.irq_lock, flags);
3110         ret = omap_dispc_unregister_isr_unlocked(isr, arg, mask);
3111         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3112
3113         return ret;
3114 }
3115 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3116
3117 #ifdef DEBUG
3118 static void print_irq_status(u32 status)
3119 {
3120         if ((status & dispc.irq_error_mask) == 0)
3121                 return;
3122
3123         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3124
3125 #define PIS(x) \
3126         if (status & DISPC_IRQ_##x) \
3127                 printk(#x " ");
3128         PIS(GFX_FIFO_UNDERFLOW);
3129         PIS(OCP_ERR);
3130         PIS(VID1_FIFO_UNDERFLOW);
3131         PIS(VID2_FIFO_UNDERFLOW);
3132         if (dss_feat_get_num_ovls() > 3)
3133                 PIS(VID3_FIFO_UNDERFLOW);
3134         PIS(SYNC_LOST);
3135         PIS(SYNC_LOST_DIGIT);
3136         if (dss_has_feature(FEAT_MGR_LCD2))
3137                 PIS(SYNC_LOST2);
3138 #undef PIS
3139
3140         printk("\n");
3141 }
3142 #endif
3143
3144 /* Called from dss.c. Note that we don't touch clocks here,
3145  * but we presume they are on because we got an IRQ. However,
3146  * an irq handler may turn the clocks off, so we may not have
3147  * clock later in the function. */
3148 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3149 {
3150         int i;
3151         u32 irqstatus, irqenable;
3152         u32 handledirqs = 0;
3153         u32 unhandled_errors;
3154         struct omap_dispc_isr_data *isr_data;
3155         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3156
3157         spin_lock(&dispc.irq_lock);
3158
3159         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3160         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3161
3162         /* IRQ is not for us */
3163         if (!(irqstatus & irqenable)) {
3164                 spin_unlock(&dispc.irq_lock);
3165                 return IRQ_NONE;
3166         }
3167
3168 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3169         spin_lock(&dispc.irq_stats_lock);
3170         dispc.irq_stats.irq_count++;
3171         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3172         spin_unlock(&dispc.irq_stats_lock);
3173 #endif
3174
3175 #ifdef DEBUG
3176         if (dss_debug)
3177                 print_irq_status(irqstatus);
3178 #endif
3179         /* Ack the interrupt. Do it here before clocks are possibly turned
3180          * off */
3181         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3182         /* flush posted write */
3183         dispc_read_reg(DISPC_IRQSTATUS);
3184
3185         /* make a copy and unlock, so that isrs can unregister
3186          * themselves */
3187         memcpy(registered_isr, dispc.registered_isr,
3188                         sizeof(registered_isr));
3189
3190         spin_unlock(&dispc.irq_lock);
3191
3192         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3193                 isr_data = &registered_isr[i];
3194
3195                 if (!isr_data->isr)
3196                         continue;
3197
3198                 if (isr_data->mask & irqstatus) {
3199                         isr_data->isr(isr_data->arg, irqstatus);
3200                         handledirqs |= isr_data->mask;
3201                 }
3202         }
3203
3204         spin_lock(&dispc.irq_lock);
3205
3206         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3207
3208         if (unhandled_errors) {
3209                 dispc.error_irqs |= unhandled_errors;
3210
3211                 dispc.irq_error_mask &= ~unhandled_errors;
3212                 _omap_dispc_set_irqs();
3213
3214                 schedule_work(&dispc.error_work);
3215         }
3216
3217         spin_unlock(&dispc.irq_lock);
3218
3219         return IRQ_HANDLED;
3220 }
3221
3222 static void dispc_error_worker(struct work_struct *work)
3223 {
3224         int i;
3225         u32 errors;
3226         unsigned long flags;
3227         static const unsigned fifo_underflow_bits[] = {
3228                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3229                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3230                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3231                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3232         };
3233
3234         static const unsigned sync_lost_bits[] = {
3235                 DISPC_IRQ_SYNC_LOST,
3236                 DISPC_IRQ_SYNC_LOST_DIGIT,
3237                 DISPC_IRQ_SYNC_LOST2,
3238         };
3239
3240         spin_lock_irqsave(&dispc.irq_lock, flags);
3241         errors = dispc.error_irqs;
3242         dispc.error_irqs = 0;
3243         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3244
3245         dispc_runtime_get();
3246
3247         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3248                 struct omap_overlay *ovl;
3249                 unsigned bit;
3250
3251                 ovl = omap_dss_get_overlay(i);
3252                 bit = fifo_underflow_bits[i];
3253
3254                 if (bit & errors) {
3255                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3256                                         ovl->name);
3257                         dispc_ovl_enable(ovl->id, false);
3258                         dispc_mgr_go(ovl->manager->id);
3259                         mdelay(50);
3260                 }
3261         }
3262
3263         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3264                 struct omap_overlay_manager *mgr;
3265                 unsigned bit;
3266
3267                 mgr = omap_dss_get_overlay_manager(i);
3268                 bit = sync_lost_bits[i];
3269
3270                 if (bit & errors) {
3271                         struct omap_dss_device *dssdev = mgr->device;
3272                         bool enable;
3273
3274                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3275                                         "with video overlays disabled\n",
3276                                         mgr->name);
3277
3278                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3279                         dssdev->driver->disable(dssdev);
3280
3281                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3282                                 struct omap_overlay *ovl;
3283                                 ovl = omap_dss_get_overlay(i);
3284
3285                                 if (ovl->id != OMAP_DSS_GFX &&
3286                                                 ovl->manager == mgr)
3287                                         dispc_ovl_enable(ovl->id, false);
3288                         }
3289
3290                         dispc_mgr_go(mgr->id);
3291                         mdelay(50);
3292
3293                         if (enable)
3294                                 dssdev->driver->enable(dssdev);
3295                 }
3296         }
3297
3298         if (errors & DISPC_IRQ_OCP_ERR) {
3299                 DSSERR("OCP_ERR\n");
3300                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3301                         struct omap_overlay_manager *mgr;
3302                         mgr = omap_dss_get_overlay_manager(i);
3303                         mgr->device->driver->disable(mgr->device);
3304                 }
3305         }
3306
3307         spin_lock_irqsave(&dispc.irq_lock, flags);
3308         dispc.irq_error_mask |= errors;
3309         _omap_dispc_set_irqs();
3310         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3311
3312         dispc_runtime_put();
3313 }
3314
3315 static void dispc_irq_wait_handler(void *data, u32 mask)
3316 {
3317         complete((struct completion *)data);
3318 }
3319
3320 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3321 {
3322         int r;
3323         DECLARE_COMPLETION_ONSTACK(completion);
3324
3325         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3326                         irqmask);
3327
3328         if (r)
3329                 return r;
3330
3331         timeout = wait_for_completion_timeout(&completion, timeout);
3332
3333         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3334
3335         if (timeout == 0)
3336                 return -ETIMEDOUT;
3337
3338         if (timeout == -ERESTARTSYS)
3339                 return -ERESTARTSYS;
3340
3341         return 0;
3342 }
3343
3344 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3345                 unsigned long timeout)
3346 {
3347         int r;
3348         DECLARE_COMPLETION_ONSTACK(completion);
3349
3350         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3351                         irqmask);
3352
3353         if (r)
3354                 return r;
3355
3356         timeout = wait_for_completion_interruptible_timeout(&completion,
3357                         timeout);
3358
3359         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3360
3361         if (timeout == 0)
3362                 return -ETIMEDOUT;
3363
3364         if (timeout == -ERESTARTSYS)
3365                 return -ERESTARTSYS;
3366
3367         return 0;
3368 }
3369
3370 static void dispc_irq_vsync_on_frame_handler(void *data, u32 mask)
3371 {
3372         struct completion *completion;
3373         unsigned int i;
3374         u32 diff;
3375         int ret;
3376
3377         spin_lock(&dispc.irq_lock);
3378
3379         dispc.frame_counter++;
3380
3381         diff = dispc.frame_counter - dispc.fc_last_use;
3382         if (diff > 5 * 60 && dispc.fc_isr_registered) {
3383                 ret = omap_dispc_unregister_isr_unlocked(
3384                         dispc_irq_vsync_on_frame_handler,
3385                         data, DISPC_IRQ_VSYNC);
3386                 if (ret == 0)
3387                         dispc.fc_isr_registered = false;
3388         }
3389
3390         for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3391                 completion = xchg(&dispc.fc_complete[i], NULL);
3392                 if (completion != NULL)
3393                         complete(completion);
3394         }
3395
3396         spin_unlock(&dispc.irq_lock);
3397 }
3398
3399 int omap_dispc_wait_for_vsync_on_frame(u32 *frame,
3400         unsigned long timeout, bool force)
3401 {
3402         DECLARE_COMPLETION_ONSTACK(completion);
3403         bool need_to_wait = force;
3404         unsigned long flags;
3405         unsigned int i;
3406         long time;
3407         int ret;
3408
3409         spin_lock_irqsave(&dispc.irq_lock, flags);
3410
3411         if (!dispc.fc_isr_registered) {
3412                 ret = omap_dispc_register_isr_unlocked(
3413                         dispc_irq_vsync_on_frame_handler,
3414                         NULL, DISPC_IRQ_VSYNC);
3415                 if (ret)
3416                         goto out_unlock;
3417                 dispc.fc_isr_registered = true;
3418         }
3419         else {
3420                 need_to_wait |= *frame == dispc.frame_counter;
3421         }
3422         dispc.fc_last_use = dispc.frame_counter;
3423
3424         if (need_to_wait) {
3425                 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3426                         if (dispc.fc_complete[i] == NULL) {
3427                                 dispc.fc_complete[i] = &completion;
3428                                 break;
3429                         }
3430                 }
3431                 if (i == ARRAY_SIZE(dispc.fc_complete)) {
3432                         ret = -EBUSY;
3433                         goto out_unlock;
3434                 }
3435         }
3436
3437         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3438
3439         ret = 0;
3440         if (need_to_wait) {
3441                 time = wait_for_completion_interruptible_timeout(
3442                                 &completion, msecs_to_jiffies(17 * 2));
3443                 if (time == 0)
3444                         ret = -ETIMEDOUT;
3445                 else if (time < 0)
3446                         ret = time;
3447         }
3448         if (ret != 0) {
3449                 spin_lock(&dispc.irq_lock);
3450
3451                 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3452                         if (dispc.fc_complete[i] == &completion) {
3453                                 dispc.fc_complete[i] = NULL;
3454                                 break;
3455                         }
3456                 }
3457
3458                 spin_unlock(&dispc.irq_lock);
3459         }
3460
3461         *frame = dispc.frame_counter;
3462         return ret;
3463
3464 out_unlock:
3465         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3466         return ret;
3467 }
3468
3469 int omap_dispc_get_line_status(void)
3470 {
3471         int r;
3472
3473         r = dispc_runtime_get();
3474         if (r < 0)
3475                 return r;
3476
3477         r = dispc_read_reg(DISPC_LINE_STATUS);
3478
3479         dispc_runtime_put();
3480
3481         return r;
3482 }
3483
3484 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3485 void dispc_fake_vsync_irq(void)
3486 {
3487         u32 irqstatus = DISPC_IRQ_VSYNC;
3488         int i;
3489
3490         WARN_ON(!in_interrupt());
3491
3492         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3493                 struct omap_dispc_isr_data *isr_data;
3494                 isr_data = &dispc.registered_isr[i];
3495
3496                 if (!isr_data->isr)
3497                         continue;
3498
3499                 if (isr_data->mask & irqstatus)
3500                         isr_data->isr(isr_data->arg, irqstatus);
3501         }
3502 }
3503 #endif
3504
3505 static void _omap_dispc_initialize_irq(void)
3506 {
3507         unsigned long flags;
3508
3509         spin_lock_irqsave(&dispc.irq_lock, flags);
3510
3511         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3512
3513         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3514         if (dss_has_feature(FEAT_MGR_LCD2))
3515                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3516         if (dss_feat_get_num_ovls() > 3)
3517                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3518
3519         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3520          * so clear it */
3521         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3522
3523         _omap_dispc_set_irqs();
3524
3525         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3526 }
3527
3528 void dispc_enable_sidle(void)
3529 {
3530         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3531 }
3532
3533 void dispc_disable_sidle(void)
3534 {
3535         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3536 }
3537
3538 static void _omap_dispc_initial_config(void)
3539 {
3540         u32 l;
3541
3542         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3543         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3544                 l = dispc_read_reg(DISPC_DIVISOR);
3545                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3546                 l = FLD_MOD(l, 1, 0, 0);
3547                 l = FLD_MOD(l, 1, 23, 16);
3548                 dispc_write_reg(DISPC_DIVISOR, l);
3549         }
3550
3551         /* FUNCGATED */
3552         if (dss_has_feature(FEAT_FUNCGATED))
3553                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3554
3555         /* L3 firewall setting: enable access to OCM RAM */
3556         /* XXX this should be somewhere in plat-omap */
3557         if (cpu_is_omap24xx())
3558                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3559
3560         _dispc_setup_color_conv_coef();
3561
3562         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3563
3564         dispc_read_plane_fifo_sizes();
3565
3566         dispc_configure_burst_sizes();
3567
3568         dispc_ovl_enable_zorder_planes();
3569 }
3570
3571 /* DISPC HW IP initialisation */
3572 static int omap_dispchw_probe(struct platform_device *pdev)
3573 {
3574         u32 rev;
3575         int r = 0;
3576         struct resource *dispc_mem;
3577         struct clk *clk;
3578
3579         dispc.pdev = pdev;
3580
3581         clk = clk_get(&pdev->dev, "fck");
3582         if (IS_ERR(clk)) {
3583                 DSSERR("can't get fck\n");
3584                 r = PTR_ERR(clk);
3585                 goto err_get_clk;
3586         }
3587
3588         dispc.dss_clk = clk;
3589
3590         spin_lock_init(&dispc.irq_lock);
3591
3592 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3593         spin_lock_init(&dispc.irq_stats_lock);
3594         dispc.irq_stats.last_reset = jiffies;
3595 #endif
3596
3597         INIT_WORK(&dispc.error_work, dispc_error_worker);
3598
3599         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3600         if (!dispc_mem) {
3601                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3602                 r = -EINVAL;
3603                 goto err_ioremap;
3604         }
3605         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3606         if (!dispc.base) {
3607                 DSSERR("can't ioremap DISPC\n");
3608                 r = -ENOMEM;
3609                 goto err_ioremap;
3610         }
3611         dispc.irq = platform_get_irq(dispc.pdev, 0);
3612         if (dispc.irq < 0) {
3613                 DSSERR("platform_get_irq failed\n");
3614                 r = -ENODEV;
3615                 goto err_irq;
3616         }
3617
3618         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3619                 "OMAP DISPC", dispc.pdev);
3620         if (r < 0) {
3621                 DSSERR("request_irq failed\n");
3622                 goto err_irq;
3623         }
3624
3625         pdev->dev.coherent_dma_mask = ~0;
3626         dispc.table_virt = dma_alloc_writecombine(&pdev->dev,
3627                 TABLE_SIZE, &dispc.table_phys, GFP_KERNEL);
3628         if (dispc.table_virt == NULL) {
3629                 dev_err(&pdev->dev, "failed to alloc palette memory\n");
3630                 goto err_palette;
3631         }
3632         memset(dispc.table_virt, 0, TABLE_SIZE);
3633
3634         pm_runtime_enable(&pdev->dev);
3635
3636         r = dispc_runtime_get();
3637         if (r)
3638                 goto err_runtime_get;
3639
3640         _omap_dispc_initial_config();
3641
3642         _omap_dispc_initialize_irq();
3643
3644         rev = dispc_read_reg(DISPC_REVISION);
3645         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3646                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3647
3648         dispc_runtime_put();
3649
3650         return 0;
3651
3652 err_runtime_get:
3653         pm_runtime_disable(&pdev->dev);
3654         dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3655                 dispc.table_virt, dispc.table_phys);
3656 err_palette:
3657         free_irq(dispc.irq, dispc.pdev);
3658 err_irq:
3659         iounmap(dispc.base);
3660 err_ioremap:
3661         clk_put(dispc.dss_clk);
3662 err_get_clk:
3663         return r;
3664 }
3665
3666 static int omap_dispchw_remove(struct platform_device *pdev)
3667 {
3668         pm_runtime_disable(&pdev->dev);
3669
3670         dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3671                 dispc.table_virt, dispc.table_phys);
3672
3673         clk_put(dispc.dss_clk);
3674
3675         free_irq(dispc.irq, dispc.pdev);
3676         iounmap(dispc.base);
3677         return 0;
3678 }
3679
3680 static int dispc_runtime_suspend(struct device *dev)
3681 {
3682         dispc_save_context();
3683         dss_runtime_put();
3684
3685         return 0;
3686 }
3687
3688 static int dispc_runtime_resume(struct device *dev)
3689 {
3690         int r;
3691
3692         r = dss_runtime_get();
3693         if (r < 0)
3694                 return r;
3695
3696         dispc_restore_context();
3697
3698         return 0;
3699 }
3700
3701 static const struct dev_pm_ops dispc_pm_ops = {
3702         .runtime_suspend = dispc_runtime_suspend,
3703         .runtime_resume = dispc_runtime_resume,
3704 };
3705
3706 static struct platform_driver omap_dispchw_driver = {
3707         .remove         = omap_dispchw_remove,
3708         .driver         = {
3709                 .name   = "omapdss_dispc",
3710                 .owner  = THIS_MODULE,
3711                 .pm     = &dispc_pm_ops,
3712         },
3713 };
3714
3715 int dispc_init_platform_driver(void)
3716 {
3717         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3718 }
3719
3720 void dispc_uninit_platform_driver(void)
3721 {
3722         return platform_driver_unregister(&omap_dispchw_driver);
3723 }