DSS2: Swap field 0 and field 1 registers
[pandora-kernel.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2  * linux/drivers/video/omap2/dss/dispc.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
29 #include <linux/io.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
34
35 #include <mach/sram.h>
36 #include <mach/board.h>
37 #include <mach/clock.h>
38
39 #include <mach/display.h>
40
41 #include "dss.h"
42
43 /* DISPC */
44 #define DISPC_BASE                      0x48050400
45
46 #define DISPC_SZ_REGS                   SZ_1K
47
48 struct dispc_reg { u16 idx; };
49
50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
51
52 /* DISPC common */
53 #define DISPC_REVISION                  DISPC_REG(0x0000)
54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
74
75 /* DISPC GFX plane */
76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
87
88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
91
92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
95
96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
97
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
100
101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
114
115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
119 /* coef index i = {0, 1, 2, 3, 4} */
120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
123
124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
125
126
127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
128                                          DISPC_IRQ_OCP_ERR | \
129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
131                                          DISPC_IRQ_SYNC_LOST | \
132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
133
134 #define DISPC_MAX_NR_ISRS               8
135
136 struct omap_dispc_isr_data {
137         omap_dispc_isr_t        isr;
138         void                    *arg;
139         u32                     mask;
140 };
141
142 #define REG_GET(idx, start, end) \
143         FLD_GET(dispc_read_reg(idx), start, end)
144
145 #define REG_FLD_MOD(idx, val, start, end)                               \
146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
147
148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
149         DISPC_VID_ATTRIBUTES(0),
150         DISPC_VID_ATTRIBUTES(1) };
151
152 static struct {
153         void __iomem    *base;
154
155         struct clk      *dpll4_m4_ck;
156
157         spinlock_t      irq_lock;
158
159         unsigned long   cache_req_pck;
160         unsigned long   cache_prate;
161         struct dispc_clock_info cache_cinfo;
162
163         u32             irq_error_mask;
164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
165
166         spinlock_t error_lock;
167         u32 error_irqs;
168         struct work_struct error_work;
169
170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
171 } dispc;
172
173 static void omap_dispc_set_irqs(void);
174
175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
176 {
177         __raw_writel(val, dispc.base + idx.idx);
178 }
179
180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
181 {
182         return __raw_readl(dispc.base + idx.idx);
183 }
184
185 #define SR(reg) \
186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
187 #define RR(reg) \
188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
189
190 void dispc_save_context(void)
191 {
192         if (cpu_is_omap24xx())
193                 return;
194
195         SR(SYSCONFIG);
196         SR(IRQENABLE);
197         SR(CONTROL);
198         SR(CONFIG);
199         SR(DEFAULT_COLOR0);
200         SR(DEFAULT_COLOR1);
201         SR(TRANS_COLOR0);
202         SR(TRANS_COLOR1);
203         SR(LINE_NUMBER);
204         SR(TIMING_H);
205         SR(TIMING_V);
206         SR(POL_FREQ);
207         SR(DIVISOR);
208         SR(GLOBAL_ALPHA);
209         SR(SIZE_DIG);
210         SR(SIZE_LCD);
211
212         SR(GFX_BA0);
213         SR(GFX_BA1);
214         SR(GFX_POSITION);
215         SR(GFX_SIZE);
216         SR(GFX_ATTRIBUTES);
217         SR(GFX_FIFO_THRESHOLD);
218         SR(GFX_ROW_INC);
219         SR(GFX_PIXEL_INC);
220         SR(GFX_WINDOW_SKIP);
221         SR(GFX_TABLE_BA);
222
223         SR(DATA_CYCLE1);
224         SR(DATA_CYCLE2);
225         SR(DATA_CYCLE3);
226
227         SR(CPR_COEF_R);
228         SR(CPR_COEF_G);
229         SR(CPR_COEF_B);
230
231         SR(GFX_PRELOAD);
232
233         /* VID1 */
234         SR(VID_BA0(0));
235         SR(VID_BA1(0));
236         SR(VID_POSITION(0));
237         SR(VID_SIZE(0));
238         SR(VID_ATTRIBUTES(0));
239         SR(VID_FIFO_THRESHOLD(0));
240         SR(VID_ROW_INC(0));
241         SR(VID_PIXEL_INC(0));
242         SR(VID_FIR(0));
243         SR(VID_PICTURE_SIZE(0));
244         SR(VID_ACCU0(0));
245         SR(VID_ACCU1(0));
246
247         SR(VID_FIR_COEF_H(0, 0));
248         SR(VID_FIR_COEF_H(0, 1));
249         SR(VID_FIR_COEF_H(0, 2));
250         SR(VID_FIR_COEF_H(0, 3));
251         SR(VID_FIR_COEF_H(0, 4));
252         SR(VID_FIR_COEF_H(0, 5));
253         SR(VID_FIR_COEF_H(0, 6));
254         SR(VID_FIR_COEF_H(0, 7));
255
256         SR(VID_FIR_COEF_HV(0, 0));
257         SR(VID_FIR_COEF_HV(0, 1));
258         SR(VID_FIR_COEF_HV(0, 2));
259         SR(VID_FIR_COEF_HV(0, 3));
260         SR(VID_FIR_COEF_HV(0, 4));
261         SR(VID_FIR_COEF_HV(0, 5));
262         SR(VID_FIR_COEF_HV(0, 6));
263         SR(VID_FIR_COEF_HV(0, 7));
264
265         SR(VID_CONV_COEF(0, 0));
266         SR(VID_CONV_COEF(0, 1));
267         SR(VID_CONV_COEF(0, 2));
268         SR(VID_CONV_COEF(0, 3));
269         SR(VID_CONV_COEF(0, 4));
270
271         SR(VID_FIR_COEF_V(0, 0));
272         SR(VID_FIR_COEF_V(0, 1));
273         SR(VID_FIR_COEF_V(0, 2));
274         SR(VID_FIR_COEF_V(0, 3));
275         SR(VID_FIR_COEF_V(0, 4));
276         SR(VID_FIR_COEF_V(0, 5));
277         SR(VID_FIR_COEF_V(0, 6));
278         SR(VID_FIR_COEF_V(0, 7));
279
280         SR(VID_PRELOAD(0));
281
282         /* VID2 */
283         SR(VID_BA0(1));
284         SR(VID_BA1(1));
285         SR(VID_POSITION(1));
286         SR(VID_SIZE(1));
287         SR(VID_ATTRIBUTES(1));
288         SR(VID_FIFO_THRESHOLD(1));
289         SR(VID_ROW_INC(1));
290         SR(VID_PIXEL_INC(1));
291         SR(VID_FIR(1));
292         SR(VID_PICTURE_SIZE(1));
293         SR(VID_ACCU0(1));
294         SR(VID_ACCU1(1));
295
296         SR(VID_FIR_COEF_H(1, 0));
297         SR(VID_FIR_COEF_H(1, 1));
298         SR(VID_FIR_COEF_H(1, 2));
299         SR(VID_FIR_COEF_H(1, 3));
300         SR(VID_FIR_COEF_H(1, 4));
301         SR(VID_FIR_COEF_H(1, 5));
302         SR(VID_FIR_COEF_H(1, 6));
303         SR(VID_FIR_COEF_H(1, 7));
304
305         SR(VID_FIR_COEF_HV(1, 0));
306         SR(VID_FIR_COEF_HV(1, 1));
307         SR(VID_FIR_COEF_HV(1, 2));
308         SR(VID_FIR_COEF_HV(1, 3));
309         SR(VID_FIR_COEF_HV(1, 4));
310         SR(VID_FIR_COEF_HV(1, 5));
311         SR(VID_FIR_COEF_HV(1, 6));
312         SR(VID_FIR_COEF_HV(1, 7));
313
314         SR(VID_CONV_COEF(1, 0));
315         SR(VID_CONV_COEF(1, 1));
316         SR(VID_CONV_COEF(1, 2));
317         SR(VID_CONV_COEF(1, 3));
318         SR(VID_CONV_COEF(1, 4));
319
320         SR(VID_FIR_COEF_V(1, 0));
321         SR(VID_FIR_COEF_V(1, 1));
322         SR(VID_FIR_COEF_V(1, 2));
323         SR(VID_FIR_COEF_V(1, 3));
324         SR(VID_FIR_COEF_V(1, 4));
325         SR(VID_FIR_COEF_V(1, 5));
326         SR(VID_FIR_COEF_V(1, 6));
327         SR(VID_FIR_COEF_V(1, 7));
328
329         SR(VID_PRELOAD(1));
330 }
331
332 void dispc_restore_context(void)
333 {
334         RR(SYSCONFIG);
335         RR(IRQENABLE);
336         /*RR(CONTROL);*/
337         RR(CONFIG);
338         RR(DEFAULT_COLOR0);
339         RR(DEFAULT_COLOR1);
340         RR(TRANS_COLOR0);
341         RR(TRANS_COLOR1);
342         RR(LINE_NUMBER);
343         RR(TIMING_H);
344         RR(TIMING_V);
345         RR(POL_FREQ);
346         RR(DIVISOR);
347         RR(GLOBAL_ALPHA);
348         RR(SIZE_DIG);
349         RR(SIZE_LCD);
350
351         RR(GFX_BA0);
352         RR(GFX_BA1);
353         RR(GFX_POSITION);
354         RR(GFX_SIZE);
355         RR(GFX_ATTRIBUTES);
356         RR(GFX_FIFO_THRESHOLD);
357         RR(GFX_ROW_INC);
358         RR(GFX_PIXEL_INC);
359         RR(GFX_WINDOW_SKIP);
360         RR(GFX_TABLE_BA);
361
362         RR(DATA_CYCLE1);
363         RR(DATA_CYCLE2);
364         RR(DATA_CYCLE3);
365
366         RR(CPR_COEF_R);
367         RR(CPR_COEF_G);
368         RR(CPR_COEF_B);
369
370         RR(GFX_PRELOAD);
371
372         /* VID1 */
373         RR(VID_BA0(0));
374         RR(VID_BA1(0));
375         RR(VID_POSITION(0));
376         RR(VID_SIZE(0));
377         RR(VID_ATTRIBUTES(0));
378         RR(VID_FIFO_THRESHOLD(0));
379         RR(VID_ROW_INC(0));
380         RR(VID_PIXEL_INC(0));
381         RR(VID_FIR(0));
382         RR(VID_PICTURE_SIZE(0));
383         RR(VID_ACCU0(0));
384         RR(VID_ACCU1(0));
385
386         RR(VID_FIR_COEF_H(0, 0));
387         RR(VID_FIR_COEF_H(0, 1));
388         RR(VID_FIR_COEF_H(0, 2));
389         RR(VID_FIR_COEF_H(0, 3));
390         RR(VID_FIR_COEF_H(0, 4));
391         RR(VID_FIR_COEF_H(0, 5));
392         RR(VID_FIR_COEF_H(0, 6));
393         RR(VID_FIR_COEF_H(0, 7));
394
395         RR(VID_FIR_COEF_HV(0, 0));
396         RR(VID_FIR_COEF_HV(0, 1));
397         RR(VID_FIR_COEF_HV(0, 2));
398         RR(VID_FIR_COEF_HV(0, 3));
399         RR(VID_FIR_COEF_HV(0, 4));
400         RR(VID_FIR_COEF_HV(0, 5));
401         RR(VID_FIR_COEF_HV(0, 6));
402         RR(VID_FIR_COEF_HV(0, 7));
403
404         RR(VID_CONV_COEF(0, 0));
405         RR(VID_CONV_COEF(0, 1));
406         RR(VID_CONV_COEF(0, 2));
407         RR(VID_CONV_COEF(0, 3));
408         RR(VID_CONV_COEF(0, 4));
409
410         RR(VID_FIR_COEF_V(0, 0));
411         RR(VID_FIR_COEF_V(0, 1));
412         RR(VID_FIR_COEF_V(0, 2));
413         RR(VID_FIR_COEF_V(0, 3));
414         RR(VID_FIR_COEF_V(0, 4));
415         RR(VID_FIR_COEF_V(0, 5));
416         RR(VID_FIR_COEF_V(0, 6));
417         RR(VID_FIR_COEF_V(0, 7));
418
419         RR(VID_PRELOAD(0));
420
421         /* VID2 */
422         RR(VID_BA0(1));
423         RR(VID_BA1(1));
424         RR(VID_POSITION(1));
425         RR(VID_SIZE(1));
426         RR(VID_ATTRIBUTES(1));
427         RR(VID_FIFO_THRESHOLD(1));
428         RR(VID_ROW_INC(1));
429         RR(VID_PIXEL_INC(1));
430         RR(VID_FIR(1));
431         RR(VID_PICTURE_SIZE(1));
432         RR(VID_ACCU0(1));
433         RR(VID_ACCU1(1));
434
435         RR(VID_FIR_COEF_H(1, 0));
436         RR(VID_FIR_COEF_H(1, 1));
437         RR(VID_FIR_COEF_H(1, 2));
438         RR(VID_FIR_COEF_H(1, 3));
439         RR(VID_FIR_COEF_H(1, 4));
440         RR(VID_FIR_COEF_H(1, 5));
441         RR(VID_FIR_COEF_H(1, 6));
442         RR(VID_FIR_COEF_H(1, 7));
443
444         RR(VID_FIR_COEF_HV(1, 0));
445         RR(VID_FIR_COEF_HV(1, 1));
446         RR(VID_FIR_COEF_HV(1, 2));
447         RR(VID_FIR_COEF_HV(1, 3));
448         RR(VID_FIR_COEF_HV(1, 4));
449         RR(VID_FIR_COEF_HV(1, 5));
450         RR(VID_FIR_COEF_HV(1, 6));
451         RR(VID_FIR_COEF_HV(1, 7));
452
453         RR(VID_CONV_COEF(1, 0));
454         RR(VID_CONV_COEF(1, 1));
455         RR(VID_CONV_COEF(1, 2));
456         RR(VID_CONV_COEF(1, 3));
457         RR(VID_CONV_COEF(1, 4));
458
459         RR(VID_FIR_COEF_V(1, 0));
460         RR(VID_FIR_COEF_V(1, 1));
461         RR(VID_FIR_COEF_V(1, 2));
462         RR(VID_FIR_COEF_V(1, 3));
463         RR(VID_FIR_COEF_V(1, 4));
464         RR(VID_FIR_COEF_V(1, 5));
465         RR(VID_FIR_COEF_V(1, 6));
466         RR(VID_FIR_COEF_V(1, 7));
467
468         RR(VID_PRELOAD(1));
469
470         /* enable last, because LCD & DIGIT enable are here */
471         RR(CONTROL);
472 }
473
474 #undef SR
475 #undef RR
476
477 static inline void enable_clocks(bool enable)
478 {
479         if (enable)
480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
481         else
482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
483 }
484
485 void dispc_go(enum omap_channel channel)
486 {
487         int bit;
488         unsigned long tmo;
489
490         enable_clocks(1);
491
492         if (channel == OMAP_DSS_CHANNEL_LCD)
493                 bit = 0; /* LCDENABLE */
494         else
495                 bit = 1; /* DIGITALENABLE */
496
497         /* if the channel is not enabled, we don't need GO */
498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
499                 goto end;
500
501         if (channel == OMAP_DSS_CHANNEL_LCD)
502                 bit = 5; /* GOLCD */
503         else
504                 bit = 6; /* GODIGIT */
505
506         tmo = jiffies + msecs_to_jiffies(200);
507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
508                 if (time_after(jiffies, tmo)) {
509                         DSSERR("timeout waiting GO flag\n");
510                         goto end;
511                 }
512                 cpu_relax();
513         }
514
515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
516
517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
518 end:
519         enable_clocks(0);
520 }
521
522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
523 {
524         BUG_ON(plane == OMAP_DSS_GFX);
525
526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
527 }
528
529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
530 {
531         BUG_ON(plane == OMAP_DSS_GFX);
532
533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
534 }
535
536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
537 {
538         BUG_ON(plane == OMAP_DSS_GFX);
539
540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
541 }
542
543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
544                 int vscaleup, int five_taps)
545 {
546         /* Coefficients for horizontal up-sampling */
547         static const u32 coef_hup[8] = {
548                 0x00800000,
549                 0x0D7CF800,
550                 0x1E70F5FF,
551                 0x335FF5FE,
552                 0xF74949F7,
553                 0xF55F33FB,
554                 0xF5701EFE,
555                 0xF87C0DFF,
556         };
557
558         /* Coefficients for horizontal down-sampling */
559         static const u32 coef_hdown[8] = {
560                 0x24382400,
561                 0x28371FFE,
562                 0x2C361BFB,
563                 0x303516F9,
564                 0x11343311,
565                 0x1635300C,
566                 0x1B362C08,
567                 0x1F372804,
568         };
569
570         /* Coefficients for horizontal and vertical up-sampling */
571         static const u32 coef_hvup[2][8] = {
572                 {
573                 0x00800000,
574                 0x037B02FF,
575                 0x0C6F05FE,
576                 0x205907FB,
577                 0x00404000,
578                 0x075920FE,
579                 0x056F0CFF,
580                 0x027B0300,
581                 },
582                 {
583                 0x00800000,
584                 0x0D7CF8FF,
585                 0x1E70F5FE,
586                 0x335FF5FB,
587                 0xF7404000,
588                 0xF55F33FE,
589                 0xF5701EFF,
590                 0xF87C0D00,
591                 },
592         };
593
594         /* Coefficients for horizontal and vertical down-sampling */
595         static const u32 coef_hvdown[2][8] = {
596                 {
597                 0x24382400,
598                 0x28391F04,
599                 0x2D381B08,
600                 0x3237170C,
601                 0x123737F7,
602                 0x173732F9,
603                 0x1B382DFB,
604                 0x1F3928FE,
605                 },
606                 {
607                 0x24382400,
608                 0x28371F04,
609                 0x2C361B08,
610                 0x3035160C,
611                 0x113433F7,
612                 0x163530F9,
613                 0x1B362CFB,
614                 0x1F3728FE,
615                 },
616         };
617
618         /* Coefficients for vertical up-sampling */
619         static const u32 coef_vup[8] = {
620                 0x00000000,
621                 0x0000FF00,
622                 0x0000FEFF,
623                 0x0000FBFE,
624                 0x000000F7,
625                 0x0000FEFB,
626                 0x0000FFFE,
627                 0x000000FF,
628         };
629
630
631         /* Coefficients for vertical down-sampling */
632         static const u32 coef_vdown[8] = {
633                 0x00000000,
634                 0x000004FE,
635                 0x000008FB,
636                 0x00000CF9,
637                 0x0000F711,
638                 0x0000F90C,
639                 0x0000FB08,
640                 0x0000FE04,
641         };
642
643         const u32 *h_coef;
644         const u32 *hv_coef;
645         const u32 *hv_coef_mod;
646         const u32 *v_coef;
647         int i;
648
649         if (hscaleup)
650                 h_coef = coef_hup;
651         else
652                 h_coef = coef_hdown;
653
654         if (vscaleup) {
655                 hv_coef = coef_hvup[five_taps];
656                 v_coef = coef_vup;
657
658                 if (hscaleup)
659                         hv_coef_mod = NULL;
660                 else
661                         hv_coef_mod = coef_hvdown[five_taps];
662         } else {
663                 hv_coef = coef_hvdown[five_taps];
664                 v_coef = coef_vdown;
665
666                 if (hscaleup)
667                         hv_coef_mod = coef_hvup[five_taps];
668                 else
669                         hv_coef_mod = NULL;
670         }
671
672         for (i = 0; i < 8; i++) {
673                 u32 h, hv;
674
675                 h = h_coef[i];
676
677                 hv = hv_coef[i];
678
679                 if (hv_coef_mod) {
680                         hv &= 0xffffff00;
681                         hv |= (hv_coef_mod[i] & 0xff);
682                 }
683
684                 _dispc_write_firh_reg(plane, i, h);
685                 _dispc_write_firhv_reg(plane, i, hv);
686         }
687
688         if (!five_taps)
689                 return;
690
691         for (i = 0; i < 8; i++) {
692                 u32 v;
693                 v = v_coef[i];
694                 _dispc_write_firv_reg(plane, i, v);
695         }
696 }
697
698 static void _dispc_setup_color_conv_coef(void)
699 {
700         const struct color_conv_coef {
701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
702                 int  full_range;
703         }  ctbl_bt601_5 = {
704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
705         };
706
707         const struct color_conv_coef *ct;
708
709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
710
711         ct = &ctbl_bt601_5;
712
713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
718
719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
724
725 #undef CVAL
726
727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
729 }
730
731
732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
733 {
734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
735                 DISPC_VID_BA0(0),
736                 DISPC_VID_BA0(1) };
737
738         dispc_write_reg(ba0_reg[plane], paddr);
739 }
740
741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
742 {
743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
744                                       DISPC_VID_BA1(0),
745                                       DISPC_VID_BA1(1) };
746
747         dispc_write_reg(ba1_reg[plane], paddr);
748 }
749
750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
751 {
752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
753                                       DISPC_VID_POSITION(0),
754                                       DISPC_VID_POSITION(1) };
755
756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
757         dispc_write_reg(pos_reg[plane], val);
758 }
759
760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
761 {
762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
763                                       DISPC_VID_PICTURE_SIZE(0),
764                                       DISPC_VID_PICTURE_SIZE(1) };
765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
766         dispc_write_reg(siz_reg[plane], val);
767 }
768
769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
770 {
771         u32 val;
772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
773                                       DISPC_VID_SIZE(1) };
774
775         BUG_ON(plane == OMAP_DSS_GFX);
776
777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
778         dispc_write_reg(vsi_reg[plane-1], val);
779 }
780
781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
782 {
783         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
784                                      DISPC_VID_PIXEL_INC(0),
785                                      DISPC_VID_PIXEL_INC(1) };
786
787         dispc_write_reg(ri_reg[plane], inc);
788 }
789
790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
791 {
792         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
793                                      DISPC_VID_ROW_INC(0),
794                                      DISPC_VID_ROW_INC(1) };
795
796         dispc_write_reg(ri_reg[plane], inc);
797 }
798
799 static void _dispc_set_color_mode(enum omap_plane plane,
800                 enum omap_color_mode color_mode)
801 {
802         u32 m = 0;
803
804         switch (color_mode) {
805         case OMAP_DSS_COLOR_CLUT1:
806                 m = 0x0; break;
807         case OMAP_DSS_COLOR_CLUT2:
808                 m = 0x1; break;
809         case OMAP_DSS_COLOR_CLUT4:
810                 m = 0x2; break;
811         case OMAP_DSS_COLOR_CLUT8:
812                 m = 0x3; break;
813         case OMAP_DSS_COLOR_RGB12U:
814                 m = 0x4; break;
815         case OMAP_DSS_COLOR_ARGB16:
816                 m = 0x5; break;
817         case OMAP_DSS_COLOR_RGB16:
818                 m = 0x6; break;
819         case OMAP_DSS_COLOR_RGB24U:
820                 m = 0x8; break;
821         case OMAP_DSS_COLOR_RGB24P:
822                 m = 0x9; break;
823         case OMAP_DSS_COLOR_YUV2:
824                 m = 0xa; break;
825         case OMAP_DSS_COLOR_UYVY:
826                 m = 0xb; break;
827         case OMAP_DSS_COLOR_ARGB32:
828                 m = 0xc; break;
829         case OMAP_DSS_COLOR_RGBA32:
830                 m = 0xd; break;
831         case OMAP_DSS_COLOR_RGBX32:
832                 m = 0xe; break;
833         default:
834                 BUG(); break;
835         }
836
837         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
838 }
839
840 static void _dispc_set_channel_out(enum omap_plane plane,
841                 enum omap_channel channel)
842 {
843         int shift;
844         u32 val;
845
846         switch (plane) {
847         case OMAP_DSS_GFX:
848                 shift = 8;
849                 break;
850         case OMAP_DSS_VIDEO1:
851         case OMAP_DSS_VIDEO2:
852                 shift = 16;
853                 break;
854         default:
855                 BUG();
856                 return;
857         }
858
859         val = dispc_read_reg(dispc_reg_att[plane]);
860         val = FLD_MOD(val, channel, shift, shift);
861         dispc_write_reg(dispc_reg_att[plane], val);
862 }
863
864 void dispc_set_burst_size(enum omap_plane plane,
865                 enum omap_burst_size burst_size)
866 {
867         int shift;
868         u32 val;
869
870         enable_clocks(1);
871
872         switch (plane) {
873         case OMAP_DSS_GFX:
874                 shift = 6;
875                 break;
876         case OMAP_DSS_VIDEO1:
877         case OMAP_DSS_VIDEO2:
878                 shift = 14;
879                 break;
880         default:
881                 BUG();
882                 return;
883         }
884
885         val = dispc_read_reg(dispc_reg_att[plane]);
886         val = FLD_MOD(val, burst_size, shift+1, shift);
887         dispc_write_reg(dispc_reg_att[plane], val);
888
889         enable_clocks(0);
890 }
891
892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
893 {
894         u32 val;
895
896         BUG_ON(plane == OMAP_DSS_GFX);
897
898         val = dispc_read_reg(dispc_reg_att[plane]);
899         val = FLD_MOD(val, enable, 9, 9);
900         dispc_write_reg(dispc_reg_att[plane], val);
901 }
902
903 void dispc_set_lcd_size(u16 width, u16 height)
904 {
905         u32 val;
906         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
907         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
908         enable_clocks(1);
909         dispc_write_reg(DISPC_SIZE_LCD, val);
910         enable_clocks(0);
911 }
912
913 void dispc_set_digit_size(u16 width, u16 height)
914 {
915         u32 val;
916         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
917         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
918         enable_clocks(1);
919         dispc_write_reg(DISPC_SIZE_DIG, val);
920         enable_clocks(0);
921 }
922
923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
924 {
925         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
926                                       DISPC_VID_FIFO_SIZE_STATUS(0),
927                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
928         u32 size;
929
930         enable_clocks(1);
931
932         if (cpu_is_omap24xx())
933                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
934         else if (cpu_is_omap34xx())
935                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
936         else
937                 BUG();
938
939         if (cpu_is_omap34xx()) {
940                 /* FIFOMERGE */
941                 if (REG_GET(DISPC_CONFIG, 14, 14))
942                         size *= 3;
943         }
944
945         enable_clocks(0);
946
947         return size;
948 }
949
950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
951 {
952         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
953                                        DISPC_VID_FIFO_THRESHOLD(0),
954                                        DISPC_VID_FIFO_THRESHOLD(1) };
955         u32 size;
956
957         enable_clocks(1);
958
959         size = dispc_get_plane_fifo_size(plane);
960
961         BUG_ON(low > size || high > size);
962
963         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
964                         plane, size,
965                         REG_GET(ftrs_reg[plane], 11, 0),
966                         REG_GET(ftrs_reg[plane], 27, 16),
967                         low, high);
968
969         if (cpu_is_omap24xx())
970                 dispc_write_reg(ftrs_reg[plane],
971                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
972         else
973                 dispc_write_reg(ftrs_reg[plane],
974                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
975
976         enable_clocks(0);
977 }
978
979 void dispc_enable_fifomerge(bool enable)
980 {
981         enable_clocks(1);
982
983         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
984         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
985
986         enable_clocks(0);
987 }
988
989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
990 {
991         u32 val;
992         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
993                                       DISPC_VID_FIR(1) };
994
995         BUG_ON(plane == OMAP_DSS_GFX);
996
997         if (cpu_is_omap24xx())
998                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
999         else
1000                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1001         dispc_write_reg(fir_reg[plane-1], val);
1002 }
1003
1004 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1005 {
1006         u32 val;
1007         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1008                                       DISPC_VID_ACCU0(1) };
1009
1010         BUG_ON(plane == OMAP_DSS_GFX);
1011
1012         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1013         dispc_write_reg(ac0_reg[plane-1], val);
1014 }
1015
1016 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1017 {
1018         u32 val;
1019         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1020                                       DISPC_VID_ACCU1(1) };
1021
1022         BUG_ON(plane == OMAP_DSS_GFX);
1023
1024         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1025         dispc_write_reg(ac1_reg[plane-1], val);
1026 }
1027
1028
1029 static void _dispc_set_scaling(enum omap_plane plane,
1030                 u16 orig_width, u16 orig_height,
1031                 u16 out_width, u16 out_height,
1032                 bool ilace, bool five_taps,
1033                 bool fieldmode)
1034 {
1035         int fir_hinc;
1036         int fir_vinc;
1037         int hscaleup, vscaleup;
1038         int accu0 = 0;
1039         int accu1 = 0;
1040         u32 l;
1041
1042         BUG_ON(plane == OMAP_DSS_GFX);
1043
1044         hscaleup = orig_width <= out_width;
1045         vscaleup = orig_height <= out_height;
1046
1047         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1048
1049         if (!orig_width || orig_width == out_width)
1050                 fir_hinc = 0;
1051         else
1052                 fir_hinc = 1024 * orig_width / out_width;
1053
1054         if (!orig_height || orig_height == out_height)
1055                 fir_vinc = 0;
1056         else
1057                 fir_vinc = 1024 * orig_height / out_height;
1058
1059         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1060
1061         l = dispc_read_reg(dispc_reg_att[plane]);
1062         l &= ~((0x0f << 5) | (0x3 << 21));
1063
1064         l |= fir_hinc ? (1 << 5) : 0;
1065         l |= fir_vinc ? (1 << 6) : 0;
1066
1067         l |= hscaleup ? 0 : (1 << 7);
1068         l |= vscaleup ? 0 : (1 << 8);
1069
1070         l |= five_taps ? (1 << 21) : 0;
1071         l |= five_taps ? (1 << 22) : 0;
1072
1073         dispc_write_reg(dispc_reg_att[plane], l);
1074
1075         /*
1076          * field 0 = even field = bottom field
1077          * field 1 = odd field = top field
1078          */
1079         if (ilace && !fieldmode) {
1080                 accu1 = 0;
1081                 accu0 = fir_vinc / 2;
1082                 if (accu0 >= 1024/2) {
1083                         accu1 = 1024/2;
1084                         accu0 -= accu1;
1085                 }
1086         }
1087
1088         _dispc_set_vid_accu0(plane, 0, accu0);
1089         _dispc_set_vid_accu1(plane, 0, accu1);
1090 }
1091
1092 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1093                 bool mirroring, enum omap_color_mode color_mode)
1094 {
1095         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1096                         color_mode == OMAP_DSS_COLOR_UYVY) {
1097                 int vidrot = 0;
1098
1099                 if (mirroring) {
1100                         switch (rotation) {
1101                         case 0: vidrot = 2; break;
1102                         case 1: vidrot = 3; break;
1103                         case 2: vidrot = 0; break;
1104                         case 3: vidrot = 1; break;
1105                         }
1106                 } else {
1107                         switch (rotation) {
1108                         case 0: vidrot = 0; break;
1109                         case 1: vidrot = 1; break;
1110                         case 2: vidrot = 2; break;
1111                         case 3: vidrot = 3; break;
1112                         }
1113                 }
1114
1115                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1116
1117                 if (rotation == 1 || rotation == 3)
1118                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1119                 else
1120                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1121         } else {
1122                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1123                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1124         }
1125 }
1126
1127 static s32 pixinc(int pixels, u8 ps)
1128 {
1129         if (pixels == 1)
1130                 return 1;
1131         else if (pixels > 1)
1132                 return 1 + (pixels - 1) * ps;
1133         else if (pixels < 0)
1134                 return 1 - (-pixels + 1) * ps;
1135         else
1136                 BUG();
1137 }
1138
1139 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1140                 u16 screen_width,
1141                 u16 width, u16 height,
1142                 enum omap_color_mode color_mode, bool fieldmode,
1143                 unsigned *offset0, unsigned *offset1,
1144                 s32 *row_inc, s32 *pix_inc)
1145 {
1146         u8 ps;
1147
1148         switch (color_mode) {
1149         case OMAP_DSS_COLOR_RGB16:
1150         case OMAP_DSS_COLOR_ARGB16:
1151                 ps = 2;
1152                 break;
1153
1154         case OMAP_DSS_COLOR_RGB24P:
1155                 ps = 3;
1156                 break;
1157
1158         case OMAP_DSS_COLOR_RGB24U:
1159         case OMAP_DSS_COLOR_ARGB32:
1160         case OMAP_DSS_COLOR_RGBA32:
1161         case OMAP_DSS_COLOR_RGBX32:
1162         case OMAP_DSS_COLOR_YUV2:
1163         case OMAP_DSS_COLOR_UYVY:
1164                 ps = 4;
1165                 break;
1166
1167         default:
1168                 BUG();
1169                 return;
1170         }
1171
1172         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1173                         width, height);
1174         switch (rotation + mirror * 4) {
1175         case 0:
1176         case 2:
1177                 /*
1178                  * If the pixel format is YUV or UYVY divide the width
1179                  * of the image by 2 for 0 and 180 degree rotation.
1180                  */
1181                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1182                         color_mode == OMAP_DSS_COLOR_UYVY)
1183                         width = width >> 1;
1184         case 1:
1185         case 3:
1186                 *offset0 = 0;
1187                 if (fieldmode)
1188                         *offset1 = screen_width * ps;
1189                 else
1190                         *offset1 = 0;
1191
1192                 *row_inc = pixinc(1 + (screen_width - width) +
1193                                 (fieldmode ? screen_width : 0),
1194                                 ps);
1195                 *pix_inc = pixinc(1, ps);
1196                 break;
1197
1198         case 4:
1199         case 6:
1200                 /* If the pixel format is YUV or UYVY divide the width
1201                  * of the image by 2  for 0 degree and 180 degree
1202                  */
1203                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1204                         color_mode == OMAP_DSS_COLOR_UYVY)
1205                         width = width >> 1;
1206         case 5:
1207         case 7:
1208                 *offset0 = 0;
1209                 if (fieldmode)
1210                         *offset1 = screen_width * ps;
1211                 else
1212                         *offset1 = 0;
1213                 *row_inc = pixinc(1 - (screen_width + width) -
1214                                 (fieldmode ? screen_width : 0),
1215                                 ps);
1216                 *pix_inc = pixinc(1, ps);
1217                 break;
1218
1219         default:
1220                 BUG();
1221         }
1222 }
1223
1224 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1225                 u16 screen_width,
1226                 u16 width, u16 height,
1227                 enum omap_color_mode color_mode, bool fieldmode,
1228                 unsigned *offset0, unsigned *offset1,
1229                 s32 *row_inc, s32 *pix_inc)
1230 {
1231         u8 ps;
1232         u16 fbw, fbh;
1233
1234         switch (color_mode) {
1235         case OMAP_DSS_COLOR_RGB16:
1236         case OMAP_DSS_COLOR_ARGB16:
1237                 ps = 2;
1238                 break;
1239
1240         case OMAP_DSS_COLOR_RGB24P:
1241                 ps = 3;
1242                 break;
1243
1244         case OMAP_DSS_COLOR_RGB24U:
1245         case OMAP_DSS_COLOR_ARGB32:
1246         case OMAP_DSS_COLOR_RGBA32:
1247         case OMAP_DSS_COLOR_RGBX32:
1248                 ps = 4;
1249                 break;
1250
1251         case OMAP_DSS_COLOR_YUV2:
1252         case OMAP_DSS_COLOR_UYVY:
1253                 ps = 2;
1254                 break;
1255         default:
1256                 BUG();
1257                 return;
1258         }
1259
1260         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1261                         width, height);
1262
1263         /* width & height are overlay sizes, convert to fb sizes */
1264
1265         if (rotation == 0 || rotation == 2) {
1266                 fbw = width;
1267                 fbh = height;
1268         } else {
1269                 fbw = height;
1270                 fbh = width;
1271         }
1272
1273         /*
1274          * field 0 = even field = bottom field
1275          * field 1 = odd field = top field
1276          */
1277         switch (rotation + mirror * 4) {
1278         case 0:
1279                 *offset1 = 0;
1280                 if (fieldmode)
1281                         *offset0 = screen_width * ps;
1282                 else
1283                         *offset0 = 0;
1284                 *row_inc = pixinc(1 + (screen_width - fbw) +
1285                                 (fieldmode ? screen_width : 0),
1286                                 ps);
1287                 *pix_inc = pixinc(1, ps);
1288                 break;
1289         case 1:
1290                 *offset1 = screen_width * (fbh - 1) * ps;
1291                 if (fieldmode)
1292                         *offset0 = *offset1 + ps;
1293                 else
1294                         *offset0 = *offset1;
1295                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1296                                 (fieldmode ? 1 : 0), ps);
1297                 *pix_inc = pixinc(-screen_width, ps);
1298                 break;
1299         case 2:
1300                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1301                 if (fieldmode)
1302                         *offset0 = *offset1 - screen_width * ps;
1303                 else
1304                         *offset0 = *offset1;
1305                 *row_inc = pixinc(-1 -
1306                                 (screen_width - fbw) -
1307                                 (fieldmode ? screen_width : 0),
1308                                 ps);
1309                 *pix_inc = pixinc(-1, ps);
1310                 break;
1311         case 3:
1312                 *offset1 = (fbw - 1) * ps;
1313                 if (fieldmode)
1314                         *offset0 = *offset1 - ps;
1315                 else
1316                         *offset0 = *offset1;
1317                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1318                                 (fieldmode ? 1 : 0), ps);
1319                 *pix_inc = pixinc(screen_width, ps);
1320                 break;
1321
1322         /* mirroring */
1323         case 0 + 4:
1324                 *offset1 = (fbw - 1) * ps;
1325                 if (fieldmode)
1326                         *offset0 = *offset1 + screen_width * ps;
1327                 else
1328                         *offset0 = *offset1;
1329                 *row_inc = pixinc(screen_width * 2 - 1 +
1330                                 (fieldmode ? screen_width : 0),
1331                                 ps);
1332                 *pix_inc = pixinc(-1, ps);
1333                 break;
1334
1335         case 1 + 4:
1336                 *offset1 = 0;
1337                 if (fieldmode)
1338                         *offset0 = *offset1 + screen_width * ps;
1339                 else
1340                         *offset0 = *offset1;
1341                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1342                                 (fieldmode ? 1 : 0),
1343                                 ps);
1344                 *pix_inc = pixinc(screen_width, ps);
1345                 break;
1346
1347         case 2 + 4:
1348                 *offset1 = screen_width * (fbh - 1) * ps;
1349                 if (fieldmode)
1350                         *offset0 = *offset1 + screen_width * ps;
1351                 else
1352                         *offset0 = *offset1;
1353                 *row_inc = pixinc(1 - screen_width * 2 -
1354                                 (fieldmode ? screen_width : 0),
1355                                 ps);
1356                 *pix_inc = pixinc(1, ps);
1357                 break;
1358
1359         case 3 + 4:
1360                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1361                 if (fieldmode)
1362                         *offset0 = *offset1 + screen_width * ps;
1363                 else
1364                         *offset0 = *offset1;
1365                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1366                                 (fieldmode ? 1 : 0),
1367                                 ps);
1368                 *pix_inc = pixinc(-screen_width, ps);
1369                 break;
1370
1371         default:
1372                 BUG();
1373         }
1374 }
1375
1376 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1377                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1378 {
1379         u32 fclk = 0;
1380         /* FIXME venc pclk? */
1381         u64 tmp, pclk = dispc_pclk_rate();
1382
1383         if (height > out_height) {
1384                 /* FIXME get real display PPL */
1385                 unsigned int ppl = 800;
1386
1387                 tmp = pclk * height * out_width;
1388                 do_div(tmp, 2 * out_height * ppl);
1389                 fclk = tmp;
1390
1391                 if (height > 2 * out_height) {
1392                         tmp = pclk * (height - 2 * out_height) * out_width;
1393                         do_div(tmp, 2 * out_height * (ppl - out_width));
1394                         fclk = max(fclk, (u32) tmp);
1395                 }
1396         }
1397
1398         if (width > out_width) {
1399                 tmp = pclk * width;
1400                 do_div(tmp, out_width);
1401                 fclk = max(fclk, (u32) tmp);
1402
1403                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1404                         fclk <<= 1;
1405         }
1406
1407         return fclk;
1408 }
1409
1410 static unsigned long calc_fclk(u16 width, u16 height,
1411                 u16 out_width, u16 out_height)
1412 {
1413         unsigned int hf, vf;
1414
1415         /*
1416          * FIXME how to determine the 'A' factor
1417          * for the no downscaling case ?
1418          */
1419
1420         if (width > 3 * out_width)
1421                 hf = 4;
1422         else if (width > 2 * out_width)
1423                 hf = 3;
1424         else if (width > out_width)
1425                 hf = 2;
1426         else
1427                 hf = 1;
1428
1429         if (height > out_height)
1430                 vf = 2;
1431         else
1432                 vf = 1;
1433
1434         /* FIXME venc pclk? */
1435         return dispc_pclk_rate() * vf * hf;
1436 }
1437
1438 static int _dispc_setup_plane(enum omap_plane plane,
1439                 enum omap_channel channel_out,
1440                 u32 paddr, u16 screen_width,
1441                 u16 pos_x, u16 pos_y,
1442                 u16 width, u16 height,
1443                 u16 out_width, u16 out_height,
1444                 enum omap_color_mode color_mode,
1445                 bool ilace,
1446                 enum omap_dss_rotation_type rotation_type,
1447                 u8 rotation, int mirror)
1448 {
1449         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1450         bool five_taps = 0;
1451         bool fieldmode = 0;
1452         int cconv = 0;
1453         unsigned offset0, offset1;
1454         s32 row_inc;
1455         s32 pix_inc;
1456         u16 frame_height = height;
1457
1458         if (paddr == 0)
1459                 return -EINVAL;
1460
1461         if (ilace && height == out_height)
1462                 fieldmode = 1;
1463
1464         if (ilace) {
1465                 if (fieldmode)
1466                         height /= 2;
1467                 pos_y /= 2;
1468                 out_height /= 2;
1469
1470                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1471                                 "out_height %d\n",
1472                                 height, pos_y, out_height);
1473         }
1474
1475         if (plane == OMAP_DSS_GFX) {
1476                 if (width != out_width || height != out_height)
1477                         return -EINVAL;
1478
1479                 switch (color_mode) {
1480                 case OMAP_DSS_COLOR_ARGB16:
1481                 case OMAP_DSS_COLOR_RGB16:
1482                 case OMAP_DSS_COLOR_RGB24P:
1483                 case OMAP_DSS_COLOR_RGB24U:
1484                 case OMAP_DSS_COLOR_ARGB32:
1485                 case OMAP_DSS_COLOR_RGBA32:
1486                 case OMAP_DSS_COLOR_RGBX32:
1487                         break;
1488
1489                 default:
1490                         return -EINVAL;
1491                 }
1492         } else {
1493                 /* video plane */
1494
1495                 unsigned long fclk = 0;
1496
1497                 if (out_width < width / maxdownscale ||
1498                    out_width > width * 8)
1499                         return -EINVAL;
1500
1501                 if (out_height < height / maxdownscale ||
1502                    out_height > height * 8)
1503                         return -EINVAL;
1504
1505                 switch (color_mode) {
1506                 case OMAP_DSS_COLOR_RGB16:
1507                 case OMAP_DSS_COLOR_RGB24P:
1508                 case OMAP_DSS_COLOR_RGB24U:
1509                 case OMAP_DSS_COLOR_RGBX32:
1510                         break;
1511
1512                 case OMAP_DSS_COLOR_ARGB16:
1513                 case OMAP_DSS_COLOR_ARGB32:
1514                 case OMAP_DSS_COLOR_RGBA32:
1515                         if (plane == OMAP_DSS_VIDEO1)
1516                                 return -EINVAL;
1517                         break;
1518
1519                 case OMAP_DSS_COLOR_YUV2:
1520                 case OMAP_DSS_COLOR_UYVY:
1521                         cconv = 1;
1522                         break;
1523
1524                 default:
1525                         return -EINVAL;
1526                 }
1527
1528                 /* Must use 5-tap filter? */
1529                 five_taps = height > out_height * 2;
1530
1531                 if (!five_taps) {
1532                         fclk = calc_fclk(width, height,
1533                                         out_width, out_height);
1534
1535                         /* Try 5-tap filter if 3-tap fclk is too high */
1536                         if (cpu_is_omap34xx() && height > out_height &&
1537                                         fclk > dispc_fclk_rate())
1538                                 five_taps = true;
1539                 }
1540
1541                 if (width > (2048 >> five_taps))
1542                         return -EINVAL;
1543
1544                 if (five_taps)
1545                         fclk = calc_fclk_five_taps(width, height,
1546                                         out_width, out_height, color_mode);
1547
1548                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1549                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1550
1551                 if (fclk > dispc_fclk_rate())
1552                         return -EINVAL;
1553         }
1554
1555         if (rotation_type == OMAP_DSS_ROT_DMA)
1556                 calc_dma_rotation_offset(rotation, mirror,
1557                                 screen_width, width, frame_height, color_mode,
1558                                 fieldmode,
1559                                 &offset0, &offset1, &row_inc, &pix_inc);
1560         else
1561                 calc_vrfb_rotation_offset(rotation, mirror,
1562                                 screen_width, width, frame_height, color_mode,
1563                                 fieldmode,
1564                                 &offset0, &offset1, &row_inc, &pix_inc);
1565
1566         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1567                         offset0, offset1, row_inc, pix_inc);
1568
1569         _dispc_set_channel_out(plane, channel_out);
1570         _dispc_set_color_mode(plane, color_mode);
1571
1572         _dispc_set_plane_ba0(plane, paddr + offset0);
1573         _dispc_set_plane_ba1(plane, paddr + offset1);
1574
1575         _dispc_set_row_inc(plane, row_inc);
1576         _dispc_set_pix_inc(plane, pix_inc);
1577
1578         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1579                         out_width, out_height);
1580
1581         _dispc_set_plane_pos(plane, pos_x, pos_y);
1582
1583         _dispc_set_pic_size(plane, width, height);
1584
1585         if (plane != OMAP_DSS_GFX) {
1586                 _dispc_set_scaling(plane, width, height,
1587                                    out_width, out_height,
1588                                    ilace, five_taps, fieldmode);
1589                 _dispc_set_vid_size(plane, out_width, out_height);
1590                 _dispc_set_vid_color_conv(plane, cconv);
1591         }
1592
1593         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1594
1595         return 0;
1596 }
1597
1598 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1599 {
1600         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1601 }
1602
1603 static void dispc_disable_isr(void *data, u32 mask)
1604 {
1605         struct completion *compl = data;
1606         complete(compl);
1607 }
1608
1609 static void _enable_lcd_out(bool enable)
1610 {
1611         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1612 }
1613
1614 void dispc_enable_lcd_out(bool enable)
1615 {
1616         struct completion frame_done_completion;
1617         bool is_on;
1618         int r;
1619
1620         enable_clocks(1);
1621
1622         /* When we disable LCD output, we need to wait until frame is done.
1623          * Otherwise the DSS is still working, and turning off the clocks
1624          * prevents DSS from going to OFF mode */
1625         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1626
1627         if (!enable && is_on) {
1628                 init_completion(&frame_done_completion);
1629
1630                 r = omap_dispc_register_isr(dispc_disable_isr,
1631                                 &frame_done_completion,
1632                                 DISPC_IRQ_FRAMEDONE);
1633
1634                 if (r)
1635                         DSSERR("failed to register FRAMEDONE isr\n");
1636         }
1637
1638         _enable_lcd_out(enable);
1639
1640         if (!enable && is_on) {
1641                 if (!wait_for_completion_timeout(&frame_done_completion,
1642                                         msecs_to_jiffies(100)))
1643                         DSSERR("timeout waiting for FRAME DONE\n");
1644
1645                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1646                                 &frame_done_completion,
1647                                 DISPC_IRQ_FRAMEDONE);
1648
1649                 if (r)
1650                         DSSERR("failed to unregister FRAMEDONE isr\n");
1651         }
1652
1653         enable_clocks(0);
1654 }
1655
1656 static void _enable_digit_out(bool enable)
1657 {
1658         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1659 }
1660
1661 void dispc_enable_digit_out(bool enable)
1662 {
1663         struct completion frame_done_completion;
1664         int r;
1665
1666         enable_clocks(1);
1667
1668         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1669                 enable_clocks(0);
1670                 return;
1671         }
1672
1673         if (enable) {
1674                 /* When we enable digit output, we'll get an extra digit
1675                  * sync lost interrupt, that we need to ignore */
1676                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1677                 omap_dispc_set_irqs();
1678         }
1679
1680         /* When we disable digit output, we need to wait until fields are done.
1681          * Otherwise the DSS is still working, and turning off the clocks
1682          * prevents DSS from going to OFF mode. And when enabling, we need to
1683          * wait for the extra sync losts */
1684         init_completion(&frame_done_completion);
1685
1686         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1687                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1688         if (r)
1689                 DSSERR("failed to register EVSYNC isr\n");
1690
1691         _enable_digit_out(enable);
1692
1693         /* XXX I understand from TRM that we should only wait for the
1694          * current field to complete. But it seems we have to wait
1695          * for both fields */
1696         if (!wait_for_completion_timeout(&frame_done_completion,
1697                                 msecs_to_jiffies(100)))
1698                 DSSERR("timeout waiting for EVSYNC\n");
1699
1700         if (!wait_for_completion_timeout(&frame_done_completion,
1701                                 msecs_to_jiffies(100)))
1702                 DSSERR("timeout waiting for EVSYNC\n");
1703
1704         r = omap_dispc_unregister_isr(dispc_disable_isr,
1705                         &frame_done_completion,
1706                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1707         if (r)
1708                 DSSERR("failed to unregister EVSYNC isr\n");
1709
1710         if (enable) {
1711                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1712                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1713                 omap_dispc_set_irqs();
1714         }
1715
1716         enable_clocks(0);
1717 }
1718
1719 void dispc_lcd_enable_signal_polarity(bool act_high)
1720 {
1721         enable_clocks(1);
1722         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1723         enable_clocks(0);
1724 }
1725
1726 void dispc_lcd_enable_signal(bool enable)
1727 {
1728         enable_clocks(1);
1729         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1730         enable_clocks(0);
1731 }
1732
1733 void dispc_pck_free_enable(bool enable)
1734 {
1735         enable_clocks(1);
1736         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1737         enable_clocks(0);
1738 }
1739
1740 void dispc_enable_fifohandcheck(bool enable)
1741 {
1742         enable_clocks(1);
1743         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1744         enable_clocks(0);
1745 }
1746
1747
1748 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1749 {
1750         int mode;
1751
1752         switch (type) {
1753         case OMAP_DSS_LCD_DISPLAY_STN:
1754                 mode = 0;
1755                 break;
1756
1757         case OMAP_DSS_LCD_DISPLAY_TFT:
1758                 mode = 1;
1759                 break;
1760
1761         default:
1762                 BUG();
1763                 return;
1764         }
1765
1766         enable_clocks(1);
1767         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1768         enable_clocks(0);
1769 }
1770
1771 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1772 {
1773         enable_clocks(1);
1774         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1775         enable_clocks(0);
1776 }
1777
1778
1779 void dispc_set_default_color(enum omap_channel channel, u32 color)
1780 {
1781         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1782                                 DISPC_DEFAULT_COLOR1 };
1783
1784         enable_clocks(1);
1785         dispc_write_reg(def_reg[channel], color);
1786         enable_clocks(0);
1787 }
1788
1789 u32 dispc_get_default_color(enum omap_channel channel)
1790 {
1791         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1792                                 DISPC_DEFAULT_COLOR1 };
1793         u32 l;
1794
1795         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1796                channel != OMAP_DSS_CHANNEL_LCD);
1797
1798         enable_clocks(1);
1799         l = dispc_read_reg(def_reg[channel]);
1800         enable_clocks(0);
1801
1802         return l;
1803 }
1804
1805 void dispc_set_trans_key(enum omap_channel ch,
1806                 enum omap_dss_color_key_type type,
1807                 u32 trans_key)
1808 {
1809         const struct dispc_reg tr_reg[] = {
1810                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1811
1812         enable_clocks(1);
1813         if (ch == OMAP_DSS_CHANNEL_LCD)
1814                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1815         else /* OMAP_DSS_CHANNEL_DIGIT */
1816                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1817
1818         dispc_write_reg(tr_reg[ch], trans_key);
1819         enable_clocks(0);
1820 }
1821
1822 void dispc_get_trans_key(enum omap_channel ch,
1823                 enum omap_dss_color_key_type *type,
1824                 u32 *trans_key)
1825 {
1826         const struct dispc_reg tr_reg[] = {
1827                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1828
1829         enable_clocks(1);
1830         if (type) {
1831                 if (ch == OMAP_DSS_CHANNEL_LCD)
1832                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1833                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1834                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1835                 else
1836                         BUG();
1837         }
1838
1839         if (trans_key)
1840                 *trans_key = dispc_read_reg(tr_reg[ch]);
1841         enable_clocks(0);
1842 }
1843
1844 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1845 {
1846         enable_clocks(1);
1847         if (ch == OMAP_DSS_CHANNEL_LCD)
1848                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1849         else /* OMAP_DSS_CHANNEL_DIGIT */
1850                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1851         enable_clocks(0);
1852 }
1853 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1854 {
1855         enable_clocks(1);
1856         if (ch == OMAP_DSS_CHANNEL_LCD)
1857                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1858         else /* OMAP_DSS_CHANNEL_DIGIT */
1859                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1860         enable_clocks(0);
1861 }
1862 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1863 {
1864         bool enabled;
1865
1866         enable_clocks(1);
1867         if (ch == OMAP_DSS_CHANNEL_LCD)
1868                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1869         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1870                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1871         else
1872                 BUG();
1873         enable_clocks(0);
1874
1875         return enabled;
1876
1877 }
1878
1879
1880 bool dispc_trans_key_enabled(enum omap_channel ch)
1881 {
1882         bool enabled;
1883
1884         enable_clocks(1);
1885         if (ch == OMAP_DSS_CHANNEL_LCD)
1886                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1887         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1888                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1889         else BUG();
1890         enable_clocks(0);
1891
1892         return enabled;
1893 }
1894
1895
1896 void dispc_set_tft_data_lines(u8 data_lines)
1897 {
1898         int code;
1899
1900         switch (data_lines) {
1901         case 12:
1902                 code = 0;
1903                 break;
1904         case 16:
1905                 code = 1;
1906                 break;
1907         case 18:
1908                 code = 2;
1909                 break;
1910         case 24:
1911                 code = 3;
1912                 break;
1913         default:
1914                 BUG();
1915                 return;
1916         }
1917
1918         enable_clocks(1);
1919         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1920         enable_clocks(0);
1921 }
1922
1923 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1924 {
1925         u32 l;
1926         int stallmode;
1927         int gpout0 = 1;
1928         int gpout1;
1929
1930         switch (mode) {
1931         case OMAP_DSS_PARALLELMODE_BYPASS:
1932                 stallmode = 0;
1933                 gpout1 = 1;
1934                 break;
1935
1936         case OMAP_DSS_PARALLELMODE_RFBI:
1937                 stallmode = 1;
1938                 gpout1 = 0;
1939                 break;
1940
1941         case OMAP_DSS_PARALLELMODE_DSI:
1942                 stallmode = 1;
1943                 gpout1 = 1;
1944                 break;
1945
1946         default:
1947                 BUG();
1948                 return;
1949         }
1950
1951         enable_clocks(1);
1952
1953         l = dispc_read_reg(DISPC_CONTROL);
1954
1955         l = FLD_MOD(l, stallmode, 11, 11);
1956         l = FLD_MOD(l, gpout0, 15, 15);
1957         l = FLD_MOD(l, gpout1, 16, 16);
1958
1959         dispc_write_reg(DISPC_CONTROL, l);
1960
1961         enable_clocks(0);
1962 }
1963
1964 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1965                                    int vsw, int vfp, int vbp)
1966 {
1967         u32 timing_h, timing_v;
1968
1969         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1970                 BUG_ON(hsw < 1 || hsw > 64);
1971                 BUG_ON(hfp < 1 || hfp > 256);
1972                 BUG_ON(hbp < 1 || hbp > 256);
1973
1974                 BUG_ON(vsw < 1 || vsw > 64);
1975                 BUG_ON(vfp < 0 || vfp > 255);
1976                 BUG_ON(vbp < 0 || vbp > 255);
1977
1978                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1979                         FLD_VAL(hbp-1, 27, 20);
1980
1981                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1982                         FLD_VAL(vbp, 27, 20);
1983         } else {
1984                 BUG_ON(hsw < 1 || hsw > 256);
1985                 BUG_ON(hfp < 1 || hfp > 4096);
1986                 BUG_ON(hbp < 1 || hbp > 4096);
1987
1988                 BUG_ON(vsw < 1 || vsw > 256);
1989                 BUG_ON(vfp < 0 || vfp > 4095);
1990                 BUG_ON(vbp < 0 || vbp > 4095);
1991
1992                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1993                         FLD_VAL(hbp-1, 31, 20);
1994
1995                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1996                         FLD_VAL(vbp, 31, 20);
1997         }
1998
1999         enable_clocks(1);
2000         dispc_write_reg(DISPC_TIMING_H, timing_h);
2001         dispc_write_reg(DISPC_TIMING_V, timing_v);
2002         enable_clocks(0);
2003 }
2004
2005 /* change name to mode? */
2006 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2007 {
2008         unsigned xtot, ytot;
2009         unsigned long ht, vt;
2010
2011         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2012                         timings->vsw, timings->vfp, timings->vbp);
2013
2014         dispc_set_lcd_size(timings->x_res, timings->y_res);
2015
2016         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2017         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2018
2019         ht = (timings->pixel_clock * 1000) / xtot;
2020         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2021
2022         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2023         DSSDBG("pck %u\n", timings->pixel_clock);
2024         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2025                         timings->hsw, timings->hfp, timings->hbp,
2026                         timings->vsw, timings->vfp, timings->vbp);
2027
2028         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2029 }
2030
2031 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2032 {
2033         BUG_ON(lck_div < 1);
2034         BUG_ON(pck_div < 2);
2035
2036         enable_clocks(1);
2037         dispc_write_reg(DISPC_DIVISOR,
2038                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2039         enable_clocks(0);
2040 }
2041
2042 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2043 {
2044         u32 l;
2045         l = dispc_read_reg(DISPC_DIVISOR);
2046         *lck_div = FLD_GET(l, 23, 16);
2047         *pck_div = FLD_GET(l, 7, 0);
2048 }
2049
2050 unsigned long dispc_fclk_rate(void)
2051 {
2052         unsigned long r = 0;
2053
2054         if (dss_get_dispc_clk_source() == 0)
2055                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2056         else
2057 #ifdef CONFIG_OMAP2_DSS_DSI
2058                 r = dsi_get_dsi1_pll_rate();
2059 #else
2060         BUG();
2061 #endif
2062         return r;
2063 }
2064
2065 unsigned long dispc_lclk_rate(void)
2066 {
2067         int lcd;
2068         unsigned long r;
2069         u32 l;
2070
2071         l = dispc_read_reg(DISPC_DIVISOR);
2072
2073         lcd = FLD_GET(l, 23, 16);
2074
2075         r = dispc_fclk_rate();
2076
2077         return r / lcd;
2078 }
2079
2080 unsigned long dispc_pclk_rate(void)
2081 {
2082         int lcd, pcd;
2083         unsigned long r;
2084         u32 l;
2085
2086         l = dispc_read_reg(DISPC_DIVISOR);
2087
2088         lcd = FLD_GET(l, 23, 16);
2089         pcd = FLD_GET(l, 7, 0);
2090
2091         r = dispc_fclk_rate();
2092
2093         return r / lcd / pcd;
2094 }
2095
2096 void dispc_dump_clocks(struct seq_file *s)
2097 {
2098         int lcd, pcd;
2099
2100         enable_clocks(1);
2101
2102         dispc_get_lcd_divisor(&lcd, &pcd);
2103
2104         seq_printf(s, "- dispc -\n");
2105
2106         seq_printf(s, "dispc fclk source = %s\n",
2107                         dss_get_dispc_clk_source() == 0 ?
2108                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2109
2110         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
2111                         dispc_fclk_rate(),
2112                         lcd, pcd,
2113                         dispc_pclk_rate());
2114
2115         enable_clocks(0);
2116 }
2117
2118 void dispc_dump_regs(struct seq_file *s)
2119 {
2120 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2121
2122         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2123
2124         DUMPREG(DISPC_REVISION);
2125         DUMPREG(DISPC_SYSCONFIG);
2126         DUMPREG(DISPC_SYSSTATUS);
2127         DUMPREG(DISPC_IRQSTATUS);
2128         DUMPREG(DISPC_IRQENABLE);
2129         DUMPREG(DISPC_CONTROL);
2130         DUMPREG(DISPC_CONFIG);
2131         DUMPREG(DISPC_CAPABLE);
2132         DUMPREG(DISPC_DEFAULT_COLOR0);
2133         DUMPREG(DISPC_DEFAULT_COLOR1);
2134         DUMPREG(DISPC_TRANS_COLOR0);
2135         DUMPREG(DISPC_TRANS_COLOR1);
2136         DUMPREG(DISPC_LINE_STATUS);
2137         DUMPREG(DISPC_LINE_NUMBER);
2138         DUMPREG(DISPC_TIMING_H);
2139         DUMPREG(DISPC_TIMING_V);
2140         DUMPREG(DISPC_POL_FREQ);
2141         DUMPREG(DISPC_DIVISOR);
2142         DUMPREG(DISPC_GLOBAL_ALPHA);
2143         DUMPREG(DISPC_SIZE_DIG);
2144         DUMPREG(DISPC_SIZE_LCD);
2145
2146         DUMPREG(DISPC_GFX_BA0);
2147         DUMPREG(DISPC_GFX_BA1);
2148         DUMPREG(DISPC_GFX_POSITION);
2149         DUMPREG(DISPC_GFX_SIZE);
2150         DUMPREG(DISPC_GFX_ATTRIBUTES);
2151         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2152         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2153         DUMPREG(DISPC_GFX_ROW_INC);
2154         DUMPREG(DISPC_GFX_PIXEL_INC);
2155         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2156         DUMPREG(DISPC_GFX_TABLE_BA);
2157
2158         DUMPREG(DISPC_DATA_CYCLE1);
2159         DUMPREG(DISPC_DATA_CYCLE2);
2160         DUMPREG(DISPC_DATA_CYCLE3);
2161
2162         DUMPREG(DISPC_CPR_COEF_R);
2163         DUMPREG(DISPC_CPR_COEF_G);
2164         DUMPREG(DISPC_CPR_COEF_B);
2165
2166         DUMPREG(DISPC_GFX_PRELOAD);
2167
2168         DUMPREG(DISPC_VID_BA0(0));
2169         DUMPREG(DISPC_VID_BA1(0));
2170         DUMPREG(DISPC_VID_POSITION(0));
2171         DUMPREG(DISPC_VID_SIZE(0));
2172         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2173         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2174         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2175         DUMPREG(DISPC_VID_ROW_INC(0));
2176         DUMPREG(DISPC_VID_PIXEL_INC(0));
2177         DUMPREG(DISPC_VID_FIR(0));
2178         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2179         DUMPREG(DISPC_VID_ACCU0(0));
2180         DUMPREG(DISPC_VID_ACCU1(0));
2181
2182         DUMPREG(DISPC_VID_BA0(1));
2183         DUMPREG(DISPC_VID_BA1(1));
2184         DUMPREG(DISPC_VID_POSITION(1));
2185         DUMPREG(DISPC_VID_SIZE(1));
2186         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2187         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2188         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2189         DUMPREG(DISPC_VID_ROW_INC(1));
2190         DUMPREG(DISPC_VID_PIXEL_INC(1));
2191         DUMPREG(DISPC_VID_FIR(1));
2192         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2193         DUMPREG(DISPC_VID_ACCU0(1));
2194         DUMPREG(DISPC_VID_ACCU1(1));
2195
2196         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2197         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2198         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2199         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2200         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2201         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2202         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2203         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2204         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2205         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2206         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2207         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2208         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2209         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2210         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2211         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2212         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2213         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2214         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2215         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2216         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2217         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2218         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2219         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2220         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2221         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2222         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2223         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2224         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2225
2226         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2227         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2228         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2229         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2230         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2231         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2232         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2233         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2234         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2235         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2236         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2237         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2238         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2239         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2240         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2241         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2242         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2243         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2244         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2245         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2246         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2247         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2248         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2249         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2250         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2251         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2252         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2253         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2254         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2255
2256         DUMPREG(DISPC_VID_PRELOAD(0));
2257         DUMPREG(DISPC_VID_PRELOAD(1));
2258
2259         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2260 #undef DUMPREG
2261 }
2262
2263 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2264                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2265 {
2266         u32 l = 0;
2267
2268         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2269                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2270
2271         l |= FLD_VAL(onoff, 17, 17);
2272         l |= FLD_VAL(rf, 16, 16);
2273         l |= FLD_VAL(ieo, 15, 15);
2274         l |= FLD_VAL(ipc, 14, 14);
2275         l |= FLD_VAL(ihs, 13, 13);
2276         l |= FLD_VAL(ivs, 12, 12);
2277         l |= FLD_VAL(acbi, 11, 8);
2278         l |= FLD_VAL(acb, 7, 0);
2279
2280         enable_clocks(1);
2281         dispc_write_reg(DISPC_POL_FREQ, l);
2282         enable_clocks(0);
2283 }
2284
2285 void dispc_set_pol_freq(struct omap_panel *panel)
2286 {
2287         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2288                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2289                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2290                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2291                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2292                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2293                                  panel->acbi, panel->acb);
2294 }
2295
2296 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2297                 u16 *lck_div, u16 *pck_div)
2298 {
2299         u16 pcd_min = is_tft ? 2 : 3;
2300         unsigned long best_pck;
2301         u16 best_ld, cur_ld;
2302         u16 best_pd, cur_pd;
2303
2304         best_pck = 0;
2305         best_ld = 0;
2306         best_pd = 0;
2307
2308         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2309                 unsigned long lck = fck / cur_ld;
2310
2311                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2312                         unsigned long pck = lck / cur_pd;
2313                         long old_delta = abs(best_pck - req_pck);
2314                         long new_delta = abs(pck - req_pck);
2315
2316                         if (best_pck == 0 || new_delta < old_delta) {
2317                                 best_pck = pck;
2318                                 best_ld = cur_ld;
2319                                 best_pd = cur_pd;
2320
2321                                 if (pck == req_pck)
2322                                         goto found;
2323                         }
2324
2325                         if (pck < req_pck)
2326                                 break;
2327                 }
2328
2329                 if (lck / pcd_min < req_pck)
2330                         break;
2331         }
2332
2333 found:
2334         *lck_div = best_ld;
2335         *pck_div = best_pd;
2336 }
2337
2338 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2339                 struct dispc_clock_info *cinfo)
2340 {
2341         unsigned long prate;
2342         struct dispc_clock_info cur, best;
2343         int match = 0;
2344         int min_fck_per_pck;
2345         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2346
2347         if (cpu_is_omap34xx())
2348                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2349         else
2350                 prate = 0;
2351
2352         if (req_pck == dispc.cache_req_pck &&
2353                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2354                          dispc.cache_cinfo.fck == fck_rate)) {
2355                 DSSDBG("dispc clock info found from cache.\n");
2356                 *cinfo = dispc.cache_cinfo;
2357                 return 0;
2358         }
2359
2360         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2361
2362         if (min_fck_per_pck &&
2363                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2364                 DSSERR("Requested pixel clock not possible with the current "
2365                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2366                                 "the constraint off.\n");
2367                 min_fck_per_pck = 0;
2368         }
2369
2370 retry:
2371         memset(&cur, 0, sizeof(cur));
2372         memset(&best, 0, sizeof(best));
2373
2374         if (cpu_is_omap24xx()) {
2375                 /* XXX can we change the clock on omap2? */
2376                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2377                 cur.fck_div = 1;
2378
2379                 match = 1;
2380
2381                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2382                                 &cur.lck_div, &cur.pck_div);
2383
2384                 cur.lck = cur.fck / cur.lck_div;
2385                 cur.pck = cur.lck / cur.pck_div;
2386
2387                 best = cur;
2388
2389                 goto found;
2390         } else if (cpu_is_omap34xx()) {
2391                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2392                         cur.fck = prate / cur.fck_div * 2;
2393
2394                         if (cur.fck > DISPC_MAX_FCK)
2395                                 continue;
2396
2397                         if (min_fck_per_pck &&
2398                                         cur.fck < req_pck * min_fck_per_pck)
2399                                 continue;
2400
2401                         match = 1;
2402
2403                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2404                                         &cur.lck_div, &cur.pck_div);
2405
2406                         cur.lck = cur.fck / cur.lck_div;
2407                         cur.pck = cur.lck / cur.pck_div;
2408
2409                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2410                                 best = cur;
2411
2412                                 if (cur.pck == req_pck)
2413                                         goto found;
2414                         }
2415                 }
2416         } else {
2417                 BUG();
2418         }
2419
2420 found:
2421         if (!match) {
2422                 if (min_fck_per_pck) {
2423                         DSSERR("Could not find suitable clock settings.\n"
2424                                         "Turning FCK/PCK constraint off and"
2425                                         "trying again.\n");
2426                         min_fck_per_pck = 0;
2427                         goto retry;
2428                 }
2429
2430                 DSSERR("Could not find suitable clock settings.\n");
2431
2432                 return -EINVAL;
2433         }
2434
2435         if (cinfo)
2436                 *cinfo = best;
2437
2438         dispc.cache_req_pck = req_pck;
2439         dispc.cache_prate = prate;
2440         dispc.cache_cinfo = best;
2441
2442         return 0;
2443 }
2444
2445 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2446 {
2447         unsigned long prate;
2448         int r;
2449
2450         if (cpu_is_omap34xx()) {
2451                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2452                 DSSDBG("dpll4_m4 = %ld\n", prate);
2453         }
2454
2455         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2456         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2457         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2458
2459         if (cpu_is_omap34xx()) {
2460                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2461                 if (r)
2462                         return r;
2463         }
2464
2465         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2466
2467         return 0;
2468 }
2469
2470 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2471 {
2472         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2473
2474         if (cpu_is_omap34xx()) {
2475                 unsigned long prate;
2476                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2477                 cinfo->fck_div = prate / (cinfo->fck / 2);
2478         } else {
2479                 cinfo->fck_div = 0;
2480         }
2481
2482         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2483         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2484
2485         cinfo->lck = cinfo->fck / cinfo->lck_div;
2486         cinfo->pck = cinfo->lck / cinfo->pck_div;
2487
2488         return 0;
2489 }
2490
2491 static void omap_dispc_set_irqs(void)
2492 {
2493         unsigned long flags;
2494         u32 mask = dispc.irq_error_mask;
2495         int i;
2496         struct omap_dispc_isr_data *isr_data;
2497
2498         spin_lock_irqsave(&dispc.irq_lock, flags);
2499
2500         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2501                 isr_data = &dispc.registered_isr[i];
2502
2503                 if (isr_data->isr == NULL)
2504                         continue;
2505
2506                 mask |= isr_data->mask;
2507         }
2508
2509         enable_clocks(1);
2510         dispc_write_reg(DISPC_IRQENABLE, mask);
2511         enable_clocks(0);
2512
2513         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2514 }
2515
2516 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2517 {
2518         int i;
2519         int ret;
2520         unsigned long flags;
2521         struct omap_dispc_isr_data *isr_data;
2522
2523         if (isr == NULL)
2524                 return -EINVAL;
2525
2526         spin_lock_irqsave(&dispc.irq_lock, flags);
2527
2528         /* check for duplicate entry */
2529         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2530                 isr_data = &dispc.registered_isr[i];
2531                 if (isr_data->isr == isr && isr_data->arg == arg &&
2532                                 isr_data->mask == mask) {
2533                         ret = -EINVAL;
2534                         goto err;
2535                 }
2536         }
2537
2538         isr_data = NULL;
2539         ret = -EBUSY;
2540
2541         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2542                 isr_data = &dispc.registered_isr[i];
2543
2544                 if (isr_data->isr != NULL)
2545                         continue;
2546
2547                 isr_data->isr = isr;
2548                 isr_data->arg = arg;
2549                 isr_data->mask = mask;
2550                 ret = 0;
2551
2552                 break;
2553         }
2554 err:
2555         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2556
2557         if (ret == 0)
2558                 omap_dispc_set_irqs();
2559
2560         return ret;
2561 }
2562 EXPORT_SYMBOL(omap_dispc_register_isr);
2563
2564 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2565 {
2566         int i;
2567         unsigned long flags;
2568         int ret = -EINVAL;
2569         struct omap_dispc_isr_data *isr_data;
2570
2571         spin_lock_irqsave(&dispc.irq_lock, flags);
2572
2573         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2574                 isr_data = &dispc.registered_isr[i];
2575                 if (isr_data->isr != isr || isr_data->arg != arg ||
2576                                 isr_data->mask != mask)
2577                         continue;
2578
2579                 /* found the correct isr */
2580
2581                 isr_data->isr = NULL;
2582                 isr_data->arg = NULL;
2583                 isr_data->mask = 0;
2584
2585                 ret = 0;
2586                 break;
2587         }
2588
2589         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2590
2591         if (ret == 0)
2592                 omap_dispc_set_irqs();
2593
2594         return ret;
2595 }
2596 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2597
2598 #ifdef DEBUG
2599 static void print_irq_status(u32 status)
2600 {
2601         if ((status & dispc.irq_error_mask) == 0)
2602                 return;
2603
2604         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2605
2606 #define PIS(x) \
2607         if (status & DISPC_IRQ_##x) \
2608                 printk(#x " ");
2609         PIS(GFX_FIFO_UNDERFLOW);
2610         PIS(OCP_ERR);
2611         PIS(VID1_FIFO_UNDERFLOW);
2612         PIS(VID2_FIFO_UNDERFLOW);
2613         PIS(SYNC_LOST);
2614         PIS(SYNC_LOST_DIGIT);
2615 #undef PIS
2616
2617         printk("\n");
2618 }
2619 #endif
2620
2621 /* Called from dss.c. Note that we don't touch clocks here,
2622  * but we presume they are on because we got an IRQ. However,
2623  * an irq handler may turn the clocks off, so we may not have
2624  * clock later in the function. */
2625 void dispc_irq_handler(void)
2626 {
2627         int i;
2628         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2629         u32 handledirqs = 0;
2630         u32 unhandled_errors;
2631         struct omap_dispc_isr_data *isr_data;
2632
2633 #ifdef DEBUG
2634         if (dss_debug)
2635                 print_irq_status(irqstatus);
2636 #endif
2637         /* Ack the interrupt. Do it here before clocks are possibly turned
2638          * off */
2639         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2640
2641         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2642                 isr_data = &dispc.registered_isr[i];
2643
2644                 if (!isr_data->isr)
2645                         continue;
2646
2647                 if (isr_data->mask & irqstatus) {
2648                         isr_data->isr(isr_data->arg, irqstatus);
2649                         handledirqs |= isr_data->mask;
2650                 }
2651         }
2652
2653         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2654
2655         if (unhandled_errors) {
2656                 spin_lock(&dispc.error_lock);
2657                 dispc.error_irqs |= unhandled_errors;
2658                 spin_unlock(&dispc.error_lock);
2659
2660                 dispc.irq_error_mask &= ~unhandled_errors;
2661                 omap_dispc_set_irqs();
2662
2663                 schedule_work(&dispc.error_work);
2664         }
2665 }
2666
2667 static void dispc_error_worker(struct work_struct *work)
2668 {
2669         int i;
2670         u32 errors;
2671         unsigned long flags;
2672
2673         spin_lock_irqsave(&dispc.error_lock, flags);
2674         errors = dispc.error_irqs;
2675         dispc.error_irqs = 0;
2676         spin_unlock_irqrestore(&dispc.error_lock, flags);
2677
2678         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2679                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2680                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2681                         struct omap_overlay *ovl;
2682                         ovl = omap_dss_get_overlay(i);
2683
2684                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2685                                 continue;
2686
2687                         if (ovl->id == 0) {
2688                                 dispc_enable_plane(ovl->id, 0);
2689                                 dispc_go(ovl->manager->id);
2690                                 mdelay(50);
2691                                 break;
2692                         }
2693                 }
2694         }
2695
2696         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2697                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2698                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2699                         struct omap_overlay *ovl;
2700                         ovl = omap_dss_get_overlay(i);
2701
2702                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2703                                 continue;
2704
2705                         if (ovl->id == 1) {
2706                                 dispc_enable_plane(ovl->id, 0);
2707                                 dispc_go(ovl->manager->id);
2708                                 mdelay(50);
2709                                 break;
2710                         }
2711                 }
2712         }
2713
2714         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2715                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2716                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2717                         struct omap_overlay *ovl;
2718                         ovl = omap_dss_get_overlay(i);
2719
2720                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2721                                 continue;
2722
2723                         if (ovl->id == 2) {
2724                                 dispc_enable_plane(ovl->id, 0);
2725                                 dispc_go(ovl->manager->id);
2726                                 mdelay(50);
2727                                 break;
2728                         }
2729                 }
2730         }
2731
2732         if (errors & DISPC_IRQ_SYNC_LOST) {
2733                 struct omap_overlay_manager *manager = NULL;
2734                 bool enable = false;
2735
2736                 DSSERR("SYNC_LOST, disabling LCD\n");
2737
2738                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2739                         struct omap_overlay_manager *mgr;
2740                         mgr = omap_dss_get_overlay_manager(i);
2741
2742                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2743                                 manager = mgr;
2744                                 enable = mgr->display->state ==
2745                                                 OMAP_DSS_DISPLAY_ACTIVE;
2746                                 mgr->display->disable(mgr->display);
2747                                 break;
2748                         }
2749                 }
2750
2751                 if (manager) {
2752                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2753                                 struct omap_overlay *ovl;
2754                                 ovl = omap_dss_get_overlay(i);
2755
2756                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2757                                         continue;
2758
2759                                 if (ovl->id != 0 && ovl->manager == manager)
2760                                         dispc_enable_plane(ovl->id, 0);
2761                         }
2762
2763                         dispc_go(manager->id);
2764                         mdelay(50);
2765                         if (enable)
2766                                 manager->display->enable(manager->display);
2767                 }
2768         }
2769
2770         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2771                 struct omap_overlay_manager *manager = NULL;
2772                 bool enable = false;
2773
2774                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2775
2776                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2777                         struct omap_overlay_manager *mgr;
2778                         mgr = omap_dss_get_overlay_manager(i);
2779
2780                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2781                                 manager = mgr;
2782                                 enable = mgr->display->state ==
2783                                                 OMAP_DSS_DISPLAY_ACTIVE;
2784                                 mgr->display->disable(mgr->display);
2785                                 break;
2786                         }
2787                 }
2788
2789                 if (manager) {
2790                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2791                                 struct omap_overlay *ovl;
2792                                 ovl = omap_dss_get_overlay(i);
2793
2794                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2795                                         continue;
2796
2797                                 if (ovl->id != 0 && ovl->manager == manager)
2798                                         dispc_enable_plane(ovl->id, 0);
2799                         }
2800
2801                         dispc_go(manager->id);
2802                         mdelay(50);
2803                         if (enable)
2804                                 manager->display->enable(manager->display);
2805                 }
2806         }
2807
2808         if (errors & DISPC_IRQ_OCP_ERR) {
2809                 DSSERR("OCP_ERR\n");
2810                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2811                         struct omap_overlay_manager *mgr;
2812                         mgr = omap_dss_get_overlay_manager(i);
2813
2814                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2815                                 mgr->display->disable(mgr->display);
2816                 }
2817         }
2818
2819         dispc.irq_error_mask |= errors;
2820         omap_dispc_set_irqs();
2821 }
2822
2823 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2824 {
2825         void dispc_irq_wait_handler(void *data, u32 mask)
2826         {
2827                 complete((struct completion *)data);
2828         }
2829
2830         int r;
2831         DECLARE_COMPLETION_ONSTACK(completion);
2832
2833         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2834                         irqmask);
2835
2836         if (r)
2837                 return r;
2838
2839         timeout = wait_for_completion_timeout(&completion, timeout);
2840
2841         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2842
2843         if (timeout == 0)
2844                 return -ETIMEDOUT;
2845
2846         if (timeout == -ERESTARTSYS)
2847                 return -ERESTARTSYS;
2848
2849         return 0;
2850 }
2851
2852 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2853                 unsigned long timeout)
2854 {
2855         void dispc_irq_wait_handler(void *data, u32 mask)
2856         {
2857                 complete((struct completion *)data);
2858         }
2859
2860         int r;
2861         DECLARE_COMPLETION_ONSTACK(completion);
2862
2863         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2864                         irqmask);
2865
2866         if (r)
2867                 return r;
2868
2869         timeout = wait_for_completion_interruptible_timeout(&completion,
2870                         timeout);
2871
2872         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2873
2874         if (timeout == 0)
2875                 return -ETIMEDOUT;
2876
2877         if (timeout == -ERESTARTSYS)
2878                 return -ERESTARTSYS;
2879
2880         return 0;
2881 }
2882
2883 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2884 void dispc_fake_vsync_irq(void)
2885 {
2886         u32 irqstatus = DISPC_IRQ_VSYNC;
2887         int i;
2888
2889         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2890                 struct omap_dispc_isr_data *isr_data;
2891                 isr_data = &dispc.registered_isr[i];
2892
2893                 if (!isr_data->isr)
2894                         continue;
2895
2896                 if (isr_data->mask & irqstatus)
2897                         isr_data->isr(isr_data->arg, irqstatus);
2898         }
2899 }
2900 #endif
2901
2902 static void _omap_dispc_initialize_irq(void)
2903 {
2904         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2905
2906         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2907
2908         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2909          * so clear it */
2910         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2911
2912         omap_dispc_set_irqs();
2913 }
2914
2915 void dispc_enable_sidle(void)
2916 {
2917         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
2918 }
2919
2920 void dispc_disable_sidle(void)
2921 {
2922         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
2923 }
2924
2925 static void _omap_dispc_initial_config(void)
2926 {
2927         u32 l;
2928
2929         l = dispc_read_reg(DISPC_SYSCONFIG);
2930         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2931         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2932         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2933         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2934         dispc_write_reg(DISPC_SYSCONFIG, l);
2935
2936         /* FUNCGATED */
2937         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2938
2939         /* L3 firewall setting: enable access to OCM RAM */
2940         if (cpu_is_omap24xx())
2941                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2942
2943         _dispc_setup_color_conv_coef();
2944
2945         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2946 }
2947
2948 int dispc_init(void)
2949 {
2950         u32 rev;
2951
2952         spin_lock_init(&dispc.irq_lock);
2953         spin_lock_init(&dispc.error_lock);
2954
2955         INIT_WORK(&dispc.error_work, dispc_error_worker);
2956
2957         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2958         if (!dispc.base) {
2959                 DSSERR("can't ioremap DISPC\n");
2960                 return -ENOMEM;
2961         }
2962
2963         if (cpu_is_omap34xx()) {
2964                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2965                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2966                         DSSERR("Failed to get dpll4_m4_ck\n");
2967                         return -ENODEV;
2968                 }
2969         }
2970
2971         enable_clocks(1);
2972
2973         _omap_dispc_initial_config();
2974
2975         _omap_dispc_initialize_irq();
2976
2977         dispc_save_context();
2978
2979         rev = dispc_read_reg(DISPC_REVISION);
2980         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2981                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2982
2983         enable_clocks(0);
2984
2985         return 0;
2986 }
2987
2988 void dispc_exit(void)
2989 {
2990         if (cpu_is_omap34xx())
2991                 clk_put(dispc.dpll4_m4_ck);
2992         iounmap(dispc.base);
2993 }
2994
2995 int dispc_enable_plane(enum omap_plane plane, bool enable)
2996 {
2997         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2998
2999         enable_clocks(1);
3000         _dispc_enable_plane(plane, enable);
3001         enable_clocks(0);
3002
3003         return 0;
3004 }
3005
3006 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
3007                        u32 paddr, u16 screen_width,
3008                        u16 pos_x, u16 pos_y,
3009                        u16 width, u16 height,
3010                        u16 out_width, u16 out_height,
3011                        enum omap_color_mode color_mode,
3012                        bool ilace,
3013                        enum omap_dss_rotation_type rotation_type,
3014                        u8 rotation, bool mirror)
3015 {
3016         int r = 0;
3017
3018         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
3019                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3020                plane, channel_out, paddr, screen_width, pos_x, pos_y,
3021                width, height,
3022                out_width, out_height,
3023                ilace, color_mode,
3024                rotation, mirror);
3025
3026         enable_clocks(1);
3027
3028         r = _dispc_setup_plane(plane, channel_out,
3029                            paddr, screen_width,
3030                            pos_x, pos_y,
3031                            width, height,
3032                            out_width, out_height,
3033                            color_mode, ilace,
3034                            rotation_type,
3035                            rotation, mirror);
3036
3037         enable_clocks(0);
3038
3039         return r;
3040 }
3041
3042 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
3043                                  int x2, int y2, int w2, int h2)
3044 {
3045         if (x1 >= (x2+w2))
3046                 return 0;
3047
3048         if ((x1+w1) <= x2)
3049                 return 0;
3050
3051         if (y1 >= (y2+h2))
3052                 return 0;
3053
3054         if ((y1+h1) <= y2)
3055                 return 0;
3056
3057         return 1;
3058 }
3059
3060 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
3061 {
3062         if (pi->width != pi->out_width)
3063                 return 1;
3064
3065         if (pi->height != pi->out_height)
3066                 return 1;
3067
3068         return 0;
3069 }
3070
3071 /* returns the area that needs updating */
3072 void dispc_setup_partial_planes(struct omap_display *display,
3073                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
3074 {
3075         struct omap_overlay_manager *mgr;
3076         int i;
3077
3078         int x, y, w, h;
3079
3080         x = *xi;
3081         y = *yi;
3082         w = *wi;
3083         h = *hi;
3084
3085         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
3086                 *xi, *yi, *wi, *hi);
3087
3088
3089         mgr = display->manager;
3090
3091         if (!mgr) {
3092                 DSSDBG("no manager\n");
3093                 return;
3094         }
3095
3096         for (i = 0; i < mgr->num_overlays; i++) {
3097                 struct omap_overlay *ovl;
3098                 struct omap_overlay_info *pi;
3099                 ovl = mgr->overlays[i];
3100
3101                 if (ovl->manager != mgr)
3102                         continue;
3103
3104                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
3105                         continue;
3106
3107                 pi = &ovl->info;
3108
3109                 if (!pi->enabled)
3110                         continue;
3111                 /*
3112                  * If the plane is intersecting and scaled, we
3113                  * enlarge the update region to accomodate the
3114                  * whole area
3115                  */
3116
3117                 if (dispc_is_intersecting(x, y, w, h,
3118                                           pi->pos_x, pi->pos_y,
3119                                           pi->out_width, pi->out_height)) {
3120                         if (dispc_is_overlay_scaled(pi)) {
3121
3122                                 int x1, y1, x2, y2;
3123
3124                                 if (x > pi->pos_x)
3125                                         x1 = pi->pos_x;
3126                                 else
3127                                         x1 = x;
3128
3129                                 if (y > pi->pos_y)
3130                                         y1 = pi->pos_y;
3131                                 else
3132                                         y1 = y;
3133
3134                                 if ((x + w) < (pi->pos_x + pi->out_width))
3135                                         x2 = pi->pos_x + pi->out_width;
3136                                 else
3137                                         x2 = x + w;
3138
3139                                 if ((y + h) < (pi->pos_y + pi->out_height))
3140                                         y2 = pi->pos_y + pi->out_height;
3141                                 else
3142                                         y2 = y + h;
3143
3144                                 x = x1;
3145                                 y = y1;
3146                                 w = x2 - x1;
3147                                 h = y2 - y1;
3148
3149                                 DSSDBG("Update area after enlarge due to "
3150                                         "scaling %d, %d %dx%d\n",
3151                                         x, y, w, h);
3152                         }
3153                 }
3154         }
3155
3156         for (i = 0; i < mgr->num_overlays; i++) {
3157                 struct omap_overlay *ovl = mgr->overlays[i];
3158                 struct omap_overlay_info *pi = &ovl->info;
3159
3160                 int px = pi->pos_x;
3161                 int py = pi->pos_y;
3162                 int pw = pi->width;