drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34
  35 #include <mach/sram.h>
  36 #include <mach/board.h>
  37 #include <mach/clock.h>
  38
  39 #include <mach/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 #define REG_GET(idx, start, end) \
 143         FLD_GET(dispc_read_reg(idx), start, end)
 144
 145 #define REG_FLD_MOD(idx, val, start, end)                               \
 146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 147
 148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 149         DISPC_VID_ATTRIBUTES(0),
 150         DISPC_VID_ATTRIBUTES(1) };
 151
 152 static struct {
 153         void __iomem    *base;
 154
 155         struct clk      *dpll4_m4_ck;
 156
 157         spinlock_t      irq_lock;
 158
 159         unsigned long   cache_req_pck;
 160         unsigned long   cache_prate;
 161         struct dispc_clock_info cache_cinfo;
 162
 163         u32             irq_error_mask;
 164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 165
 166         spinlock_t error_lock;
 167         u32 error_irqs;
 168         struct work_struct error_work;
 169
 170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 171 } dispc;
 172
 173 static void omap_dispc_set_irqs(void);
 174
 175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 176 {
 177         __raw_writel(val, dispc.base + idx.idx);
 178 }
 179
 180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 181 {
 182         return __raw_readl(dispc.base + idx.idx);
 183 }
 184
 185 #define SR(reg) \
 186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 187 #define RR(reg) \
 188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 189
 190 void dispc_save_context(void)
 191 {
 192         if (cpu_is_omap24xx())
 193                 return;
 194
 195         SR(SYSCONFIG);
 196         SR(IRQENABLE);
 197         SR(CONTROL);
 198         SR(CONFIG);
 199         SR(DEFAULT_COLOR0);
 200         SR(DEFAULT_COLOR1);
 201         SR(TRANS_COLOR0);
 202         SR(TRANS_COLOR1);
 203         SR(LINE_NUMBER);
 204         SR(TIMING_H);
 205         SR(TIMING_V);
 206         SR(POL_FREQ);
 207         SR(DIVISOR);
 208         SR(GLOBAL_ALPHA);
 209         SR(SIZE_DIG);
 210         SR(SIZE_LCD);
 211
 212         SR(GFX_BA0);
 213         SR(GFX_BA1);
 214         SR(GFX_POSITION);
 215         SR(GFX_SIZE);
 216         SR(GFX_ATTRIBUTES);
 217         SR(GFX_FIFO_THRESHOLD);
 218         SR(GFX_ROW_INC);
 219         SR(GFX_PIXEL_INC);
 220         SR(GFX_WINDOW_SKIP);
 221         SR(GFX_TABLE_BA);
 222
 223         SR(DATA_CYCLE1);
 224         SR(DATA_CYCLE2);
 225         SR(DATA_CYCLE3);
 226
 227         SR(CPR_COEF_R);
 228         SR(CPR_COEF_G);
 229         SR(CPR_COEF_B);
 230
 231         SR(GFX_PRELOAD);
 232
 233         /* VID1 */
 234         SR(VID_BA0(0));
 235         SR(VID_BA1(0));
 236         SR(VID_POSITION(0));
 237         SR(VID_SIZE(0));
 238         SR(VID_ATTRIBUTES(0));
 239         SR(VID_FIFO_THRESHOLD(0));
 240         SR(VID_ROW_INC(0));
 241         SR(VID_PIXEL_INC(0));
 242         SR(VID_FIR(0));
 243         SR(VID_PICTURE_SIZE(0));
 244         SR(VID_ACCU0(0));
 245         SR(VID_ACCU1(0));
 246
 247         SR(VID_FIR_COEF_H(0, 0));
 248         SR(VID_FIR_COEF_H(0, 1));
 249         SR(VID_FIR_COEF_H(0, 2));
 250         SR(VID_FIR_COEF_H(0, 3));
 251         SR(VID_FIR_COEF_H(0, 4));
 252         SR(VID_FIR_COEF_H(0, 5));
 253         SR(VID_FIR_COEF_H(0, 6));
 254         SR(VID_FIR_COEF_H(0, 7));
 255
 256         SR(VID_FIR_COEF_HV(0, 0));
 257         SR(VID_FIR_COEF_HV(0, 1));
 258         SR(VID_FIR_COEF_HV(0, 2));
 259         SR(VID_FIR_COEF_HV(0, 3));
 260         SR(VID_FIR_COEF_HV(0, 4));
 261         SR(VID_FIR_COEF_HV(0, 5));
 262         SR(VID_FIR_COEF_HV(0, 6));
 263         SR(VID_FIR_COEF_HV(0, 7));
 264
 265         SR(VID_CONV_COEF(0, 0));
 266         SR(VID_CONV_COEF(0, 1));
 267         SR(VID_CONV_COEF(0, 2));
 268         SR(VID_CONV_COEF(0, 3));
 269         SR(VID_CONV_COEF(0, 4));
 270
 271         SR(VID_FIR_COEF_V(0, 0));
 272         SR(VID_FIR_COEF_V(0, 1));
 273         SR(VID_FIR_COEF_V(0, 2));
 274         SR(VID_FIR_COEF_V(0, 3));
 275         SR(VID_FIR_COEF_V(0, 4));
 276         SR(VID_FIR_COEF_V(0, 5));
 277         SR(VID_FIR_COEF_V(0, 6));
 278         SR(VID_FIR_COEF_V(0, 7));
 279
 280         SR(VID_PRELOAD(0));
 281
 282         /* VID2 */
 283         SR(VID_BA0(1));
 284         SR(VID_BA1(1));
 285         SR(VID_POSITION(1));
 286         SR(VID_SIZE(1));
 287         SR(VID_ATTRIBUTES(1));
 288         SR(VID_FIFO_THRESHOLD(1));
 289         SR(VID_ROW_INC(1));
 290         SR(VID_PIXEL_INC(1));
 291         SR(VID_FIR(1));
 292         SR(VID_PICTURE_SIZE(1));
 293         SR(VID_ACCU0(1));
 294         SR(VID_ACCU1(1));
 295
 296         SR(VID_FIR_COEF_H(1, 0));
 297         SR(VID_FIR_COEF_H(1, 1));
 298         SR(VID_FIR_COEF_H(1, 2));
 299         SR(VID_FIR_COEF_H(1, 3));
 300         SR(VID_FIR_COEF_H(1, 4));
 301         SR(VID_FIR_COEF_H(1, 5));
 302         SR(VID_FIR_COEF_H(1, 6));
 303         SR(VID_FIR_COEF_H(1, 7));
 304
 305         SR(VID_FIR_COEF_HV(1, 0));
 306         SR(VID_FIR_COEF_HV(1, 1));
 307         SR(VID_FIR_COEF_HV(1, 2));
 308         SR(VID_FIR_COEF_HV(1, 3));
 309         SR(VID_FIR_COEF_HV(1, 4));
 310         SR(VID_FIR_COEF_HV(1, 5));
 311         SR(VID_FIR_COEF_HV(1, 6));
 312         SR(VID_FIR_COEF_HV(1, 7));
 313
 314         SR(VID_CONV_COEF(1, 0));
 315         SR(VID_CONV_COEF(1, 1));
 316         SR(VID_CONV_COEF(1, 2));
 317         SR(VID_CONV_COEF(1, 3));
 318         SR(VID_CONV_COEF(1, 4));
 319
 320         SR(VID_FIR_COEF_V(1, 0));
 321         SR(VID_FIR_COEF_V(1, 1));
 322         SR(VID_FIR_COEF_V(1, 2));
 323         SR(VID_FIR_COEF_V(1, 3));
 324         SR(VID_FIR_COEF_V(1, 4));
 325         SR(VID_FIR_COEF_V(1, 5));
 326         SR(VID_FIR_COEF_V(1, 6));
 327         SR(VID_FIR_COEF_V(1, 7));
 328
 329         SR(VID_PRELOAD(1));
 330 }
 331
 332 void dispc_restore_context(void)
 333 {
 334         RR(SYSCONFIG);
 335         RR(IRQENABLE);
 336         /*RR(CONTROL);*/
 337         RR(CONFIG);
 338         RR(DEFAULT_COLOR0);
 339         RR(DEFAULT_COLOR1);
 340         RR(TRANS_COLOR0);
 341         RR(TRANS_COLOR1);
 342         RR(LINE_NUMBER);
 343         RR(TIMING_H);
 344         RR(TIMING_V);
 345         RR(POL_FREQ);
 346         RR(DIVISOR);
 347         RR(GLOBAL_ALPHA);
 348         RR(SIZE_DIG);
 349         RR(SIZE_LCD);
 350
 351         RR(GFX_BA0);
 352         RR(GFX_BA1);
 353         RR(GFX_POSITION);
 354         RR(GFX_SIZE);
 355         RR(GFX_ATTRIBUTES);
 356         RR(GFX_FIFO_THRESHOLD);
 357         RR(GFX_ROW_INC);
 358         RR(GFX_PIXEL_INC);
 359         RR(GFX_WINDOW_SKIP);
 360         RR(GFX_TABLE_BA);
 361
 362         RR(DATA_CYCLE1);
 363         RR(DATA_CYCLE2);
 364         RR(DATA_CYCLE3);
 365
 366         RR(CPR_COEF_R);
 367         RR(CPR_COEF_G);
 368         RR(CPR_COEF_B);
 369
 370         RR(GFX_PRELOAD);
 371
 372         /* VID1 */
 373         RR(VID_BA0(0));
 374         RR(VID_BA1(0));
 375         RR(VID_POSITION(0));
 376         RR(VID_SIZE(0));
 377         RR(VID_ATTRIBUTES(0));
 378         RR(VID_FIFO_THRESHOLD(0));
 379         RR(VID_ROW_INC(0));
 380         RR(VID_PIXEL_INC(0));
 381         RR(VID_FIR(0));
 382         RR(VID_PICTURE_SIZE(0));
 383         RR(VID_ACCU0(0));
 384         RR(VID_ACCU1(0));
 385
 386         RR(VID_FIR_COEF_H(0, 0));
 387         RR(VID_FIR_COEF_H(0, 1));
 388         RR(VID_FIR_COEF_H(0, 2));
 389         RR(VID_FIR_COEF_H(0, 3));
 390         RR(VID_FIR_COEF_H(0, 4));
 391         RR(VID_FIR_COEF_H(0, 5));
 392         RR(VID_FIR_COEF_H(0, 6));
 393         RR(VID_FIR_COEF_H(0, 7));
 394
 395         RR(VID_FIR_COEF_HV(0, 0));
 396         RR(VID_FIR_COEF_HV(0, 1));
 397         RR(VID_FIR_COEF_HV(0, 2));
 398         RR(VID_FIR_COEF_HV(0, 3));
 399         RR(VID_FIR_COEF_HV(0, 4));
 400         RR(VID_FIR_COEF_HV(0, 5));
 401         RR(VID_FIR_COEF_HV(0, 6));
 402         RR(VID_FIR_COEF_HV(0, 7));
 403
 404         RR(VID_CONV_COEF(0, 0));
 405         RR(VID_CONV_COEF(0, 1));
 406         RR(VID_CONV_COEF(0, 2));
 407         RR(VID_CONV_COEF(0, 3));
 408         RR(VID_CONV_COEF(0, 4));
 409
 410         RR(VID_FIR_COEF_V(0, 0));
 411         RR(VID_FIR_COEF_V(0, 1));
 412         RR(VID_FIR_COEF_V(0, 2));
 413         RR(VID_FIR_COEF_V(0, 3));
 414         RR(VID_FIR_COEF_V(0, 4));
 415         RR(VID_FIR_COEF_V(0, 5));
 416         RR(VID_FIR_COEF_V(0, 6));
 417         RR(VID_FIR_COEF_V(0, 7));
 418
 419         RR(VID_PRELOAD(0));
 420
 421         /* VID2 */
 422         RR(VID_BA0(1));
 423         RR(VID_BA1(1));
 424         RR(VID_POSITION(1));
 425         RR(VID_SIZE(1));
 426         RR(VID_ATTRIBUTES(1));
 427         RR(VID_FIFO_THRESHOLD(1));
 428         RR(VID_ROW_INC(1));
 429         RR(VID_PIXEL_INC(1));
 430         RR(VID_FIR(1));
 431         RR(VID_PICTURE_SIZE(1));
 432         RR(VID_ACCU0(1));
 433         RR(VID_ACCU1(1));
 434
 435         RR(VID_FIR_COEF_H(1, 0));
 436         RR(VID_FIR_COEF_H(1, 1));
 437         RR(VID_FIR_COEF_H(1, 2));
 438         RR(VID_FIR_COEF_H(1, 3));
 439         RR(VID_FIR_COEF_H(1, 4));
 440         RR(VID_FIR_COEF_H(1, 5));
 441         RR(VID_FIR_COEF_H(1, 6));
 442         RR(VID_FIR_COEF_H(1, 7));
 443
 444         RR(VID_FIR_COEF_HV(1, 0));
 445         RR(VID_FIR_COEF_HV(1, 1));
 446         RR(VID_FIR_COEF_HV(1, 2));
 447         RR(VID_FIR_COEF_HV(1, 3));
 448         RR(VID_FIR_COEF_HV(1, 4));
 449         RR(VID_FIR_COEF_HV(1, 5));
 450         RR(VID_FIR_COEF_HV(1, 6));
 451         RR(VID_FIR_COEF_HV(1, 7));
 452
 453         RR(VID_CONV_COEF(1, 0));
 454         RR(VID_CONV_COEF(1, 1));
 455         RR(VID_CONV_COEF(1, 2));
 456         RR(VID_CONV_COEF(1, 3));
 457         RR(VID_CONV_COEF(1, 4));
 458
 459         RR(VID_FIR_COEF_V(1, 0));
 460         RR(VID_FIR_COEF_V(1, 1));
 461         RR(VID_FIR_COEF_V(1, 2));
 462         RR(VID_FIR_COEF_V(1, 3));
 463         RR(VID_FIR_COEF_V(1, 4));
 464         RR(VID_FIR_COEF_V(1, 5));
 465         RR(VID_FIR_COEF_V(1, 6));
 466         RR(VID_FIR_COEF_V(1, 7));
 467
 468         RR(VID_PRELOAD(1));
 469
 470         /* enable last, because LCD & DIGIT enable are here */
 471         RR(CONTROL);
 472 }
 473
 474 #undef SR
 475 #undef RR
 476
 477 static inline void enable_clocks(bool enable)
 478 {
 479         if (enable)
 480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 481         else
 482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 483 }
 484
 485 void dispc_go(enum omap_channel channel)
 486 {
 487         int bit;
 488         unsigned long tmo;
 489
 490         enable_clocks(1);
 491
 492         if (channel == OMAP_DSS_CHANNEL_LCD)
 493                 bit = 0; /* LCDENABLE */
 494         else
 495                 bit = 1; /* DIGITALENABLE */
 496
 497         /* if the channel is not enabled, we don't need GO */
 498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 499                 goto end;
 500
 501         if (channel == OMAP_DSS_CHANNEL_LCD)
 502                 bit = 5; /* GOLCD */
 503         else
 504                 bit = 6; /* GODIGIT */
 505
 506         tmo = jiffies + msecs_to_jiffies(200);
 507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 508                 if (time_after(jiffies, tmo)) {
 509                         DSSERR("timeout waiting GO flag\n");
 510                         goto end;
 511                 }
 512                 cpu_relax();
 513         }
 514
 515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 516
 517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 518 end:
 519         enable_clocks(0);
 520 }
 521
 522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 523 {
 524         BUG_ON(plane == OMAP_DSS_GFX);
 525
 526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 527 }
 528
 529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         BUG_ON(plane == OMAP_DSS_GFX);
 532
 533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 534 }
 535
 536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 537 {
 538         BUG_ON(plane == OMAP_DSS_GFX);
 539
 540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 541 }
 542
 543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 544                 int vscaleup, int five_taps)
 545 {
 546         /* Coefficients for horizontal up-sampling */
 547         static const u32 coef_hup[8] = {
 548                 0x00800000,
 549                 0x0D7CF800,
 550                 0x1E70F5FF,
 551                 0x335FF5FE,
 552                 0xF74949F7,
 553                 0xF55F33FB,
 554                 0xF5701EFE,
 555                 0xF87C0DFF,
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const u32 coef_hdown[8] = {
 560                 0x24382400,
 561                 0x28371FFE,
 562                 0x2C361BFB,
 563                 0x303516F9,
 564                 0x11343311,
 565                 0x1635300C,
 566                 0x1B362C08,
 567                 0x1F372804,
 568         };
 569
 570         /* Coefficients for horizontal and vertical up-sampling */
 571         static const u32 coef_hvup[2][8] = {
 572                 {
 573                 0x00800000,
 574                 0x037B02FF,
 575                 0x0C6F05FE,
 576                 0x205907FB,
 577                 0x00404000,
 578                 0x075920FE,
 579                 0x056F0CFF,
 580                 0x027B0300,
 581                 },
 582                 {
 583                 0x00800000,
 584                 0x0D7CF8FF,
 585                 0x1E70F5FE,
 586                 0x335FF5FB,
 587                 0xF7404000,
 588                 0xF55F33FE,
 589                 0xF5701EFF,
 590                 0xF87C0D00,
 591                 },
 592         };
 593
 594         /* Coefficients for horizontal and vertical down-sampling */
 595         static const u32 coef_hvdown[2][8] = {
 596                 {
 597                 0x24382400,
 598                 0x28391F04,
 599                 0x2D381B08,
 600                 0x3237170C,
 601                 0x123737F7,
 602                 0x173732F9,
 603                 0x1B382DFB,
 604                 0x1F3928FE,
 605                 },
 606                 {
 607                 0x24382400,
 608                 0x28371F04,
 609                 0x2C361B08,
 610                 0x3035160C,
 611                 0x113433F7,
 612                 0x163530F9,
 613                 0x1B362CFB,
 614                 0x1F3728FE,
 615                 },
 616         };
 617
 618         /* Coefficients for vertical up-sampling */
 619         static const u32 coef_vup[8] = {
 620                 0x00000000,
 621                 0x0000FF00,
 622                 0x0000FEFF,
 623                 0x0000FBFE,
 624                 0x000000F7,
 625                 0x0000FEFB,
 626                 0x0000FFFE,
 627                 0x000000FF,
 628         };
 629
 630
 631         /* Coefficients for vertical down-sampling */
 632         static const u32 coef_vdown[8] = {
 633                 0x00000000,
 634                 0x000004FE,
 635                 0x000008FB,
 636                 0x00000CF9,
 637                 0x0000F711,
 638                 0x0000F90C,
 639                 0x0000FB08,
 640                 0x0000FE04,
 641         };
 642
 643         const u32 *h_coef;
 644         const u32 *hv_coef;
 645         const u32 *hv_coef_mod;
 646         const u32 *v_coef;
 647         int i;
 648
 649         if (hscaleup)
 650                 h_coef = coef_hup;
 651         else
 652                 h_coef = coef_hdown;
 653
 654         if (vscaleup) {
 655                 hv_coef = coef_hvup[five_taps];
 656                 v_coef = coef_vup;
 657
 658                 if (hscaleup)
 659                         hv_coef_mod = NULL;
 660                 else
 661                         hv_coef_mod = coef_hvdown[five_taps];
 662         } else {
 663                 hv_coef = coef_hvdown[five_taps];
 664                 v_coef = coef_vdown;
 665
 666                 if (hscaleup)
 667                         hv_coef_mod = coef_hvup[five_taps];
 668                 else
 669                         hv_coef_mod = NULL;
 670         }
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = h_coef[i];
 676
 677                 hv = hv_coef[i];
 678
 679                 if (hv_coef_mod) {
 680                         hv &= 0xffffff00;
 681                         hv |= (hv_coef_mod[i] & 0xff);
 682                 }
 683
 684                 _dispc_write_firh_reg(plane, i, h);
 685                 _dispc_write_firhv_reg(plane, i, hv);
 686         }
 687
 688         if (!five_taps)
 689                 return;
 690
 691         for (i = 0; i < 8; i++) {
 692                 u32 v;
 693                 v = v_coef[i];
 694                 _dispc_write_firv_reg(plane, i, v);
 695         }
 696 }
 697
 698 static void _dispc_setup_color_conv_coef(void)
 699 {
 700         const struct color_conv_coef {
 701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 702                 int  full_range;
 703         }  ctbl_bt601_5 = {
 704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 705         };
 706
 707         const struct color_conv_coef *ct;
 708
 709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 710
 711         ct = &ctbl_bt601_5;
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 718
 719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 724
 725 #undef CVAL
 726
 727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 729 }
 730
 731
 732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 733 {
 734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 735                 DISPC_VID_BA0(0),
 736                 DISPC_VID_BA0(1) };
 737
 738         dispc_write_reg(ba0_reg[plane], paddr);
 739 }
 740
 741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 742 {
 743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 744                                       DISPC_VID_BA1(0),
 745                                       DISPC_VID_BA1(1) };
 746
 747         dispc_write_reg(ba1_reg[plane], paddr);
 748 }
 749
 750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 751 {
 752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 753                                       DISPC_VID_POSITION(0),
 754                                       DISPC_VID_POSITION(1) };
 755
 756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 757         dispc_write_reg(pos_reg[plane], val);
 758 }
 759
 760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 761 {
 762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 763                                       DISPC_VID_PICTURE_SIZE(0),
 764                                       DISPC_VID_PICTURE_SIZE(1) };
 765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 766         dispc_write_reg(siz_reg[plane], val);
 767 }
 768
 769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 770 {
 771         u32 val;
 772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 773                                       DISPC_VID_SIZE(1) };
 774
 775         BUG_ON(plane == OMAP_DSS_GFX);
 776
 777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 778         dispc_write_reg(vsi_reg[plane-1], val);
 779 }
 780
 781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 782 {
 783         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 784                                      DISPC_VID_PIXEL_INC(0),
 785                                      DISPC_VID_PIXEL_INC(1) };
 786
 787         dispc_write_reg(ri_reg[plane], inc);
 788 }
 789
 790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 791 {
 792         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 793                                      DISPC_VID_ROW_INC(0),
 794                                      DISPC_VID_ROW_INC(1) };
 795
 796         dispc_write_reg(ri_reg[plane], inc);
 797 }
 798
 799 static void _dispc_set_color_mode(enum omap_plane plane,
 800                 enum omap_color_mode color_mode)
 801 {
 802         u32 m = 0;
 803
 804         switch (color_mode) {
 805         case OMAP_DSS_COLOR_CLUT1:
 806                 m = 0x0; break;
 807         case OMAP_DSS_COLOR_CLUT2:
 808                 m = 0x1; break;
 809         case OMAP_DSS_COLOR_CLUT4:
 810                 m = 0x2; break;
 811         case OMAP_DSS_COLOR_CLUT8:
 812                 m = 0x3; break;
 813         case OMAP_DSS_COLOR_RGB12U:
 814                 m = 0x4; break;
 815         case OMAP_DSS_COLOR_ARGB16:
 816                 m = 0x5; break;
 817         case OMAP_DSS_COLOR_RGB16:
 818                 m = 0x6; break;
 819         case OMAP_DSS_COLOR_RGB24U:
 820                 m = 0x8; break;
 821         case OMAP_DSS_COLOR_RGB24P:
 822                 m = 0x9; break;
 823         case OMAP_DSS_COLOR_YUV2:
 824                 m = 0xa; break;
 825         case OMAP_DSS_COLOR_UYVY:
 826                 m = 0xb; break;
 827         case OMAP_DSS_COLOR_ARGB32:
 828                 m = 0xc; break;
 829         case OMAP_DSS_COLOR_RGBA32:
 830                 m = 0xd; break;
 831         case OMAP_DSS_COLOR_RGBX32:
 832                 m = 0xe; break;
 833         default:
 834                 BUG(); break;
 835         }
 836
 837         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 838 }
 839
 840 static void _dispc_set_channel_out(enum omap_plane plane,
 841                 enum omap_channel channel)
 842 {
 843         int shift;
 844         u32 val;
 845
 846         switch (plane) {
 847         case OMAP_DSS_GFX:
 848                 shift = 8;
 849                 break;
 850         case OMAP_DSS_VIDEO1:
 851         case OMAP_DSS_VIDEO2:
 852                 shift = 16;
 853                 break;
 854         default:
 855                 BUG();
 856                 return;
 857         }
 858
 859         val = dispc_read_reg(dispc_reg_att[plane]);
 860         val = FLD_MOD(val, channel, shift, shift);
 861         dispc_write_reg(dispc_reg_att[plane], val);
 862 }
 863
 864 void dispc_set_burst_size(enum omap_plane plane,
 865                 enum omap_burst_size burst_size)
 866 {
 867         int shift;
 868         u32 val;
 869
 870         enable_clocks(1);
 871
 872         switch (plane) {
 873         case OMAP_DSS_GFX:
 874                 shift = 6;
 875                 break;
 876         case OMAP_DSS_VIDEO1:
 877         case OMAP_DSS_VIDEO2:
 878                 shift = 14;
 879                 break;
 880         default:
 881                 BUG();
 882                 return;
 883         }
 884
 885         val = dispc_read_reg(dispc_reg_att[plane]);
 886         val = FLD_MOD(val, burst_size, shift+1, shift);
 887         dispc_write_reg(dispc_reg_att[plane], val);
 888
 889         enable_clocks(0);
 890 }
 891
 892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 893 {
 894         u32 val;
 895
 896         BUG_ON(plane == OMAP_DSS_GFX);
 897
 898         val = dispc_read_reg(dispc_reg_att[plane]);
 899         val = FLD_MOD(val, enable, 9, 9);
 900         dispc_write_reg(dispc_reg_att[plane], val);
 901 }
 902
 903 void dispc_set_lcd_size(u16 width, u16 height)
 904 {
 905         u32 val;
 906         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 907         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 908         enable_clocks(1);
 909         dispc_write_reg(DISPC_SIZE_LCD, val);
 910         enable_clocks(0);
 911 }
 912
 913 void dispc_set_digit_size(u16 width, u16 height)
 914 {
 915         u32 val;
 916         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 917         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 918         enable_clocks(1);
 919         dispc_write_reg(DISPC_SIZE_DIG, val);
 920         enable_clocks(0);
 921 }
 922
 923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 924 {
 925         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 926                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 927                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 928         u32 size;
 929
 930         enable_clocks(1);
 931
 932         if (cpu_is_omap24xx())
 933                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 934         else if (cpu_is_omap34xx())
 935                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 936         else
 937                 BUG();
 938
 939         if (cpu_is_omap34xx()) {
 940                 /* FIFOMERGE */
 941                 if (REG_GET(DISPC_CONFIG, 14, 14))
 942                         size *= 3;
 943         }
 944
 945         enable_clocks(0);
 946
 947         return size;
 948 }
 949
 950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 951 {
 952         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 953                                        DISPC_VID_FIFO_THRESHOLD(0),
 954                                        DISPC_VID_FIFO_THRESHOLD(1) };
 955         u32 size;
 956
 957         enable_clocks(1);
 958
 959         size = dispc_get_plane_fifo_size(plane);
 960
 961         BUG_ON(low > size || high > size);
 962
 963         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
 964                         plane, size,
 965                         REG_GET(ftrs_reg[plane], 11, 0),
 966                         REG_GET(ftrs_reg[plane], 27, 16),
 967                         low, high);
 968
 969         if (cpu_is_omap24xx())
 970                 dispc_write_reg(ftrs_reg[plane],
 971                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
 972         else
 973                 dispc_write_reg(ftrs_reg[plane],
 974                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
 975
 976         enable_clocks(0);
 977 }
 978
 979 void dispc_enable_fifomerge(bool enable)
 980 {
 981         enable_clocks(1);
 982
 983         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
 984         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
 985
 986         enable_clocks(0);
 987 }
 988
 989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
 990 {
 991         u32 val;
 992         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
 993                                       DISPC_VID_FIR(1) };
 994
 995         BUG_ON(plane == OMAP_DSS_GFX);
 996
 997         val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
 998         dispc_write_reg(fir_reg[plane-1], val);
 999 }
1000
1001 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1002 {
1003         u32 val;
1004         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1005                                       DISPC_VID_ACCU0(1) };
1006
1007         BUG_ON(plane == OMAP_DSS_GFX);
1008
1009         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1010         dispc_write_reg(ac0_reg[plane-1], val);
1011 }
1012
1013 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1014 {
1015         u32 val;
1016         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1017                                       DISPC_VID_ACCU1(1) };
1018
1019         BUG_ON(plane == OMAP_DSS_GFX);
1020
1021         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1022         dispc_write_reg(ac1_reg[plane-1], val);
1023 }
1024
1025
1026 static void _dispc_set_scaling(enum omap_plane plane,
1027                 u16 orig_width, u16 orig_height,
1028                 u16 out_width, u16 out_height,
1029                 bool ilace, bool five_taps)
1030 {
1031         int fir_hinc;
1032         int fir_vinc;
1033         int hscaleup, vscaleup;
1034         int fieldmode = 0;
1035         int accu0 = 0;
1036         int accu1 = 0;
1037         u32 l;
1038
1039         BUG_ON(plane == OMAP_DSS_GFX);
1040
1041         hscaleup = orig_width <= out_width;
1042         vscaleup = orig_height <= out_height;
1043
1044         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1045
1046         if (!orig_width || orig_width == out_width)
1047                 fir_hinc = 0;
1048         else
1049                 fir_hinc = 1024 * orig_width / out_width;
1050
1051         if (!orig_height || orig_height == out_height)
1052                 fir_vinc = 0;
1053         else
1054                 fir_vinc = 1024 * orig_height / out_height;
1055
1056         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1057
1058         l = dispc_read_reg(dispc_reg_att[plane]);
1059         l &= ~((0x0f << 5) | (0x3 << 21));
1060
1061         l |= fir_hinc ? (1 << 5) : 0;
1062         l |= fir_vinc ? (1 << 6) : 0;
1063
1064         l |= hscaleup ? 0 : (1 << 7);
1065         l |= vscaleup ? 0 : (1 << 8);
1066
1067         l |= five_taps ? (1 << 21) : 0;
1068         l |= five_taps ? (1 << 22) : 0;
1069
1070         dispc_write_reg(dispc_reg_att[plane], l);
1071
1072         if (ilace) {
1073                 if (fieldmode) {
1074                         accu0 = fir_vinc / 2;
1075                         accu1 = 0;
1076                 } else {
1077                         accu0 = 0;
1078                         accu1 = fir_vinc / 2;
1079                         if (accu1 >= 1024/2) {
1080                                 accu0 = 1024/2;
1081                                 accu1 -= accu0;
1082                         }
1083                 }
1084         }
1085
1086         _dispc_set_vid_accu0(plane, 0, accu0);
1087         _dispc_set_vid_accu1(plane, 0, accu1);
1088 }
1089
1090 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1091                 bool mirroring, enum omap_color_mode color_mode)
1092 {
1093         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1094                         color_mode == OMAP_DSS_COLOR_UYVY) {
1095                 int vidrot = 0;
1096
1097                 if (mirroring) {
1098                         switch (rotation) {
1099                         case 0: vidrot = 2; break;
1100                         case 1: vidrot = 3; break;
1101                         case 2: vidrot = 0; break;
1102                         case 3: vidrot = 1; break;
1103                         }
1104                 } else {
1105                         switch (rotation) {
1106                         case 0: vidrot = 0; break;
1107                         case 1: vidrot = 1; break;
1108                         case 2: vidrot = 2; break;
1109                         case 3: vidrot = 1; break;
1110                         }
1111                 }
1112
1113                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1114
1115                 if (rotation == 1 || rotation == 3)
1116                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1117                 else
1118                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1119         } else {
1120                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1121                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1122         }
1123 }
1124
1125 static s32 pixinc(int pixels, u8 ps)
1126 {
1127         if (pixels == 1)
1128                 return 1;
1129         else if (pixels > 1)
1130                 return 1 + (pixels - 1) * ps;
1131         else if (pixels < 0)
1132                 return 1 - (-pixels + 1) * ps;
1133         else
1134                 BUG();
1135 }
1136
1137 static void calc_rotation_offset(u8 rotation, bool mirror,
1138                 u16 screen_width,
1139                 u16 width, u16 height,
1140                 enum omap_color_mode color_mode, bool fieldmode,
1141                 unsigned *offset0, unsigned *offset1,
1142                 s32 *row_inc, s32 *pix_inc)
1143 {
1144         u8 ps;
1145         u16 fbw, fbh;
1146
1147         switch (color_mode) {
1148         case OMAP_DSS_COLOR_RGB16:
1149         case OMAP_DSS_COLOR_ARGB16:
1150                 ps = 2;
1151                 break;
1152
1153         case OMAP_DSS_COLOR_RGB24P:
1154                 ps = 3;
1155                 break;
1156
1157         case OMAP_DSS_COLOR_RGB24U:
1158         case OMAP_DSS_COLOR_ARGB32:
1159         case OMAP_DSS_COLOR_RGBA32:
1160         case OMAP_DSS_COLOR_RGBX32:
1161                 ps = 4;
1162                 break;
1163
1164         case OMAP_DSS_COLOR_YUV2:
1165         case OMAP_DSS_COLOR_UYVY:
1166                 ps = 2;
1167                 break;
1168         default:
1169                 BUG();
1170                 return;
1171         }
1172
1173         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1174                         width, height);
1175
1176         /* width & height are overlay sizes, convert to fb sizes */
1177
1178         if (rotation == 0 || rotation == 2) {
1179                 fbw = width;
1180                 fbh = height;
1181         } else {
1182                 fbw = height;
1183                 fbh = width;
1184         }
1185
1186         switch (rotation + mirror * 4) {
1187         case 0:
1188                 *offset0 = 0;
1189                 if (fieldmode)
1190                         *offset1 = screen_width * ps;
1191                 else
1192                         *offset1 = 0;
1193                 *row_inc = pixinc(1 + (screen_width - fbw) +
1194                                 (fieldmode ? screen_width : 0),
1195                                 ps);
1196                 *pix_inc = pixinc(1, ps);
1197                 break;
1198         case 1:
1199                 *offset0 = screen_width * (fbh - 1) * ps;
1200                 if (fieldmode)
1201                         *offset1 = *offset0 + ps;
1202                 else
1203                         *offset1 = *offset0;
1204                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1205                                 (fieldmode ? 1 : 0), ps);
1206                 *pix_inc = pixinc(-screen_width, ps);
1207                 break;
1208         case 2:
1209                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1210                 if (fieldmode)
1211                         *offset1 = *offset0 - screen_width * ps;
1212                 else
1213                         *offset1 = *offset0;
1214                 *row_inc = pixinc(-1 -
1215                                 (screen_width - fbw) -
1216                                 (fieldmode ? screen_width : 0),
1217                                 ps);
1218                 *pix_inc = pixinc(-1, ps);
1219                 break;
1220         case 3:
1221                 *offset0 = (fbw - 1) * ps;
1222                 if (fieldmode)
1223                         *offset1 = *offset0 - ps;
1224                 else
1225                         *offset1 = *offset0;
1226                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1227                                 (fieldmode ? 1 : 0), ps);
1228                 *pix_inc = pixinc(screen_width, ps);
1229                 break;
1230
1231         /* mirroring */
1232         case 0 + 4:
1233                 *offset0 = (fbw - 1) * ps;
1234                 if (fieldmode)
1235                         *offset1 = *offset0 + screen_width * ps;
1236                 else
1237                         *offset1 = *offset0;
1238                 *row_inc = pixinc(screen_width * 2 - 1 +
1239                                 (fieldmode ? screen_width : 0),
1240                                 ps);
1241                 *pix_inc = pixinc(-1, ps);
1242                 break;
1243
1244         case 1 + 4:
1245                 *offset0 = 0;
1246                 if (fieldmode)
1247                         *offset1 = *offset0 + screen_width * ps;
1248                 else
1249                         *offset1 = *offset0;
1250                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1251                                 (fieldmode ? 1 : 0),
1252                                 ps);
1253                 *pix_inc = pixinc(screen_width, ps);
1254                 break;
1255
1256         case 2 + 4:
1257                 *offset0 = screen_width * (fbh - 1) * ps;
1258                 if (fieldmode)
1259                         *offset1 = *offset0 + screen_width * ps;
1260                 else
1261                         *offset1 = *offset0;
1262                 *row_inc = pixinc(1 - screen_width * 2 -
1263                                 (fieldmode ? screen_width : 0),
1264                                 ps);
1265                 *pix_inc = pixinc(1, ps);
1266                 break;
1267
1268         case 3 + 4:
1269                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1270                 if (fieldmode)
1271                         *offset1 = *offset0 + screen_width * ps;
1272                 else
1273                         *offset1 = *offset0;
1274                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1275                                 (fieldmode ? 1 : 0),
1276                                 ps);
1277                 *pix_inc = pixinc(-screen_width, ps);
1278                 break;
1279
1280         default:
1281                 BUG();
1282         }
1283 }
1284
1285 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1286                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1287 {
1288         u32 fclk = 0;
1289         /* FIXME venc pclk? */
1290         u64 tmp, pclk = dispc_pclk_rate();
1291
1292         if (height > out_height) {
1293                 /* FIXME get real display PPL */
1294                 unsigned int ppl = 800;
1295
1296                 tmp = pclk * height * out_width;
1297                 do_div(tmp, 2 * out_height * ppl);
1298                 fclk = tmp;
1299
1300                 if (height > 2 * out_height) {
1301                         tmp = pclk * (height - 2 * out_height) * out_width;
1302                         do_div(tmp, 2 * out_height * (ppl - out_width));
1303                         fclk = max(fclk, (u32) tmp);
1304                 }
1305         }
1306
1307         if (width > out_width) {
1308                 tmp = pclk * width;
1309                 do_div(tmp, out_width);
1310                 fclk = max(fclk, (u32) tmp);
1311
1312                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1313                         fclk <<= 1;
1314         }
1315
1316         return fclk;
1317 }
1318
1319 static unsigned long calc_fclk(u16 width, u16 height,
1320                 u16 out_width, u16 out_height,
1321                 enum omap_color_mode color_mode, bool five_taps)
1322 {
1323         unsigned int hf, vf;
1324
1325         if (five_taps)
1326                 return calc_fclk_five_taps(width, height,
1327                                 out_width, out_height, color_mode);
1328
1329         /*
1330          * FIXME how to determine the 'A' factor
1331          * for the no downscaling case ?
1332          */
1333
1334         if (width > 3 * out_width)
1335                 hf = 4;
1336         else if (width > 2 * out_width)
1337                 hf = 3;
1338         else if (width > out_width)
1339                 hf = 2;
1340         else
1341                 hf = 1;
1342
1343         if (height > out_height)
1344                 vf = 2;
1345         else
1346                 vf = 1;
1347
1348         /* FIXME venc pclk? */
1349         return dispc_pclk_rate() * vf * hf;
1350 }
1351
1352 static int _dispc_setup_plane(enum omap_plane plane,
1353                 enum omap_channel channel_out,
1354                 u32 paddr, u16 screen_width,
1355                 u16 pos_x, u16 pos_y,
1356                 u16 width, u16 height,
1357                 u16 out_width, u16 out_height,
1358                 enum omap_color_mode color_mode,
1359                 bool ilace,
1360                 u8 rotation, int mirror)
1361 {
1362         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1363         bool five_taps = 0;
1364         bool fieldmode = 0;
1365         int cconv = 0;
1366         unsigned offset0, offset1;
1367         s32 row_inc;
1368         s32 pix_inc;
1369
1370         if (paddr == 0)
1371                 return -EINVAL;
1372
1373         if (plane == OMAP_DSS_GFX) {
1374                 if (width != out_width || height != out_height)
1375                         return -EINVAL;
1376
1377                 switch (color_mode) {
1378                 case OMAP_DSS_COLOR_ARGB16:
1379                 case OMAP_DSS_COLOR_RGB16:
1380                 case OMAP_DSS_COLOR_RGB24P:
1381                 case OMAP_DSS_COLOR_RGB24U:
1382                 case OMAP_DSS_COLOR_ARGB32:
1383                 case OMAP_DSS_COLOR_RGBA32:
1384                 case OMAP_DSS_COLOR_RGBX32:
1385                         break;
1386
1387                 default:
1388                         return -EINVAL;
1389                 }
1390         } else {
1391                 /* video plane */
1392
1393                 unsigned long fclk;
1394
1395                 if (out_width < width / maxdownscale ||
1396                    out_width > width * 8)
1397                         return -EINVAL;
1398
1399                 if (out_height < height / maxdownscale ||
1400                    out_height > height * 8)
1401                         return -EINVAL;
1402
1403                 switch (color_mode) {
1404                 case OMAP_DSS_COLOR_RGB16:
1405                 case OMAP_DSS_COLOR_RGB24P:
1406                 case OMAP_DSS_COLOR_RGB24U:
1407                 case OMAP_DSS_COLOR_RGBX32:
1408                         break;
1409
1410                 case OMAP_DSS_COLOR_ARGB16:
1411                 case OMAP_DSS_COLOR_ARGB32:
1412                 case OMAP_DSS_COLOR_RGBA32:
1413                         if (plane == OMAP_DSS_VIDEO1)
1414                                 return -EINVAL;
1415                         break;
1416
1417                 case OMAP_DSS_COLOR_YUV2:
1418                 case OMAP_DSS_COLOR_UYVY:
1419                         cconv = 1;
1420                         break;
1421
1422                 default:
1423                         return -EINVAL;
1424                 }
1425
1426                 /* Must use 5-tap filter? */
1427                 five_taps = height > out_height * 2;
1428
1429                 /* Try to use 5-tap filter whenever possible. */
1430                 if (cpu_is_omap34xx() && !five_taps &&
1431                     height > out_height && width <= 1024) {
1432                         fclk = calc_fclk_five_taps(width, height,
1433                                         out_width, out_height, color_mode);
1434                         if (fclk <= dispc_fclk_rate())
1435                                 five_taps = true;
1436                 }
1437
1438                 if (width > (2048 >> five_taps))
1439                         return -EINVAL;
1440
1441                 fclk = calc_fclk(width, height, out_width, out_height,
1442                                 color_mode, five_taps);
1443
1444                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1445                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1446
1447                 if (fclk > dispc_fclk_rate())
1448                         return -EINVAL;
1449         }
1450
1451         if (ilace && height >= out_height)
1452                 fieldmode = 1;
1453
1454         calc_rotation_offset(rotation, mirror,
1455                         screen_width, width, height, color_mode,
1456                         fieldmode,
1457                         &offset0, &offset1, &row_inc, &pix_inc);
1458
1459         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1460                         offset0, offset1, row_inc, pix_inc);
1461
1462         if (ilace) {
1463                 if (fieldmode)
1464                         height /= 2;
1465                 pos_y /= 2;
1466                 out_height /= 2;
1467
1468                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1469                                 "out_height %d\n",
1470                                 height, pos_y, out_height);
1471         }
1472
1473         _dispc_set_channel_out(plane, channel_out);
1474         _dispc_set_color_mode(plane, color_mode);
1475
1476         _dispc_set_plane_ba0(plane, paddr + offset0);
1477         _dispc_set_plane_ba1(plane, paddr + offset1);
1478
1479         _dispc_set_row_inc(plane, row_inc);
1480         _dispc_set_pix_inc(plane, pix_inc);
1481
1482         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1483                         out_width, out_height);
1484
1485         _dispc_set_plane_pos(plane, pos_x, pos_y);
1486
1487         _dispc_set_pic_size(plane, width, height);
1488
1489         if (plane != OMAP_DSS_GFX) {
1490                 _dispc_set_scaling(plane, width, height,
1491                                    out_width, out_height,
1492                                    ilace, five_taps);
1493                 _dispc_set_vid_size(plane, out_width, out_height);
1494                 _dispc_set_vid_color_conv(plane, cconv);
1495         }
1496
1497         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1498
1499         return 0;
1500 }
1501
1502 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1503 {
1504         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1505 }
1506
1507 static void dispc_disable_isr(void *data, u32 mask)
1508 {
1509         struct completion *compl = data;
1510         complete(compl);
1511 }
1512
1513 static void _enable_lcd_out(bool enable)
1514 {
1515         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1516 }
1517
1518 void dispc_enable_lcd_out(bool enable)
1519 {
1520         struct completion frame_done_completion;
1521         bool is_on;
1522         int r;
1523
1524         enable_clocks(1);
1525
1526         /* When we disable LCD output, we need to wait until frame is done.
1527          * Otherwise the DSS is still working, and turning off the clocks
1528          * prevents DSS from going to OFF mode */
1529         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1530
1531         if (!enable && is_on) {
1532                 init_completion(&frame_done_completion);
1533
1534                 r = omap_dispc_register_isr(dispc_disable_isr,
1535                                 &frame_done_completion,
1536                                 DISPC_IRQ_FRAMEDONE);
1537
1538                 if (r)
1539                         DSSERR("failed to register FRAMEDONE isr\n");
1540         }
1541
1542         _enable_lcd_out(enable);
1543
1544         if (!enable && is_on) {
1545                 if (!wait_for_completion_timeout(&frame_done_completion,
1546                                         msecs_to_jiffies(100)))
1547                         DSSERR("timeout waiting for FRAME DONE\n");
1548
1549                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1550                                 &frame_done_completion,
1551                                 DISPC_IRQ_FRAMEDONE);
1552
1553                 if (r)
1554                         DSSERR("failed to unregister FRAMEDONE isr\n");
1555         }
1556
1557         enable_clocks(0);
1558 }
1559
1560 static void _enable_digit_out(bool enable)
1561 {
1562         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1563 }
1564
1565 void dispc_enable_digit_out(bool enable)
1566 {
1567         struct completion frame_done_completion;
1568         int r;
1569
1570         enable_clocks(1);
1571
1572         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1573                 enable_clocks(0);
1574                 return;
1575         }
1576
1577         if (enable) {
1578                 /* When we enable digit output, we'll get an extra digit
1579                  * sync lost interrupt, that we need to ignore */
1580                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1581                 omap_dispc_set_irqs();
1582         }
1583
1584         /* When we disable digit output, we need to wait until fields are done.
1585          * Otherwise the DSS is still working, and turning off the clocks
1586          * prevents DSS from going to OFF mode. And when enabling, we need to
1587          * wait for the extra sync losts */
1588         init_completion(&frame_done_completion);
1589
1590         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1591                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1592         if (r)
1593                 DSSERR("failed to register EVSYNC isr\n");
1594
1595         _enable_digit_out(enable);
1596
1597         /* XXX I understand from TRM that we should only wait for the
1598          * current field to complete. But it seems we have to wait
1599          * for both fields */
1600         if (!wait_for_completion_timeout(&frame_done_completion,
1601                                 msecs_to_jiffies(100)))
1602                 DSSERR("timeout waiting for EVSYNC\n");
1603
1604         if (!wait_for_completion_timeout(&frame_done_completion,
1605                                 msecs_to_jiffies(100)))
1606                 DSSERR("timeout waiting for EVSYNC\n");
1607
1608         r = omap_dispc_unregister_isr(dispc_disable_isr,
1609                         &frame_done_completion,
1610                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1611         if (r)
1612                 DSSERR("failed to unregister EVSYNC isr\n");
1613
1614         if (enable) {
1615                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1616                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1617                 omap_dispc_set_irqs();
1618         }
1619
1620         enable_clocks(0);
1621 }
1622
1623 void dispc_lcd_enable_signal_polarity(bool act_high)
1624 {
1625         enable_clocks(1);
1626         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1627         enable_clocks(0);
1628 }
1629
1630 void dispc_lcd_enable_signal(bool enable)
1631 {
1632         enable_clocks(1);
1633         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1634         enable_clocks(0);
1635 }
1636
1637 void dispc_pck_free_enable(bool enable)
1638 {
1639         enable_clocks(1);
1640         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1641         enable_clocks(0);
1642 }
1643
1644 void dispc_enable_fifohandcheck(bool enable)
1645 {
1646         enable_clocks(1);
1647         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1648         enable_clocks(0);
1649 }
1650
1651
1652 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1653 {
1654         int mode;
1655
1656         switch (type) {
1657         case OMAP_DSS_LCD_DISPLAY_STN:
1658                 mode = 0;
1659                 break;
1660
1661         case OMAP_DSS_LCD_DISPLAY_TFT:
1662                 mode = 1;
1663                 break;
1664
1665         default:
1666                 BUG();
1667                 return;
1668         }
1669
1670         enable_clocks(1);
1671         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1672         enable_clocks(0);
1673 }
1674
1675 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1676 {
1677         enable_clocks(1);
1678         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1679         enable_clocks(0);
1680 }
1681
1682
1683 void dispc_set_default_color(enum omap_channel channel, u32 color)
1684 {
1685         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1686                                 DISPC_DEFAULT_COLOR1 };
1687
1688         enable_clocks(1);
1689         dispc_write_reg(def_reg[channel], color);
1690         enable_clocks(0);
1691 }
1692
1693 u32 dispc_get_default_color(enum omap_channel channel)
1694 {
1695         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1696                                 DISPC_DEFAULT_COLOR1 };
1697         u32 l;
1698
1699         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1700                channel != OMAP_DSS_CHANNEL_LCD);
1701
1702         enable_clocks(1);
1703         l = dispc_read_reg(def_reg[channel]);
1704         enable_clocks(0);
1705
1706         return l;
1707 }
1708
1709 void dispc_set_trans_key(enum omap_channel ch,
1710                 enum omap_dss_color_key_type type,
1711                 u32 trans_key)
1712 {
1713         const struct dispc_reg tr_reg[] = {
1714                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1715
1716         enable_clocks(1);
1717         if (ch == OMAP_DSS_CHANNEL_LCD)
1718                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1719         else /* OMAP_DSS_CHANNEL_DIGIT */
1720                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1721
1722         dispc_write_reg(tr_reg[ch], trans_key);
1723         enable_clocks(0);
1724 }
1725
1726 void dispc_get_trans_key(enum omap_channel ch,
1727                 enum omap_dss_color_key_type *type,
1728                 u32 *trans_key)
1729 {
1730         const struct dispc_reg tr_reg[] = {
1731                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1732
1733         enable_clocks(1);
1734         if (type) {
1735                 if (ch == OMAP_DSS_CHANNEL_LCD)
1736                         *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
1737                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1738                         *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
1739                 else
1740                         BUG();
1741         }
1742
1743         if (trans_key)
1744                 *trans_key = dispc_read_reg(tr_reg[ch]);
1745         enable_clocks(0);
1746 }
1747
1748 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1749 {
1750         enable_clocks(1);
1751         if (ch == OMAP_DSS_CHANNEL_LCD)
1752                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1753         else /* OMAP_DSS_CHANNEL_DIGIT */
1754                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1755         enable_clocks(0);
1756 }
1757
1758 bool dispc_trans_key_enabled(enum omap_channel ch)
1759 {
1760         bool enabled;
1761
1762         enable_clocks(1);
1763         if (ch == OMAP_DSS_CHANNEL_LCD)
1764                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1765         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1766                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1767         else BUG();
1768         enable_clocks(0);
1769
1770         return enabled;
1771 }
1772
1773
1774 void dispc_set_tft_data_lines(u8 data_lines)
1775 {
1776         int code;
1777
1778         switch (data_lines) {
1779         case 12:
1780                 code = 0;
1781                 break;
1782         case 16:
1783                 code = 1;
1784                 break;
1785         case 18:
1786                 code = 2;
1787                 break;
1788         case 24:
1789                 code = 3;
1790                 break;
1791         default:
1792                 BUG();
1793                 return;
1794         }
1795
1796         enable_clocks(1);
1797         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1798         enable_clocks(0);
1799 }
1800
1801 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1802 {
1803         u32 l;
1804         int stallmode;
1805         int gpout0 = 1;
1806         int gpout1;
1807
1808         switch (mode) {
1809         case OMAP_DSS_PARALLELMODE_BYPASS:
1810                 stallmode = 0;
1811                 gpout1 = 1;
1812                 break;
1813
1814         case OMAP_DSS_PARALLELMODE_RFBI:
1815                 stallmode = 1;
1816                 gpout1 = 0;
1817                 break;
1818
1819         case OMAP_DSS_PARALLELMODE_DSI:
1820                 stallmode = 1;
1821                 gpout1 = 1;
1822                 break;
1823
1824         default:
1825                 BUG();
1826                 return;
1827         }
1828
1829         enable_clocks(1);
1830
1831         l = dispc_read_reg(DISPC_CONTROL);
1832
1833         l = FLD_MOD(l, stallmode, 11, 11);
1834         l = FLD_MOD(l, gpout0, 15, 15);
1835         l = FLD_MOD(l, gpout1, 16, 16);
1836
1837         dispc_write_reg(DISPC_CONTROL, l);
1838
1839         enable_clocks(0);
1840 }
1841
1842 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1843                                    int vsw, int vfp, int vbp)
1844 {
1845         u32 timing_h, timing_v;
1846
1847         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1848                 BUG_ON(hsw < 1 || hsw > 64);
1849                 BUG_ON(hfp < 1 || hfp > 256);
1850                 BUG_ON(hbp < 1 || hbp > 256);
1851
1852                 BUG_ON(vsw < 1 || vsw > 64);
1853                 BUG_ON(vfp < 0 || vfp > 255);
1854                 BUG_ON(vbp < 0 || vbp > 255);
1855
1856                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1857                         FLD_VAL(hbp-1, 27, 20);
1858
1859                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1860                         FLD_VAL(vbp, 27, 20);
1861         } else {
1862                 BUG_ON(hsw < 1 || hsw > 256);
1863                 BUG_ON(hfp < 1 || hfp > 4096);
1864                 BUG_ON(hbp < 1 || hbp > 4096);
1865
1866                 BUG_ON(vsw < 1 || vsw > 256);
1867                 BUG_ON(vfp < 0 || vfp > 4095);
1868                 BUG_ON(vbp < 0 || vbp > 4095);
1869
1870                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1871                         FLD_VAL(hbp-1, 31, 20);
1872
1873                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1874                         FLD_VAL(vbp, 31, 20);
1875         }
1876
1877         enable_clocks(1);
1878         dispc_write_reg(DISPC_TIMING_H, timing_h);
1879         dispc_write_reg(DISPC_TIMING_V, timing_v);
1880         enable_clocks(0);
1881 }
1882
1883 /* change name to mode? */
1884 void dispc_set_lcd_timings(struct omap_video_timings *timings)
1885 {
1886         unsigned xtot, ytot;
1887         unsigned long ht, vt;
1888
1889         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
1890                         timings->vsw, timings->vfp, timings->vbp);
1891
1892         dispc_set_lcd_size(timings->x_res, timings->y_res);
1893
1894         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
1895         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
1896
1897         ht = (timings->pixel_clock * 1000) / xtot;
1898         vt = (timings->pixel_clock * 1000) / xtot / ytot;
1899
1900         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
1901         DSSDBG("pck %u\n", timings->pixel_clock);
1902         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
1903                         timings->hsw, timings->hfp, timings->hbp,
1904                         timings->vsw, timings->vfp, timings->vbp);
1905
1906         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
1907 }
1908
1909 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
1910 {
1911         BUG_ON(lck_div < 1);
1912         BUG_ON(pck_div < 2);
1913
1914         enable_clocks(1);
1915         dispc_write_reg(DISPC_DIVISOR,
1916                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
1917         enable_clocks(0);
1918 }
1919
1920 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
1921 {
1922         u32 l;
1923         l = dispc_read_reg(DISPC_DIVISOR);
1924         *lck_div = FLD_GET(l, 23, 16);
1925         *pck_div = FLD_GET(l, 7, 0);
1926 }
1927
1928 unsigned long dispc_fclk_rate(void)
1929 {
1930         unsigned long r = 0;
1931
1932         if (dss_get_dispc_clk_source() == 0)
1933                 r = dss_clk_get_rate(DSS_CLK_FCK1);
1934         else
1935 #ifdef CONFIG_OMAP2_DSS_DSI
1936                 r = dsi_get_dsi1_pll_rate();
1937 #else
1938         BUG();
1939 #endif
1940         return r;
1941 }
1942
1943 unsigned long dispc_lclk_rate(void)
1944 {
1945         int lcd;
1946         unsigned long r;
1947         u32 l;
1948
1949         l = dispc_read_reg(DISPC_DIVISOR);
1950
1951         lcd = FLD_GET(l, 23, 16);
1952
1953         r = dispc_fclk_rate();
1954
1955         return r / lcd;
1956 }
1957
1958 unsigned long dispc_pclk_rate(void)
1959 {
1960         int lcd, pcd;
1961         unsigned long r;
1962         u32 l;
1963
1964         l = dispc_read_reg(DISPC_DIVISOR);
1965
1966         lcd = FLD_GET(l, 23, 16);
1967         pcd = FLD_GET(l, 7, 0);
1968
1969         r = dispc_fclk_rate();
1970
1971         return r / lcd / pcd;
1972 }
1973
1974 void dispc_dump_clocks(struct seq_file *s)
1975 {
1976         int lcd, pcd;
1977
1978         enable_clocks(1);
1979
1980         dispc_get_lcd_divisor(&lcd, &pcd);
1981
1982         seq_printf(s, "- dispc -\n");
1983
1984         seq_printf(s, "dispc fclk source = %s\n",
1985                         dss_get_dispc_clk_source() == 0 ?
1986                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
1987
1988         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
1989                         dispc_fclk_rate(),
1990                         lcd, pcd,
1991                         dispc_pclk_rate());
1992
1993         enable_clocks(0);
1994 }
1995
1996 void dispc_dump_regs(struct seq_file *s)
1997 {
1998 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
1999
2000         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2001
2002         DUMPREG(DISPC_REVISION);
2003         DUMPREG(DISPC_SYSCONFIG);
2004         DUMPREG(DISPC_SYSSTATUS);
2005         DUMPREG(DISPC_IRQSTATUS);
2006         DUMPREG(DISPC_IRQENABLE);
2007         DUMPREG(DISPC_CONTROL);
2008         DUMPREG(DISPC_CONFIG);
2009         DUMPREG(DISPC_CAPABLE);
2010         DUMPREG(DISPC_DEFAULT_COLOR0);
2011         DUMPREG(DISPC_DEFAULT_COLOR1);
2012         DUMPREG(DISPC_TRANS_COLOR0);
2013         DUMPREG(DISPC_TRANS_COLOR1);
2014         DUMPREG(DISPC_LINE_STATUS);
2015         DUMPREG(DISPC_LINE_NUMBER);
2016         DUMPREG(DISPC_TIMING_H);
2017         DUMPREG(DISPC_TIMING_V);
2018         DUMPREG(DISPC_POL_FREQ);
2019         DUMPREG(DISPC_DIVISOR);
2020         DUMPREG(DISPC_GLOBAL_ALPHA);
2021         DUMPREG(DISPC_SIZE_DIG);
2022         DUMPREG(DISPC_SIZE_LCD);
2023
2024         DUMPREG(DISPC_GFX_BA0);
2025         DUMPREG(DISPC_GFX_BA1);
2026         DUMPREG(DISPC_GFX_POSITION);
2027         DUMPREG(DISPC_GFX_SIZE);
2028         DUMPREG(DISPC_GFX_ATTRIBUTES);
2029         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2030         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2031         DUMPREG(DISPC_GFX_ROW_INC);
2032         DUMPREG(DISPC_GFX_PIXEL_INC);
2033         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2034         DUMPREG(DISPC_GFX_TABLE_BA);
2035
2036         DUMPREG(DISPC_DATA_CYCLE1);
2037         DUMPREG(DISPC_DATA_CYCLE2);
2038         DUMPREG(DISPC_DATA_CYCLE3);
2039
2040         DUMPREG(DISPC_CPR_COEF_R);
2041         DUMPREG(DISPC_CPR_COEF_G);
2042         DUMPREG(DISPC_CPR_COEF_B);
2043
2044         DUMPREG(DISPC_GFX_PRELOAD);
2045
2046         DUMPREG(DISPC_VID_BA0(0));
2047         DUMPREG(DISPC_VID_BA1(0));
2048         DUMPREG(DISPC_VID_POSITION(0));
2049         DUMPREG(DISPC_VID_SIZE(0));
2050         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2051         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2052         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2053         DUMPREG(DISPC_VID_ROW_INC(0));
2054         DUMPREG(DISPC_VID_PIXEL_INC(0));
2055         DUMPREG(DISPC_VID_FIR(0));
2056         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2057         DUMPREG(DISPC_VID_ACCU0(0));
2058         DUMPREG(DISPC_VID_ACCU1(0));
2059
2060         DUMPREG(DISPC_VID_BA0(1));
2061         DUMPREG(DISPC_VID_BA1(1));
2062         DUMPREG(DISPC_VID_POSITION(1));
2063         DUMPREG(DISPC_VID_SIZE(1));
2064         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2065         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2066         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2067         DUMPREG(DISPC_VID_ROW_INC(1));
2068         DUMPREG(DISPC_VID_PIXEL_INC(1));
2069         DUMPREG(DISPC_VID_FIR(1));
2070         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2071         DUMPREG(DISPC_VID_ACCU0(1));
2072         DUMPREG(DISPC_VID_ACCU1(1));
2073
2074         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2075         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2076         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2077         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2078         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2079         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2080         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2081         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2082         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2083         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2084         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2085         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2086         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2087         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2088         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2089         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2090         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2091         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2092         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2093         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2094         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2095         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2096         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2097         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2098         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2099         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2100         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2101         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2102         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2103
2104         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2105         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2106         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2107         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2108         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2109         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2110         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2111         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2112         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2113         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2114         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2115         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2116         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2117         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2118         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2119         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2120         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2121         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2122         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2123         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2124         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2125         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2126         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2127         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2128         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2129         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2130         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2131         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2132         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2133
2134         DUMPREG(DISPC_VID_PRELOAD(0));
2135         DUMPREG(DISPC_VID_PRELOAD(1));
2136
2137         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2138 #undef DUMPREG
2139 }
2140
2141 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2142                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2143 {
2144         u32 l = 0;
2145
2146         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2147                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2148
2149         l |= FLD_VAL(onoff, 17, 17);
2150         l |= FLD_VAL(rf, 16, 16);
2151         l |= FLD_VAL(ieo, 15, 15);
2152         l |= FLD_VAL(ipc, 14, 14);
2153         l |= FLD_VAL(ihs, 13, 13);
2154         l |= FLD_VAL(ivs, 12, 12);
2155         l |= FLD_VAL(acbi, 11, 8);
2156         l |= FLD_VAL(acb, 7, 0);
2157
2158         enable_clocks(1);
2159         dispc_write_reg(DISPC_POL_FREQ, l);
2160         enable_clocks(0);
2161 }
2162
2163 void dispc_set_pol_freq(struct omap_panel *panel)
2164 {
2165         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2166                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2167                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2168                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2169                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2170                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2171                                  panel->acbi, panel->acb);
2172 }
2173
2174 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2175                 u16 *lck_div, u16 *pck_div)
2176 {
2177         u16 pcd_min = is_tft ? 2 : 3;
2178         unsigned long best_pck;
2179         u16 best_ld, cur_ld;
2180         u16 best_pd, cur_pd;
2181
2182         best_pck = 0;
2183         best_ld = 0;
2184         best_pd = 0;
2185
2186         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2187                 unsigned long lck = fck / cur_ld;
2188
2189                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2190                         unsigned long pck = lck / cur_pd;
2191                         long old_delta = abs(best_pck - req_pck);
2192                         long new_delta = abs(pck - req_pck);
2193
2194                         if (best_pck == 0 || new_delta < old_delta) {
2195                                 best_pck = pck;
2196                                 best_ld = cur_ld;
2197                                 best_pd = cur_pd;
2198
2199                                 if (pck == req_pck)
2200                                         goto found;
2201                         }
2202
2203                         if (pck < req_pck)
2204                                 break;
2205                 }
2206
2207                 if (lck / pcd_min < req_pck)
2208                         break;
2209         }
2210
2211 found:
2212         *lck_div = best_ld;
2213         *pck_div = best_pd;
2214 }
2215
2216 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2217                 struct dispc_clock_info *cinfo)
2218 {
2219         unsigned long prate;
2220         struct dispc_clock_info cur, best;
2221         int match = 0;
2222         int min_fck_per_pck;
2223         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2224
2225         if (cpu_is_omap34xx())
2226                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2227         else
2228                 prate = 0;
2229
2230         if (req_pck == dispc.cache_req_pck &&
2231                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2232                          dispc.cache_cinfo.fck == fck_rate)) {
2233                 DSSDBG("dispc clock info found from cache.\n");
2234                 *cinfo = dispc.cache_cinfo;
2235                 return 0;
2236         }
2237
2238         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2239
2240         if (min_fck_per_pck &&
2241                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2242                 DSSERR("Requested pixel clock not possible with the current "
2243                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2244                                 "the constraint off.\n");
2245                 min_fck_per_pck = 0;
2246         }
2247
2248 retry:
2249         memset(&cur, 0, sizeof(cur));
2250         memset(&best, 0, sizeof(best));
2251
2252         if (cpu_is_omap24xx()) {
2253                 /* XXX can we change the clock on omap2? */
2254                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2255                 cur.fck_div = 1;
2256
2257                 match = 1;
2258
2259                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2260                                 &cur.lck_div, &cur.pck_div);
2261
2262                 cur.lck = cur.fck / cur.lck_div;
2263                 cur.pck = cur.lck / cur.pck_div;
2264
2265                 best = cur;
2266
2267                 goto found;
2268         } else if (cpu_is_omap34xx()) {
2269                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2270                         cur.fck = prate / cur.fck_div * 2;
2271
2272                         if (cur.fck > DISPC_MAX_FCK)
2273                                 continue;
2274
2275                         if (min_fck_per_pck &&
2276                                         cur.fck < req_pck * min_fck_per_pck)
2277                                 continue;
2278
2279                         match = 1;
2280
2281                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2282                                         &cur.lck_div, &cur.pck_div);
2283
2284                         cur.lck = cur.fck / cur.lck_div;
2285                         cur.pck = cur.lck / cur.pck_div;
2286
2287                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2288                                 best = cur;
2289
2290                                 if (cur.pck == req_pck)
2291                                         goto found;
2292                         }
2293                 }
2294         } else {
2295                 BUG();
2296         }
2297
2298 found:
2299         if (!match) {
2300                 if (min_fck_per_pck) {
2301                         DSSERR("Could not find suitable clock settings.\n"
2302                                         "Turning FCK/PCK constraint off and"
2303                                         "trying again.\n");
2304                         min_fck_per_pck = 0;
2305                         goto retry;
2306                 }
2307
2308                 DSSERR("Could not find suitable clock settings.\n");
2309
2310                 return -EINVAL;
2311         }
2312
2313         if (cinfo)
2314                 *cinfo = best;
2315
2316         dispc.cache_req_pck = req_pck;
2317         dispc.cache_prate = prate;
2318         dispc.cache_cinfo = best;
2319
2320         return 0;
2321 }
2322
2323 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2324 {
2325         unsigned long prate;
2326         int r;
2327
2328         if (cpu_is_omap34xx()) {
2329                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2330                 DSSDBG("dpll4_m4 = %ld\n", prate);
2331         }
2332
2333         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2334         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2335         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2336
2337         if (cpu_is_omap34xx()) {
2338                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2339                 if (r)
2340                         return r;
2341         }
2342
2343         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2344
2345         return 0;
2346 }
2347
2348 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2349 {
2350         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2351
2352         if (cpu_is_omap34xx()) {
2353                 unsigned long prate;
2354                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2355                 cinfo->fck_div = prate / (cinfo->fck / 2);
2356         } else {
2357                 cinfo->fck_div = 0;
2358         }
2359
2360         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2361         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2362
2363         cinfo->lck = cinfo->fck / cinfo->lck_div;
2364         cinfo->pck = cinfo->lck / cinfo->pck_div;
2365
2366         return 0;
2367 }
2368
2369 static void omap_dispc_set_irqs(void)
2370 {
2371         unsigned long flags;
2372         u32 mask = dispc.irq_error_mask;
2373         int i;
2374         struct omap_dispc_isr_data *isr_data;
2375
2376         spin_lock_irqsave(&dispc.irq_lock, flags);
2377
2378         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2379                 isr_data = &dispc.registered_isr[i];
2380
2381                 if (isr_data->isr == NULL)
2382                         continue;
2383
2384                 mask |= isr_data->mask;
2385         }
2386
2387         enable_clocks(1);
2388         dispc_write_reg(DISPC_IRQENABLE, mask);
2389         enable_clocks(0);
2390
2391         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2392 }
2393
2394 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2395 {
2396         int i;
2397         int ret;
2398         unsigned long flags;
2399         struct omap_dispc_isr_data *isr_data;
2400
2401         if (isr == NULL)
2402                 return -EINVAL;
2403
2404         spin_lock_irqsave(&dispc.irq_lock, flags);
2405
2406         /* check for duplicate entry */
2407         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2408                 isr_data = &dispc.registered_isr[i];
2409                 if (isr_data->isr == isr && isr_data->arg == arg &&
2410                                 isr_data->mask == mask) {
2411                         ret = -EINVAL;
2412                         goto err;
2413                 }
2414         }
2415
2416         isr_data = NULL;
2417         ret = -EBUSY;
2418
2419         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2420                 isr_data = &dispc.registered_isr[i];
2421
2422                 if (isr_data->isr != NULL)
2423                         continue;
2424
2425                 isr_data->isr = isr;
2426                 isr_data->arg = arg;
2427                 isr_data->mask = mask;
2428                 ret = 0;
2429
2430                 break;
2431         }
2432 err:
2433         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2434
2435         if (ret == 0)
2436                 omap_dispc_set_irqs();
2437
2438         return ret;
2439 }
2440 EXPORT_SYMBOL(omap_dispc_register_isr);
2441
2442 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2443 {
2444         int i;
2445         unsigned long flags;
2446         int ret = -EINVAL;
2447         struct omap_dispc_isr_data *isr_data;
2448
2449         spin_lock_irqsave(&dispc.irq_lock, flags);
2450
2451         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2452                 isr_data = &dispc.registered_isr[i];
2453                 if (isr_data->isr != isr || isr_data->arg != arg ||
2454                                 isr_data->mask != mask)
2455                         continue;
2456
2457                 /* found the correct isr */
2458
2459                 isr_data->isr = NULL;
2460                 isr_data->arg = NULL;
2461                 isr_data->mask = 0;
2462
2463                 ret = 0;
2464                 break;
2465         }
2466
2467         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2468
2469         if (ret == 0)
2470                 omap_dispc_set_irqs();
2471
2472         return ret;
2473 }
2474 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2475
2476 #ifdef DEBUG
2477 static void print_irq_status(u32 status)
2478 {
2479         if ((status & dispc.irq_error_mask) == 0)
2480                 return;
2481
2482         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2483
2484 #define PIS(x) \
2485         if (status & DISPC_IRQ_##x) \
2486                 printk(#x " ");
2487         PIS(GFX_FIFO_UNDERFLOW);
2488         PIS(OCP_ERR);
2489         PIS(VID1_FIFO_UNDERFLOW);
2490         PIS(VID2_FIFO_UNDERFLOW);
2491         PIS(SYNC_LOST);
2492         PIS(SYNC_LOST_DIGIT);
2493 #undef PIS
2494
2495         printk("\n");
2496 }
2497 #endif
2498
2499 /* Called from dss.c. Note that we don't touch clocks here,
2500  * but we presume they are on because we got an IRQ. However,
2501  * an irq handler may turn the clocks off, so we may not have
2502  * clock later in the function. */
2503 void dispc_irq_handler(void)
2504 {
2505         int i;
2506         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2507         u32 handledirqs = 0;
2508         u32 unhandled_errors;
2509         struct omap_dispc_isr_data *isr_data;
2510
2511 #ifdef DEBUG
2512         if (dss_debug)
2513                 print_irq_status(irqstatus);
2514 #endif
2515         /* Ack the interrupt. Do it here before clocks are possibly turned
2516          * off */
2517         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2518
2519         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2520                 isr_data = &dispc.registered_isr[i];
2521
2522                 if (!isr_data->isr)
2523                         continue;
2524
2525                 if (isr_data->mask & irqstatus) {
2526                         isr_data->isr(isr_data->arg, irqstatus);
2527                         handledirqs |= isr_data->mask;
2528                 }
2529         }
2530
2531         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2532
2533         if (unhandled_errors) {
2534                 spin_lock(&dispc.error_lock);
2535                 dispc.error_irqs |= unhandled_errors;
2536                 spin_unlock(&dispc.error_lock);
2537
2538                 dispc.irq_error_mask &= ~unhandled_errors;
2539                 omap_dispc_set_irqs();
2540
2541                 schedule_work(&dispc.error_work);
2542         }
2543 }
2544
2545 static void dispc_error_worker(struct work_struct *work)
2546 {
2547         int i;
2548         u32 errors;
2549         unsigned long flags;
2550
2551         spin_lock_irqsave(&dispc.error_lock, flags);
2552         errors = dispc.error_irqs;
2553         dispc.error_irqs = 0;
2554         spin_unlock_irqrestore(&dispc.error_lock, flags);
2555
2556         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2557                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2558                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2559                         struct omap_overlay *ovl;
2560                         ovl = omap_dss_get_overlay(i);
2561
2562                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2563                                 continue;
2564
2565                         if (ovl->id == 0) {
2566                                 dispc_enable_plane(ovl->id, 0);
2567                                 dispc_go(ovl->manager->id);
2568                                 mdelay(50);
2569                                 break;
2570                         }
2571                 }
2572         }
2573
2574         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2575                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2576                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2577                         struct omap_overlay *ovl;
2578                         ovl = omap_dss_get_overlay(i);
2579
2580                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2581                                 continue;
2582
2583                         if (ovl->id == 1) {
2584                                 dispc_enable_plane(ovl->id, 0);
2585                                 dispc_go(ovl->manager->id);
2586                                 mdelay(50);
2587                                 break;
2588                         }
2589                 }
2590         }
2591
2592         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2593                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2594                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2595                         struct omap_overlay *ovl;
2596                         ovl = omap_dss_get_overlay(i);
2597
2598                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2599                                 continue;
2600
2601                         if (ovl->id == 2) {
2602                                 dispc_enable_plane(ovl->id, 0);
2603                                 dispc_go(ovl->manager->id);
2604                                 mdelay(50);
2605                                 break;
2606                         }
2607                 }
2608         }
2609
2610         if (errors & DISPC_IRQ_SYNC_LOST) {
2611                 struct omap_overlay_manager *manager = NULL;
2612                 bool enable = false;
2613
2614                 DSSERR("SYNC_LOST, disabling LCD\n");
2615
2616                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2617                         struct omap_overlay_manager *mgr;
2618                         mgr = omap_dss_get_overlay_manager(i);
2619
2620                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2621                                 manager = mgr;
2622                                 enable = mgr->display->state ==
2623                                                 OMAP_DSS_DISPLAY_ACTIVE;
2624                                 mgr->display->disable(mgr->display);
2625                                 break;
2626                         }
2627                 }
2628
2629                 if (manager) {
2630                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2631                                 struct omap_overlay *ovl;
2632                                 ovl = omap_dss_get_overlay(i);
2633
2634                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2635                                         continue;
2636
2637                                 if (ovl->id != 0 && ovl->manager == manager)
2638                                         dispc_enable_plane(ovl->id, 0);
2639                         }
2640
2641                         dispc_go(manager->id);
2642                         mdelay(50);
2643                         if (enable)
2644                                 manager->display->enable(manager->display);
2645                 }
2646         }
2647
2648         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2649                 struct omap_overlay_manager *manager = NULL;
2650                 bool enable = false;
2651
2652                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2653
2654                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2655                         struct omap_overlay_manager *mgr;
2656                         mgr = omap_dss_get_overlay_manager(i);
2657
2658                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2659                                 manager = mgr;
2660                                 enable = mgr->display->state ==
2661                                                 OMAP_DSS_DISPLAY_ACTIVE;
2662                                 mgr->display->disable(mgr->display);
2663                                 break;
2664                         }
2665                 }
2666
2667                 if (manager) {
2668                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2669                                 struct omap_overlay *ovl;
2670                                 ovl = omap_dss_get_overlay(i);
2671
2672                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2673                                         continue;
2674
2675                                 if (ovl->id != 0 && ovl->manager == manager)
2676                                         dispc_enable_plane(ovl->id, 0);
2677                         }
2678
2679                         dispc_go(manager->id);
2680                         mdelay(50);
2681                         if (enable)
2682                                 manager->display->enable(manager->display);
2683                 }
2684         }
2685
2686         if (errors & DISPC_IRQ_OCP_ERR) {
2687                 DSSERR("OCP_ERR\n");
2688                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2689                         struct omap_overlay_manager *mgr;
2690                         mgr = omap_dss_get_overlay_manager(i);
2691
2692                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2693                                 mgr->display->disable(mgr->display);
2694                 }
2695         }
2696
2697         dispc.irq_error_mask |= errors;
2698         omap_dispc_set_irqs();
2699 }
2700
2701 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2702 {
2703         void dispc_irq_wait_handler(void *data, u32 mask)
2704         {
2705                 complete((struct completion *)data);
2706         }
2707
2708         int r;
2709         DECLARE_COMPLETION_ONSTACK(completion);
2710
2711         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2712                         irqmask);
2713
2714         if (r)
2715                 return r;
2716
2717         timeout = wait_for_completion_timeout(&completion, timeout);
2718
2719         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2720
2721         if (timeout == 0)
2722                 return -ETIMEDOUT;
2723
2724         if (timeout == -ERESTARTSYS)
2725                 return -ERESTARTSYS;
2726
2727         return 0;
2728 }
2729
2730 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2731                 unsigned long timeout)
2732 {
2733         void dispc_irq_wait_handler(void *data, u32 mask)
2734         {
2735                 complete((struct completion *)data);
2736         }
2737
2738         int r;
2739         DECLARE_COMPLETION_ONSTACK(completion);
2740
2741         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2742                         irqmask);
2743
2744         if (r)
2745                 return r;
2746
2747         timeout = wait_for_completion_interruptible_timeout(&completion,
2748                         timeout);
2749
2750         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2751
2752         if (timeout == 0)
2753                 return -ETIMEDOUT;
2754
2755         if (timeout == -ERESTARTSYS)
2756                 return -ERESTARTSYS;
2757
2758         return 0;
2759 }
2760
2761 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2762 void dispc_fake_vsync_irq(void)
2763 {
2764         u32 irqstatus = DISPC_IRQ_VSYNC;
2765         int i;
2766
2767         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2768                 struct omap_dispc_isr_data *isr_data;
2769                 isr_data = &dispc.registered_isr[i];
2770
2771                 if (!isr_data->isr)
2772                         continue;
2773
2774                 if (isr_data->mask & irqstatus)
2775                         isr_data->isr(isr_data->arg, irqstatus);
2776         }
2777 }
2778 #endif
2779
2780 static void _omap_dispc_initialize_irq(void)
2781 {
2782         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2783
2784         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2785
2786         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2787          * so clear it */
2788         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2789
2790         omap_dispc_set_irqs();
2791 }
2792
2793 static void _omap_dispc_initial_config(void)
2794 {
2795         u32 l;
2796
2797         l = dispc_read_reg(DISPC_SYSCONFIG);
2798         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2799         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2800         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2801         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2802         dispc_write_reg(DISPC_SYSCONFIG, l);
2803
2804         /* FUNCGATED */
2805         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2806
2807         /* L3 firewall setting: enable access to OCM RAM */
2808         if (cpu_is_omap24xx())
2809                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2810
2811         _dispc_setup_color_conv_coef();
2812
2813         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2814 }
2815
2816 int dispc_init(void)
2817 {
2818         u32 rev;
2819
2820         spin_lock_init(&dispc.irq_lock);
2821         spin_lock_init(&dispc.error_lock);
2822
2823         INIT_WORK(&dispc.error_work, dispc_error_worker);
2824
2825         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2826         if (!dispc.base) {
2827                 DSSERR("can't ioremap DISPC\n");
2828                 return -ENOMEM;
2829         }
2830
2831         if (cpu_is_omap34xx()) {
2832                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2833                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2834                         DSSERR("Failed to get dpll4_m4_ck\n");
2835                         return -ENODEV;
2836                 }
2837         }
2838
2839         enable_clocks(1);
2840
2841         _omap_dispc_initial_config();
2842
2843         _omap_dispc_initialize_irq();
2844
2845         dispc_save_context();
2846
2847         rev = dispc_read_reg(DISPC_REVISION);
2848         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2849                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2850
2851         enable_clocks(0);
2852
2853         return 0;
2854 }
2855
2856 void dispc_exit(void)
2857 {
2858         if (cpu_is_omap34xx())
2859                 clk_put(dispc.dpll4_m4_ck);
2860         iounmap(dispc.base);
2861 }
2862
2863 int dispc_enable_plane(enum omap_plane plane, bool enable)
2864 {
2865         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2866
2867         enable_clocks(1);
2868         _dispc_enable_plane(plane, enable);
2869         enable_clocks(0);
2870
2871         return 0;
2872 }
2873
2874 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
2875                        u32 paddr, u16 screen_width,
2876                        u16 pos_x, u16 pos_y,
2877                        u16 width, u16 height,
2878                        u16 out_width, u16 out_height,
2879                        enum omap_color_mode color_mode,
2880                        bool ilace,
2881                        u8 rotation, bool mirror)
2882 {
2883         int r = 0;
2884
2885         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
2886                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
2887                plane, channel_out, paddr, screen_width, pos_x, pos_y,
2888                width, height,
2889                out_width, out_height,
2890                ilace, color_mode,
2891                rotation, mirror);
2892
2893         enable_clocks(1);
2894
2895         r = _dispc_setup_plane(plane, channel_out,
2896                            paddr, screen_width,
2897                            pos_x, pos_y,
2898                            width, height,
2899                            out_width, out_height,
2900                            color_mode, ilace,
2901                            rotation, mirror);
2902
2903         enable_clocks(0);
2904
2905         return r;
2906 }
2907
2908 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
2909                                  int x2, int y2, int w2, int h2)
2910 {
2911         if (x1 >= (x2+w2))
2912                 return 0;
2913
2914         if ((x1+w1) <= x2)
2915                 return 0;
2916
2917         if (y1 >= (y2+h2))
2918                 return 0;
2919
2920         if ((y1+h1) <= y2)
2921                 return 0;
2922
2923         return 1;
2924 }
2925
2926 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
2927 {
2928         if (pi->width != pi->out_width)
2929                 return 1;
2930
2931         if (pi->height != pi->out_height)
2932                 return 1;
2933
2934         return 0;
2935 }
2936
2937 /* returns the area that needs updating */
2938 void dispc_setup_partial_planes(struct omap_display *display,
2939                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
2940 {
2941         struct omap_overlay_manager *mgr;
2942         int i;
2943
2944         int x, y, w, h;
2945
2946         x = *xi;
2947         y = *yi;
2948         w = *wi;
2949         h = *hi;
2950
2951         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
2952                 *xi, *yi, *wi, *hi);
2953
2954
2955         mgr = display->manager;
2956
2957         if (!mgr) {
2958                 DSSDBG("no manager\n");
2959                 return;
2960         }
2961
2962         for (i = 0; i < mgr->num_overlays; i++) {
2963                 struct omap_overlay *ovl;
2964                 struct omap_overlay_info *pi;
2965                 ovl = mgr->overlays[i];
2966
2967                 if (ovl->manager != mgr)
2968                         continue;
2969
2970                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2971                         continue;
2972
2973                 pi = &ovl->info;
2974
2975                 if (!pi->enabled)
2976                         continue;
2977                 /*
2978                  * If the plane is intersecting and scaled, we
2979                  * enlarge the update region to accomodate the
2980                  * whole area
2981                  */
2982
2983                 if (dispc_is_intersecting(x, y, w, h,
2984                                           pi->pos_x, pi->pos_y,
2985                                           pi->out_width, pi->out_height)) {
2986                         if (dispc_is_overlay_scaled(pi)) {
2987
2988                                 int x1, y1, x2, y2;
2989
2990                                 if (x > pi->pos_x)
2991                                         x1 = pi->pos_x;
2992                                 else
2993                                         x1 = x;
2994
2995                                 if (y > pi->pos_y)
2996                                         y1 = pi->pos_y;
2997                                 else
2998                                         y1 = y;
2999
3000                                 if ((x + w) < (pi->pos_x + pi->out_width))
3001                                         x2 = pi->pos_x + pi->out_width;
3002                                 else
3003                                         x2 = x + w;
3004
3005                                 if ((y + h) < (pi->pos_y + pi->out_height))
3006                                         y2 = pi->pos_y + pi->out_height;
3007                                 else
3008                                         y2 = y + h;
3009
3010                                 x = x1;
3011                                 y = y1;
3012                                 w = x2 - x1;
3013                                 h = y2 - y1;
3014
3015                                 DSSDBG("Update area after enlarge due to "
3016                                         "scaling %d, %d %dx%d\n",
3017                                         x, y, w, h);
3018                         }
3019                 }
3020         }
3021
3022         for (i = 0; i < mgr->num_overlays; i++) {
3023                 struct omap_overlay *ovl = mgr->overlays[i];
3024                 struct omap_overlay_info *pi = &ovl->info;
3025
3026                 int px = pi->pos_x;
3027                 int py = pi->pos_y;
3028                 int pw = pi->width;
3029                 int ph = pi->height;
3030                 int pow = pi->out_width;
3031                 int poh = pi->out_height;
3032                 u32 pa = pi->paddr;
3033                 int psw = pi->screen_width;
3034                 int bpp;
3035
3036                 if (ovl->manager != mgr)
3037                         continue;
3038
3039                 /*
3040                  * If plane is not enabled or the update region
3041                  * does not intersect with the plane in question,
3042                  * we really disable the plane from hardware
3043                  */
3044
3045                 if (!pi->enabled ||
3046                     !dispc_is_intersecting(x, y, w, h,
3047                                            px, py, pow, poh)) {
3048                         dispc_enable_plane(ovl->id, 0);
3049                         continue;
3050                 }
3051
3052                 switch (pi->color_mode) {
3053                 case OMAP_DSS_COLOR_RGB16:
3054                 case OMAP_DSS_COLOR_ARGB16:
3055                 case OMAP_DSS_COLOR_YUV2:
3056                 case OMAP_DSS_COLOR_UYVY:
3057                         bpp = 16;
3058                         break;
3059
3060                 case OMAP_DSS_COLOR_RGB24P:
3061                         bpp = 24;
3062                         break;
3063
3064                 case OMAP_DSS_COLOR_RGB24U:
3065                 case OMAP_DSS_COLOR_ARGB32:
3066                 case OMAP_DSS_COLOR_RGBA32:
3067                 case OMAP_DSS_COLOR_RGBX32:
3068                         bpp = 32;
3069                         break;
3070
3071                 default:
3072                         BUG();
3073                         return;
3074                 }
3075
3076                 if (x > pi->pos_x) {
3077                         px = 0;
3078                         pw -= (x - pi->pos_x);
3079                         pa += (x - pi->pos_x) * bpp / 8;
3080                 } else {
3081                         px = pi->pos_x - x;
3082                 }
3083
3084                 if (y > pi->pos_y) {
3085                         py = 0;
3086                         ph -= (y - pi->pos_y);
3087                         pa += (y - pi->pos_y) * psw * bpp / 8;
3088                 } else {
3089                         py = pi->pos_y - y;
3090                 }
3091
3092                 if (w < (px+pw))
3093                         pw -= (px+pw) - (w);
3094
3095                 if (h < (py+ph))
3096                         ph -= (py+ph) - (h);
3097
3098                 /* Can't scale the GFX plane */
3099                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3100                                 dispc_is_overlay_scaled(pi) == 0) {
3101                         pow = pw;
3102                         poh = ph;
3103                 }
3104
3105                 DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3106                                 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3107
3108                 dispc_setup_plane(ovl->id, mgr->id,
3109                                 pa, psw,
3110                                 px, py,
3111                                 pw, ph,
3112                                 pow, poh,
3113                                 pi->color_mode, 0,
3114                                 pi->rotation, // XXX rotation probably wrong
3115                                 pi->mirror);
3116
3117                 dispc_enable_plane(ovl->id, 1);
3118         }
3119
3120         *xi = x;
3121         *yi = y;
3122         *wi = w;
3123         *hi = h;
3124
3125 }
3126