drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/ioport.h>
  47 #include <linux/io.h>
  48 #include <linux/list.h>
  49 #include <linux/delay.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/of.h>
  52
  53 #include <linux/usb/ch9.h>
  54 #include <linux/usb/gadget.h>
  55
  56 #include "core.h"
  57 #include "gadget.h"
  58 #include "io.h"
  59
  60 #include "debug.h"
  61
  62 static char *maximum_speed = "super";
  63 module_param(maximum_speed, charp, 0);
  64 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
  65
  66 /* -------------------------------------------------------------------------- */
  67
  68 #define DWC3_DEVS_POSSIBLE      32
  69
  70 static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
  71
  72 int dwc3_get_device_id(void)
  73 {
  74         int             id;
  75
  76 again:
  77         id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
  78         if (id < DWC3_DEVS_POSSIBLE) {
  79                 int old;
  80
  81                 old = test_and_set_bit(id, dwc3_devs);
  82                 if (old)
  83                         goto again;
  84         } else {
  85                 pr_err("dwc3: no space for new device\n");
  86                 id = -ENOMEM;
  87         }
  88
  89         return 0;
  90 }
  91 EXPORT_SYMBOL_GPL(dwc3_get_device_id);
  92
  93 void dwc3_put_device_id(int id)
  94 {
  95         int                     ret;
  96
  97         if (id < 0)
  98                 return;
  99
 100         ret = test_bit(id, dwc3_devs);
 101         WARN(!ret, "dwc3: ID %d not in use\n", id);
 102         clear_bit(id, dwc3_devs);
 103 }
 104 EXPORT_SYMBOL_GPL(dwc3_put_device_id);
 105
 106 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 107 {
 108         u32 reg;
 109
 110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 111         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 112         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 113         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 114 }
 115
 116 /**
 117  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 118  * @dwc: pointer to our context structure
 119  */
 120 static void dwc3_core_soft_reset(struct dwc3 *dwc)
 121 {
 122         u32             reg;
 123
 124         /* Before Resetting PHY, put Core in Reset */
 125         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 126         reg |= DWC3_GCTL_CORESOFTRESET;
 127         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 128
 129         /* Assert USB3 PHY reset */
 130         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 131         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
 132         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 133
 134         /* Assert USB2 PHY reset */
 135         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 136         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
 137         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 138
 139         mdelay(100);
 140
 141         /* Clear USB3 PHY reset */
 142         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 143         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 144         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 145
 146         /* Clear USB2 PHY reset */
 147         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 148         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 149         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 150
 151         /* After PHYs are stable we can take Core out of reset state */
 152         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 153         reg &= ~DWC3_GCTL_CORESOFTRESET;
 154         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 155 }
 156
 157 /**
 158  * dwc3_free_one_event_buffer - Frees one event buffer
 159  * @dwc: Pointer to our controller context structure
 160  * @evt: Pointer to event buffer to be freed
 161  */
 162 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 163                 struct dwc3_event_buffer *evt)
 164 {
 165         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 166         kfree(evt);
 167 }
 168
 169 /**
 170  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 171  * @dwc: Pointer to our controller context structure
 172  * @length: size of the event buffer
 173  *
 174  * Returns a pointer to the allocated event buffer structure on success
 175  * otherwise ERR_PTR(errno).
 176  */
 177 static struct dwc3_event_buffer *__devinit
 178 dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
 179 {
 180         struct dwc3_event_buffer        *evt;
 181
 182         evt = kzalloc(sizeof(*evt), GFP_KERNEL);
 183         if (!evt)
 184                 return ERR_PTR(-ENOMEM);
 185
 186         evt->dwc        = dwc;
 187         evt->length     = length;
 188         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 189                         &evt->dma, GFP_KERNEL);
 190         if (!evt->buf) {
 191                 kfree(evt);
 192                 return ERR_PTR(-ENOMEM);
 193         }
 194
 195         return evt;
 196 }
 197
 198 /**
 199  * dwc3_free_event_buffers - frees all allocated event buffers
 200  * @dwc: Pointer to our controller context structure
 201  */
 202 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 203 {
 204         struct dwc3_event_buffer        *evt;
 205         int i;
 206
 207         for (i = 0; i < dwc->num_event_buffers; i++) {
 208                 evt = dwc->ev_buffs[i];
 209                 if (evt) {
 210                         dwc3_free_one_event_buffer(dwc, evt);
 211                         dwc->ev_buffs[i] = NULL;
 212                 }
 213         }
 214 }
 215
 216 /**
 217  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 218  * @dwc: pointer to our controller context structure
 219  * @length: size of event buffer
 220  *
 221  * Returns 0 on success otherwise negative errno. In the error case, dwc
 222  * may contain some buffers allocated but not all which were requested.
 223  */
 224 static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 225 {
 226         int                     num;
 227         int                     i;
 228
 229         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 230         dwc->num_event_buffers = num;
 231
 232         dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
 233         if (!dwc->ev_buffs) {
 234                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 235                 return -ENOMEM;
 236         }
 237
 238         for (i = 0; i < num; i++) {
 239                 struct dwc3_event_buffer        *evt;
 240
 241                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 242                 if (IS_ERR(evt)) {
 243                         dev_err(dwc->dev, "can't allocate event buffer\n");
 244                         return PTR_ERR(evt);
 245                 }
 246                 dwc->ev_buffs[i] = evt;
 247         }
 248
 249         return 0;
 250 }
 251
 252 /**
 253  * dwc3_event_buffers_setup - setup our allocated event buffers
 254  * @dwc: pointer to our controller context structure
 255  *
 256  * Returns 0 on success otherwise negative errno.
 257  */
 258 static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
 259 {
 260         struct dwc3_event_buffer        *evt;
 261         int                             n;
 262
 263         for (n = 0; n < dwc->num_event_buffers; n++) {
 264                 evt = dwc->ev_buffs[n];
 265                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 266                                 evt->buf, (unsigned long long) evt->dma,
 267                                 evt->length);
 268
 269                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 270                                 lower_32_bits(evt->dma));
 271                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 272                                 upper_32_bits(evt->dma));
 273                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 274                                 evt->length & 0xffff);
 275                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 282 {
 283         struct dwc3_event_buffer        *evt;
 284         int                             n;
 285
 286         for (n = 0; n < dwc->num_event_buffers; n++) {
 287                 evt = dwc->ev_buffs[n];
 288                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 289                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 290                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
 291                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 292         }
 293 }
 294
 295 static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
 296 {
 297         struct dwc3_hwparams    *parms = &dwc->hwparams;
 298
 299         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 300         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 301         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 302         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 303         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 304         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 305         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 306         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 307         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 308 }
 309
 310 /**
 311  * dwc3_core_init - Low-level initialization of DWC3 Core
 312  * @dwc: Pointer to our controller context structure
 313  *
 314  * Returns 0 on success otherwise negative errno.
 315  */
 316 static int __devinit dwc3_core_init(struct dwc3 *dwc)
 317 {
 318         unsigned long           timeout;
 319         u32                     reg;
 320         int                     ret;
 321
 322         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 323         /* This should read as U3 followed by revision number */
 324         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 325                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 326                 ret = -ENODEV;
 327                 goto err0;
 328         }
 329         dwc->revision = reg;
 330
 331         dwc3_core_soft_reset(dwc);
 332
 333         /* issue device SoftReset too */
 334         timeout = jiffies + msecs_to_jiffies(500);
 335         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 336         do {
 337                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 338                 if (!(reg & DWC3_DCTL_CSFTRST))
 339                         break;
 340
 341                 if (time_after(jiffies, timeout)) {
 342                         dev_err(dwc->dev, "Reset Timed Out\n");
 343                         ret = -ETIMEDOUT;
 344                         goto err0;
 345                 }
 346
 347                 cpu_relax();
 348         } while (true);
 349
 350         dwc3_cache_hwparams(dwc);
 351
 352         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 353         reg &= ~DWC3_GCTL_SCALEDOWN(3);
 354         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 355
 356         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 357         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 358                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 359                 break;
 360         default:
 361                 dev_dbg(dwc->dev, "No power optimization available\n");
 362         }
 363
 364         /*
 365          * WORKAROUND: DWC3 revisions <1.90a have a bug
 366          * where the device can fail to connect at SuperSpeed
 367          * and falls back to high-speed mode which causes
 368          * the device to enter a Connect/Disconnect loop
 369          */
 370         if (dwc->revision < DWC3_REVISION_190A)
 371                 reg |= DWC3_GCTL_U2RSTECN;
 372
 373         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 374
 375         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 376         if (ret) {
 377                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 378                 ret = -ENOMEM;
 379                 goto err1;
 380         }
 381
 382         ret = dwc3_event_buffers_setup(dwc);
 383         if (ret) {
 384                 dev_err(dwc->dev, "failed to setup event buffers\n");
 385                 goto err1;
 386         }
 387
 388         return 0;
 389
 390 err1:
 391         dwc3_free_event_buffers(dwc);
 392
 393 err0:
 394         return ret;
 395 }
 396
 397 static void dwc3_core_exit(struct dwc3 *dwc)
 398 {
 399         dwc3_event_buffers_cleanup(dwc);
 400         dwc3_free_event_buffers(dwc);
 401 }
 402
 403 #define DWC3_ALIGN_MASK         (16 - 1)
 404
 405 static int __devinit dwc3_probe(struct platform_device *pdev)
 406 {
 407         struct device_node      *node = pdev->dev.of_node;
 408         struct resource         *res;
 409         struct dwc3             *dwc;
 410         struct device           *dev = &pdev->dev;
 411
 412         int                     ret = -ENOMEM;
 413         int                     irq;
 414
 415         void __iomem            *regs;
 416         void                    *mem;
 417
 418         u8                      mode;
 419
 420         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 421         if (!mem) {
 422                 dev_err(dev, "not enough memory\n");
 423                 return -ENOMEM;
 424         }
 425         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 426         dwc->mem = mem;
 427
 428         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 429         if (!res) {
 430                 dev_err(dev, "missing resource\n");
 431                 return -ENODEV;
 432         }
 433
 434         dwc->res = res;
 435
 436         res = devm_request_mem_region(dev, res->start, resource_size(res),
 437                         dev_name(dev));
 438         if (!res) {
 439                 dev_err(dev, "can't request mem region\n");
 440                 return -ENOMEM;
 441         }
 442
 443         regs = devm_ioremap(dev, res->start, resource_size(res));
 444         if (!regs) {
 445                 dev_err(dev, "ioremap failed\n");
 446                 return -ENOMEM;
 447         }
 448
 449         irq = platform_get_irq(pdev, 0);
 450         if (irq < 0) {
 451                 dev_err(dev, "missing IRQ\n");
 452                 return -ENODEV;
 453         }
 454
 455         spin_lock_init(&dwc->lock);
 456         platform_set_drvdata(pdev, dwc);
 457
 458         dwc->regs       = regs;
 459         dwc->regs_size  = resource_size(res);
 460         dwc->dev        = dev;
 461         dwc->irq        = irq;
 462
 463         if (!strncmp("super", maximum_speed, 5))
 464                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 465         else if (!strncmp("high", maximum_speed, 4))
 466                 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
 467         else if (!strncmp("full", maximum_speed, 4))
 468                 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
 469         else if (!strncmp("low", maximum_speed, 3))
 470                 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
 471         else
 472                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 473
 474         if (of_get_property(node, "tx-fifo-resize", NULL))
 475                 dwc->needs_fifo_resize = true;
 476
 477         pm_runtime_enable(dev);
 478         pm_runtime_get_sync(dev);
 479         pm_runtime_forbid(dev);
 480
 481         ret = dwc3_core_init(dwc);
 482         if (ret) {
 483                 dev_err(dev, "failed to initialize core\n");
 484                 return ret;
 485         }
 486
 487         mode = DWC3_MODE(dwc->hwparams.hwparams0);
 488
 489         switch (mode) {
 490         case DWC3_MODE_DEVICE:
 491                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 492                 ret = dwc3_gadget_init(dwc);
 493                 if (ret) {
 494                         dev_err(dev, "failed to initialize gadget\n");
 495                         goto err1;
 496                 }
 497                 break;
 498         case DWC3_MODE_HOST:
 499                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 500                 ret = dwc3_host_init(dwc);
 501                 if (ret) {
 502                         dev_err(dev, "failed to initialize host\n");
 503                         goto err1;
 504                 }
 505                 break;
 506         case DWC3_MODE_DRD:
 507                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 508                 ret = dwc3_host_init(dwc);
 509                 if (ret) {
 510                         dev_err(dev, "failed to initialize host\n");
 511                         goto err1;
 512                 }
 513
 514                 ret = dwc3_gadget_init(dwc);
 515                 if (ret) {
 516                         dev_err(dev, "failed to initialize gadget\n");
 517                         goto err1;
 518                 }
 519                 break;
 520         default:
 521                 dev_err(dev, "Unsupported mode of operation %d\n", mode);
 522                 goto err1;
 523         }
 524         dwc->mode = mode;
 525
 526         ret = dwc3_debugfs_init(dwc);
 527         if (ret) {
 528                 dev_err(dev, "failed to initialize debugfs\n");
 529                 goto err2;
 530         }
 531
 532         pm_runtime_allow(dev);
 533
 534         return 0;
 535
 536 err2:
 537         switch (mode) {
 538         case DWC3_MODE_DEVICE:
 539                 dwc3_gadget_exit(dwc);
 540                 break;
 541         case DWC3_MODE_HOST:
 542                 dwc3_host_exit(dwc);
 543                 break;
 544         case DWC3_MODE_DRD:
 545                 dwc3_host_exit(dwc);
 546                 dwc3_gadget_exit(dwc);
 547                 break;
 548         default:
 549                 /* do nothing */
 550                 break;
 551         }
 552
 553 err1:
 554         dwc3_core_exit(dwc);
 555
 556         return ret;
 557 }
 558
 559 static int __devexit dwc3_remove(struct platform_device *pdev)
 560 {
 561         struct dwc3     *dwc = platform_get_drvdata(pdev);
 562         struct resource *res;
 563
 564         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 565
 566         pm_runtime_put(&pdev->dev);
 567         pm_runtime_disable(&pdev->dev);
 568
 569         dwc3_debugfs_exit(dwc);
 570
 571         switch (dwc->mode) {
 572         case DWC3_MODE_DEVICE:
 573                 dwc3_gadget_exit(dwc);
 574                 break;
 575         case DWC3_MODE_HOST:
 576                 dwc3_host_exit(dwc);
 577                 break;
 578         case DWC3_MODE_DRD:
 579                 dwc3_host_exit(dwc);
 580                 dwc3_gadget_exit(dwc);
 581                 break;
 582         default:
 583                 /* do nothing */
 584                 break;
 585         }
 586
 587         dwc3_core_exit(dwc);
 588
 589         return 0;
 590 }
 591
 592 static struct platform_driver dwc3_driver = {
 593         .probe          = dwc3_probe,
 594         .remove         = __devexit_p(dwc3_remove),
 595         .driver         = {
 596                 .name   = "dwc3",
 597         },
 598 };
 599
 600 MODULE_ALIAS("platform:dwc3");
 601 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 602 MODULE_LICENSE("Dual BSD/GPL");
 603 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 604
 605 static int __devinit dwc3_init(void)
 606 {
 607         return platform_driver_register(&dwc3_driver);
 608 }
 609 module_init(dwc3_init);
 610
 611 static void __exit dwc3_exit(void)
 612 {
 613         platform_driver_unregister(&dwc3_driver);
 614 }
 615 module_exit(dwc3_exit);