drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright (c) 2006-2007 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/string.h>
  28 #include <linux/ioport.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/nand.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <linux/mtd/partitions.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/fsl_lbc.h>
  40
  41 #define MAX_BANKS 8
  42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  44
  45 struct fsl_elbc_ctrl;
  46
  47 /* mtd information per set */
  48
  49 struct fsl_elbc_mtd {
  50         struct mtd_info mtd;
  51         struct nand_chip chip;
  52         struct fsl_elbc_ctrl *ctrl;
  53
  54         struct device *dev;
  55         int bank;               /* Chip select bank number           */
  56         u8 __iomem *vbase;      /* Chip select base virtual address  */
  57         int page_size;          /* NAND page size (0=512, 1=2048)    */
  58         unsigned int fmr;       /* FCM Flash Mode Register value     */
  59 };
  60
  61 /* overview of the fsl elbc controller */
  62
  63 struct fsl_elbc_ctrl {
  64         struct nand_hw_control controller;
  65         struct fsl_elbc_mtd *chips[MAX_BANKS];
  66
  67         /* device info */
  68         struct device *dev;
  69         struct fsl_lbc_regs __iomem *regs;
  70         int irq;
  71         wait_queue_head_t irq_wait;
  72         unsigned int irq_status; /* status read from LTESR by irq handler */
  73         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  74         unsigned int page;       /* Last page written to / read from      */
  75         unsigned int read_bytes; /* Number of bytes read during command   */
  76         unsigned int column;     /* Saved column from SEQIN               */
  77         unsigned int index;      /* Pointer to next byte to 'read'        */
  78         unsigned int status;     /* status read from LTESR after last op  */
  79         unsigned int mdr;        /* UPM/FCM Data Register value           */
  80         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  81         unsigned int oob;        /* Non zero if operating on OOB data     */
  82         char *oob_poi;           /* Place to write ECC after read back    */
  83 };
  84
  85 /* These map to the positions used by the FCM hardware ECC generator */
  86
  87 /* Small Page FLASH with FMR[ECCM] = 0 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  89         .eccbytes = 3,
  90         .eccpos = {6, 7, 8},
  91         .oobfree = { {0, 5}, {9, 7} },
  92         .oobavail = 12,
  93 };
  94
  95 /* Small Page FLASH with FMR[ECCM] = 1 */
  96 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  97         .eccbytes = 3,
  98         .eccpos = {8, 9, 10},
  99         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 100         .oobavail = 12,
 101 };
 102
 103 /* Large Page FLASH with FMR[ECCM] = 0 */
 104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 105         .eccbytes = 12,
 106         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 107         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 108         .oobavail = 48,
 109 };
 110
 111 /* Large Page FLASH with FMR[ECCM] = 1 */
 112 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 113         .eccbytes = 12,
 114         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 115         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 116         .oobavail = 48,
 117 };
 118
 119 /*=================================*/
 120
 121 /*
 122  * Set up the FCM hardware block and page address fields, and the fcm
 123  * structure addr field to point to the correct FCM buffer in memory
 124  */
 125 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 126 {
 127         struct nand_chip *chip = mtd->priv;
 128         struct fsl_elbc_mtd *priv = chip->priv;
 129         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 130         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 131         int buf_num;
 132
 133         ctrl->page = page_addr;
 134
 135         out_be32(&lbc->fbar,
 136                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 137
 138         if (priv->page_size) {
 139                 out_be32(&lbc->fpar,
 140                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 141                          (oob ? FPAR_LP_MS : 0) | column);
 142                 buf_num = (page_addr & 1) << 2;
 143         } else {
 144                 out_be32(&lbc->fpar,
 145                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 146                          (oob ? FPAR_SP_MS : 0) | column);
 147                 buf_num = page_addr & 7;
 148         }
 149
 150         ctrl->addr = priv->vbase + buf_num * 1024;
 151         ctrl->index = column;
 152
 153         /* for OOB data point to the second half of the buffer */
 154         if (oob)
 155                 ctrl->index += priv->page_size ? 2048 : 512;
 156
 157         dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 158                             "index %x, pes %d ps %d\n",
 159                  buf_num, ctrl->addr, priv->vbase, ctrl->index,
 160                  chip->phys_erase_shift, chip->page_shift);
 161 }
 162
 163 /*
 164  * execute FCM command and wait for it to complete
 165  */
 166 static int fsl_elbc_run_command(struct mtd_info *mtd)
 167 {
 168         struct nand_chip *chip = mtd->priv;
 169         struct fsl_elbc_mtd *priv = chip->priv;
 170         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 171         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 172
 173         /* Setup the FMR[OP] to execute without write protection */
 174         out_be32(&lbc->fmr, priv->fmr | 3);
 175         if (ctrl->use_mdr)
 176                 out_be32(&lbc->mdr, ctrl->mdr);
 177
 178         dev_vdbg(ctrl->dev,
 179                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 180                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 181         dev_vdbg(ctrl->dev,
 182                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 183                  "fbcr=%08x bank=%d\n",
 184                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 185                  in_be32(&lbc->fbcr), priv->bank);
 186
 187         ctrl->irq_status = 0;
 188         /* execute special operation */
 189         out_be32(&lbc->lsor, priv->bank);
 190
 191         /* wait for FCM complete flag or timeout */
 192         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 193                            FCM_TIMEOUT_MSECS * HZ/1000);
 194         ctrl->status = ctrl->irq_status;
 195
 196         /* store mdr value in case it was needed */
 197         if (ctrl->use_mdr)
 198                 ctrl->mdr = in_be32(&lbc->mdr);
 199
 200         ctrl->use_mdr = 0;
 201
 202         dev_vdbg(ctrl->dev,
 203                  "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 204                  ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 205
 206         /* returns 0 on success otherwise non-zero) */
 207         return ctrl->status == LTESR_CC ? 0 : -EIO;
 208 }
 209
 210 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 211 {
 212         struct fsl_elbc_mtd *priv = chip->priv;
 213         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 214         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 215
 216         if (priv->page_size) {
 217                 out_be32(&lbc->fir,
 218                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 219                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 220                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 221                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 222                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 223
 224                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 225                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 226         } else {
 227                 out_be32(&lbc->fir,
 228                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 229                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 230                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 231                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 232
 233                 if (oob)
 234                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 235                 else
 236                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 237         }
 238 }
 239
 240 /* cmdfunc send commands to the FCM */
 241 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 242                              int column, int page_addr)
 243 {
 244         struct nand_chip *chip = mtd->priv;
 245         struct fsl_elbc_mtd *priv = chip->priv;
 246         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 247         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 248
 249         ctrl->use_mdr = 0;
 250
 251         /* clear the read buffer */
 252         ctrl->read_bytes = 0;
 253         if (command != NAND_CMD_PAGEPROG)
 254                 ctrl->index = 0;
 255
 256         switch (command) {
 257         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 258         case NAND_CMD_READ1:
 259                 column += 256;
 260
 261         /* fall-through */
 262         case NAND_CMD_READ0:
 263                 dev_dbg(ctrl->dev,
 264                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 265                         " 0x%x, column: 0x%x.\n", page_addr, column);
 266
 267
 268                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 269                 set_addr(mtd, 0, page_addr, 0);
 270
 271                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 272                 ctrl->index += column;
 273
 274                 fsl_elbc_do_read(chip, 0);
 275                 fsl_elbc_run_command(mtd);
 276                 return;
 277
 278         /* READOOB reads only the OOB because no ECC is performed. */
 279         case NAND_CMD_READOOB:
 280                 dev_vdbg(ctrl->dev,
 281                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 282                          " 0x%x, column: 0x%x.\n", page_addr, column);
 283
 284                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 285                 set_addr(mtd, column, page_addr, 1);
 286
 287                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 288
 289                 fsl_elbc_do_read(chip, 1);
 290                 fsl_elbc_run_command(mtd);
 291                 return;
 292
 293         /* READID must read all 5 possible bytes while CEB is active */
 294         case NAND_CMD_READID:
 295                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 296
 297                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 298                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 299                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 300                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 301                 /* 5 bytes for manuf, device and exts */
 302                 out_be32(&lbc->fbcr, 5);
 303                 ctrl->read_bytes = 5;
 304                 ctrl->use_mdr = 1;
 305                 ctrl->mdr = 0;
 306
 307                 set_addr(mtd, 0, 0, 0);
 308                 fsl_elbc_run_command(mtd);
 309                 return;
 310
 311         /* ERASE1 stores the block and page address */
 312         case NAND_CMD_ERASE1:
 313                 dev_vdbg(ctrl->dev,
 314                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 315                          "page_addr: 0x%x.\n", page_addr);
 316                 set_addr(mtd, 0, page_addr, 0);
 317                 return;
 318
 319         /* ERASE2 uses the block and page address from ERASE1 */
 320         case NAND_CMD_ERASE2:
 321                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 322
 323                 out_be32(&lbc->fir,
 324                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 325                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 326                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 327
 328                 out_be32(&lbc->fcr,
 329                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 330                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 331
 332                 out_be32(&lbc->fbcr, 0);
 333                 ctrl->read_bytes = 0;
 334
 335                 fsl_elbc_run_command(mtd);
 336                 return;
 337
 338         /* SEQIN sets up the addr buffer and all registers except the length */
 339         case NAND_CMD_SEQIN: {
 340                 __be32 fcr;
 341                 dev_vdbg(ctrl->dev,
 342                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 343                          "page_addr: 0x%x, column: 0x%x.\n",
 344                          page_addr, column);
 345
 346                 ctrl->column = column;
 347                 ctrl->oob = 0;
 348
 349                 if (priv->page_size) {
 350                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 351                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 352
 353                         out_be32(&lbc->fir,
 354                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 355                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 356                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 357                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 358                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 359                 } else {
 360                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 361                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 362
 363                         out_be32(&lbc->fir,
 364                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 365                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 366                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 367                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 368                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 369                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 370
 371                         if (column >= mtd->writesize) {
 372                                 /* OOB area --> READOOB */
 373                                 column -= mtd->writesize;
 374                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 375                                 ctrl->oob = 1;
 376                         } else if (column < 256) {
 377                                 /* First 256 bytes --> READ0 */
 378                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 379                         } else {
 380                                 /* Second 256 bytes --> READ1 */
 381                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 382                         }
 383                 }
 384
 385                 out_be32(&lbc->fcr, fcr);
 386                 set_addr(mtd, column, page_addr, ctrl->oob);
 387                 return;
 388         }
 389
 390         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 391         case NAND_CMD_PAGEPROG: {
 392                 int full_page;
 393                 dev_vdbg(ctrl->dev,
 394                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 395                          "writing %d bytes.\n", ctrl->index);
 396
 397                 /* if the write did not start at 0 or is not a full page
 398                  * then set the exact length, otherwise use a full page
 399                  * write so the HW generates the ECC.
 400                  */
 401                 if (ctrl->oob || ctrl->column != 0 ||
 402                     ctrl->index != mtd->writesize + mtd->oobsize) {
 403                         out_be32(&lbc->fbcr, ctrl->index);
 404                         full_page = 0;
 405                 } else {
 406                         out_be32(&lbc->fbcr, 0);
 407                         full_page = 1;
 408                 }
 409
 410                 fsl_elbc_run_command(mtd);
 411
 412                 /* Read back the page in order to fill in the ECC for the
 413                  * caller.  Is this really needed?
 414                  */
 415                 if (full_page && ctrl->oob_poi) {
 416                         out_be32(&lbc->fbcr, 3);
 417                         set_addr(mtd, 6, page_addr, 1);
 418
 419                         ctrl->read_bytes = mtd->writesize + 9;
 420
 421                         fsl_elbc_do_read(chip, 1);
 422                         fsl_elbc_run_command(mtd);
 423
 424                         memcpy_fromio(ctrl->oob_poi + 6,
 425                                       &ctrl->addr[ctrl->index], 3);
 426                         ctrl->index += 3;
 427                 }
 428
 429                 ctrl->oob_poi = NULL;
 430                 return;
 431         }
 432
 433         /* CMD_STATUS must read the status byte while CEB is active */
 434         /* Note - it does not wait for the ready line */
 435         case NAND_CMD_STATUS:
 436                 out_be32(&lbc->fir,
 437                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 438                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 439                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 440                 out_be32(&lbc->fbcr, 1);
 441                 set_addr(mtd, 0, 0, 0);
 442                 ctrl->read_bytes = 1;
 443
 444                 fsl_elbc_run_command(mtd);
 445
 446                 /* The chip always seems to report that it is
 447                  * write-protected, even when it is not.
 448                  */
 449                 setbits8(ctrl->addr, NAND_STATUS_WP);
 450                 return;
 451
 452         /* RESET without waiting for the ready line */
 453         case NAND_CMD_RESET:
 454                 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 455                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 456                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 457                 fsl_elbc_run_command(mtd);
 458                 return;
 459
 460         default:
 461                 dev_err(ctrl->dev,
 462                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 463                         command);
 464         }
 465 }
 466
 467 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 468 {
 469         /* The hardware does not seem to support multiple
 470          * chips per bank.
 471          */
 472 }
 473
 474 /*
 475  * Write buf to the FCM Controller Data Buffer
 476  */
 477 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 478 {
 479         struct nand_chip *chip = mtd->priv;
 480         struct fsl_elbc_mtd *priv = chip->priv;
 481         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 482         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 483
 484         if (len <= 0) {
 485                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 486                 ctrl->status = 0;
 487                 return;
 488         }
 489
 490         if ((unsigned int)len > bufsize - ctrl->index) {
 491                 dev_err(ctrl->dev,
 492                         "write_buf beyond end of buffer "
 493                         "(%d requested, %u available)\n",
 494                         len, bufsize - ctrl->index);
 495                 len = bufsize - ctrl->index;
 496         }
 497
 498         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 499         /*
 500          * This is workaround for the weird elbc hangs during nand write,
 501          * Scott Wood says: "...perhaps difference in how long it takes a
 502          * write to make it through the localbus compared to a write to IMMR
 503          * is causing problems, and sync isn't helping for some reason."
 504          * Reading back the last byte helps though.
 505          */
 506         in_8(&ctrl->addr[ctrl->index] + len - 1);
 507
 508         ctrl->index += len;
 509 }
 510
 511 /*
 512  * read a byte from either the FCM hardware buffer if it has any data left
 513  * otherwise issue a command to read a single byte.
 514  */
 515 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 516 {
 517         struct nand_chip *chip = mtd->priv;
 518         struct fsl_elbc_mtd *priv = chip->priv;
 519         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 520
 521         /* If there are still bytes in the FCM, then use the next byte. */
 522         if (ctrl->index < ctrl->read_bytes)
 523                 return in_8(&ctrl->addr[ctrl->index++]);
 524
 525         dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
 526         return ERR_BYTE;
 527 }
 528
 529 /*
 530  * Read from the FCM Controller Data Buffer
 531  */
 532 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 533 {
 534         struct nand_chip *chip = mtd->priv;
 535         struct fsl_elbc_mtd *priv = chip->priv;
 536         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 537         int avail;
 538
 539         if (len < 0)
 540                 return;
 541
 542         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 543         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 544         ctrl->index += avail;
 545
 546         if (len > avail)
 547                 dev_err(ctrl->dev,
 548                         "read_buf beyond end of buffer "
 549                         "(%d requested, %d available)\n",
 550                         len, avail);
 551 }
 552
 553 /*
 554  * Verify buffer against the FCM Controller Data Buffer
 555  */
 556 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 557 {
 558         struct nand_chip *chip = mtd->priv;
 559         struct fsl_elbc_mtd *priv = chip->priv;
 560         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 561         int i;
 562
 563         if (len < 0) {
 564                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 565                 return -EINVAL;
 566         }
 567
 568         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 569                 dev_err(ctrl->dev,
 570                         "verify_buf beyond end of buffer "
 571                         "(%d requested, %u available)\n",
 572                         len, ctrl->read_bytes - ctrl->index);
 573
 574                 ctrl->index = ctrl->read_bytes;
 575                 return -EINVAL;
 576         }
 577
 578         for (i = 0; i < len; i++)
 579                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 580                         break;
 581
 582         ctrl->index += len;
 583         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 584 }
 585
 586 /* This function is called after Program and Erase Operations to
 587  * check for success or failure.
 588  */
 589 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 590 {
 591         struct fsl_elbc_mtd *priv = chip->priv;
 592         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 593         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 594
 595         if (ctrl->status != LTESR_CC)
 596                 return NAND_STATUS_FAIL;
 597
 598         /* Use READ_STATUS command, but wait for the device to be ready */
 599         ctrl->use_mdr = 0;
 600         out_be32(&lbc->fir,
 601                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 602                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 603         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 604         out_be32(&lbc->fbcr, 1);
 605         set_addr(mtd, 0, 0, 0);
 606         ctrl->read_bytes = 1;
 607
 608         fsl_elbc_run_command(mtd);
 609
 610         if (ctrl->status != LTESR_CC)
 611                 return NAND_STATUS_FAIL;
 612
 613         /* The chip always seems to report that it is
 614          * write-protected, even when it is not.
 615          */
 616         setbits8(ctrl->addr, NAND_STATUS_WP);
 617         return fsl_elbc_read_byte(mtd);
 618 }
 619
 620 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 621 {
 622         struct nand_chip *chip = mtd->priv;
 623         struct fsl_elbc_mtd *priv = chip->priv;
 624         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 625         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 626         unsigned int al;
 627
 628         /* calculate FMR Address Length field */
 629         al = 0;
 630         if (chip->pagemask & 0xffff0000)
 631                 al++;
 632         if (chip->pagemask & 0xff000000)
 633                 al++;
 634
 635         /* add to ECCM mode set in fsl_elbc_init */
 636         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 637                      (al << FMR_AL_SHIFT);
 638
 639         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
 640                 chip->numchips);
 641         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
 642                 chip->chipsize);
 643         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 644                 chip->pagemask);
 645         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 646                 chip->chip_delay);
 647         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 648                 chip->badblockpos);
 649         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 650                 chip->chip_shift);
 651         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 652                 chip->page_shift);
 653         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 654                 chip->phys_erase_shift);
 655         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 656                 chip->ecclayout);
 657         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 658                 chip->ecc.mode);
 659         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 660                 chip->ecc.steps);
 661         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 662                 chip->ecc.bytes);
 663         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 664                 chip->ecc.total);
 665         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 666                 chip->ecc.layout);
 667         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 668         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
 669         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 670                 mtd->erasesize);
 671         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 672                 mtd->writesize);
 673         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 674                 mtd->oobsize);
 675
 676         /* adjust Option Register and ECC to match Flash page size */
 677         if (mtd->writesize == 512) {
 678                 priv->page_size = 0;
 679                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 680         } else if (mtd->writesize == 2048) {
 681                 priv->page_size = 1;
 682                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 683                 /* adjust ecc setup if needed */
 684                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 685                     BR_DECC_CHK_GEN) {
 686                         chip->ecc.size = 512;
 687                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 688                                            &fsl_elbc_oob_lp_eccm1 :
 689                                            &fsl_elbc_oob_lp_eccm0;
 690                         mtd->ecclayout = chip->ecc.layout;
 691                         mtd->oobavail = chip->ecc.layout->oobavail;
 692                 }
 693         } else {
 694                 dev_err(ctrl->dev,
 695                         "fsl_elbc_init: page size %d is not supported\n",
 696                         mtd->writesize);
 697                 return -1;
 698         }
 699
 700         return 0;
 701 }
 702
 703 static int fsl_elbc_read_page(struct mtd_info *mtd,
 704                               struct nand_chip *chip,
 705                               uint8_t *buf)
 706 {
 707         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 708         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 709
 710         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 711                 mtd->ecc_stats.failed++;
 712
 713         return 0;
 714 }
 715
 716 /* ECC will be calculated automatically, and errors will be detected in
 717  * waitfunc.
 718  */
 719 static void fsl_elbc_write_page(struct mtd_info *mtd,
 720                                 struct nand_chip *chip,
 721                                 const uint8_t *buf)
 722 {
 723         struct fsl_elbc_mtd *priv = chip->priv;
 724         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 725
 726         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 727         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 728
 729         ctrl->oob_poi = chip->oob_poi;
 730 }
 731
 732 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 733 {
 734         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 735         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 736         struct nand_chip *chip = &priv->chip;
 737
 738         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 739
 740         /* Fill in fsl_elbc_mtd structure */
 741         priv->mtd.priv = chip;
 742         priv->mtd.owner = THIS_MODULE;
 743         priv->fmr = 0; /* rest filled in later */
 744
 745         /* fill in nand_chip structure */
 746         /* set up function call table */
 747         chip->read_byte = fsl_elbc_read_byte;
 748         chip->write_buf = fsl_elbc_write_buf;
 749         chip->read_buf = fsl_elbc_read_buf;
 750         chip->verify_buf = fsl_elbc_verify_buf;
 751         chip->select_chip = fsl_elbc_select_chip;
 752         chip->cmdfunc = fsl_elbc_cmdfunc;
 753         chip->waitfunc = fsl_elbc_wait;
 754
 755         /* set up nand options */
 756         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 757
 758         chip->controller = &ctrl->controller;
 759         chip->priv = priv;
 760
 761         chip->ecc.read_page = fsl_elbc_read_page;
 762         chip->ecc.write_page = fsl_elbc_write_page;
 763
 764         /* If CS Base Register selects full hardware ECC then use it */
 765         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 766             BR_DECC_CHK_GEN) {
 767                 chip->ecc.mode = NAND_ECC_HW;
 768                 /* put in small page settings and adjust later if needed */
 769                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 770                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 771                 chip->ecc.size = 512;
 772                 chip->ecc.bytes = 3;
 773         } else {
 774                 /* otherwise fall back to default software ECC */
 775                 chip->ecc.mode = NAND_ECC_SOFT;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 782 {
 783         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 784
 785         nand_release(&priv->mtd);
 786
 787         kfree(priv->mtd.name);
 788
 789         if (priv->vbase)
 790                 iounmap(priv->vbase);
 791
 792         ctrl->chips[priv->bank] = NULL;
 793         kfree(priv);
 794
 795         return 0;
 796 }
 797
 798 static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
 799                                struct device_node *node)
 800 {
 801         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 802         struct fsl_elbc_mtd *priv;
 803         struct resource res;
 804 #ifdef CONFIG_MTD_PARTITIONS
 805         static const char *part_probe_types[]
 806                 = { "cmdlinepart", "RedBoot", NULL };
 807         struct mtd_partition *parts;
 808 #endif
 809         int ret;
 810         int bank;
 811
 812         /* get, allocate and map the memory resource */
 813         ret = of_address_to_resource(node, 0, &res);
 814         if (ret) {
 815                 dev_err(ctrl->dev, "failed to get resource\n");
 816                 return ret;
 817         }
 818
 819         /* find which chip select it is connected to */
 820         for (bank = 0; bank < MAX_BANKS; bank++)
 821                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 822                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 823                     (in_be32(&lbc->bank[bank].br) &
 824                      in_be32(&lbc->bank[bank].or) & BR_BA)
 825                      == res.start)
 826                         break;
 827
 828         if (bank >= MAX_BANKS) {
 829                 dev_err(ctrl->dev, "address did not match any chip selects\n");
 830                 return -ENODEV;
 831         }
 832
 833         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 834         if (!priv)
 835                 return -ENOMEM;
 836
 837         ctrl->chips[bank] = priv;
 838         priv->bank = bank;
 839         priv->ctrl = ctrl;
 840         priv->dev = ctrl->dev;
 841
 842         priv->vbase = ioremap(res.start, res.end - res.start + 1);
 843         if (!priv->vbase) {
 844                 dev_err(ctrl->dev, "failed to map chip region\n");
 845                 ret = -ENOMEM;
 846                 goto err;
 847         }
 848
 849         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", res.start);
 850         if (!priv->mtd.name) {
 851                 ret = -ENOMEM;
 852                 goto err;
 853         }
 854
 855         ret = fsl_elbc_chip_init(priv);
 856         if (ret)
 857                 goto err;
 858
 859         ret = nand_scan_ident(&priv->mtd, 1);
 860         if (ret)
 861                 goto err;
 862
 863         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 864         if (ret)
 865                 goto err;
 866
 867         ret = nand_scan_tail(&priv->mtd);
 868         if (ret)
 869                 goto err;
 870
 871 #ifdef CONFIG_MTD_PARTITIONS
 872         /* First look for RedBoot table or partitions on the command
 873          * line, these take precedence over device tree information */
 874         ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
 875         if (ret < 0)
 876                 goto err;
 877
 878 #ifdef CONFIG_MTD_OF_PARTS
 879         if (ret == 0) {
 880                 ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
 881                                               node, &parts);
 882                 if (ret < 0)
 883                         goto err;
 884         }
 885 #endif
 886
 887         if (ret > 0)
 888                 add_mtd_partitions(&priv->mtd, parts, ret);
 889         else
 890 #endif
 891                 add_mtd_device(&priv->mtd);
 892
 893         printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
 894                res.start, priv->bank);
 895         return 0;
 896
 897 err:
 898         fsl_elbc_chip_remove(priv);
 899         return ret;
 900 }
 901
 902 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 903 {
 904         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 905
 906         /* clear event registers */
 907         setbits32(&lbc->ltesr, LTESR_NAND_MASK);
 908         out_be32(&lbc->lteatr, 0);
 909
 910         /* Enable interrupts for any detected events */
 911         out_be32(&lbc->lteir, LTESR_NAND_MASK);
 912
 913         ctrl->read_bytes = 0;
 914         ctrl->index = 0;
 915         ctrl->addr = NULL;
 916
 917         return 0;
 918 }
 919
 920 static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
 921 {
 922         struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
 923         int i;
 924
 925         for (i = 0; i < MAX_BANKS; i++)
 926                 if (ctrl->chips[i])
 927                         fsl_elbc_chip_remove(ctrl->chips[i]);
 928
 929         if (ctrl->irq)
 930                 free_irq(ctrl->irq, ctrl);
 931
 932         if (ctrl->regs)
 933                 iounmap(ctrl->regs);
 934
 935         dev_set_drvdata(&ofdev->dev, NULL);
 936         kfree(ctrl);
 937         return 0;
 938 }
 939
 940 /* NOTE: This interrupt is also used to report other localbus events,
 941  * such as transaction errors on other chipselects.  If we want to
 942  * capture those, we'll need to move the IRQ code into a shared
 943  * LBC driver.
 944  */
 945
 946 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
 947 {
 948         struct fsl_elbc_ctrl *ctrl = data;
 949         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 950         __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
 951
 952         if (status) {
 953                 out_be32(&lbc->ltesr, status);
 954                 out_be32(&lbc->lteatr, 0);
 955
 956                 ctrl->irq_status = status;
 957                 smp_wmb();
 958                 wake_up(&ctrl->irq_wait);
 959
 960                 return IRQ_HANDLED;
 961         }
 962
 963         return IRQ_NONE;
 964 }
 965
 966 /* fsl_elbc_ctrl_probe
 967  *
 968  * called by device layer when it finds a device matching
 969  * one our driver can handled. This code allocates all of
 970  * the resources needed for the controller only.  The
 971  * resources for the NAND banks themselves are allocated
 972  * in the chip probe function.
 973 */
 974
 975 static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
 976                                          const struct of_device_id *match)
 977 {
 978         struct device_node *child;
 979         struct fsl_elbc_ctrl *ctrl;
 980         int ret;
 981
 982         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 983         if (!ctrl)
 984                 return -ENOMEM;
 985
 986         dev_set_drvdata(&ofdev->dev, ctrl);
 987
 988         spin_lock_init(&ctrl->controller.lock);
 989         init_waitqueue_head(&ctrl->controller.wq);
 990         init_waitqueue_head(&ctrl->irq_wait);
 991
 992         ctrl->regs = of_iomap(ofdev->node, 0);
 993         if (!ctrl->regs) {
 994                 dev_err(&ofdev->dev, "failed to get memory region\n");
 995                 ret = -ENODEV;
 996                 goto err;
 997         }
 998
 999         ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
1000         if (ctrl->irq == NO_IRQ) {
1001                 dev_err(&ofdev->dev, "failed to get irq resource\n");
1002                 ret = -ENODEV;
1003                 goto err;
1004         }
1005
1006         ctrl->dev = &ofdev->dev;
1007
1008         ret = fsl_elbc_ctrl_init(ctrl);
1009         if (ret < 0)
1010                 goto err;
1011
1012         ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1013         if (ret != 0) {
1014                 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1015                         ctrl->irq);
1016                 ret = ctrl->irq;
1017                 goto err;
1018         }
1019
1020         for_each_child_of_node(ofdev->node, child)
1021                 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1022                         fsl_elbc_chip_probe(ctrl, child);
1023
1024         return 0;
1025
1026 err:
1027         fsl_elbc_ctrl_remove(ofdev);
1028         return ret;
1029 }
1030
1031 static const struct of_device_id fsl_elbc_match[] = {
1032         {
1033                 .compatible = "fsl,elbc",
1034         },
1035         {}
1036 };
1037
1038 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1039         .driver = {
1040                 .name   = "fsl-elbc",
1041         },
1042         .match_table = fsl_elbc_match,
1043         .probe = fsl_elbc_ctrl_probe,
1044         .remove = __devexit_p(fsl_elbc_ctrl_remove),
1045 };
1046
1047 static int __init fsl_elbc_init(void)
1048 {
1049         return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1050 }
1051
1052 static void __exit fsl_elbc_exit(void)
1053 {
1054         of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1055 }
1056
1057 module_init(fsl_elbc_init);
1058 module_exit(fsl_elbc_exit);
1059
1060 MODULE_LICENSE("GPL");
1061 MODULE_AUTHOR("Freescale");
1062 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");