drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *          Jack Lan <jack.lan@freescale.com>
   8  *          Roy Zang <tie-fei.zang@freescale.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/types.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/string.h>
  30 #include <linux/ioport.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/interrupt.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/fsl_lbc.h>
  43
  44 #define MAX_BANKS 8
  45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  47
  48 /* mtd information per set */
  49
  50 struct fsl_elbc_mtd {
  51         struct mtd_info mtd;
  52         struct nand_chip chip;
  53         struct fsl_lbc_ctrl *ctrl;
  54
  55         struct device *dev;
  56         int bank;               /* Chip select bank number           */
  57         u8 __iomem *vbase;      /* Chip select base virtual address  */
  58         int page_size;          /* NAND page size (0=512, 1=2048)    */
  59         unsigned int fmr;       /* FCM Flash Mode Register value     */
  60 };
  61
  62 /* Freescale eLBC FCM controller information */
  63
  64 struct fsl_elbc_fcm_ctrl {
  65         struct nand_hw_control controller;
  66         struct fsl_elbc_mtd *chips[MAX_BANKS];
  67
  68         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  69         unsigned int page;       /* Last page written to / read from      */
  70         unsigned int read_bytes; /* Number of bytes read during command   */
  71         unsigned int column;     /* Saved column from SEQIN               */
  72         unsigned int index;      /* Pointer to next byte to 'read'        */
  73         unsigned int status;     /* status read from LTESR after last op  */
  74         unsigned int mdr;        /* UPM/FCM Data Register value           */
  75         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  76         unsigned int oob;        /* Non zero if operating on OOB data     */
  77         unsigned int counter;    /* counter for the initializations       */
  78 };
  79
  80 /* These map to the positions used by the FCM hardware ECC generator */
  81
  82 /* Small Page FLASH with FMR[ECCM] = 0 */
  83 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  84         .eccbytes = 3,
  85         .eccpos = {6, 7, 8},
  86         .oobfree = { {0, 5}, {9, 7} },
  87 };
  88
  89 /* Small Page FLASH with FMR[ECCM] = 1 */
  90 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  91         .eccbytes = 3,
  92         .eccpos = {8, 9, 10},
  93         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  94 };
  95
  96 /* Large Page FLASH with FMR[ECCM] = 0 */
  97 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  98         .eccbytes = 12,
  99         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 100         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 101 };
 102
 103 /* Large Page FLASH with FMR[ECCM] = 1 */
 104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 105         .eccbytes = 12,
 106         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 107         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 108 };
 109
 110 /*
 111  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 112  * 1, so we have to adjust bad block pattern. This pattern should be used for
 113  * x8 chips only. So far hardware does not support x16 chips anyway.
 114  */
 115 static u8 scan_ff_pattern[] = { 0xff, };
 116
 117 static struct nand_bbt_descr largepage_memorybased = {
 118         .options = 0,
 119         .offs = 0,
 120         .len = 1,
 121         .pattern = scan_ff_pattern,
 122 };
 123
 124 /*
 125  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 126  * interfere with ECC positions, that's why we implement our own descriptors.
 127  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 128  */
 129 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 130 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 131
 132 static struct nand_bbt_descr bbt_main_descr = {
 133         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 134                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 135         .offs = 11,
 136         .len = 4,
 137         .veroffs = 15,
 138         .maxblocks = 4,
 139         .pattern = bbt_pattern,
 140 };
 141
 142 static struct nand_bbt_descr bbt_mirror_descr = {
 143         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 144                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 145         .offs = 11,
 146         .len = 4,
 147         .veroffs = 15,
 148         .maxblocks = 4,
 149         .pattern = mirror_pattern,
 150 };
 151
 152 /*=================================*/
 153
 154 /*
 155  * Set up the FCM hardware block and page address fields, and the fcm
 156  * structure addr field to point to the correct FCM buffer in memory
 157  */
 158 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 159 {
 160         struct nand_chip *chip = mtd->priv;
 161         struct fsl_elbc_mtd *priv = chip->priv;
 162         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 163         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 164         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 165         int buf_num;
 166
 167         elbc_fcm_ctrl->page = page_addr;
 168
 169         out_be32(&lbc->fbar,
 170                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 171
 172         if (priv->page_size) {
 173                 out_be32(&lbc->fpar,
 174                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 175                          (oob ? FPAR_LP_MS : 0) | column);
 176                 buf_num = (page_addr & 1) << 2;
 177         } else {
 178                 out_be32(&lbc->fpar,
 179                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 180                          (oob ? FPAR_SP_MS : 0) | column);
 181                 buf_num = page_addr & 7;
 182         }
 183
 184         elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
 185         elbc_fcm_ctrl->index = column;
 186
 187         /* for OOB data point to the second half of the buffer */
 188         if (oob)
 189                 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
 190
 191         dev_vdbg(priv->dev, "set_addr: bank=%d, "
 192                             "elbc_fcm_ctrl->addr=0x%p (0x%p), "
 193                             "index %x, pes %d ps %d\n",
 194                  buf_num, elbc_fcm_ctrl->addr, priv->vbase,
 195                  elbc_fcm_ctrl->index,
 196                  chip->phys_erase_shift, chip->page_shift);
 197 }
 198
 199 /*
 200  * execute FCM command and wait for it to complete
 201  */
 202 static int fsl_elbc_run_command(struct mtd_info *mtd)
 203 {
 204         struct nand_chip *chip = mtd->priv;
 205         struct fsl_elbc_mtd *priv = chip->priv;
 206         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 207         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 208         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 209
 210         /* Setup the FMR[OP] to execute without write protection */
 211         out_be32(&lbc->fmr, priv->fmr | 3);
 212         if (elbc_fcm_ctrl->use_mdr)
 213                 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
 214
 215         dev_vdbg(priv->dev,
 216                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 217                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 218         dev_vdbg(priv->dev,
 219                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 220                  "fbcr=%08x bank=%d\n",
 221                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 222                  in_be32(&lbc->fbcr), priv->bank);
 223
 224         ctrl->irq_status = 0;
 225         /* execute special operation */
 226         out_be32(&lbc->lsor, priv->bank);
 227
 228         /* wait for FCM complete flag or timeout */
 229         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 230                            FCM_TIMEOUT_MSECS * HZ/1000);
 231         elbc_fcm_ctrl->status = ctrl->irq_status;
 232         /* store mdr value in case it was needed */
 233         if (elbc_fcm_ctrl->use_mdr)
 234                 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
 235
 236         elbc_fcm_ctrl->use_mdr = 0;
 237
 238         if (elbc_fcm_ctrl->status != LTESR_CC) {
 239                 dev_info(priv->dev,
 240                          "command failed: fir %x fcr %x status %x mdr %x\n",
 241                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
 242                          elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
 243                 return -EIO;
 244         }
 245
 246         if (chip->ecc.mode != NAND_ECC_HW)
 247                 return 0;
 248
 249         if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
 250                 uint32_t lteccr = in_be32(&lbc->lteccr);
 251                 /*
 252                  * if command was a full page read and the ELBC
 253                  * has the LTECCR register, then bits 12-15 (ppc order) of
 254                  * LTECCR indicates which 512 byte sub-pages had fixed errors.
 255                  * bits 28-31 are uncorrectable errors, marked elsewhere.
 256                  * for small page nand only 1 bit is used.
 257                  * if the ELBC doesn't have the lteccr register it reads 0
 258                  */
 259                 if (lteccr & 0x000F000F)
 260                         out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
 261                 if (lteccr & 0x000F0000)
 262                         mtd->ecc_stats.corrected++;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 269 {
 270         struct fsl_elbc_mtd *priv = chip->priv;
 271         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 272         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 273
 274         if (priv->page_size) {
 275                 out_be32(&lbc->fir,
 276                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 277                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 278                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 279                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
 280                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 281
 282                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 283                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 284         } else {
 285                 out_be32(&lbc->fir,
 286                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 287                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 288                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 289                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 290
 291                 if (oob)
 292                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 293                 else
 294                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 295         }
 296 }
 297
 298 /* cmdfunc send commands to the FCM */
 299 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 300                              int column, int page_addr)
 301 {
 302         struct nand_chip *chip = mtd->priv;
 303         struct fsl_elbc_mtd *priv = chip->priv;
 304         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 305         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 306         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 307
 308         elbc_fcm_ctrl->use_mdr = 0;
 309
 310         /* clear the read buffer */
 311         elbc_fcm_ctrl->read_bytes = 0;
 312         if (command != NAND_CMD_PAGEPROG)
 313                 elbc_fcm_ctrl->index = 0;
 314
 315         switch (command) {
 316         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 317         case NAND_CMD_READ1:
 318                 column += 256;
 319
 320         /* fall-through */
 321         case NAND_CMD_READ0:
 322                 dev_dbg(priv->dev,
 323                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 324                         " 0x%x, column: 0x%x.\n", page_addr, column);
 325
 326
 327                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 328                 set_addr(mtd, 0, page_addr, 0);
 329
 330                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 331                 elbc_fcm_ctrl->index += column;
 332
 333                 fsl_elbc_do_read(chip, 0);
 334                 fsl_elbc_run_command(mtd);
 335                 return;
 336
 337         /* READOOB reads only the OOB because no ECC is performed. */
 338         case NAND_CMD_READOOB:
 339                 dev_vdbg(priv->dev,
 340                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 341                          " 0x%x, column: 0x%x.\n", page_addr, column);
 342
 343                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 344                 set_addr(mtd, column, page_addr, 1);
 345
 346                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 347
 348                 fsl_elbc_do_read(chip, 1);
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* READID must read all 5 possible bytes while CEB is active */
 353         case NAND_CMD_READID:
 354                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 355
 356                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 357                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 358                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 359                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 360                 /* nand_get_flash_type() reads 8 bytes of entire ID string */
 361                 out_be32(&lbc->fbcr, 8);
 362                 elbc_fcm_ctrl->read_bytes = 8;
 363                 elbc_fcm_ctrl->use_mdr = 1;
 364                 elbc_fcm_ctrl->mdr = 0;
 365
 366                 set_addr(mtd, 0, 0, 0);
 367                 fsl_elbc_run_command(mtd);
 368                 return;
 369
 370         /* ERASE1 stores the block and page address */
 371         case NAND_CMD_ERASE1:
 372                 dev_vdbg(priv->dev,
 373                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 374                          "page_addr: 0x%x.\n", page_addr);
 375                 set_addr(mtd, 0, page_addr, 0);
 376                 return;
 377
 378         /* ERASE2 uses the block and page address from ERASE1 */
 379         case NAND_CMD_ERASE2:
 380                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 381
 382                 out_be32(&lbc->fir,
 383                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 384                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 385                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
 386                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 387                          (FIR_OP_RS  << FIR_OP4_SHIFT));
 388
 389                 out_be32(&lbc->fcr,
 390                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 391                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
 392                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
 393
 394                 out_be32(&lbc->fbcr, 0);
 395                 elbc_fcm_ctrl->read_bytes = 0;
 396                 elbc_fcm_ctrl->use_mdr = 1;
 397
 398                 fsl_elbc_run_command(mtd);
 399                 return;
 400
 401         /* SEQIN sets up the addr buffer and all registers except the length */
 402         case NAND_CMD_SEQIN: {
 403                 __be32 fcr;
 404                 dev_vdbg(priv->dev,
 405                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 406                          "page_addr: 0x%x, column: 0x%x.\n",
 407                          page_addr, column);
 408
 409                 elbc_fcm_ctrl->column = column;
 410                 elbc_fcm_ctrl->oob = 0;
 411                 elbc_fcm_ctrl->use_mdr = 1;
 412
 413                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
 414                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
 415                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
 416
 417                 if (priv->page_size) {
 418                         out_be32(&lbc->fir,
 419                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
 420                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 421                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 422                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 423                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
 424                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
 425                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
 426                 } else {
 427                         out_be32(&lbc->fir,
 428                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 429                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 430                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 431                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 432                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 433                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
 434                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
 435                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
 436
 437                         if (column >= mtd->writesize) {
 438                                 /* OOB area --> READOOB */
 439                                 column -= mtd->writesize;
 440                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 441                                 elbc_fcm_ctrl->oob = 1;
 442                         } else {
 443                                 WARN_ON(column != 0);
 444                                 /* First 256 bytes --> READ0 */
 445                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 446                         }
 447                 }
 448
 449                 out_be32(&lbc->fcr, fcr);
 450                 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
 451                 return;
 452         }
 453
 454         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 455         case NAND_CMD_PAGEPROG: {
 456                 dev_vdbg(priv->dev,
 457                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 458                          "writing %d bytes.\n", elbc_fcm_ctrl->index);
 459
 460                 /* if the write did not start at 0 or is not a full page
 461                  * then set the exact length, otherwise use a full page
 462                  * write so the HW generates the ECC.
 463                  */
 464                 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
 465                     elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
 466                         out_be32(&lbc->fbcr, elbc_fcm_ctrl->index);
 467                 else
 468                         out_be32(&lbc->fbcr, 0);
 469
 470                 fsl_elbc_run_command(mtd);
 471                 return;
 472         }
 473
 474         /* CMD_STATUS must read the status byte while CEB is active */
 475         /* Note - it does not wait for the ready line */
 476         case NAND_CMD_STATUS:
 477                 out_be32(&lbc->fir,
 478                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 479                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 480                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 481                 out_be32(&lbc->fbcr, 1);
 482                 set_addr(mtd, 0, 0, 0);
 483                 elbc_fcm_ctrl->read_bytes = 1;
 484
 485                 fsl_elbc_run_command(mtd);
 486
 487                 /* The chip always seems to report that it is
 488                  * write-protected, even when it is not.
 489                  */
 490                 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
 491                 return;
 492
 493         /* RESET without waiting for the ready line */
 494         case NAND_CMD_RESET:
 495                 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 496                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 497                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 498                 fsl_elbc_run_command(mtd);
 499                 return;
 500
 501         default:
 502                 dev_err(priv->dev,
 503                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 504                         command);
 505         }
 506 }
 507
 508 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 509 {
 510         /* The hardware does not seem to support multiple
 511          * chips per bank.
 512          */
 513 }
 514
 515 /*
 516  * Write buf to the FCM Controller Data Buffer
 517  */
 518 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 519 {
 520         struct nand_chip *chip = mtd->priv;
 521         struct fsl_elbc_mtd *priv = chip->priv;
 522         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 523         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 524
 525         if (len <= 0) {
 526                 dev_err(priv->dev, "write_buf of %d bytes", len);
 527                 elbc_fcm_ctrl->status = 0;
 528                 return;
 529         }
 530
 531         if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
 532                 dev_err(priv->dev,
 533                         "write_buf beyond end of buffer "
 534                         "(%d requested, %u available)\n",
 535                         len, bufsize - elbc_fcm_ctrl->index);
 536                 len = bufsize - elbc_fcm_ctrl->index;
 537         }
 538
 539         memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
 540         /*
 541          * This is workaround for the weird elbc hangs during nand write,
 542          * Scott Wood says: "...perhaps difference in how long it takes a
 543          * write to make it through the localbus compared to a write to IMMR
 544          * is causing problems, and sync isn't helping for some reason."
 545          * Reading back the last byte helps though.
 546          */
 547         in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
 548
 549         elbc_fcm_ctrl->index += len;
 550 }
 551
 552 /*
 553  * read a byte from either the FCM hardware buffer if it has any data left
 554  * otherwise issue a command to read a single byte.
 555  */
 556 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 557 {
 558         struct nand_chip *chip = mtd->priv;
 559         struct fsl_elbc_mtd *priv = chip->priv;
 560         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 561
 562         /* If there are still bytes in the FCM, then use the next byte. */
 563         if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
 564                 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
 565
 566         dev_err(priv->dev, "read_byte beyond end of buffer\n");
 567         return ERR_BYTE;
 568 }
 569
 570 /*
 571  * Read from the FCM Controller Data Buffer
 572  */
 573 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 574 {
 575         struct nand_chip *chip = mtd->priv;
 576         struct fsl_elbc_mtd *priv = chip->priv;
 577         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 578         int avail;
 579
 580         if (len < 0)
 581                 return;
 582
 583         avail = min((unsigned int)len,
 584                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 585         memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
 586         elbc_fcm_ctrl->index += avail;
 587
 588         if (len > avail)
 589                 dev_err(priv->dev,
 590                         "read_buf beyond end of buffer "
 591                         "(%d requested, %d available)\n",
 592                         len, avail);
 593 }
 594
 595 /*
 596  * Verify buffer against the FCM Controller Data Buffer
 597  */
 598 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 599 {
 600         struct nand_chip *chip = mtd->priv;
 601         struct fsl_elbc_mtd *priv = chip->priv;
 602         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 603         int i;
 604
 605         if (len < 0) {
 606                 dev_err(priv->dev, "write_buf of %d bytes", len);
 607                 return -EINVAL;
 608         }
 609
 610         if ((unsigned int)len >
 611                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
 612                 dev_err(priv->dev,
 613                         "verify_buf beyond end of buffer "
 614                         "(%d requested, %u available)\n",
 615                         len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 616
 617                 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
 618                 return -EINVAL;
 619         }
 620
 621         for (i = 0; i < len; i++)
 622                 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
 623                                 != buf[i])
 624                         break;
 625
 626         elbc_fcm_ctrl->index += len;
 627         return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
 628 }
 629
 630 /* This function is called after Program and Erase Operations to
 631  * check for success or failure.
 632  */
 633 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 634 {
 635         struct fsl_elbc_mtd *priv = chip->priv;
 636         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 637
 638         if (elbc_fcm_ctrl->status != LTESR_CC)
 639                 return NAND_STATUS_FAIL;
 640
 641         /* The chip always seems to report that it is
 642          * write-protected, even when it is not.
 643          */
 644         return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
 645 }
 646
 647 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 648 {
 649         struct nand_chip *chip = mtd->priv;
 650         struct fsl_elbc_mtd *priv = chip->priv;
 651         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 652         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 653         unsigned int al;
 654
 655         /* calculate FMR Address Length field */
 656         al = 0;
 657         if (chip->pagemask & 0xffff0000)
 658                 al++;
 659         if (chip->pagemask & 0xff000000)
 660                 al++;
 661
 662         /* add to ECCM mode set in fsl_elbc_init */
 663         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 664                      (al << FMR_AL_SHIFT);
 665
 666         dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
 667                 chip->numchips);
 668         dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
 669                 chip->chipsize);
 670         dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 671                 chip->pagemask);
 672         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 673                 chip->chip_delay);
 674         dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 675                 chip->badblockpos);
 676         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 677                 chip->chip_shift);
 678         dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 679                 chip->page_shift);
 680         dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 681                 chip->phys_erase_shift);
 682         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 683                 chip->ecclayout);
 684         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 685                 chip->ecc.mode);
 686         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 687                 chip->ecc.steps);
 688         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 689                 chip->ecc.bytes);
 690         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 691                 chip->ecc.total);
 692         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 693                 chip->ecc.layout);
 694         dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 695         dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
 696         dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 697                 mtd->erasesize);
 698         dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 699                 mtd->writesize);
 700         dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 701                 mtd->oobsize);
 702
 703         /* adjust Option Register and ECC to match Flash page size */
 704         if (mtd->writesize == 512) {
 705                 priv->page_size = 0;
 706                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 707         } else if (mtd->writesize == 2048) {
 708                 priv->page_size = 1;
 709                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 710                 /* adjust ecc setup if needed */
 711                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 712                     BR_DECC_CHK_GEN) {
 713                         chip->ecc.size = 512;
 714                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 715                                            &fsl_elbc_oob_lp_eccm1 :
 716                                            &fsl_elbc_oob_lp_eccm0;
 717                         chip->badblock_pattern = &largepage_memorybased;
 718                 }
 719         } else {
 720                 dev_err(priv->dev,
 721                         "fsl_elbc_init: page size %d is not supported\n",
 722                         mtd->writesize);
 723                 return -1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int fsl_elbc_read_page(struct mtd_info *mtd,
 730                               struct nand_chip *chip,
 731                               uint8_t *buf,
 732                               int page)
 733 {
 734         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 735         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 736
 737         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 738                 mtd->ecc_stats.failed++;
 739
 740         return 0;
 741 }
 742
 743 /* ECC will be calculated automatically, and errors will be detected in
 744  * waitfunc.
 745  */
 746 static void fsl_elbc_write_page(struct mtd_info *mtd,
 747                                 struct nand_chip *chip,
 748                                 const uint8_t *buf)
 749 {
 750         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 751         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 752 }
 753
 754 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 755 {
 756         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 757         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 758         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 759         struct nand_chip *chip = &priv->chip;
 760
 761         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 762
 763         /* Fill in fsl_elbc_mtd structure */
 764         priv->mtd.priv = chip;
 765         priv->mtd.owner = THIS_MODULE;
 766
 767         /* Set the ECCM according to the settings in bootloader.*/
 768         priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
 769
 770         /* fill in nand_chip structure */
 771         /* set up function call table */
 772         chip->read_byte = fsl_elbc_read_byte;
 773         chip->write_buf = fsl_elbc_write_buf;
 774         chip->read_buf = fsl_elbc_read_buf;
 775         chip->verify_buf = fsl_elbc_verify_buf;
 776         chip->select_chip = fsl_elbc_select_chip;
 777         chip->cmdfunc = fsl_elbc_cmdfunc;
 778         chip->waitfunc = fsl_elbc_wait;
 779
 780         chip->bbt_td = &bbt_main_descr;
 781         chip->bbt_md = &bbt_mirror_descr;
 782
 783         /* set up nand options */
 784         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 785         chip->bbt_options = NAND_BBT_USE_FLASH;
 786
 787         chip->controller = &elbc_fcm_ctrl->controller;
 788         chip->priv = priv;
 789
 790         chip->ecc.read_page = fsl_elbc_read_page;
 791         chip->ecc.write_page = fsl_elbc_write_page;
 792
 793         /* If CS Base Register selects full hardware ECC then use it */
 794         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 795             BR_DECC_CHK_GEN) {
 796                 chip->ecc.mode = NAND_ECC_HW;
 797                 /* put in small page settings and adjust later if needed */
 798                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 799                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 800                 chip->ecc.size = 512;
 801                 chip->ecc.bytes = 3;
 802         } else {
 803                 /* otherwise fall back to default software ECC */
 804                 chip->ecc.mode = NAND_ECC_SOFT;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 811 {
 812         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 813         nand_release(&priv->mtd);
 814
 815         kfree(priv->mtd.name);
 816
 817         if (priv->vbase)
 818                 iounmap(priv->vbase);
 819
 820         elbc_fcm_ctrl->chips[priv->bank] = NULL;
 821         kfree(priv);
 822         return 0;
 823 }
 824
 825 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
 826
 827 static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
 828 {
 829         struct fsl_lbc_regs __iomem *lbc;
 830         struct fsl_elbc_mtd *priv;
 831         struct resource res;
 832         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
 833         static const char *part_probe_types[]
 834                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 835         int ret;
 836         int bank;
 837         struct device *dev;
 838         struct device_node *node = pdev->dev.of_node;
 839         struct mtd_part_parser_data ppdata;
 840
 841         ppdata.of_node = pdev->dev.of_node;
 842         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
 843                 return -ENODEV;
 844         lbc = fsl_lbc_ctrl_dev->regs;
 845         dev = fsl_lbc_ctrl_dev->dev;
 846
 847         /* get, allocate and map the memory resource */
 848         ret = of_address_to_resource(node, 0, &res);
 849         if (ret) {
 850                 dev_err(dev, "failed to get resource\n");
 851                 return ret;
 852         }
 853
 854         /* find which chip select it is connected to */
 855         for (bank = 0; bank < MAX_BANKS; bank++)
 856                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 857                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 858                     (in_be32(&lbc->bank[bank].br) &
 859                      in_be32(&lbc->bank[bank].or) & BR_BA)
 860                      == fsl_lbc_addr(res.start))
 861                         break;
 862
 863         if (bank >= MAX_BANKS) {
 864                 dev_err(dev, "address did not match any chip selects\n");
 865                 return -ENODEV;
 866         }
 867
 868         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 869         if (!priv)
 870                 return -ENOMEM;
 871
 872         mutex_lock(&fsl_elbc_nand_mutex);
 873         if (!fsl_lbc_ctrl_dev->nand) {
 874                 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
 875                 if (!elbc_fcm_ctrl) {
 876                         dev_err(dev, "failed to allocate memory\n");
 877                         mutex_unlock(&fsl_elbc_nand_mutex);
 878                         ret = -ENOMEM;
 879                         goto err;
 880                 }
 881                 elbc_fcm_ctrl->counter++;
 882
 883                 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
 884                 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
 885                 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
 886         } else {
 887                 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 888         }
 889         mutex_unlock(&fsl_elbc_nand_mutex);
 890
 891         elbc_fcm_ctrl->chips[bank] = priv;
 892         priv->bank = bank;
 893         priv->ctrl = fsl_lbc_ctrl_dev;
 894         priv->dev = dev;
 895
 896         priv->vbase = ioremap(res.start, resource_size(&res));
 897         if (!priv->vbase) {
 898                 dev_err(dev, "failed to map chip region\n");
 899                 ret = -ENOMEM;
 900                 goto err;
 901         }
 902
 903         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
 904         if (!priv->mtd.name) {
 905                 ret = -ENOMEM;
 906                 goto err;
 907         }
 908
 909         ret = fsl_elbc_chip_init(priv);
 910         if (ret)
 911                 goto err;
 912
 913         ret = nand_scan_ident(&priv->mtd, 1, NULL);
 914         if (ret)
 915                 goto err;
 916
 917         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 918         if (ret)
 919                 goto err;
 920
 921         ret = nand_scan_tail(&priv->mtd);
 922         if (ret)
 923                 goto err;
 924
 925         /* First look for RedBoot table or partitions on the command
 926          * line, these take precedence over device tree information */
 927         mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
 928                                   NULL, 0);
 929
 930         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
 931                (unsigned long long)res.start, priv->bank);
 932         return 0;
 933
 934 err:
 935         fsl_elbc_chip_remove(priv);
 936         return ret;
 937 }
 938
 939 static int fsl_elbc_nand_remove(struct platform_device *pdev)
 940 {
 941         int i;
 942         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 943         for (i = 0; i < MAX_BANKS; i++)
 944                 if (elbc_fcm_ctrl->chips[i])
 945                         fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
 946
 947         mutex_lock(&fsl_elbc_nand_mutex);
 948         elbc_fcm_ctrl->counter--;
 949         if (!elbc_fcm_ctrl->counter) {
 950                 fsl_lbc_ctrl_dev->nand = NULL;
 951                 kfree(elbc_fcm_ctrl);
 952         }
 953         mutex_unlock(&fsl_elbc_nand_mutex);
 954
 955         return 0;
 956
 957 }
 958
 959 static const struct of_device_id fsl_elbc_nand_match[] = {
 960         { .compatible = "fsl,elbc-fcm-nand", },
 961         {}
 962 };
 963
 964 static struct platform_driver fsl_elbc_nand_driver = {
 965         .driver = {
 966                 .name = "fsl,elbc-fcm-nand",
 967                 .owner = THIS_MODULE,
 968                 .of_match_table = fsl_elbc_nand_match,
 969         },
 970         .probe = fsl_elbc_nand_probe,
 971         .remove = fsl_elbc_nand_remove,
 972 };
 973
 974 static int __init fsl_elbc_nand_init(void)
 975 {
 976         return platform_driver_register(&fsl_elbc_nand_driver);
 977 }
 978
 979 static void __exit fsl_elbc_nand_exit(void)
 980 {
 981         platform_driver_unregister(&fsl_elbc_nand_driver);
 982 }
 983
 984 module_init(fsl_elbc_nand_init);
 985 module_exit(fsl_elbc_nand_exit);
 986
 987 MODULE_LICENSE("GPL");
 988 MODULE_AUTHOR("Freescale");
 989 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");