drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright (c) 2006-2007 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/string.h>
  28 #include <linux/ioport.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/nand.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <linux/mtd/partitions.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/fsl_lbc.h>
  40
  41 #define MAX_BANKS 8
  42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  44
  45 struct fsl_elbc_ctrl;
  46
  47 /* mtd information per set */
  48
  49 struct fsl_elbc_mtd {
  50         struct mtd_info mtd;
  51         struct nand_chip chip;
  52         struct fsl_elbc_ctrl *ctrl;
  53
  54         struct device *dev;
  55         int bank;               /* Chip select bank number           */
  56         u8 __iomem *vbase;      /* Chip select base virtual address  */
  57         int page_size;          /* NAND page size (0=512, 1=2048)    */
  58         unsigned int fmr;       /* FCM Flash Mode Register value     */
  59 };
  60
  61 /* overview of the fsl elbc controller */
  62
  63 struct fsl_elbc_ctrl {
  64         struct nand_hw_control controller;
  65         struct fsl_elbc_mtd *chips[MAX_BANKS];
  66
  67         /* device info */
  68         struct device *dev;
  69         struct fsl_lbc_regs __iomem *regs;
  70         int irq;
  71         wait_queue_head_t irq_wait;
  72         unsigned int irq_status; /* status read from LTESR by irq handler */
  73         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  74         unsigned int page;       /* Last page written to / read from      */
  75         unsigned int read_bytes; /* Number of bytes read during command   */
  76         unsigned int column;     /* Saved column from SEQIN               */
  77         unsigned int index;      /* Pointer to next byte to 'read'        */
  78         unsigned int status;     /* status read from LTESR after last op  */
  79         unsigned int mdr;        /* UPM/FCM Data Register value           */
  80         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  81         unsigned int oob;        /* Non zero if operating on OOB data     */
  82         char *oob_poi;           /* Place to write ECC after read back    */
  83 };
  84
  85 /* These map to the positions used by the FCM hardware ECC generator */
  86
  87 /* Small Page FLASH with FMR[ECCM] = 0 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  89         .eccbytes = 3,
  90         .eccpos = {6, 7, 8},
  91         .oobfree = { {0, 5}, {9, 7} },
  92         .oobavail = 12,
  93 };
  94
  95 /* Small Page FLASH with FMR[ECCM] = 1 */
  96 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  97         .eccbytes = 3,
  98         .eccpos = {8, 9, 10},
  99         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 100         .oobavail = 12,
 101 };
 102
 103 /* Large Page FLASH with FMR[ECCM] = 0 */
 104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 105         .eccbytes = 12,
 106         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 107         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 108         .oobavail = 48,
 109 };
 110
 111 /* Large Page FLASH with FMR[ECCM] = 1 */
 112 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 113         .eccbytes = 12,
 114         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 115         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 116         .oobavail = 48,
 117 };
 118
 119 /*=================================*/
 120
 121 /*
 122  * Set up the FCM hardware block and page address fields, and the fcm
 123  * structure addr field to point to the correct FCM buffer in memory
 124  */
 125 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 126 {
 127         struct nand_chip *chip = mtd->priv;
 128         struct fsl_elbc_mtd *priv = chip->priv;
 129         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 130         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 131         int buf_num;
 132
 133         ctrl->page = page_addr;
 134
 135         out_be32(&lbc->fbar,
 136                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 137
 138         if (priv->page_size) {
 139                 out_be32(&lbc->fpar,
 140                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 141                          (oob ? FPAR_LP_MS : 0) | column);
 142                 buf_num = (page_addr & 1) << 2;
 143         } else {
 144                 out_be32(&lbc->fpar,
 145                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 146                          (oob ? FPAR_SP_MS : 0) | column);
 147                 buf_num = page_addr & 7;
 148         }
 149
 150         ctrl->addr = priv->vbase + buf_num * 1024;
 151         ctrl->index = column;
 152
 153         /* for OOB data point to the second half of the buffer */
 154         if (oob)
 155                 ctrl->index += priv->page_size ? 2048 : 512;
 156
 157         dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 158                             "index %x, pes %d ps %d\n",
 159                  buf_num, ctrl->addr, priv->vbase, ctrl->index,
 160                  chip->phys_erase_shift, chip->page_shift);
 161 }
 162
 163 /*
 164  * execute FCM command and wait for it to complete
 165  */
 166 static int fsl_elbc_run_command(struct mtd_info *mtd)
 167 {
 168         struct nand_chip *chip = mtd->priv;
 169         struct fsl_elbc_mtd *priv = chip->priv;
 170         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 171         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 172
 173         /* Setup the FMR[OP] to execute without write protection */
 174         out_be32(&lbc->fmr, priv->fmr | 3);
 175         if (ctrl->use_mdr)
 176                 out_be32(&lbc->mdr, ctrl->mdr);
 177
 178         dev_vdbg(ctrl->dev,
 179                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 180                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 181         dev_vdbg(ctrl->dev,
 182                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 183                  "fbcr=%08x bank=%d\n",
 184                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 185                  in_be32(&lbc->fbcr), priv->bank);
 186
 187         /* execute special operation */
 188         out_be32(&lbc->lsor, priv->bank);
 189
 190         /* wait for FCM complete flag or timeout */
 191         ctrl->irq_status = 0;
 192         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 193                            FCM_TIMEOUT_MSECS * HZ/1000);
 194         ctrl->status = ctrl->irq_status;
 195
 196         /* store mdr value in case it was needed */
 197         if (ctrl->use_mdr)
 198                 ctrl->mdr = in_be32(&lbc->mdr);
 199
 200         ctrl->use_mdr = 0;
 201
 202         dev_vdbg(ctrl->dev,
 203                  "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 204                  ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 205
 206         /* returns 0 on success otherwise non-zero) */
 207         return ctrl->status == LTESR_CC ? 0 : -EIO;
 208 }
 209
 210 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 211 {
 212         struct fsl_elbc_mtd *priv = chip->priv;
 213         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 214         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 215
 216         if (priv->page_size) {
 217                 out_be32(&lbc->fir,
 218                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 219                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 220                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 221                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 222                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 223
 224                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 225                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 226         } else {
 227                 out_be32(&lbc->fir,
 228                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 229                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 230                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 231                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 232
 233                 if (oob)
 234                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 235                 else
 236                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 237         }
 238 }
 239
 240 /* cmdfunc send commands to the FCM */
 241 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 242                              int column, int page_addr)
 243 {
 244         struct nand_chip *chip = mtd->priv;
 245         struct fsl_elbc_mtd *priv = chip->priv;
 246         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 247         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 248
 249         ctrl->use_mdr = 0;
 250
 251         /* clear the read buffer */
 252         ctrl->read_bytes = 0;
 253         if (command != NAND_CMD_PAGEPROG)
 254                 ctrl->index = 0;
 255
 256         switch (command) {
 257         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 258         case NAND_CMD_READ1:
 259                 column += 256;
 260
 261         /* fall-through */
 262         case NAND_CMD_READ0:
 263                 dev_dbg(ctrl->dev,
 264                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 265                         " 0x%x, column: 0x%x.\n", page_addr, column);
 266
 267
 268                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 269                 set_addr(mtd, 0, page_addr, 0);
 270
 271                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 272                 ctrl->index += column;
 273
 274                 fsl_elbc_do_read(chip, 0);
 275                 fsl_elbc_run_command(mtd);
 276                 return;
 277
 278         /* READOOB reads only the OOB because no ECC is performed. */
 279         case NAND_CMD_READOOB:
 280                 dev_vdbg(ctrl->dev,
 281                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 282                          " 0x%x, column: 0x%x.\n", page_addr, column);
 283
 284                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 285                 set_addr(mtd, column, page_addr, 1);
 286
 287                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 288
 289                 fsl_elbc_do_read(chip, 1);
 290                 fsl_elbc_run_command(mtd);
 291                 return;
 292
 293         /* READID must read all 5 possible bytes while CEB is active */
 294         case NAND_CMD_READID:
 295                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 296
 297                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 298                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 299                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 300                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 301                 /* 5 bytes for manuf, device and exts */
 302                 out_be32(&lbc->fbcr, 5);
 303                 ctrl->read_bytes = 5;
 304                 ctrl->use_mdr = 1;
 305                 ctrl->mdr = 0;
 306
 307                 set_addr(mtd, 0, 0, 0);
 308                 fsl_elbc_run_command(mtd);
 309                 return;
 310
 311         /* ERASE1 stores the block and page address */
 312         case NAND_CMD_ERASE1:
 313                 dev_vdbg(ctrl->dev,
 314                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 315                          "page_addr: 0x%x.\n", page_addr);
 316                 set_addr(mtd, 0, page_addr, 0);
 317                 return;
 318
 319         /* ERASE2 uses the block and page address from ERASE1 */
 320         case NAND_CMD_ERASE2:
 321                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 322
 323                 out_be32(&lbc->fir,
 324                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 325                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 326                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 327
 328                 out_be32(&lbc->fcr,
 329                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 330                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 331
 332                 out_be32(&lbc->fbcr, 0);
 333                 ctrl->read_bytes = 0;
 334
 335                 fsl_elbc_run_command(mtd);
 336                 return;
 337
 338         /* SEQIN sets up the addr buffer and all registers except the length */
 339         case NAND_CMD_SEQIN: {
 340                 __be32 fcr;
 341                 dev_vdbg(ctrl->dev,
 342                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 343                          "page_addr: 0x%x, column: 0x%x.\n",
 344                          page_addr, column);
 345
 346                 ctrl->column = column;
 347                 ctrl->oob = 0;
 348
 349                 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 350                       (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 351
 352                 if (priv->page_size) {
 353                         out_be32(&lbc->fir,
 354                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 355                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 356                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 357                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 358                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 359
 360                         fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 361                 } else {
 362                         out_be32(&lbc->fir,
 363                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 364                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 365                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 366                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 367                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 368                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 369
 370                         if (column >= mtd->writesize) {
 371                                 /* OOB area --> READOOB */
 372                                 column -= mtd->writesize;
 373                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 374                                 ctrl->oob = 1;
 375                         } else if (column < 256) {
 376                                 /* First 256 bytes --> READ0 */
 377                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 378                         } else {
 379                                 /* Second 256 bytes --> READ1 */
 380                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 381                         }
 382                 }
 383
 384                 out_be32(&lbc->fcr, fcr);
 385                 set_addr(mtd, column, page_addr, ctrl->oob);
 386                 return;
 387         }
 388
 389         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 390         case NAND_CMD_PAGEPROG: {
 391                 int full_page;
 392                 dev_vdbg(ctrl->dev,
 393                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 394                          "writing %d bytes.\n", ctrl->index);
 395
 396                 /* if the write did not start at 0 or is not a full page
 397                  * then set the exact length, otherwise use a full page
 398                  * write so the HW generates the ECC.
 399                  */
 400                 if (ctrl->oob || ctrl->column != 0 ||
 401                     ctrl->index != mtd->writesize + mtd->oobsize) {
 402                         out_be32(&lbc->fbcr, ctrl->index);
 403                         full_page = 0;
 404                 } else {
 405                         out_be32(&lbc->fbcr, 0);
 406                         full_page = 1;
 407                 }
 408
 409                 fsl_elbc_run_command(mtd);
 410
 411                 /* Read back the page in order to fill in the ECC for the
 412                  * caller.  Is this really needed?
 413                  */
 414                 if (full_page && ctrl->oob_poi) {
 415                         out_be32(&lbc->fbcr, 3);
 416                         set_addr(mtd, 6, page_addr, 1);
 417
 418                         ctrl->read_bytes = mtd->writesize + 9;
 419
 420                         fsl_elbc_do_read(chip, 1);
 421                         fsl_elbc_run_command(mtd);
 422
 423                         memcpy_fromio(ctrl->oob_poi + 6,
 424                                       &ctrl->addr[ctrl->index], 3);
 425                         ctrl->index += 3;
 426                 }
 427
 428                 ctrl->oob_poi = NULL;
 429                 return;
 430         }
 431
 432         /* CMD_STATUS must read the status byte while CEB is active */
 433         /* Note - it does not wait for the ready line */
 434         case NAND_CMD_STATUS:
 435                 out_be32(&lbc->fir,
 436                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 437                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 438                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 439                 out_be32(&lbc->fbcr, 1);
 440                 set_addr(mtd, 0, 0, 0);
 441                 ctrl->read_bytes = 1;
 442
 443                 fsl_elbc_run_command(mtd);
 444
 445                 /* The chip always seems to report that it is
 446                  * write-protected, even when it is not.
 447                  */
 448                 setbits8(ctrl->addr, NAND_STATUS_WP);
 449                 return;
 450
 451         /* RESET without waiting for the ready line */
 452         case NAND_CMD_RESET:
 453                 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 454                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 455                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 456                 fsl_elbc_run_command(mtd);
 457                 return;
 458
 459         default:
 460                 dev_err(ctrl->dev,
 461                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 462                         command);
 463         }
 464 }
 465
 466 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 467 {
 468         /* The hardware does not seem to support multiple
 469          * chips per bank.
 470          */
 471 }
 472
 473 /*
 474  * Write buf to the FCM Controller Data Buffer
 475  */
 476 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 477 {
 478         struct nand_chip *chip = mtd->priv;
 479         struct fsl_elbc_mtd *priv = chip->priv;
 480         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 481         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 482
 483         if (len < 0) {
 484                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 485                 ctrl->status = 0;
 486                 return;
 487         }
 488
 489         if ((unsigned int)len > bufsize - ctrl->index) {
 490                 dev_err(ctrl->dev,
 491                         "write_buf beyond end of buffer "
 492                         "(%d requested, %u available)\n",
 493                         len, bufsize - ctrl->index);
 494                 len = bufsize - ctrl->index;
 495         }
 496
 497         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 498         ctrl->index += len;
 499 }
 500
 501 /*
 502  * read a byte from either the FCM hardware buffer if it has any data left
 503  * otherwise issue a command to read a single byte.
 504  */
 505 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 506 {
 507         struct nand_chip *chip = mtd->priv;
 508         struct fsl_elbc_mtd *priv = chip->priv;
 509         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 510
 511         /* If there are still bytes in the FCM, then use the next byte. */
 512         if (ctrl->index < ctrl->read_bytes)
 513                 return in_8(&ctrl->addr[ctrl->index++]);
 514
 515         dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
 516         return ERR_BYTE;
 517 }
 518
 519 /*
 520  * Read from the FCM Controller Data Buffer
 521  */
 522 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 523 {
 524         struct nand_chip *chip = mtd->priv;
 525         struct fsl_elbc_mtd *priv = chip->priv;
 526         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 527         int avail;
 528
 529         if (len < 0)
 530                 return;
 531
 532         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 533         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 534         ctrl->index += avail;
 535
 536         if (len > avail)
 537                 dev_err(ctrl->dev,
 538                         "read_buf beyond end of buffer "
 539                         "(%d requested, %d available)\n",
 540                         len, avail);
 541 }
 542
 543 /*
 544  * Verify buffer against the FCM Controller Data Buffer
 545  */
 546 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 547 {
 548         struct nand_chip *chip = mtd->priv;
 549         struct fsl_elbc_mtd *priv = chip->priv;
 550         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 551         int i;
 552
 553         if (len < 0) {
 554                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 555                 return -EINVAL;
 556         }
 557
 558         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 559                 dev_err(ctrl->dev,
 560                         "verify_buf beyond end of buffer "
 561                         "(%d requested, %u available)\n",
 562                         len, ctrl->read_bytes - ctrl->index);
 563
 564                 ctrl->index = ctrl->read_bytes;
 565                 return -EINVAL;
 566         }
 567
 568         for (i = 0; i < len; i++)
 569                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 570                         break;
 571
 572         ctrl->index += len;
 573         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 574 }
 575
 576 /* This function is called after Program and Erase Operations to
 577  * check for success or failure.
 578  */
 579 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 580 {
 581         struct fsl_elbc_mtd *priv = chip->priv;
 582         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 583         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 584
 585         if (ctrl->status != LTESR_CC)
 586                 return NAND_STATUS_FAIL;
 587
 588         /* Use READ_STATUS command, but wait for the device to be ready */
 589         ctrl->use_mdr = 0;
 590         out_be32(&lbc->fir,
 591                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 592                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 593         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 594         out_be32(&lbc->fbcr, 1);
 595         set_addr(mtd, 0, 0, 0);
 596         ctrl->read_bytes = 1;
 597
 598         fsl_elbc_run_command(mtd);
 599
 600         if (ctrl->status != LTESR_CC)
 601                 return NAND_STATUS_FAIL;
 602
 603         /* The chip always seems to report that it is
 604          * write-protected, even when it is not.
 605          */
 606         setbits8(ctrl->addr, NAND_STATUS_WP);
 607         return fsl_elbc_read_byte(mtd);
 608 }
 609
 610 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 611 {
 612         struct nand_chip *chip = mtd->priv;
 613         struct fsl_elbc_mtd *priv = chip->priv;
 614         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 615         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 616         unsigned int al;
 617
 618         /* calculate FMR Address Length field */
 619         al = 0;
 620         if (chip->pagemask & 0xffff0000)
 621                 al++;
 622         if (chip->pagemask & 0xff000000)
 623                 al++;
 624
 625         /* add to ECCM mode set in fsl_elbc_init */
 626         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 627                      (al << FMR_AL_SHIFT);
 628
 629         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
 630                 chip->numchips);
 631         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
 632                 chip->chipsize);
 633         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 634                 chip->pagemask);
 635         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 636                 chip->chip_delay);
 637         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 638                 chip->badblockpos);
 639         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 640                 chip->chip_shift);
 641         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 642                 chip->page_shift);
 643         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 644                 chip->phys_erase_shift);
 645         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 646                 chip->ecclayout);
 647         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 648                 chip->ecc.mode);
 649         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 650                 chip->ecc.steps);
 651         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 652                 chip->ecc.bytes);
 653         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 654                 chip->ecc.total);
 655         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 656                 chip->ecc.layout);
 657         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 658         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
 659         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 660                 mtd->erasesize);
 661         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 662                 mtd->writesize);
 663         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 664                 mtd->oobsize);
 665
 666         /* adjust Option Register and ECC to match Flash page size */
 667         if (mtd->writesize == 512) {
 668                 priv->page_size = 0;
 669                 clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);
 670         } else if (mtd->writesize == 2048) {
 671                 priv->page_size = 1;
 672                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 673                 /* adjust ecc setup if needed */
 674                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 675                     BR_DECC_CHK_GEN) {
 676                         chip->ecc.size = 512;
 677                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 678                                            &fsl_elbc_oob_lp_eccm1 :
 679                                            &fsl_elbc_oob_lp_eccm0;
 680                         mtd->ecclayout = chip->ecc.layout;
 681                         mtd->oobavail = chip->ecc.layout->oobavail;
 682                 }
 683         } else {
 684                 dev_err(ctrl->dev,
 685                         "fsl_elbc_init: page size %d is not supported\n",
 686                         mtd->writesize);
 687                 return -1;
 688         }
 689
 690         /* The default u-boot configuration on MPC8313ERDB causes errors;
 691          * more delay is needed.  This should be safe for other boards
 692          * as well.
 693          */
 694         setbits32(&lbc->bank[priv->bank].or, 0x70);
 695         return 0;
 696 }
 697
 698 static int fsl_elbc_read_page(struct mtd_info *mtd,
 699                               struct nand_chip *chip,
 700                               uint8_t *buf)
 701 {
 702         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 703         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 704
 705         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 706                 mtd->ecc_stats.failed++;
 707
 708         return 0;
 709 }
 710
 711 /* ECC will be calculated automatically, and errors will be detected in
 712  * waitfunc.
 713  */
 714 static void fsl_elbc_write_page(struct mtd_info *mtd,
 715                                 struct nand_chip *chip,
 716                                 const uint8_t *buf)
 717 {
 718         struct fsl_elbc_mtd *priv = chip->priv;
 719         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 720
 721         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 722         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 723
 724         ctrl->oob_poi = chip->oob_poi;
 725 }
 726
 727 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 728 {
 729         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 730         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 731         struct nand_chip *chip = &priv->chip;
 732
 733         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 734
 735         /* Fill in fsl_elbc_mtd structure */
 736         priv->mtd.priv = chip;
 737         priv->mtd.owner = THIS_MODULE;
 738         priv->fmr = 0; /* rest filled in later */
 739
 740         /* fill in nand_chip structure */
 741         /* set up function call table */
 742         chip->read_byte = fsl_elbc_read_byte;
 743         chip->write_buf = fsl_elbc_write_buf;
 744         chip->read_buf = fsl_elbc_read_buf;
 745         chip->verify_buf = fsl_elbc_verify_buf;
 746         chip->select_chip = fsl_elbc_select_chip;
 747         chip->cmdfunc = fsl_elbc_cmdfunc;
 748         chip->waitfunc = fsl_elbc_wait;
 749
 750         /* set up nand options */
 751         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 752
 753         chip->controller = &ctrl->controller;
 754         chip->priv = priv;
 755
 756         chip->ecc.read_page = fsl_elbc_read_page;
 757         chip->ecc.write_page = fsl_elbc_write_page;
 758
 759         /* If CS Base Register selects full hardware ECC then use it */
 760         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 761             BR_DECC_CHK_GEN) {
 762                 chip->ecc.mode = NAND_ECC_HW;
 763                 /* put in small page settings and adjust later if needed */
 764                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 765                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 766                 chip->ecc.size = 512;
 767                 chip->ecc.bytes = 3;
 768         } else {
 769                 /* otherwise fall back to default software ECC */
 770                 chip->ecc.mode = NAND_ECC_SOFT;
 771         }
 772
 773         return 0;
 774 }
 775
 776 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 777 {
 778         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 779
 780         nand_release(&priv->mtd);
 781
 782         if (priv->vbase)
 783                 iounmap(priv->vbase);
 784
 785         ctrl->chips[priv->bank] = NULL;
 786         kfree(priv);
 787
 788         return 0;
 789 }
 790
 791 static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
 792                                struct device_node *node)
 793 {
 794         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 795         struct fsl_elbc_mtd *priv;
 796         struct resource res;
 797 #ifdef CONFIG_MTD_PARTITIONS
 798         static const char *part_probe_types[]
 799                 = { "cmdlinepart", "RedBoot", NULL };
 800         struct mtd_partition *parts;
 801 #endif
 802         int ret;
 803         int bank;
 804
 805         /* get, allocate and map the memory resource */
 806         ret = of_address_to_resource(node, 0, &res);
 807         if (ret) {
 808                 dev_err(ctrl->dev, "failed to get resource\n");
 809                 return ret;
 810         }
 811
 812         /* find which chip select it is connected to */
 813         for (bank = 0; bank < MAX_BANKS; bank++)
 814                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 815                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 816                     (in_be32(&lbc->bank[bank].br) &
 817                      in_be32(&lbc->bank[bank].or) & BR_BA)
 818                      == res.start)
 819                         break;
 820
 821         if (bank >= MAX_BANKS) {
 822                 dev_err(ctrl->dev, "address did not match any chip selects\n");
 823                 return -ENODEV;
 824         }
 825
 826         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 827         if (!priv)
 828                 return -ENOMEM;
 829
 830         ctrl->chips[bank] = priv;
 831         priv->bank = bank;
 832         priv->ctrl = ctrl;
 833         priv->dev = ctrl->dev;
 834
 835         priv->vbase = ioremap(res.start, res.end - res.start + 1);
 836         if (!priv->vbase) {
 837                 dev_err(ctrl->dev, "failed to map chip region\n");
 838                 ret = -ENOMEM;
 839                 goto err;
 840         }
 841
 842         ret = fsl_elbc_chip_init(priv);
 843         if (ret)
 844                 goto err;
 845
 846         ret = nand_scan_ident(&priv->mtd, 1);
 847         if (ret)
 848                 goto err;
 849
 850         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 851         if (ret)
 852                 goto err;
 853
 854         ret = nand_scan_tail(&priv->mtd);
 855         if (ret)
 856                 goto err;
 857
 858 #ifdef CONFIG_MTD_PARTITIONS
 859         /* First look for RedBoot table or partitions on the command
 860          * line, these take precedence over device tree information */
 861         ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
 862         if (ret < 0)
 863                 goto err;
 864
 865 #ifdef CONFIG_MTD_OF_PARTS
 866         if (ret == 0) {
 867                 ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
 868                                               node, &parts);
 869                 if (ret < 0)
 870                         goto err;
 871         }
 872 #endif
 873
 874         if (ret > 0)
 875                 add_mtd_partitions(&priv->mtd, parts, ret);
 876         else
 877 #endif
 878                 add_mtd_device(&priv->mtd);
 879
 880         printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
 881                res.start, priv->bank);
 882         return 0;
 883
 884 err:
 885         fsl_elbc_chip_remove(priv);
 886         return ret;
 887 }
 888
 889 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 890 {
 891         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 892
 893         /* clear event registers */
 894         setbits32(&lbc->ltesr, LTESR_NAND_MASK);
 895         out_be32(&lbc->lteatr, 0);
 896
 897         /* Enable interrupts for any detected events */
 898         out_be32(&lbc->lteir, LTESR_NAND_MASK);
 899
 900         ctrl->read_bytes = 0;
 901         ctrl->index = 0;
 902         ctrl->addr = NULL;
 903
 904         return 0;
 905 }
 906
 907 static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
 908 {
 909         struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
 910         int i;
 911
 912         for (i = 0; i < MAX_BANKS; i++)
 913                 if (ctrl->chips[i])
 914                         fsl_elbc_chip_remove(ctrl->chips[i]);
 915
 916         if (ctrl->irq)
 917                 free_irq(ctrl->irq, ctrl);
 918
 919         if (ctrl->regs)
 920                 iounmap(ctrl->regs);
 921
 922         dev_set_drvdata(&ofdev->dev, NULL);
 923         kfree(ctrl);
 924         return 0;
 925 }
 926
 927 /* NOTE: This interrupt is also used to report other localbus events,
 928  * such as transaction errors on other chipselects.  If we want to
 929  * capture those, we'll need to move the IRQ code into a shared
 930  * LBC driver.
 931  */
 932
 933 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
 934 {
 935         struct fsl_elbc_ctrl *ctrl = data;
 936         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 937         __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
 938
 939         if (status) {
 940                 out_be32(&lbc->ltesr, status);
 941                 out_be32(&lbc->lteatr, 0);
 942
 943                 ctrl->irq_status = status;
 944                 smp_wmb();
 945                 wake_up(&ctrl->irq_wait);
 946
 947                 return IRQ_HANDLED;
 948         }
 949
 950         return IRQ_NONE;
 951 }
 952
 953 /* fsl_elbc_ctrl_probe
 954  *
 955  * called by device layer when it finds a device matching
 956  * one our driver can handled. This code allocates all of
 957  * the resources needed for the controller only.  The
 958  * resources for the NAND banks themselves are allocated
 959  * in the chip probe function.
 960 */
 961
 962 static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
 963                                          const struct of_device_id *match)
 964 {
 965         struct device_node *child;
 966         struct fsl_elbc_ctrl *ctrl;
 967         int ret;
 968
 969         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 970         if (!ctrl)
 971                 return -ENOMEM;
 972
 973         dev_set_drvdata(&ofdev->dev, ctrl);
 974
 975         spin_lock_init(&ctrl->controller.lock);
 976         init_waitqueue_head(&ctrl->controller.wq);
 977         init_waitqueue_head(&ctrl->irq_wait);
 978
 979         ctrl->regs = of_iomap(ofdev->node, 0);
 980         if (!ctrl->regs) {
 981                 dev_err(&ofdev->dev, "failed to get memory region\n");
 982                 ret = -ENODEV;
 983                 goto err;
 984         }
 985
 986         ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
 987         if (ctrl->irq == NO_IRQ) {
 988                 dev_err(&ofdev->dev, "failed to get irq resource\n");
 989                 ret = -ENODEV;
 990                 goto err;
 991         }
 992
 993         ctrl->dev = &ofdev->dev;
 994
 995         ret = fsl_elbc_ctrl_init(ctrl);
 996         if (ret < 0)
 997                 goto err;
 998
 999         ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1000         if (ret != 0) {
1001                 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1002                         ctrl->irq);
1003                 ret = ctrl->irq;
1004                 goto err;
1005         }
1006
1007         for_each_child_of_node(ofdev->node, child)
1008                 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1009                         fsl_elbc_chip_probe(ctrl, child);
1010
1011         return 0;
1012
1013 err:
1014         fsl_elbc_ctrl_remove(ofdev);
1015         return ret;
1016 }
1017
1018 static const struct of_device_id fsl_elbc_match[] = {
1019         {
1020                 .compatible = "fsl,elbc",
1021         },
1022         {}
1023 };
1024
1025 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1026         .driver = {
1027                 .name   = "fsl-elbc",
1028         },
1029         .match_table = fsl_elbc_match,
1030         .probe = fsl_elbc_ctrl_probe,
1031         .remove = __devexit_p(fsl_elbc_ctrl_remove),
1032 };
1033
1034 static int __init fsl_elbc_init(void)
1035 {
1036         return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1037 }
1038
1039 static void __exit fsl_elbc_exit(void)
1040 {
1041         of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1042 }
1043
1044 module_init(fsl_elbc_init);
1045 module_exit(fsl_elbc_exit);
1046
1047 MODULE_LICENSE("GPL");
1048 MODULE_AUTHOR("Freescale");
1049 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");