drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30
  31 #include "sdhci.h"
  32
  33 #define DRIVER_NAME "sdhci"
  34
  35 #define DBG(f, x...) \
  36         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  37
  38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  39         defined(CONFIG_MMC_SDHCI_MODULE))
  40 #define SDHCI_USE_LEDS_CLASS
  41 #endif
  42
  43 #define MAX_TUNING_LOOP 40
  44
  45 static unsigned int debug_quirks = 0;
  46 static unsigned int debug_quirks2;
  47
  48 static void sdhci_finish_data(struct sdhci_host *);
  49
  50 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  51 static void sdhci_finish_command(struct sdhci_host *);
  52 static int sdhci_execute_tuning(struct mmc_host *mmc);
  53 static void sdhci_tuning_timer(unsigned long data);
  54
  55 #ifdef CONFIG_PM_RUNTIME
  56 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  57 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  58 #else
  59 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  60 {
  61         return 0;
  62 }
  63 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 #endif
  68
  69 static void sdhci_dumpregs(struct sdhci_host *host)
  70 {
  71         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  72                 mmc_hostname(host->mmc));
  73
  74         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  75                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  76                 sdhci_readw(host, SDHCI_HOST_VERSION));
  77         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  78                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  79                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  80         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  81                 sdhci_readl(host, SDHCI_ARGUMENT),
  82                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  83         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  84                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  85                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  86         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  87                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  88                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  89         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  90                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  91                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  92         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  93                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  94                 sdhci_readl(host, SDHCI_INT_STATUS));
  95         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_INT_ENABLE),
  97                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  98         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  99                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 100                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 101         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 102                 sdhci_readl(host, SDHCI_CAPABILITIES),
 103                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 104         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 105                 sdhci_readw(host, SDHCI_COMMAND),
 106                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 107         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 108                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 109
 110         if (host->flags & SDHCI_USE_ADMA)
 111                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 112                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 113                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 114
 115         pr_debug(DRIVER_NAME ": ===========================================\n");
 116 }
 117
 118 /*****************************************************************************\
 119  *                                                                           *
 120  * Low level functions                                                       *
 121  *                                                                           *
 122 \*****************************************************************************/
 123
 124 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 125 {
 126         u32 ier;
 127
 128         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 129         ier &= ~clear;
 130         ier |= set;
 131         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 132         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 133 }
 134
 135 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 136 {
 137         sdhci_clear_set_irqs(host, 0, irqs);
 138 }
 139
 140 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 141 {
 142         sdhci_clear_set_irqs(host, irqs, 0);
 143 }
 144
 145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 146 {
 147         u32 present, irqs;
 148
 149         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 150                 return;
 151
 152         if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
 153                 return;
 154
 155         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 156                               SDHCI_CARD_PRESENT;
 157         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 158
 159         if (enable)
 160                 sdhci_unmask_irqs(host, irqs);
 161         else
 162                 sdhci_mask_irqs(host, irqs);
 163 }
 164
 165 static void sdhci_enable_card_detection(struct sdhci_host *host)
 166 {
 167         sdhci_set_card_detection(host, true);
 168 }
 169
 170 static void sdhci_disable_card_detection(struct sdhci_host *host)
 171 {
 172         sdhci_set_card_detection(host, false);
 173 }
 174
 175 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 176 {
 177         unsigned long timeout;
 178         u32 uninitialized_var(ier);
 179
 180         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 181                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 182                         SDHCI_CARD_PRESENT))
 183                         return;
 184         }
 185
 186         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 187                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 188
 189         if (host->ops->platform_reset_enter)
 190                 host->ops->platform_reset_enter(host, mask);
 191
 192         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 193
 194         if (mask & SDHCI_RESET_ALL)
 195                 host->clock = 0;
 196
 197         /* Wait max 100 ms */
 198         timeout = 100;
 199
 200         /* hw clears the bit when it's done */
 201         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 202                 if (timeout == 0) {
 203                         pr_err("%s: Reset 0x%x never completed.\n",
 204                                 mmc_hostname(host->mmc), (int)mask);
 205                         sdhci_dumpregs(host);
 206                         return;
 207                 }
 208                 timeout--;
 209                 mdelay(1);
 210         }
 211
 212         if (host->ops->platform_reset_exit)
 213                 host->ops->platform_reset_exit(host, mask);
 214
 215         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 216                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 217 }
 218
 219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 220
 221 static void sdhci_init(struct sdhci_host *host, int soft)
 222 {
 223         if (soft)
 224                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 225         else
 226                 sdhci_reset(host, SDHCI_RESET_ALL);
 227
 228         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 229                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 230                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 231                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 232                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 233
 234         if (soft) {
 235                 /* force clock reconfiguration */
 236                 host->clock = 0;
 237                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 238         }
 239 }
 240
 241 static void sdhci_reinit(struct sdhci_host *host)
 242 {
 243         sdhci_init(host, 0);
 244         sdhci_enable_card_detection(host);
 245 }
 246
 247 static void sdhci_activate_led(struct sdhci_host *host)
 248 {
 249         u8 ctrl;
 250
 251         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 252         ctrl |= SDHCI_CTRL_LED;
 253         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 254 }
 255
 256 static void sdhci_deactivate_led(struct sdhci_host *host)
 257 {
 258         u8 ctrl;
 259
 260         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 261         ctrl &= ~SDHCI_CTRL_LED;
 262         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 263 }
 264
 265 #ifdef SDHCI_USE_LEDS_CLASS
 266 static void sdhci_led_control(struct led_classdev *led,
 267         enum led_brightness brightness)
 268 {
 269         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 270         unsigned long flags;
 271
 272         spin_lock_irqsave(&host->lock, flags);
 273
 274         if (host->runtime_suspended)
 275                 goto out;
 276
 277         if (brightness == LED_OFF)
 278                 sdhci_deactivate_led(host);
 279         else
 280                 sdhci_activate_led(host);
 281 out:
 282         spin_unlock_irqrestore(&host->lock, flags);
 283 }
 284 #endif
 285
 286 /*****************************************************************************\
 287  *                                                                           *
 288  * Core functions                                                            *
 289  *                                                                           *
 290 \*****************************************************************************/
 291
 292 static void sdhci_read_block_pio(struct sdhci_host *host)
 293 {
 294         unsigned long flags;
 295         size_t blksize, len, chunk;
 296         u32 uninitialized_var(scratch);
 297         u8 *buf;
 298
 299         DBG("PIO reading\n");
 300
 301         blksize = host->data->blksz;
 302         chunk = 0;
 303
 304         local_irq_save(flags);
 305
 306         while (blksize) {
 307                 if (!sg_miter_next(&host->sg_miter))
 308                         BUG();
 309
 310                 len = min(host->sg_miter.length, blksize);
 311
 312                 blksize -= len;
 313                 host->sg_miter.consumed = len;
 314
 315                 buf = host->sg_miter.addr;
 316
 317                 while (len) {
 318                         if (chunk == 0) {
 319                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 320                                 chunk = 4;
 321                         }
 322
 323                         *buf = scratch & 0xFF;
 324
 325                         buf++;
 326                         scratch >>= 8;
 327                         chunk--;
 328                         len--;
 329                 }
 330         }
 331
 332         sg_miter_stop(&host->sg_miter);
 333
 334         local_irq_restore(flags);
 335 }
 336
 337 static void sdhci_write_block_pio(struct sdhci_host *host)
 338 {
 339         unsigned long flags;
 340         size_t blksize, len, chunk;
 341         u32 scratch;
 342         u8 *buf;
 343
 344         DBG("PIO writing\n");
 345
 346         blksize = host->data->blksz;
 347         chunk = 0;
 348         scratch = 0;
 349
 350         local_irq_save(flags);
 351
 352         while (blksize) {
 353                 if (!sg_miter_next(&host->sg_miter))
 354                         BUG();
 355
 356                 len = min(host->sg_miter.length, blksize);
 357
 358                 blksize -= len;
 359                 host->sg_miter.consumed = len;
 360
 361                 buf = host->sg_miter.addr;
 362
 363                 while (len) {
 364                         scratch |= (u32)*buf << (chunk * 8);
 365
 366                         buf++;
 367                         chunk++;
 368                         len--;
 369
 370                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 371                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 372                                 chunk = 0;
 373                                 scratch = 0;
 374                         }
 375                 }
 376         }
 377
 378         sg_miter_stop(&host->sg_miter);
 379
 380         local_irq_restore(flags);
 381 }
 382
 383 static void sdhci_transfer_pio(struct sdhci_host *host)
 384 {
 385         u32 mask;
 386
 387         BUG_ON(!host->data);
 388
 389         if (host->blocks == 0)
 390                 return;
 391
 392         if (host->data->flags & MMC_DATA_READ)
 393                 mask = SDHCI_DATA_AVAILABLE;
 394         else
 395                 mask = SDHCI_SPACE_AVAILABLE;
 396
 397         /*
 398          * Some controllers (JMicron JMB38x) mess up the buffer bits
 399          * for transfers < 4 bytes. As long as it is just one block,
 400          * we can ignore the bits.
 401          */
 402         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 403                 (host->data->blocks == 1))
 404                 mask = ~0;
 405
 406         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 407                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 408                         udelay(100);
 409
 410                 if (host->data->flags & MMC_DATA_READ)
 411                         sdhci_read_block_pio(host);
 412                 else
 413                         sdhci_write_block_pio(host);
 414
 415                 host->blocks--;
 416                 if (host->blocks == 0)
 417                         break;
 418         }
 419
 420         DBG("PIO transfer complete.\n");
 421 }
 422
 423 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 424 {
 425         local_irq_save(*flags);
 426         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 427 }
 428
 429 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 430 {
 431         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 432         local_irq_restore(*flags);
 433 }
 434
 435 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 436 {
 437         __le32 *dataddr = (__le32 __force *)(desc + 4);
 438         __le16 *cmdlen = (__le16 __force *)desc;
 439
 440         /* SDHCI specification says ADMA descriptors should be 4 byte
 441          * aligned, so using 16 or 32bit operations should be safe. */
 442
 443         cmdlen[0] = cpu_to_le16(cmd);
 444         cmdlen[1] = cpu_to_le16(len);
 445
 446         dataddr[0] = cpu_to_le32(addr);
 447 }
 448
 449 static int sdhci_adma_table_pre(struct sdhci_host *host,
 450         struct mmc_data *data)
 451 {
 452         int direction;
 453
 454         u8 *desc;
 455         u8 *align;
 456         dma_addr_t addr;
 457         dma_addr_t align_addr;
 458         int len, offset;
 459
 460         struct scatterlist *sg;
 461         int i;
 462         char *buffer;
 463         unsigned long flags;
 464
 465         /*
 466          * The spec does not specify endianness of descriptor table.
 467          * We currently guess that it is LE.
 468          */
 469
 470         if (data->flags & MMC_DATA_READ)
 471                 direction = DMA_FROM_DEVICE;
 472         else
 473                 direction = DMA_TO_DEVICE;
 474
 475         /*
 476          * The ADMA descriptor table is mapped further down as we
 477          * need to fill it with data first.
 478          */
 479
 480         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 481                 host->align_buffer, 128 * 4, direction);
 482         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 483                 goto fail;
 484         BUG_ON(host->align_addr & 0x3);
 485
 486         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 487                 data->sg, data->sg_len, direction);
 488         if (host->sg_count == 0)
 489                 goto unmap_align;
 490
 491         desc = host->adma_desc;
 492         align = host->align_buffer;
 493
 494         align_addr = host->align_addr;
 495
 496         for_each_sg(data->sg, sg, host->sg_count, i) {
 497                 addr = sg_dma_address(sg);
 498                 len = sg_dma_len(sg);
 499
 500                 /*
 501                  * The SDHCI specification states that ADMA
 502                  * addresses must be 32-bit aligned. If they
 503                  * aren't, then we use a bounce buffer for
 504                  * the (up to three) bytes that screw up the
 505                  * alignment.
 506                  */
 507                 offset = (4 - (addr & 0x3)) & 0x3;
 508                 if (offset) {
 509                         if (data->flags & MMC_DATA_WRITE) {
 510                                 buffer = sdhci_kmap_atomic(sg, &flags);
 511                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 512                                 memcpy(align, buffer, offset);
 513                                 sdhci_kunmap_atomic(buffer, &flags);
 514                         }
 515
 516                         /* tran, valid */
 517                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 518
 519                         BUG_ON(offset > 65536);
 520
 521                         align += 4;
 522                         align_addr += 4;
 523
 524                         desc += 8;
 525
 526                         addr += offset;
 527                         len -= offset;
 528                 }
 529
 530                 BUG_ON(len > 65536);
 531
 532                 /* tran, valid */
 533                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 534                 desc += 8;
 535
 536                 /*
 537                  * If this triggers then we have a calculation bug
 538                  * somewhere. :/
 539                  */
 540                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 541         }
 542
 543         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 544                 /*
 545                 * Mark the last descriptor as the terminating descriptor
 546                 */
 547                 if (desc != host->adma_desc) {
 548                         desc -= 8;
 549                         desc[0] |= 0x2; /* end */
 550                 }
 551         } else {
 552                 /*
 553                 * Add a terminating entry.
 554                 */
 555
 556                 /* nop, end, valid */
 557                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 558         }
 559
 560         /*
 561          * Resync align buffer as we might have changed it.
 562          */
 563         if (data->flags & MMC_DATA_WRITE) {
 564                 dma_sync_single_for_device(mmc_dev(host->mmc),
 565                         host->align_addr, 128 * 4, direction);
 566         }
 567
 568         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 569                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 570         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 571                 goto unmap_entries;
 572         BUG_ON(host->adma_addr & 0x3);
 573
 574         return 0;
 575
 576 unmap_entries:
 577         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 578                 data->sg_len, direction);
 579 unmap_align:
 580         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 581                 128 * 4, direction);
 582 fail:
 583         return -EINVAL;
 584 }
 585
 586 static void sdhci_adma_table_post(struct sdhci_host *host,
 587         struct mmc_data *data)
 588 {
 589         int direction;
 590
 591         struct scatterlist *sg;
 592         int i, size;
 593         u8 *align;
 594         char *buffer;
 595         unsigned long flags;
 596
 597         if (data->flags & MMC_DATA_READ)
 598                 direction = DMA_FROM_DEVICE;
 599         else
 600                 direction = DMA_TO_DEVICE;
 601
 602         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 603                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 604
 605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 606                 128 * 4, direction);
 607
 608         if (data->flags & MMC_DATA_READ) {
 609                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 610                         data->sg_len, direction);
 611
 612                 align = host->align_buffer;
 613
 614                 for_each_sg(data->sg, sg, host->sg_count, i) {
 615                         if (sg_dma_address(sg) & 0x3) {
 616                                 size = 4 - (sg_dma_address(sg) & 0x3);
 617
 618                                 buffer = sdhci_kmap_atomic(sg, &flags);
 619                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 620                                 memcpy(buffer, align, size);
 621                                 sdhci_kunmap_atomic(buffer, &flags);
 622
 623                                 align += 4;
 624                         }
 625                 }
 626         }
 627
 628         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 629                 data->sg_len, direction);
 630 }
 631
 632 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 633 {
 634         u8 count;
 635         struct mmc_data *data = cmd->data;
 636         unsigned target_timeout, current_timeout;
 637
 638         /*
 639          * If the host controller provides us with an incorrect timeout
 640          * value, just skip the check and use 0xE.  The hardware may take
 641          * longer to time out, but that's much better than having a too-short
 642          * timeout value.
 643          */
 644         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 645                 return 0xE;
 646
 647         /* Unspecified timeout, assume max */
 648         if (!data && !cmd->cmd_timeout_ms)
 649                 return 0xE;
 650
 651         /* timeout in us */
 652         if (!data)
 653                 target_timeout = cmd->cmd_timeout_ms * 1000;
 654         else {
 655                 target_timeout = data->timeout_ns / 1000;
 656                 if (host->clock)
 657                         target_timeout += data->timeout_clks / host->clock;
 658         }
 659
 660         /*
 661          * Figure out needed cycles.
 662          * We do this in steps in order to fit inside a 32 bit int.
 663          * The first step is the minimum timeout, which will have a
 664          * minimum resolution of 6 bits:
 665          * (1) 2^13*1000 > 2^22,
 666          * (2) host->timeout_clk < 2^16
 667          *     =>
 668          *     (1) / (2) > 2^6
 669          */
 670         count = 0;
 671         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 672         while (current_timeout < target_timeout) {
 673                 count++;
 674                 current_timeout <<= 1;
 675                 if (count >= 0xF)
 676                         break;
 677         }
 678
 679         if (count >= 0xF) {
 680                 pr_warning("%s: Too large timeout requested for CMD%d!\n",
 681                        mmc_hostname(host->mmc), cmd->opcode);
 682                 count = 0xE;
 683         }
 684
 685         return count;
 686 }
 687
 688 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 689 {
 690         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 691         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 692
 693         if (host->flags & SDHCI_REQ_USE_DMA)
 694                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 695         else
 696                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 697 }
 698
 699 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 700 {
 701         u8 count;
 702         u8 ctrl;
 703         struct mmc_data *data = cmd->data;
 704         int ret;
 705
 706         WARN_ON(host->data);
 707
 708         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 709                 count = sdhci_calc_timeout(host, cmd);
 710                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 711         }
 712
 713         if (!data)
 714                 return;
 715
 716         /* Sanity checks */
 717         BUG_ON(data->blksz * data->blocks > 524288);
 718         BUG_ON(data->blksz > host->mmc->max_blk_size);
 719         BUG_ON(data->blocks > 65535);
 720
 721         host->data = data;
 722         host->data_early = 0;
 723         host->data->bytes_xfered = 0;
 724
 725         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 726                 host->flags |= SDHCI_REQ_USE_DMA;
 727
 728         /*
 729          * FIXME: This doesn't account for merging when mapping the
 730          * scatterlist.
 731          */
 732         if (host->flags & SDHCI_REQ_USE_DMA) {
 733                 int broken, i;
 734                 struct scatterlist *sg;
 735
 736                 broken = 0;
 737                 if (host->flags & SDHCI_USE_ADMA) {
 738                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 739                                 broken = 1;
 740                 } else {
 741                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 742                                 broken = 1;
 743                 }
 744
 745                 if (unlikely(broken)) {
 746                         for_each_sg(data->sg, sg, data->sg_len, i) {
 747                                 if (sg->length & 0x3) {
 748                                         DBG("Reverting to PIO because of "
 749                                                 "transfer size (%d)\n",
 750                                                 sg->length);
 751                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 752                                         break;
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         /*
 759          * The assumption here being that alignment is the same after
 760          * translation to device address space.
 761          */
 762         if (host->flags & SDHCI_REQ_USE_DMA) {
 763                 int broken, i;
 764                 struct scatterlist *sg;
 765
 766                 broken = 0;
 767                 if (host->flags & SDHCI_USE_ADMA) {
 768                         /*
 769                          * As we use 3 byte chunks to work around
 770                          * alignment problems, we need to check this
 771                          * quirk.
 772                          */
 773                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 774                                 broken = 1;
 775                 } else {
 776                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 777                                 broken = 1;
 778                 }
 779
 780                 if (unlikely(broken)) {
 781                         for_each_sg(data->sg, sg, data->sg_len, i) {
 782                                 if (sg->offset & 0x3) {
 783                                         DBG("Reverting to PIO because of "
 784                                                 "bad alignment\n");
 785                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 786                                         break;
 787                                 }
 788                         }
 789                 }
 790         }
 791
 792         if (host->flags & SDHCI_REQ_USE_DMA) {
 793                 if (host->flags & SDHCI_USE_ADMA) {
 794                         ret = sdhci_adma_table_pre(host, data);
 795                         if (ret) {
 796                                 /*
 797                                  * This only happens when someone fed
 798                                  * us an invalid request.
 799                                  */
 800                                 WARN_ON(1);
 801                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 802                         } else {
 803                                 sdhci_writel(host, host->adma_addr,
 804                                         SDHCI_ADMA_ADDRESS);
 805                         }
 806                 } else {
 807                         int sg_cnt;
 808
 809                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 810                                         data->sg, data->sg_len,
 811                                         (data->flags & MMC_DATA_READ) ?
 812                                                 DMA_FROM_DEVICE :
 813                                                 DMA_TO_DEVICE);
 814                         if (sg_cnt == 0) {
 815                                 /*
 816                                  * This only happens when someone fed
 817                                  * us an invalid request.
 818                                  */
 819                                 WARN_ON(1);
 820                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 821                         } else {
 822                                 WARN_ON(sg_cnt != 1);
 823                                 sdhci_writel(host, sg_dma_address(data->sg),
 824                                         SDHCI_DMA_ADDRESS);
 825                         }
 826                 }
 827         }
 828
 829         /*
 830          * Always adjust the DMA selection as some controllers
 831          * (e.g. JMicron) can't do PIO properly when the selection
 832          * is ADMA.
 833          */
 834         if (host->version >= SDHCI_SPEC_200) {
 835                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 836                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 837                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 838                         (host->flags & SDHCI_USE_ADMA))
 839                         ctrl |= SDHCI_CTRL_ADMA32;
 840                 else
 841                         ctrl |= SDHCI_CTRL_SDMA;
 842                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 843         }
 844
 845         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 846                 int flags;
 847
 848                 flags = SG_MITER_ATOMIC;
 849                 if (host->data->flags & MMC_DATA_READ)
 850                         flags |= SG_MITER_TO_SG;
 851                 else
 852                         flags |= SG_MITER_FROM_SG;
 853                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 854                 host->blocks = data->blocks;
 855         }
 856
 857         sdhci_set_transfer_irqs(host);
 858
 859         /* Set the DMA boundary value and block size */
 860         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 861                 data->blksz), SDHCI_BLOCK_SIZE);
 862         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 863 }
 864
 865 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 866         struct mmc_command *cmd)
 867 {
 868         u16 mode;
 869         struct mmc_data *data = cmd->data;
 870
 871         if (data == NULL)
 872                 return;
 873
 874         WARN_ON(!host->data);
 875
 876         mode = SDHCI_TRNS_BLK_CNT_EN;
 877         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 878                 mode |= SDHCI_TRNS_MULTI;
 879                 /*
 880                  * If we are sending CMD23, CMD12 never gets sent
 881                  * on successful completion (so no Auto-CMD12).
 882                  */
 883                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 884                         mode |= SDHCI_TRNS_AUTO_CMD12;
 885                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 886                         mode |= SDHCI_TRNS_AUTO_CMD23;
 887                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 888                 }
 889         }
 890
 891         if (data->flags & MMC_DATA_READ)
 892                 mode |= SDHCI_TRNS_READ;
 893         if (host->flags & SDHCI_REQ_USE_DMA)
 894                 mode |= SDHCI_TRNS_DMA;
 895
 896         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 897 }
 898
 899 static void sdhci_finish_data(struct sdhci_host *host)
 900 {
 901         struct mmc_data *data;
 902
 903         BUG_ON(!host->data);
 904
 905         data = host->data;
 906         host->data = NULL;
 907
 908         if (host->flags & SDHCI_REQ_USE_DMA) {
 909                 if (host->flags & SDHCI_USE_ADMA)
 910                         sdhci_adma_table_post(host, data);
 911                 else {
 912                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 913                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 914                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 915                 }
 916         }
 917
 918         /*
 919          * The specification states that the block count register must
 920          * be updated, but it does not specify at what point in the
 921          * data flow. That makes the register entirely useless to read
 922          * back so we have to assume that nothing made it to the card
 923          * in the event of an error.
 924          */
 925         if (data->error)
 926                 data->bytes_xfered = 0;
 927         else
 928                 data->bytes_xfered = data->blksz * data->blocks;
 929
 930         /*
 931          * Need to send CMD12 if -
 932          * a) open-ended multiblock transfer (no CMD23)
 933          * b) error in multiblock transfer
 934          */
 935         if (data->stop &&
 936             (data->error ||
 937              !host->mrq->sbc)) {
 938
 939                 /*
 940                  * The controller needs a reset of internal state machines
 941                  * upon error conditions.
 942                  */
 943                 if (data->error) {
 944                         sdhci_reset(host, SDHCI_RESET_CMD);
 945                         sdhci_reset(host, SDHCI_RESET_DATA);
 946                 }
 947
 948                 sdhci_send_command(host, data->stop);
 949         } else
 950                 tasklet_schedule(&host->finish_tasklet);
 951 }
 952
 953 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 954 {
 955         int flags;
 956         u32 mask;
 957         unsigned long timeout;
 958
 959         WARN_ON(host->cmd);
 960
 961         /* Wait max 10 ms */
 962         timeout = 10;
 963
 964         mask = SDHCI_CMD_INHIBIT;
 965         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 966                 mask |= SDHCI_DATA_INHIBIT;
 967
 968         /* We shouldn't wait for data inihibit for stop commands, even
 969            though they might use busy signaling */
 970         if (host->mrq->data && (cmd == host->mrq->data->stop))
 971                 mask &= ~SDHCI_DATA_INHIBIT;
 972
 973         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 974                 if (timeout == 0) {
 975                         pr_err("%s: Controller never released "
 976                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 977                         sdhci_dumpregs(host);
 978                         cmd->error = -EIO;
 979                         tasklet_schedule(&host->finish_tasklet);
 980                         return;
 981                 }
 982                 timeout--;
 983                 mdelay(1);
 984         }
 985
 986         mod_timer(&host->timer, jiffies + 10 * HZ);
 987
 988         host->cmd = cmd;
 989
 990         sdhci_prepare_data(host, cmd);
 991
 992         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 993
 994         sdhci_set_transfer_mode(host, cmd);
 995
 996         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 997                 pr_err("%s: Unsupported response type!\n",
 998                         mmc_hostname(host->mmc));
 999                 cmd->error = -EINVAL;
1000                 tasklet_schedule(&host->finish_tasklet);
1001                 return;
1002         }
1003
1004         if (!(cmd->flags & MMC_RSP_PRESENT))
1005                 flags = SDHCI_CMD_RESP_NONE;
1006         else if (cmd->flags & MMC_RSP_136)
1007                 flags = SDHCI_CMD_RESP_LONG;
1008         else if (cmd->flags & MMC_RSP_BUSY)
1009                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1010         else
1011                 flags = SDHCI_CMD_RESP_SHORT;
1012
1013         if (cmd->flags & MMC_RSP_CRC)
1014                 flags |= SDHCI_CMD_CRC;
1015         if (cmd->flags & MMC_RSP_OPCODE)
1016                 flags |= SDHCI_CMD_INDEX;
1017
1018         /* CMD19 is special in that the Data Present Select should be set */
1019         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
1020                 flags |= SDHCI_CMD_DATA;
1021
1022         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1023 }
1024
1025 static void sdhci_finish_command(struct sdhci_host *host)
1026 {
1027         int i;
1028
1029         BUG_ON(host->cmd == NULL);
1030
1031         if (host->cmd->flags & MMC_RSP_PRESENT) {
1032                 if (host->cmd->flags & MMC_RSP_136) {
1033                         /* CRC is stripped so we need to do some shifting. */
1034                         for (i = 0;i < 4;i++) {
1035                                 host->cmd->resp[i] = sdhci_readl(host,
1036                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1037                                 if (i != 3)
1038                                         host->cmd->resp[i] |=
1039                                                 sdhci_readb(host,
1040                                                 SDHCI_RESPONSE + (3-i)*4-1);
1041                         }
1042                 } else {
1043                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1044                 }
1045         }
1046
1047         host->cmd->error = 0;
1048
1049         /* Finished CMD23, now send actual command. */
1050         if (host->cmd == host->mrq->sbc) {
1051                 host->cmd = NULL;
1052                 sdhci_send_command(host, host->mrq->cmd);
1053         } else {
1054
1055                 /* Processed actual command. */
1056                 if (host->data && host->data_early)
1057                         sdhci_finish_data(host);
1058
1059                 if (!host->cmd->data)
1060                         tasklet_schedule(&host->finish_tasklet);
1061
1062                 host->cmd = NULL;
1063         }
1064 }
1065
1066 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1067 {
1068         int div = 0; /* Initialized for compiler warning */
1069         u16 clk = 0;
1070         unsigned long timeout;
1071
1072         if (clock == host->clock)
1073                 return;
1074
1075         if (host->ops->set_clock) {
1076                 host->ops->set_clock(host, clock);
1077                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1078                         return;
1079         }
1080
1081         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1082
1083         if (clock == 0)
1084                 goto out;
1085
1086         if (host->version >= SDHCI_SPEC_300) {
1087                 /*
1088                  * Check if the Host Controller supports Programmable Clock
1089                  * Mode.
1090                  */
1091                 if (host->clk_mul) {
1092                         u16 ctrl;
1093
1094                         /*
1095                          * We need to figure out whether the Host Driver needs
1096                          * to select Programmable Clock Mode, or the value can
1097                          * be set automatically by the Host Controller based on
1098                          * the Preset Value registers.
1099                          */
1100                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1101                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1102                                 for (div = 1; div <= 1024; div++) {
1103                                         if (((host->max_clk * host->clk_mul) /
1104                                               div) <= clock)
1105                                                 break;
1106                                 }
1107                                 /*
1108                                  * Set Programmable Clock Mode in the Clock
1109                                  * Control register.
1110                                  */
1111                                 clk = SDHCI_PROG_CLOCK_MODE;
1112                                 div--;
1113                         }
1114                 } else {
1115                         /* Version 3.00 divisors must be a multiple of 2. */
1116                         if (host->max_clk <= clock)
1117                                 div = 1;
1118                         else {
1119                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1120                                      div += 2) {
1121                                         if ((host->max_clk / div) <= clock)
1122                                                 break;
1123                                 }
1124                         }
1125                         div >>= 1;
1126                 }
1127         } else {
1128                 /* Version 2.00 divisors must be a power of 2. */
1129                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1130                         if ((host->max_clk / div) <= clock)
1131                                 break;
1132                 }
1133                 div >>= 1;
1134         }
1135
1136         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1137         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1138                 << SDHCI_DIVIDER_HI_SHIFT;
1139         clk |= SDHCI_CLOCK_INT_EN;
1140         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1141
1142         /* Wait max 20 ms */
1143         timeout = 20;
1144         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1145                 & SDHCI_CLOCK_INT_STABLE)) {
1146                 if (timeout == 0) {
1147                         pr_err("%s: Internal clock never "
1148                                 "stabilised.\n", mmc_hostname(host->mmc));
1149                         sdhci_dumpregs(host);
1150                         return;
1151                 }
1152                 timeout--;
1153                 mdelay(1);
1154         }
1155
1156         clk |= SDHCI_CLOCK_CARD_EN;
1157         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1158
1159 out:
1160         host->clock = clock;
1161 }
1162
1163 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1164 {
1165         u8 pwr = 0;
1166
1167         if (power != (unsigned short)-1) {
1168                 switch (1 << power) {
1169                 case MMC_VDD_165_195:
1170                         pwr = SDHCI_POWER_180;
1171                         break;
1172                 case MMC_VDD_29_30:
1173                 case MMC_VDD_30_31:
1174                         pwr = SDHCI_POWER_300;
1175                         break;
1176                 case MMC_VDD_32_33:
1177                 case MMC_VDD_33_34:
1178                         pwr = SDHCI_POWER_330;
1179                         break;
1180                 default:
1181                         BUG();
1182                 }
1183         }
1184
1185         if (host->pwr == pwr)
1186                 return;
1187
1188         host->pwr = pwr;
1189
1190         if (pwr == 0) {
1191                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1192                 return;
1193         }
1194
1195         /*
1196          * Spec says that we should clear the power reg before setting
1197          * a new value. Some controllers don't seem to like this though.
1198          */
1199         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1200                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1201
1202         /*
1203          * At least the Marvell CaFe chip gets confused if we set the voltage
1204          * and set turn on power at the same time, so set the voltage first.
1205          */
1206         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1207                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1208
1209         pwr |= SDHCI_POWER_ON;
1210
1211         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1212
1213         /*
1214          * Some controllers need an extra 10ms delay of 10ms before they
1215          * can apply clock after applying power
1216          */
1217         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1218                 mdelay(10);
1219 }
1220
1221 /*****************************************************************************\
1222  *                                                                           *
1223  * MMC callbacks                                                             *
1224  *                                                                           *
1225 \*****************************************************************************/
1226
1227 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1228 {
1229         struct sdhci_host *host;
1230         bool present;
1231         unsigned long flags;
1232
1233         host = mmc_priv(mmc);
1234
1235         sdhci_runtime_pm_get(host);
1236
1237         spin_lock_irqsave(&host->lock, flags);
1238
1239         WARN_ON(host->mrq != NULL);
1240
1241 #ifndef SDHCI_USE_LEDS_CLASS
1242         sdhci_activate_led(host);
1243 #endif
1244
1245         /*
1246          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1247          * requests if Auto-CMD12 is enabled.
1248          */
1249         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1250                 if (mrq->stop) {
1251                         mrq->data->stop = NULL;
1252                         mrq->stop = NULL;
1253                 }
1254         }
1255
1256         host->mrq = mrq;
1257
1258         /* If polling, assume that the card is always present. */
1259         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1260                 present = true;
1261         else
1262                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1263                                 SDHCI_CARD_PRESENT;
1264
1265         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1266                 host->mrq->cmd->error = -ENOMEDIUM;
1267                 tasklet_schedule(&host->finish_tasklet);
1268         } else {
1269                 u32 present_state;
1270
1271                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1272                 /*
1273                  * Check if the re-tuning timer has already expired and there
1274                  * is no on-going data transfer. If so, we need to execute
1275                  * tuning procedure before sending command.
1276                  */
1277                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1278                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1279                         spin_unlock_irqrestore(&host->lock, flags);
1280                         sdhci_execute_tuning(mmc);
1281                         spin_lock_irqsave(&host->lock, flags);
1282
1283                         /* Restore original mmc_request structure */
1284                         host->mrq = mrq;
1285                 }
1286
1287                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1288                         sdhci_send_command(host, mrq->sbc);
1289                 else
1290                         sdhci_send_command(host, mrq->cmd);
1291         }
1292
1293         mmiowb();
1294         spin_unlock_irqrestore(&host->lock, flags);
1295 }
1296
1297 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1298 {
1299         unsigned long flags;
1300         u8 ctrl;
1301
1302         spin_lock_irqsave(&host->lock, flags);
1303
1304         if (host->flags & SDHCI_DEVICE_DEAD)
1305                 goto out;
1306
1307         /*
1308          * Reset the chip on each power off.
1309          * Should clear out any weird states.
1310          */
1311         if (ios->power_mode == MMC_POWER_OFF) {
1312                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1313                 sdhci_reinit(host);
1314         }
1315
1316         sdhci_set_clock(host, ios->clock);
1317
1318         if (ios->power_mode == MMC_POWER_OFF)
1319                 sdhci_set_power(host, -1);
1320         else
1321                 sdhci_set_power(host, ios->vdd);
1322
1323         if (host->ops->platform_send_init_74_clocks)
1324                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1325
1326         /*
1327          * If your platform has 8-bit width support but is not a v3 controller,
1328          * or if it requires special setup code, you should implement that in
1329          * platform_8bit_width().
1330          */
1331         if (host->ops->platform_8bit_width)
1332                 host->ops->platform_8bit_width(host, ios->bus_width);
1333         else {
1334                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1335                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1336                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1337                         if (host->version >= SDHCI_SPEC_300)
1338                                 ctrl |= SDHCI_CTRL_8BITBUS;
1339                 } else {
1340                         if (host->version >= SDHCI_SPEC_300)
1341                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1342                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1343                                 ctrl |= SDHCI_CTRL_4BITBUS;
1344                         else
1345                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1346                 }
1347                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1348         }
1349
1350         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1351
1352         if ((ios->timing == MMC_TIMING_SD_HS ||
1353              ios->timing == MMC_TIMING_MMC_HS)
1354             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1355                 ctrl |= SDHCI_CTRL_HISPD;
1356         else
1357                 ctrl &= ~SDHCI_CTRL_HISPD;
1358
1359         if (host->version >= SDHCI_SPEC_300) {
1360                 u16 clk, ctrl_2;
1361                 unsigned int clock;
1362
1363                 /* In case of UHS-I modes, set High Speed Enable */
1364                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1365                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1366                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1367                     (ios->timing == MMC_TIMING_UHS_SDR25))
1368                         ctrl |= SDHCI_CTRL_HISPD;
1369
1370                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1371                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1372                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1373                         /*
1374                          * We only need to set Driver Strength if the
1375                          * preset value enable is not set.
1376                          */
1377                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1378                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1379                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1380                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1381                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1382
1383                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1384                 } else {
1385                         /*
1386                          * According to SDHC Spec v3.00, if the Preset Value
1387                          * Enable in the Host Control 2 register is set, we
1388                          * need to reset SD Clock Enable before changing High
1389                          * Speed Enable to avoid generating clock gliches.
1390                          */
1391
1392                         /* Reset SD Clock Enable */
1393                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1394                         clk &= ~SDHCI_CLOCK_CARD_EN;
1395                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1396
1397                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1398
1399                         /* Re-enable SD Clock */
1400                         clock = host->clock;
1401                         host->clock = 0;
1402                         sdhci_set_clock(host, clock);
1403                 }
1404
1405
1406                 /* Reset SD Clock Enable */
1407                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1408                 clk &= ~SDHCI_CLOCK_CARD_EN;
1409                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1410
1411                 if (host->ops->set_uhs_signaling)
1412                         host->ops->set_uhs_signaling(host, ios->timing);
1413                 else {
1414                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1415                         /* Select Bus Speed Mode for host */
1416                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1417                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1418                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1419                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1420                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1421                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1422                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1423                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1424                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1425                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1426                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1427                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1428                 }
1429
1430                 /* Re-enable SD Clock */
1431                 clock = host->clock;
1432                 host->clock = 0;
1433                 sdhci_set_clock(host, clock);
1434         } else
1435                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1436
1437         /*
1438          * Some (ENE) controllers go apeshit on some ios operation,
1439          * signalling timeout and CRC errors even on CMD0. Resetting
1440          * it on each ios seems to solve the problem.
1441          */
1442         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1443                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1444
1445 out:
1446         mmiowb();
1447         spin_unlock_irqrestore(&host->lock, flags);
1448 }
1449
1450 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1451 {
1452         struct sdhci_host *host = mmc_priv(mmc);
1453
1454         sdhci_runtime_pm_get(host);
1455         sdhci_do_set_ios(host, ios);
1456         sdhci_runtime_pm_put(host);
1457 }
1458
1459 static int sdhci_check_ro(struct sdhci_host *host)
1460 {
1461         unsigned long flags;
1462         int is_readonly;
1463
1464         spin_lock_irqsave(&host->lock, flags);
1465
1466         if (host->flags & SDHCI_DEVICE_DEAD)
1467                 is_readonly = 0;
1468         else if (host->ops->get_ro)
1469                 is_readonly = host->ops->get_ro(host);
1470         else
1471                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1472                                 & SDHCI_WRITE_PROTECT);
1473
1474         spin_unlock_irqrestore(&host->lock, flags);
1475
1476         /* This quirk needs to be replaced by a callback-function later */
1477         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1478                 !is_readonly : is_readonly;
1479 }
1480
1481 #define SAMPLE_COUNT    5
1482
1483 static int sdhci_do_get_ro(struct sdhci_host *host)
1484 {
1485         int i, ro_count;
1486
1487         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1488                 return sdhci_check_ro(host);
1489
1490         ro_count = 0;
1491         for (i = 0; i < SAMPLE_COUNT; i++) {
1492                 if (sdhci_check_ro(host)) {
1493                         if (++ro_count > SAMPLE_COUNT / 2)
1494                                 return 1;
1495                 }
1496                 msleep(30);
1497         }
1498         return 0;
1499 }
1500
1501 static void sdhci_hw_reset(struct mmc_host *mmc)
1502 {
1503         struct sdhci_host *host = mmc_priv(mmc);
1504
1505         if (host->ops && host->ops->hw_reset)
1506                 host->ops->hw_reset(host);
1507 }
1508
1509 static int sdhci_get_ro(struct mmc_host *mmc)
1510 {
1511         struct sdhci_host *host = mmc_priv(mmc);
1512         int ret;
1513
1514         sdhci_runtime_pm_get(host);
1515         ret = sdhci_do_get_ro(host);
1516         sdhci_runtime_pm_put(host);
1517         return ret;
1518 }
1519
1520 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1521 {
1522         if (host->flags & SDHCI_DEVICE_DEAD)
1523                 goto out;
1524
1525         if (enable)
1526                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1527         else
1528                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1529
1530         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1531         if (host->runtime_suspended)
1532                 goto out;
1533
1534         if (enable)
1535                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1536         else
1537                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1538 out:
1539         mmiowb();
1540 }
1541
1542 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1543 {
1544         struct sdhci_host *host = mmc_priv(mmc);
1545         unsigned long flags;
1546
1547         spin_lock_irqsave(&host->lock, flags);
1548         sdhci_enable_sdio_irq_nolock(host, enable);
1549         spin_unlock_irqrestore(&host->lock, flags);
1550 }
1551
1552 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1553                                                 struct mmc_ios *ios)
1554 {
1555         u8 pwr;
1556         u16 clk, ctrl;
1557         u32 present_state;
1558
1559         /*
1560          * Signal Voltage Switching is only applicable for Host Controllers
1561          * v3.00 and above.
1562          */
1563         if (host->version < SDHCI_SPEC_300)
1564                 return 0;
1565
1566         /*
1567          * We first check whether the request is to set signalling voltage
1568          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1569          */
1570         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1571         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1572                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1573                 ctrl &= ~SDHCI_CTRL_VDD_180;
1574                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1575
1576                 /* Wait for 5ms */
1577                 usleep_range(5000, 5500);
1578
1579                 /* 3.3V regulator output should be stable within 5 ms */
1580                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1581                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1582                         return 0;
1583                 else {
1584                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1585                                 "signalling voltage failed\n");
1586                         return -EIO;
1587                 }
1588         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1589                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1590                 /* Stop SDCLK */
1591                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1592                 clk &= ~SDHCI_CLOCK_CARD_EN;
1593                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1594
1595                 /* Check whether DAT[3:0] is 0000 */
1596                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1597                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1598                        SDHCI_DATA_LVL_SHIFT)) {
1599                         /*
1600                          * Enable 1.8V Signal Enable in the Host Control2
1601                          * register
1602                          */
1603                         ctrl |= SDHCI_CTRL_VDD_180;
1604                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1605
1606                         /* Wait for 5ms */
1607                         usleep_range(5000, 5500);
1608
1609                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1610                         if (ctrl & SDHCI_CTRL_VDD_180) {
1611                                 /* Provide SDCLK again and wait for 1ms*/
1612                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1613                                 clk |= SDHCI_CLOCK_CARD_EN;
1614                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1615                                 usleep_range(1000, 1500);
1616
1617                                 /*
1618                                  * If DAT[3:0] level is 1111b, then the card
1619                                  * was successfully switched to 1.8V signaling.
1620                                  */
1621                                 present_state = sdhci_readl(host,
1622                                                         SDHCI_PRESENT_STATE);
1623                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1624                                      SDHCI_DATA_LVL_MASK)
1625                                         return 0;
1626                         }
1627                 }
1628
1629                 /*
1630                  * If we are here, that means the switch to 1.8V signaling
1631                  * failed. We power cycle the card, and retry initialization
1632                  * sequence by setting S18R to 0.
1633                  */
1634                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1635                 pwr &= ~SDHCI_POWER_ON;
1636                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1637
1638                 /* Wait for 1ms as per the spec */
1639                 usleep_range(1000, 1500);
1640                 pwr |= SDHCI_POWER_ON;
1641                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1642
1643                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1644                         "voltage failed, retrying with S18R set to 0\n");
1645                 return -EAGAIN;
1646         } else
1647                 /* No signal voltage switch required */
1648                 return 0;
1649 }
1650
1651 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1652         struct mmc_ios *ios)
1653 {
1654         struct sdhci_host *host = mmc_priv(mmc);
1655         int err;
1656
1657         if (host->version < SDHCI_SPEC_300)
1658                 return 0;
1659         sdhci_runtime_pm_get(host);
1660         err = sdhci_do_start_signal_voltage_switch(host, ios);
1661         sdhci_runtime_pm_put(host);
1662         return err;
1663 }
1664
1665 static int sdhci_execute_tuning(struct mmc_host *mmc)
1666 {
1667         struct sdhci_host *host;
1668         u16 ctrl;
1669         u32 ier;
1670         int tuning_loop_counter = MAX_TUNING_LOOP;
1671         unsigned long timeout;
1672         int err = 0;
1673         unsigned long flags;
1674
1675         host = mmc_priv(mmc);
1676
1677         sdhci_runtime_pm_get(host);
1678         spin_lock_irqsave(&host->lock, flags);
1679
1680         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1681
1682         /*
1683          * Host Controller needs tuning only in case of SDR104 mode
1684          * and for SDR50 mode when Use Tuning for SDR50 is set in
1685          * Capabilities register.
1686          */
1687         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1688             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1689             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1690                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1691         else {
1692                 spin_unlock_irqrestore(&host->lock, flags);
1693                 sdhci_runtime_pm_put(host);
1694                 return 0;
1695         }
1696
1697         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1698
1699         /*
1700          * As per the Host Controller spec v3.00, tuning command
1701          * generates Buffer Read Ready interrupt, so enable that.
1702          *
1703          * Note: The spec clearly says that when tuning sequence
1704          * is being performed, the controller does not generate
1705          * interrupts other than Buffer Read Ready interrupt. But
1706          * to make sure we don't hit a controller bug, we _only_
1707          * enable Buffer Read Ready interrupt here.
1708          */
1709         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1710         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1711
1712         /*
1713          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1714          * of loops reaches 40 times or a timeout of 150ms occurs.
1715          */
1716         timeout = 150;
1717         do {
1718                 struct mmc_command cmd = {0};
1719                 struct mmc_request mrq = {NULL};
1720
1721                 if (!tuning_loop_counter && !timeout)
1722                         break;
1723
1724                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1725                 cmd.arg = 0;
1726                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1727                 cmd.retries = 0;
1728                 cmd.data = NULL;
1729                 cmd.error = 0;
1730
1731                 mrq.cmd = &cmd;
1732                 host->mrq = &mrq;
1733
1734                 /*
1735                  * In response to CMD19, the card sends 64 bytes of tuning
1736                  * block to the Host Controller. So we set the block size
1737                  * to 64 here.
1738                  */
1739                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1740
1741                 /*
1742                  * The tuning block is sent by the card to the host controller.
1743                  * So we set the TRNS_READ bit in the Transfer Mode register.
1744                  * This also takes care of setting DMA Enable and Multi Block
1745                  * Select in the same register to 0.
1746                  */
1747                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1748
1749                 sdhci_send_command(host, &cmd);
1750
1751                 host->cmd = NULL;
1752                 host->mrq = NULL;
1753
1754                 spin_unlock_irqrestore(&host->lock, flags);
1755                 /* Wait for Buffer Read Ready interrupt */
1756                 wait_event_interruptible_timeout(host->buf_ready_int,
1757                                         (host->tuning_done == 1),
1758                                         msecs_to_jiffies(50));
1759                 spin_lock_irqsave(&host->lock, flags);
1760
1761                 if (!host->tuning_done) {
1762                         pr_info(DRIVER_NAME ": Timeout waiting for "
1763                                 "Buffer Read Ready interrupt during tuning "
1764                                 "procedure, falling back to fixed sampling "
1765                                 "clock\n");
1766                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1768                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1769                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1770
1771                         err = -EIO;
1772                         goto out;
1773                 }
1774
1775                 host->tuning_done = 0;
1776
1777                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1778                 tuning_loop_counter--;
1779                 timeout--;
1780                 mdelay(1);
1781         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1782
1783         /*
1784          * The Host Driver has exhausted the maximum number of loops allowed,
1785          * so use fixed sampling frequency.
1786          */
1787         if (!tuning_loop_counter || !timeout) {
1788                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1789                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1790         } else {
1791                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1792                         pr_info(DRIVER_NAME ": Tuning procedure"
1793                                 " failed, falling back to fixed sampling"
1794                                 " clock\n");
1795                         err = -EIO;
1796                 }
1797         }
1798
1799 out:
1800         /*
1801          * If this is the very first time we are here, we start the retuning
1802          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1803          * flag won't be set, we check this condition before actually starting
1804          * the timer.
1805          */
1806         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1807             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1808                 mod_timer(&host->tuning_timer, jiffies +
1809                         host->tuning_count * HZ);
1810                 /* Tuning mode 1 limits the maximum data length to 4MB */
1811                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1812         } else {
1813                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1814                 /* Reload the new initial value for timer */
1815                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1816                         mod_timer(&host->tuning_timer, jiffies +
1817                                 host->tuning_count * HZ);
1818         }
1819
1820         /*
1821          * In case tuning fails, host controllers which support re-tuning can
1822          * try tuning again at a later time, when the re-tuning timer expires.
1823          * So for these controllers, we return 0. Since there might be other
1824          * controllers who do not have this capability, we return error for
1825          * them.
1826          */
1827         if (err && host->tuning_count &&
1828             host->tuning_mode == SDHCI_TUNING_MODE_1)
1829                 err = 0;
1830
1831         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1832         spin_unlock_irqrestore(&host->lock, flags);
1833         sdhci_runtime_pm_put(host);
1834
1835         return err;
1836 }
1837
1838 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1839 {
1840         u16 ctrl;
1841         unsigned long flags;
1842
1843         /* Host Controller v3.00 defines preset value registers */
1844         if (host->version < SDHCI_SPEC_300)
1845                 return;
1846
1847         spin_lock_irqsave(&host->lock, flags);
1848
1849         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1850
1851         /*
1852          * We only enable or disable Preset Value if they are not already
1853          * enabled or disabled respectively. Otherwise, we bail out.
1854          */
1855         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1856                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1857                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1858                 host->flags |= SDHCI_PV_ENABLED;
1859         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1860                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1861                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1862                 host->flags &= ~SDHCI_PV_ENABLED;
1863         }
1864
1865         spin_unlock_irqrestore(&host->lock, flags);
1866 }
1867
1868 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1869 {
1870         struct sdhci_host *host = mmc_priv(mmc);
1871
1872         sdhci_runtime_pm_get(host);
1873         sdhci_do_enable_preset_value(host, enable);
1874         sdhci_runtime_pm_put(host);
1875 }
1876
1877 static const struct mmc_host_ops sdhci_ops = {
1878         .request        = sdhci_request,
1879         .set_ios        = sdhci_set_ios,
1880         .get_ro         = sdhci_get_ro,
1881         .hw_reset       = sdhci_hw_reset,
1882         .enable_sdio_irq = sdhci_enable_sdio_irq,
1883         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1884         .execute_tuning                 = sdhci_execute_tuning,
1885         .enable_preset_value            = sdhci_enable_preset_value,
1886 };
1887
1888 /*****************************************************************************\
1889  *                                                                           *
1890  * Tasklets                                                                  *
1891  *                                                                           *
1892 \*****************************************************************************/
1893
1894 static void sdhci_tasklet_card(unsigned long param)
1895 {
1896         struct sdhci_host *host;
1897         unsigned long flags;
1898
1899         host = (struct sdhci_host*)param;
1900
1901         spin_lock_irqsave(&host->lock, flags);
1902
1903         /* Check host->mrq first in case we are runtime suspended */
1904         if (host->mrq &&
1905             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1906                 pr_err("%s: Card removed during transfer!\n",
1907                         mmc_hostname(host->mmc));
1908                 pr_err("%s: Resetting controller.\n",
1909                         mmc_hostname(host->mmc));
1910
1911                 sdhci_reset(host, SDHCI_RESET_CMD);
1912                 sdhci_reset(host, SDHCI_RESET_DATA);
1913
1914                 host->mrq->cmd->error = -ENOMEDIUM;
1915                 tasklet_schedule(&host->finish_tasklet);
1916         }
1917
1918         spin_unlock_irqrestore(&host->lock, flags);
1919
1920         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1921 }
1922
1923 static void sdhci_tasklet_finish(unsigned long param)
1924 {
1925         struct sdhci_host *host;
1926         unsigned long flags;
1927         struct mmc_request *mrq;
1928
1929         host = (struct sdhci_host*)param;
1930
1931         spin_lock_irqsave(&host->lock, flags);
1932
1933         /*
1934          * If this tasklet gets rescheduled while running, it will
1935          * be run again afterwards but without any active request.
1936          */
1937         if (!host->mrq) {
1938                 spin_unlock_irqrestore(&host->lock, flags);
1939                 return;
1940         }
1941
1942         del_timer(&host->timer);
1943
1944         mrq = host->mrq;
1945
1946         /*
1947          * The controller needs a reset of internal state machines
1948          * upon error conditions.
1949          */
1950         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1951             ((mrq->cmd && mrq->cmd->error) ||
1952                  (mrq->data && (mrq->data->error ||
1953                   (mrq->data->stop && mrq->data->stop->error))) ||
1954                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1955
1956                 /* Some controllers need this kick or reset won't work here */
1957                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1958                         unsigned int clock;
1959
1960                         /* This is to force an update */
1961                         clock = host->clock;
1962                         host->clock = 0;
1963                         sdhci_set_clock(host, clock);
1964                 }
1965
1966                 /* Spec says we should do both at the same time, but Ricoh
1967                    controllers do not like that. */
1968                 sdhci_reset(host, SDHCI_RESET_CMD);
1969                 sdhci_reset(host, SDHCI_RESET_DATA);
1970         }
1971
1972         host->mrq = NULL;
1973         host->cmd = NULL;
1974         host->data = NULL;
1975
1976 #ifndef SDHCI_USE_LEDS_CLASS
1977         sdhci_deactivate_led(host);
1978 #endif
1979
1980         mmiowb();
1981         spin_unlock_irqrestore(&host->lock, flags);
1982
1983         mmc_request_done(host->mmc, mrq);
1984         sdhci_runtime_pm_put(host);
1985 }
1986
1987 static void sdhci_timeout_timer(unsigned long data)
1988 {
1989         struct sdhci_host *host;
1990         unsigned long flags;
1991
1992         host = (struct sdhci_host*)data;
1993
1994         spin_lock_irqsave(&host->lock, flags);
1995
1996         if (host->mrq) {
1997                 pr_err("%s: Timeout waiting for hardware "
1998                         "interrupt.\n", mmc_hostname(host->mmc));
1999                 sdhci_dumpregs(host);
2000
2001                 if (host->data) {
2002                         host->data->error = -ETIMEDOUT;
2003                         sdhci_finish_data(host);
2004                 } else {
2005                         if (host->cmd)
2006                                 host->cmd->error = -ETIMEDOUT;
2007                         else
2008                                 host->mrq->cmd->error = -ETIMEDOUT;
2009
2010                         tasklet_schedule(&host->finish_tasklet);
2011                 }
2012         }
2013
2014         mmiowb();
2015         spin_unlock_irqrestore(&host->lock, flags);
2016 }
2017
2018 static void sdhci_tuning_timer(unsigned long data)
2019 {
2020         struct sdhci_host *host;
2021         unsigned long flags;
2022
2023         host = (struct sdhci_host *)data;
2024
2025         spin_lock_irqsave(&host->lock, flags);
2026
2027         host->flags |= SDHCI_NEEDS_RETUNING;
2028
2029         spin_unlock_irqrestore(&host->lock, flags);
2030 }
2031
2032 /*****************************************************************************\
2033  *                                                                           *
2034  * Interrupt handling                                                        *
2035  *                                                                           *
2036 \*****************************************************************************/
2037
2038 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2039 {
2040         BUG_ON(intmask == 0);
2041
2042         if (!host->cmd) {
2043                 pr_err("%s: Got command interrupt 0x%08x even "
2044                         "though no command operation was in progress.\n",
2045                         mmc_hostname(host->mmc), (unsigned)intmask);
2046                 sdhci_dumpregs(host);
2047                 return;
2048         }
2049
2050         if (intmask & SDHCI_INT_TIMEOUT)
2051                 host->cmd->error = -ETIMEDOUT;
2052         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2053                         SDHCI_INT_INDEX))
2054                 host->cmd->error = -EILSEQ;
2055
2056         if (host->cmd->error) {
2057                 tasklet_schedule(&host->finish_tasklet);
2058                 return;
2059         }
2060
2061         /*
2062          * The host can send and interrupt when the busy state has
2063          * ended, allowing us to wait without wasting CPU cycles.
2064          * Unfortunately this is overloaded on the "data complete"
2065          * interrupt, so we need to take some care when handling
2066          * it.
2067          *
2068          * Note: The 1.0 specification is a bit ambiguous about this
2069          *       feature so there might be some problems with older
2070          *       controllers.
2071          */
2072         if (host->cmd->flags & MMC_RSP_BUSY) {
2073                 if (host->cmd->data)
2074                         DBG("Cannot wait for busy signal when also "
2075                                 "doing a data transfer");
2076                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2077                         return;
2078
2079                 /* The controller does not support the end-of-busy IRQ,
2080                  * fall through and take the SDHCI_INT_RESPONSE */
2081         }
2082
2083         if (intmask & SDHCI_INT_RESPONSE)
2084                 sdhci_finish_command(host);
2085 }
2086
2087 #ifdef CONFIG_MMC_DEBUG
2088 static void sdhci_show_adma_error(struct sdhci_host *host)
2089 {
2090         const char *name = mmc_hostname(host->mmc);
2091         u8 *desc = host->adma_desc;
2092         __le32 *dma;
2093         __le16 *len;
2094         u8 attr;
2095
2096         sdhci_dumpregs(host);
2097
2098         while (true) {
2099                 dma = (__le32 *)(desc + 4);
2100                 len = (__le16 *)(desc + 2);
2101                 attr = *desc;
2102
2103                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2104                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2105
2106                 desc += 8;
2107
2108                 if (attr & 2)
2109                         break;
2110         }
2111 }
2112 #else
2113 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2114 #endif
2115
2116 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2117 {
2118         BUG_ON(intmask == 0);
2119
2120         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2121         if (intmask & SDHCI_INT_DATA_AVAIL) {
2122                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2123                     MMC_SEND_TUNING_BLOCK) {
2124                         host->tuning_done = 1;
2125                         wake_up(&host->buf_ready_int);
2126                         return;
2127                 }
2128         }
2129
2130         if (!host->data) {
2131                 /*
2132                  * The "data complete" interrupt is also used to
2133                  * indicate that a busy state has ended. See comment
2134                  * above in sdhci_cmd_irq().
2135                  */
2136                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2137                         if (intmask & SDHCI_INT_DATA_END) {
2138                                 sdhci_finish_command(host);
2139                                 return;
2140                         }
2141                 }
2142
2143                 pr_err("%s: Got data interrupt 0x%08x even "
2144                         "though no data operation was in progress.\n",
2145                         mmc_hostname(host->mmc), (unsigned)intmask);
2146                 sdhci_dumpregs(host);
2147
2148                 return;
2149         }
2150
2151         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2152                 host->data->error = -ETIMEDOUT;
2153         else if (intmask & SDHCI_INT_DATA_END_BIT)
2154                 host->data->error = -EILSEQ;
2155         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2156                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2157                         != MMC_BUS_TEST_R)
2158                 host->data->error = -EILSEQ;
2159         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2160                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2161                 sdhci_show_adma_error(host);
2162                 host->data->error = -EIO;
2163         }
2164
2165         if (host->data->error)
2166                 sdhci_finish_data(host);
2167         else {
2168                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2169                         sdhci_transfer_pio(host);
2170
2171                 /*
2172                  * We currently don't do anything fancy with DMA
2173                  * boundaries, but as we can't disable the feature
2174                  * we need to at least restart the transfer.
2175                  *
2176                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2177                  * should return a valid address to continue from, but as
2178                  * some controllers are faulty, don't trust them.
2179                  */
2180                 if (intmask & SDHCI_INT_DMA_END) {
2181                         u32 dmastart, dmanow;
2182                         dmastart = sg_dma_address(host->data->sg);
2183                         dmanow = dmastart + host->data->bytes_xfered;
2184                         /*
2185                          * Force update to the next DMA block boundary.
2186                          */
2187                         dmanow = (dmanow &
2188                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2189                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2190                         host->data->bytes_xfered = dmanow - dmastart;
2191                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2192                                 " next 0x%08x\n",
2193                                 mmc_hostname(host->mmc), dmastart,
2194                                 host->data->bytes_xfered, dmanow);
2195                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2196                 }
2197
2198                 if (intmask & SDHCI_INT_DATA_END) {
2199                         if (host->cmd) {
2200                                 /*
2201                                  * Data managed to finish before the
2202                                  * command completed. Make sure we do
2203                                  * things in the proper order.
2204                                  */
2205                                 host->data_early = 1;
2206                         } else {
2207                                 sdhci_finish_data(host);
2208                         }
2209                 }
2210         }
2211 }
2212
2213 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2214 {
2215         irqreturn_t result;
2216         struct sdhci_host *host = dev_id;
2217         u32 intmask;
2218         int cardint = 0;
2219
2220         spin_lock(&host->lock);
2221
2222         if (host->runtime_suspended) {
2223                 spin_unlock(&host->lock);
2224                 pr_warning("%s: got irq while runtime suspended\n",
2225                        mmc_hostname(host->mmc));
2226                 return IRQ_HANDLED;
2227         }
2228
2229         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2230
2231         if (!intmask || intmask == 0xffffffff) {
2232                 result = IRQ_NONE;
2233                 goto out;
2234         }
2235
2236         DBG("*** %s got interrupt: 0x%08x\n",
2237                 mmc_hostname(host->mmc), intmask);
2238
2239         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2240                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2241                               SDHCI_CARD_PRESENT;
2242
2243                 /*
2244                  * There is a observation on i.mx esdhc.  INSERT bit will be
2245                  * immediately set again when it gets cleared, if a card is
2246                  * inserted.  We have to mask the irq to prevent interrupt
2247                  * storm which will freeze the system.  And the REMOVE gets
2248                  * the same situation.
2249                  *
2250                  * More testing are needed here to ensure it works for other
2251                  * platforms though.
2252                  */
2253                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2254                                                 SDHCI_INT_CARD_REMOVE);
2255                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2256                                                   SDHCI_INT_CARD_INSERT);
2257
2258                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2259                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2260                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2261                 tasklet_schedule(&host->card_tasklet);
2262         }
2263
2264         if (intmask & SDHCI_INT_CMD_MASK) {
2265                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2266                         SDHCI_INT_STATUS);
2267                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2268         }
2269
2270         if (intmask & SDHCI_INT_DATA_MASK) {
2271                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2272                         SDHCI_INT_STATUS);
2273                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2274         }
2275
2276         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2277
2278         intmask &= ~SDHCI_INT_ERROR;
2279
2280         if (intmask & SDHCI_INT_BUS_POWER) {
2281                 pr_err("%s: Card is consuming too much power!\n",
2282                         mmc_hostname(host->mmc));
2283                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2284         }
2285
2286         intmask &= ~SDHCI_INT_BUS_POWER;
2287
2288         if (intmask & SDHCI_INT_CARD_INT)
2289                 cardint = 1;
2290
2291         intmask &= ~SDHCI_INT_CARD_INT;
2292
2293         if (intmask) {
2294                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2295                         mmc_hostname(host->mmc), intmask);
2296                 sdhci_dumpregs(host);
2297
2298                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2299         }
2300
2301         result = IRQ_HANDLED;
2302
2303         mmiowb();
2304 out:
2305         spin_unlock(&host->lock);
2306
2307         /*
2308          * We have to delay this as it calls back into the driver.
2309          */
2310         if (cardint)
2311                 mmc_signal_sdio_irq(host->mmc);
2312
2313         return result;
2314 }
2315
2316 /*****************************************************************************\
2317  *                                                                           *
2318  * Suspend/resume                                                            *
2319  *                                                                           *
2320 \*****************************************************************************/
2321
2322 #ifdef CONFIG_PM
2323
2324 int sdhci_suspend_host(struct sdhci_host *host)
2325 {
2326         int ret;
2327
2328         sdhci_disable_card_detection(host);
2329
2330         /* Disable tuning since we are suspending */
2331         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2332             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2333                 del_timer_sync(&host->tuning_timer);
2334                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2335         }
2336
2337         ret = mmc_suspend_host(host->mmc);
2338         if (ret)
2339                 return ret;
2340
2341         free_irq(host->irq, host);
2342
2343         if (host->vmmc)
2344                 ret = regulator_disable(host->vmmc);
2345
2346         return ret;
2347 }
2348
2349 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2350
2351 int sdhci_resume_host(struct sdhci_host *host)
2352 {
2353         int ret;
2354
2355         if (host->vmmc) {
2356                 int ret = regulator_enable(host->vmmc);
2357                 if (ret)
2358                         return ret;
2359         }
2360
2361         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2362                 if (host->ops->enable_dma)
2363                         host->ops->enable_dma(host);
2364         }
2365
2366         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2367                           mmc_hostname(host->mmc), host);
2368         if (ret)
2369                 return ret;
2370
2371         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2372         mmiowb();
2373
2374         ret = mmc_resume_host(host->mmc);
2375         sdhci_enable_card_detection(host);
2376
2377         /* Set the re-tuning expiration flag */
2378         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2379             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2380                 host->flags |= SDHCI_NEEDS_RETUNING;
2381
2382         return ret;
2383 }
2384
2385 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2386
2387 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2388 {
2389         u8 val;
2390         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2391         val |= SDHCI_WAKE_ON_INT;
2392         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2393 }
2394
2395 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2396
2397 #endif /* CONFIG_PM */
2398
2399 #ifdef CONFIG_PM_RUNTIME
2400
2401 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2402 {
2403         return pm_runtime_get_sync(host->mmc->parent);
2404 }
2405
2406 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2407 {
2408         pm_runtime_mark_last_busy(host->mmc->parent);
2409         return pm_runtime_put_autosuspend(host->mmc->parent);
2410 }
2411
2412 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2413 {
2414         unsigned long flags;
2415         int ret = 0;
2416
2417         /* Disable tuning since we are suspending */
2418         if (host->version >= SDHCI_SPEC_300 &&
2419             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2420                 del_timer_sync(&host->tuning_timer);
2421                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2422         }
2423
2424         spin_lock_irqsave(&host->lock, flags);
2425         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2426         spin_unlock_irqrestore(&host->lock, flags);
2427
2428         synchronize_irq(host->irq);
2429
2430         spin_lock_irqsave(&host->lock, flags);
2431         host->runtime_suspended = true;
2432         spin_unlock_irqrestore(&host->lock, flags);
2433
2434         return ret;
2435 }
2436 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2437
2438 int sdhci_runtime_resume_host(struct sdhci_host *host)
2439 {
2440         unsigned long flags;
2441         int ret = 0, host_flags = host->flags;
2442
2443         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2444                 if (host->ops->enable_dma)
2445                         host->ops->enable_dma(host);
2446         }
2447
2448         sdhci_init(host, 0);
2449
2450         /* Force clock and power re-program */
2451         host->pwr = 0;
2452         host->clock = 0;
2453         sdhci_do_set_ios(host, &host->mmc->ios);
2454
2455         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2456         if (host_flags & SDHCI_PV_ENABLED)
2457                 sdhci_do_enable_preset_value(host, true);
2458
2459         /* Set the re-tuning expiration flag */
2460         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2461             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2462                 host->flags |= SDHCI_NEEDS_RETUNING;
2463
2464         spin_lock_irqsave(&host->lock, flags);
2465
2466         host->runtime_suspended = false;
2467
2468         /* Enable SDIO IRQ */
2469         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2470                 sdhci_enable_sdio_irq_nolock(host, true);
2471
2472         /* Enable Card Detection */
2473         sdhci_enable_card_detection(host);
2474
2475         spin_unlock_irqrestore(&host->lock, flags);
2476
2477         return ret;
2478 }
2479 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2480
2481 #endif
2482
2483 /*****************************************************************************\
2484  *                                                                           *
2485  * Device allocation/registration                                            *
2486  *                                                                           *
2487 \*****************************************************************************/
2488
2489 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2490         size_t priv_size)
2491 {
2492         struct mmc_host *mmc;
2493         struct sdhci_host *host;
2494
2495         WARN_ON(dev == NULL);
2496
2497         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2498         if (!mmc)
2499                 return ERR_PTR(-ENOMEM);
2500
2501         host = mmc_priv(mmc);
2502         host->mmc = mmc;
2503
2504         return host;
2505 }
2506
2507 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2508
2509 int sdhci_add_host(struct sdhci_host *host)
2510 {
2511         struct mmc_host *mmc;
2512         u32 caps[2];
2513         u32 max_current_caps;
2514         unsigned int ocr_avail;
2515         int ret;
2516
2517         WARN_ON(host == NULL);
2518         if (host == NULL)
2519                 return -EINVAL;
2520
2521         mmc = host->mmc;
2522
2523         if (debug_quirks)
2524                 host->quirks = debug_quirks;
2525         if (debug_quirks2)
2526                 host->quirks2 = debug_quirks2;
2527
2528         sdhci_reset(host, SDHCI_RESET_ALL);
2529
2530         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2531         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2532                                 >> SDHCI_SPEC_VER_SHIFT;
2533         if (host->version > SDHCI_SPEC_300) {
2534                 pr_err("%s: Unknown controller version (%d). "
2535                         "You may experience problems.\n", mmc_hostname(mmc),
2536                         host->version);
2537         }
2538
2539         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2540                 sdhci_readl(host, SDHCI_CAPABILITIES);
2541
2542         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2543                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2544
2545         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2546                 host->flags |= SDHCI_USE_SDMA;
2547         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2548                 DBG("Controller doesn't have SDMA capability\n");
2549         else
2550                 host->flags |= SDHCI_USE_SDMA;
2551
2552         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2553                 (host->flags & SDHCI_USE_SDMA)) {
2554                 DBG("Disabling DMA as it is marked broken\n");
2555                 host->flags &= ~SDHCI_USE_SDMA;
2556         }
2557
2558         if ((host->version >= SDHCI_SPEC_200) &&
2559                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2560                 host->flags |= SDHCI_USE_ADMA;
2561
2562         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2563                 (host->flags & SDHCI_USE_ADMA)) {
2564                 DBG("Disabling ADMA as it is marked broken\n");
2565                 host->flags &= ~SDHCI_USE_ADMA;
2566         }
2567
2568         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2569                 if (host->ops->enable_dma) {
2570                         if (host->ops->enable_dma(host)) {
2571                                 pr_warning("%s: No suitable DMA "
2572                                         "available. Falling back to PIO.\n",
2573                                         mmc_hostname(mmc));
2574                                 host->flags &=
2575                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2576                         }
2577                 }
2578         }
2579
2580         if (host->flags & SDHCI_USE_ADMA) {
2581                 /*
2582                  * We need to allocate descriptors for all sg entries
2583                  * (128) and potentially one alignment transfer for
2584                  * each of those entries.
2585                  */
2586                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2587                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2588                 if (!host->adma_desc || !host->align_buffer) {
2589                         kfree(host->adma_desc);
2590                         kfree(host->align_buffer);
2591                         pr_warning("%s: Unable to allocate ADMA "
2592                                 "buffers. Falling back to standard DMA.\n",
2593                                 mmc_hostname(mmc));
2594                         host->flags &= ~SDHCI_USE_ADMA;
2595                 }
2596         }
2597
2598         /*
2599          * If we use DMA, then it's up to the caller to set the DMA
2600          * mask, but PIO does not need the hw shim so we set a new
2601          * mask here in that case.
2602          */
2603         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2604                 host->dma_mask = DMA_BIT_MASK(64);
2605                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2606         }
2607
2608         if (host->version >= SDHCI_SPEC_300)
2609                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2610                         >> SDHCI_CLOCK_BASE_SHIFT;
2611         else
2612                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2613                         >> SDHCI_CLOCK_BASE_SHIFT;
2614
2615         host->max_clk *= 1000000;
2616         if (host->max_clk == 0 || host->quirks &
2617                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2618                 if (!host->ops->get_max_clock) {
2619                         pr_err("%s: Hardware doesn't specify base clock "
2620                                "frequency.\n", mmc_hostname(mmc));
2621                         return -ENODEV;
2622                 }
2623                 host->max_clk = host->ops->get_max_clock(host);
2624         }
2625
2626         /*
2627          * In case of Host Controller v3.00, find out whether clock
2628          * multiplier is supported.
2629          */
2630         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2631                         SDHCI_CLOCK_MUL_SHIFT;
2632
2633         /*
2634          * In case the value in Clock Multiplier is 0, then programmable
2635          * clock mode is not supported, otherwise the actual clock
2636          * multiplier is one more than the value of Clock Multiplier
2637          * in the Capabilities Register.
2638          */
2639         if (host->clk_mul)
2640                 host->clk_mul += 1;
2641
2642         /*
2643          * Set host parameters.
2644          */
2645         mmc->ops = &sdhci_ops;
2646         mmc->f_max = host->max_clk;
2647         if (host->ops->get_min_clock)
2648                 mmc->f_min = host->ops->get_min_clock(host);
2649         else if (host->version >= SDHCI_SPEC_300) {
2650                 if (host->clk_mul) {
2651                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2652                         mmc->f_max = host->max_clk * host->clk_mul;
2653                 } else
2654                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2655         } else
2656                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2657
2658         host->timeout_clk =
2659                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2660         if (host->timeout_clk == 0) {
2661                 if (host->ops->get_timeout_clock) {
2662                         host->timeout_clk = host->ops->get_timeout_clock(host);
2663                 } else if (!(host->quirks &
2664                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2665                         pr_err("%s: Hardware doesn't specify timeout clock "
2666                                "frequency.\n", mmc_hostname(mmc));
2667                         return -ENODEV;
2668                 }
2669         }
2670         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2671                 host->timeout_clk *= 1000;
2672
2673         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2674                 host->timeout_clk = mmc->f_max / 1000;
2675
2676         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2677
2678         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2679
2680         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2681                 host->flags |= SDHCI_AUTO_CMD12;
2682
2683         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2684         if ((host->version >= SDHCI_SPEC_300) &&
2685             ((host->flags & SDHCI_USE_ADMA) ||
2686              !(host->flags & SDHCI_USE_SDMA))) {
2687                 host->flags |= SDHCI_AUTO_CMD23;
2688                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2689         } else {
2690                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2691         }
2692
2693         /*
2694          * A controller may support 8-bit width, but the board itself
2695          * might not have the pins brought out.  Boards that support
2696          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2697          * their platform code before calling sdhci_add_host(), and we
2698          * won't assume 8-bit width for hosts without that CAP.
2699          */
2700         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2701                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2702
2703         if (caps[0] & SDHCI_CAN_DO_HISPD)
2704                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2705
2706         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2707             mmc_card_is_removable(mmc))
2708                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2709
2710         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2711         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2712                        SDHCI_SUPPORT_DDR50))
2713                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2714
2715         /* SDR104 supports also implies SDR50 support */
2716         if (caps[1] & SDHCI_SUPPORT_SDR104)
2717                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2718         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2719                 mmc->caps |= MMC_CAP_UHS_SDR50;
2720
2721         if (caps[1] & SDHCI_SUPPORT_DDR50)
2722                 mmc->caps |= MMC_CAP_UHS_DDR50;
2723
2724         /* Does the host needs tuning for SDR50? */
2725         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2726                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2727
2728         /* Driver Type(s) (A, C, D) supported by the host */
2729         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2730                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2731         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2732                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2733         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2734                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2735
2736         /*
2737          * If Power Off Notify capability is enabled by the host,
2738          * set notify to short power off notify timeout value.
2739          */
2740         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2741                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2742         else
2743                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2744
2745         /* Initial value for re-tuning timer count */
2746         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2747                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2748
2749         /*
2750          * In case Re-tuning Timer is not disabled, the actual value of
2751          * re-tuning timer will be 2 ^ (n - 1).
2752          */
2753         if (host->tuning_count)
2754                 host->tuning_count = 1 << (host->tuning_count - 1);
2755
2756         /* Re-tuning mode supported by the Host Controller */
2757         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2758                              SDHCI_RETUNING_MODE_SHIFT;
2759
2760         ocr_avail = 0;
2761         /*
2762          * According to SD Host Controller spec v3.00, if the Host System
2763          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2764          * the value is meaningful only if Voltage Support in the Capabilities
2765          * register is set. The actual current value is 4 times the register
2766          * value.
2767          */
2768         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2769
2770         if (caps[0] & SDHCI_CAN_VDD_330) {
2771                 int max_current_330;
2772
2773                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2774
2775                 max_current_330 = ((max_current_caps &
2776                                    SDHCI_MAX_CURRENT_330_MASK) >>
2777                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2778                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2779
2780                 if (max_current_330 > 150)
2781                         mmc->caps |= MMC_CAP_SET_XPC_330;
2782         }
2783         if (caps[0] & SDHCI_CAN_VDD_300) {
2784                 int max_current_300;
2785
2786                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2787
2788                 max_current_300 = ((max_current_caps &
2789                                    SDHCI_MAX_CURRENT_300_MASK) >>
2790                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2791                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2792
2793                 if (max_current_300 > 150)
2794                         mmc->caps |= MMC_CAP_SET_XPC_300;
2795         }
2796         if (caps[0] & SDHCI_CAN_VDD_180) {
2797                 int max_current_180;
2798
2799                 ocr_avail |= MMC_VDD_165_195;
2800
2801                 max_current_180 = ((max_current_caps &
2802                                    SDHCI_MAX_CURRENT_180_MASK) >>
2803                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2804                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2805
2806                 if (max_current_180 > 150)
2807                         mmc->caps |= MMC_CAP_SET_XPC_180;
2808
2809                 /* Maximum current capabilities of the host at 1.8V */
2810                 if (max_current_180 >= 800)
2811                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2812                 else if (max_current_180 >= 600)
2813                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2814                 else if (max_current_180 >= 400)
2815                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2816                 else
2817                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2818         }
2819
2820         mmc->ocr_avail = ocr_avail;
2821         mmc->ocr_avail_sdio = ocr_avail;
2822         if (host->ocr_avail_sdio)
2823                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2824         mmc->ocr_avail_sd = ocr_avail;
2825         if (host->ocr_avail_sd)
2826                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2827         else /* normal SD controllers don't support 1.8V */
2828                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2829         mmc->ocr_avail_mmc = ocr_avail;
2830         if (host->ocr_avail_mmc)
2831                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2832
2833         if (mmc->ocr_avail == 0) {
2834                 pr_err("%s: Hardware doesn't report any "
2835                         "support voltages.\n", mmc_hostname(mmc));
2836                 return -ENODEV;
2837         }
2838
2839         spin_lock_init(&host->lock);
2840
2841         /*
2842          * Maximum number of segments. Depends on if the hardware
2843          * can do scatter/gather or not.
2844          */
2845         if (host->flags & SDHCI_USE_ADMA)
2846                 mmc->max_segs = 128;
2847         else if (host->flags & SDHCI_USE_SDMA)
2848                 mmc->max_segs = 1;
2849         else /* PIO */
2850                 mmc->max_segs = 128;
2851
2852         /*
2853          * Maximum number of sectors in one transfer. Limited by DMA boundary
2854          * size (512KiB).
2855          */
2856         mmc->max_req_size = 524288;
2857
2858         /*
2859          * Maximum segment size. Could be one segment with the maximum number
2860          * of bytes. When doing hardware scatter/gather, each entry cannot
2861          * be larger than 64 KiB though.
2862          */
2863         if (host->flags & SDHCI_USE_ADMA) {
2864                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2865                         mmc->max_seg_size = 65535;
2866                 else
2867                         mmc->max_seg_size = 65536;
2868         } else {
2869                 mmc->max_seg_size = mmc->max_req_size;
2870         }
2871
2872         /*
2873          * Maximum block size. This varies from controller to controller and
2874          * is specified in the capabilities register.
2875          */
2876         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2877                 mmc->max_blk_size = 2;
2878         } else {
2879                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2880                                 SDHCI_MAX_BLOCK_SHIFT;
2881                 if (mmc->max_blk_size >= 3) {
2882                         pr_warning("%s: Invalid maximum block size, "
2883                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2884                         mmc->max_blk_size = 0;
2885                 }
2886         }
2887
2888         mmc->max_blk_size = 512 << mmc->max_blk_size;
2889
2890         /*
2891          * Maximum block count.
2892          */
2893         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2894
2895         /*
2896          * Init tasklets.
2897          */
2898         tasklet_init(&host->card_tasklet,
2899                 sdhci_tasklet_card, (unsigned long)host);
2900         tasklet_init(&host->finish_tasklet,
2901                 sdhci_tasklet_finish, (unsigned long)host);
2902
2903         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2904
2905         if (host->version >= SDHCI_SPEC_300) {
2906                 init_waitqueue_head(&host->buf_ready_int);
2907
2908                 /* Initialize re-tuning timer */
2909                 init_timer(&host->tuning_timer);
2910                 host->tuning_timer.data = (unsigned long)host;
2911                 host->tuning_timer.function = sdhci_tuning_timer;
2912         }
2913
2914         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2915                 mmc_hostname(mmc), host);
2916         if (ret)
2917                 goto untasklet;
2918
2919         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2920         if (IS_ERR(host->vmmc)) {
2921                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2922                 host->vmmc = NULL;
2923         } else {
2924                 regulator_enable(host->vmmc);
2925         }
2926
2927         sdhci_init(host, 0);
2928
2929 #ifdef CONFIG_MMC_DEBUG
2930         sdhci_dumpregs(host);
2931 #endif
2932
2933 #ifdef SDHCI_USE_LEDS_CLASS
2934         snprintf(host->led_name, sizeof(host->led_name),
2935                 "%s::", mmc_hostname(mmc));
2936         host->led.name = host->led_name;
2937         host->led.brightness = LED_OFF;
2938         host->led.default_trigger = mmc_hostname(mmc);
2939         host->led.brightness_set = sdhci_led_control;
2940
2941         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2942         if (ret)
2943                 goto reset;
2944 #endif
2945
2946         mmiowb();
2947
2948         mmc_add_host(mmc);
2949
2950         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2951                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2952                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2953                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2954
2955         sdhci_enable_card_detection(host);
2956
2957         return 0;
2958
2959 #ifdef SDHCI_USE_LEDS_CLASS
2960 reset:
2961         sdhci_reset(host, SDHCI_RESET_ALL);
2962         free_irq(host->irq, host);
2963 #endif
2964 untasklet:
2965         tasklet_kill(&host->card_tasklet);
2966         tasklet_kill(&host->finish_tasklet);
2967
2968         return ret;
2969 }
2970
2971 EXPORT_SYMBOL_GPL(sdhci_add_host);
2972
2973 void sdhci_remove_host(struct sdhci_host *host, int dead)
2974 {
2975         unsigned long flags;
2976
2977         if (dead) {
2978                 spin_lock_irqsave(&host->lock, flags);
2979
2980                 host->flags |= SDHCI_DEVICE_DEAD;
2981
2982                 if (host->mrq) {
2983                         pr_err("%s: Controller removed during "
2984                                 " transfer!\n", mmc_hostname(host->mmc));
2985
2986                         host->mrq->cmd->error = -ENOMEDIUM;
2987                         tasklet_schedule(&host->finish_tasklet);
2988                 }
2989
2990                 spin_unlock_irqrestore(&host->lock, flags);
2991         }
2992
2993         sdhci_disable_card_detection(host);
2994
2995         mmc_remove_host(host->mmc);
2996
2997 #ifdef SDHCI_USE_LEDS_CLASS
2998         led_classdev_unregister(&host->led);
2999 #endif
3000
3001         if (!dead)
3002                 sdhci_reset(host, SDHCI_RESET_ALL);
3003
3004         free_irq(host->irq, host);
3005
3006         del_timer_sync(&host->timer);
3007         if (host->version >= SDHCI_SPEC_300)
3008                 del_timer_sync(&host->tuning_timer);
3009
3010         tasklet_kill(&host->card_tasklet);
3011         tasklet_kill(&host->finish_tasklet);
3012
3013         if (host->vmmc) {
3014                 regulator_disable(host->vmmc);
3015                 regulator_put(host->vmmc);
3016         }
3017
3018         kfree(host->adma_desc);
3019         kfree(host->align_buffer);
3020
3021         host->adma_desc = NULL;
3022         host->align_buffer = NULL;
3023 }
3024
3025 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3026
3027 void sdhci_free_host(struct sdhci_host *host)
3028 {
3029         mmc_free_host(host->mmc);
3030 }
3031
3032 EXPORT_SYMBOL_GPL(sdhci_free_host);
3033
3034 /*****************************************************************************\
3035  *                                                                           *
3036  * Driver init/exit                                                          *
3037  *                                                                           *
3038 \*****************************************************************************/
3039
3040 static int __init sdhci_drv_init(void)
3041 {
3042         pr_info(DRIVER_NAME
3043                 ": Secure Digital Host Controller Interface driver\n");
3044         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3045
3046         return 0;
3047 }
3048
3049 static void __exit sdhci_drv_exit(void)
3050 {
3051 }
3052
3053 module_init(sdhci_drv_init);
3054 module_exit(sdhci_drv_exit);
3055
3056 module_param(debug_quirks, uint, 0444);
3057 module_param(debug_quirks2, uint, 0444);
3058
3059 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3060 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3061 MODULE_LICENSE("GPL");
3062
3063 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3064 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");