drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30
  31 #include "sdhci.h"
  32
  33 #define DRIVER_NAME "sdhci"
  34
  35 #define DBG(f, x...) \
  36         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  37
  38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  39         defined(CONFIG_MMC_SDHCI_MODULE))
  40 #define SDHCI_USE_LEDS_CLASS
  41 #endif
  42
  43 #define MAX_TUNING_LOOP 40
  44
  45 static unsigned int debug_quirks = 0;
  46 static unsigned int debug_quirks2;
  47
  48 static void sdhci_finish_data(struct sdhci_host *);
  49
  50 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  51 static void sdhci_finish_command(struct sdhci_host *);
  52 static int sdhci_execute_tuning(struct mmc_host *mmc);
  53 static void sdhci_tuning_timer(unsigned long data);
  54
  55 #ifdef CONFIG_PM_RUNTIME
  56 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  57 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  58 #else
  59 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  60 {
  61         return 0;
  62 }
  63 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 #endif
  68
  69 static void sdhci_dumpregs(struct sdhci_host *host)
  70 {
  71         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  72                 mmc_hostname(host->mmc));
  73
  74         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  75                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  76                 sdhci_readw(host, SDHCI_HOST_VERSION));
  77         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  78                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  79                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  80         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  81                 sdhci_readl(host, SDHCI_ARGUMENT),
  82                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  83         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  84                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  85                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  86         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  87                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  88                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  89         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  90                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  91                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  92         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  93                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  94                 sdhci_readl(host, SDHCI_INT_STATUS));
  95         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_INT_ENABLE),
  97                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  98         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  99                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 100                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 101         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 102                 sdhci_readl(host, SDHCI_CAPABILITIES),
 103                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 104         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 105                 sdhci_readw(host, SDHCI_COMMAND),
 106                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 107         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 108                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 109
 110         if (host->flags & SDHCI_USE_ADMA)
 111                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 112                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 113                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 114
 115         pr_debug(DRIVER_NAME ": ===========================================\n");
 116 }
 117
 118 /*****************************************************************************\
 119  *                                                                           *
 120  * Low level functions                                                       *
 121  *                                                                           *
 122 \*****************************************************************************/
 123
 124 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 125 {
 126         u32 ier;
 127
 128         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 129         ier &= ~clear;
 130         ier |= set;
 131         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 132         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 133 }
 134
 135 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 136 {
 137         sdhci_clear_set_irqs(host, 0, irqs);
 138 }
 139
 140 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 141 {
 142         sdhci_clear_set_irqs(host, irqs, 0);
 143 }
 144
 145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 146 {
 147         u32 present, irqs;
 148
 149         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 150                 return;
 151
 152         if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
 153                 return;
 154
 155         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 156                               SDHCI_CARD_PRESENT;
 157         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 158
 159         if (enable)
 160                 sdhci_unmask_irqs(host, irqs);
 161         else
 162                 sdhci_mask_irqs(host, irqs);
 163 }
 164
 165 static void sdhci_enable_card_detection(struct sdhci_host *host)
 166 {
 167         sdhci_set_card_detection(host, true);
 168 }
 169
 170 static void sdhci_disable_card_detection(struct sdhci_host *host)
 171 {
 172         sdhci_set_card_detection(host, false);
 173 }
 174
 175 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 176 {
 177         unsigned long timeout;
 178         u32 uninitialized_var(ier);
 179
 180         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 181                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 182                         SDHCI_CARD_PRESENT))
 183                         return;
 184         }
 185
 186         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 187                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 188
 189         if (host->ops->platform_reset_enter)
 190                 host->ops->platform_reset_enter(host, mask);
 191
 192         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 193
 194         if (mask & SDHCI_RESET_ALL)
 195                 host->clock = 0;
 196
 197         /* Wait max 100 ms */
 198         timeout = 100;
 199
 200         /* hw clears the bit when it's done */
 201         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 202                 if (timeout == 0) {
 203                         pr_err("%s: Reset 0x%x never completed.\n",
 204                                 mmc_hostname(host->mmc), (int)mask);
 205                         sdhci_dumpregs(host);
 206                         return;
 207                 }
 208                 timeout--;
 209                 mdelay(1);
 210         }
 211
 212         if (host->ops->platform_reset_exit)
 213                 host->ops->platform_reset_exit(host, mask);
 214
 215         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 216                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 217 }
 218
 219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 220
 221 static void sdhci_init(struct sdhci_host *host, int soft)
 222 {
 223         if (soft)
 224                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 225         else
 226                 sdhci_reset(host, SDHCI_RESET_ALL);
 227
 228         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 229                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 230                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 231                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 232                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 233
 234         if (soft) {
 235                 /* force clock reconfiguration */
 236                 host->clock = 0;
 237                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 238         }
 239 }
 240
 241 static void sdhci_reinit(struct sdhci_host *host)
 242 {
 243         sdhci_init(host, 0);
 244         sdhci_enable_card_detection(host);
 245 }
 246
 247 static void sdhci_activate_led(struct sdhci_host *host)
 248 {
 249         u8 ctrl;
 250
 251         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 252         ctrl |= SDHCI_CTRL_LED;
 253         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 254 }
 255
 256 static void sdhci_deactivate_led(struct sdhci_host *host)
 257 {
 258         u8 ctrl;
 259
 260         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 261         ctrl &= ~SDHCI_CTRL_LED;
 262         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 263 }
 264
 265 #ifdef SDHCI_USE_LEDS_CLASS
 266 static void sdhci_led_control(struct led_classdev *led,
 267         enum led_brightness brightness)
 268 {
 269         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 270         unsigned long flags;
 271
 272         spin_lock_irqsave(&host->lock, flags);
 273
 274         if (host->runtime_suspended)
 275                 goto out;
 276
 277         if (brightness == LED_OFF)
 278                 sdhci_deactivate_led(host);
 279         else
 280                 sdhci_activate_led(host);
 281 out:
 282         spin_unlock_irqrestore(&host->lock, flags);
 283 }
 284 #endif
 285
 286 /*****************************************************************************\
 287  *                                                                           *
 288  * Core functions                                                            *
 289  *                                                                           *
 290 \*****************************************************************************/
 291
 292 static void sdhci_read_block_pio(struct sdhci_host *host)
 293 {
 294         unsigned long flags;
 295         size_t blksize, len, chunk;
 296         u32 uninitialized_var(scratch);
 297         u8 *buf;
 298
 299         DBG("PIO reading\n");
 300
 301         blksize = host->data->blksz;
 302         chunk = 0;
 303
 304         local_irq_save(flags);
 305
 306         while (blksize) {
 307                 if (!sg_miter_next(&host->sg_miter))
 308                         BUG();
 309
 310                 len = min(host->sg_miter.length, blksize);
 311
 312                 blksize -= len;
 313                 host->sg_miter.consumed = len;
 314
 315                 buf = host->sg_miter.addr;
 316
 317                 while (len) {
 318                         if (chunk == 0) {
 319                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 320                                 chunk = 4;
 321                         }
 322
 323                         *buf = scratch & 0xFF;
 324
 325                         buf++;
 326                         scratch >>= 8;
 327                         chunk--;
 328                         len--;
 329                 }
 330         }
 331
 332         sg_miter_stop(&host->sg_miter);
 333
 334         local_irq_restore(flags);
 335 }
 336
 337 static void sdhci_write_block_pio(struct sdhci_host *host)
 338 {
 339         unsigned long flags;
 340         size_t blksize, len, chunk;
 341         u32 scratch;
 342         u8 *buf;
 343
 344         DBG("PIO writing\n");
 345
 346         blksize = host->data->blksz;
 347         chunk = 0;
 348         scratch = 0;
 349
 350         local_irq_save(flags);
 351
 352         while (blksize) {
 353                 if (!sg_miter_next(&host->sg_miter))
 354                         BUG();
 355
 356                 len = min(host->sg_miter.length, blksize);
 357
 358                 blksize -= len;
 359                 host->sg_miter.consumed = len;
 360
 361                 buf = host->sg_miter.addr;
 362
 363                 while (len) {
 364                         scratch |= (u32)*buf << (chunk * 8);
 365
 366                         buf++;
 367                         chunk++;
 368                         len--;
 369
 370                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 371                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 372                                 chunk = 0;
 373                                 scratch = 0;
 374                         }
 375                 }
 376         }
 377
 378         sg_miter_stop(&host->sg_miter);
 379
 380         local_irq_restore(flags);
 381 }
 382
 383 static void sdhci_transfer_pio(struct sdhci_host *host)
 384 {
 385         u32 mask;
 386
 387         BUG_ON(!host->data);
 388
 389         if (host->blocks == 0)
 390                 return;
 391
 392         if (host->data->flags & MMC_DATA_READ)
 393                 mask = SDHCI_DATA_AVAILABLE;
 394         else
 395                 mask = SDHCI_SPACE_AVAILABLE;
 396
 397         /*
 398          * Some controllers (JMicron JMB38x) mess up the buffer bits
 399          * for transfers < 4 bytes. As long as it is just one block,
 400          * we can ignore the bits.
 401          */
 402         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 403                 (host->data->blocks == 1))
 404                 mask = ~0;
 405
 406         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 407                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 408                         udelay(100);
 409
 410                 if (host->data->flags & MMC_DATA_READ)
 411                         sdhci_read_block_pio(host);
 412                 else
 413                         sdhci_write_block_pio(host);
 414
 415                 host->blocks--;
 416                 if (host->blocks == 0)
 417                         break;
 418         }
 419
 420         DBG("PIO transfer complete.\n");
 421 }
 422
 423 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 424 {
 425         local_irq_save(*flags);
 426         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 427 }
 428
 429 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 430 {
 431         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 432         local_irq_restore(*flags);
 433 }
 434
 435 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 436 {
 437         __le32 *dataddr = (__le32 __force *)(desc + 4);
 438         __le16 *cmdlen = (__le16 __force *)desc;
 439
 440         /* SDHCI specification says ADMA descriptors should be 4 byte
 441          * aligned, so using 16 or 32bit operations should be safe. */
 442
 443         cmdlen[0] = cpu_to_le16(cmd);
 444         cmdlen[1] = cpu_to_le16(len);
 445
 446         dataddr[0] = cpu_to_le32(addr);
 447 }
 448
 449 static int sdhci_adma_table_pre(struct sdhci_host *host,
 450         struct mmc_data *data)
 451 {
 452         int direction;
 453
 454         u8 *desc;
 455         u8 *align;
 456         dma_addr_t addr;
 457         dma_addr_t align_addr;
 458         int len, offset;
 459
 460         struct scatterlist *sg;
 461         int i;
 462         char *buffer;
 463         unsigned long flags;
 464
 465         /*
 466          * The spec does not specify endianness of descriptor table.
 467          * We currently guess that it is LE.
 468          */
 469
 470         if (data->flags & MMC_DATA_READ)
 471                 direction = DMA_FROM_DEVICE;
 472         else
 473                 direction = DMA_TO_DEVICE;
 474
 475         /*
 476          * The ADMA descriptor table is mapped further down as we
 477          * need to fill it with data first.
 478          */
 479
 480         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 481                 host->align_buffer, 128 * 4, direction);
 482         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 483                 goto fail;
 484         BUG_ON(host->align_addr & 0x3);
 485
 486         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 487                 data->sg, data->sg_len, direction);
 488         if (host->sg_count == 0)
 489                 goto unmap_align;
 490
 491         desc = host->adma_desc;
 492         align = host->align_buffer;
 493
 494         align_addr = host->align_addr;
 495
 496         for_each_sg(data->sg, sg, host->sg_count, i) {
 497                 addr = sg_dma_address(sg);
 498                 len = sg_dma_len(sg);
 499
 500                 /*
 501                  * The SDHCI specification states that ADMA
 502                  * addresses must be 32-bit aligned. If they
 503                  * aren't, then we use a bounce buffer for
 504                  * the (up to three) bytes that screw up the
 505                  * alignment.
 506                  */
 507                 offset = (4 - (addr & 0x3)) & 0x3;
 508                 if (offset) {
 509                         if (data->flags & MMC_DATA_WRITE) {
 510                                 buffer = sdhci_kmap_atomic(sg, &flags);
 511                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 512                                 memcpy(align, buffer, offset);
 513                                 sdhci_kunmap_atomic(buffer, &flags);
 514                         }
 515
 516                         /* tran, valid */
 517                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 518
 519                         BUG_ON(offset > 65536);
 520
 521                         align += 4;
 522                         align_addr += 4;
 523
 524                         desc += 8;
 525
 526                         addr += offset;
 527                         len -= offset;
 528                 }
 529
 530                 BUG_ON(len > 65536);
 531
 532                 /* tran, valid */
 533                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 534                 desc += 8;
 535
 536                 /*
 537                  * If this triggers then we have a calculation bug
 538                  * somewhere. :/
 539                  */
 540                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 541         }
 542
 543         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 544                 /*
 545                 * Mark the last descriptor as the terminating descriptor
 546                 */
 547                 if (desc != host->adma_desc) {
 548                         desc -= 8;
 549                         desc[0] |= 0x2; /* end */
 550                 }
 551         } else {
 552                 /*
 553                 * Add a terminating entry.
 554                 */
 555
 556                 /* nop, end, valid */
 557                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 558         }
 559
 560         /*
 561          * Resync align buffer as we might have changed it.
 562          */
 563         if (data->flags & MMC_DATA_WRITE) {
 564                 dma_sync_single_for_device(mmc_dev(host->mmc),
 565                         host->align_addr, 128 * 4, direction);
 566         }
 567
 568         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 569                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 570         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 571                 goto unmap_entries;
 572         BUG_ON(host->adma_addr & 0x3);
 573
 574         return 0;
 575
 576 unmap_entries:
 577         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 578                 data->sg_len, direction);
 579 unmap_align:
 580         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 581                 128 * 4, direction);
 582 fail:
 583         return -EINVAL;
 584 }
 585
 586 static void sdhci_adma_table_post(struct sdhci_host *host,
 587         struct mmc_data *data)
 588 {
 589         int direction;
 590
 591         struct scatterlist *sg;
 592         int i, size;
 593         u8 *align;
 594         char *buffer;
 595         unsigned long flags;
 596
 597         if (data->flags & MMC_DATA_READ)
 598                 direction = DMA_FROM_DEVICE;
 599         else
 600                 direction = DMA_TO_DEVICE;
 601
 602         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 603                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 604
 605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 606                 128 * 4, direction);
 607
 608         if (data->flags & MMC_DATA_READ) {
 609                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 610                         data->sg_len, direction);
 611
 612                 align = host->align_buffer;
 613
 614                 for_each_sg(data->sg, sg, host->sg_count, i) {
 615                         if (sg_dma_address(sg) & 0x3) {
 616                                 size = 4 - (sg_dma_address(sg) & 0x3);
 617
 618                                 buffer = sdhci_kmap_atomic(sg, &flags);
 619                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 620                                 memcpy(buffer, align, size);
 621                                 sdhci_kunmap_atomic(buffer, &flags);
 622
 623                                 align += 4;
 624                         }
 625                 }
 626         }
 627
 628         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 629                 data->sg_len, direction);
 630 }
 631
 632 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 633 {
 634         u8 count;
 635         struct mmc_data *data = cmd->data;
 636         unsigned target_timeout, current_timeout;
 637
 638         /*
 639          * If the host controller provides us with an incorrect timeout
 640          * value, just skip the check and use 0xE.  The hardware may take
 641          * longer to time out, but that's much better than having a too-short
 642          * timeout value.
 643          */
 644         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 645                 return 0xE;
 646
 647         /* Unspecified timeout, assume max */
 648         if (!data && !cmd->cmd_timeout_ms)
 649                 return 0xE;
 650
 651         /* timeout in us */
 652         if (!data)
 653                 target_timeout = cmd->cmd_timeout_ms * 1000;
 654         else {
 655                 target_timeout = data->timeout_ns / 1000;
 656                 if (host->clock)
 657                         target_timeout += data->timeout_clks / host->clock;
 658         }
 659
 660         /*
 661          * Figure out needed cycles.
 662          * We do this in steps in order to fit inside a 32 bit int.
 663          * The first step is the minimum timeout, which will have a
 664          * minimum resolution of 6 bits:
 665          * (1) 2^13*1000 > 2^22,
 666          * (2) host->timeout_clk < 2^16
 667          *     =>
 668          *     (1) / (2) > 2^6
 669          */
 670         count = 0;
 671         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 672         while (current_timeout < target_timeout) {
 673                 count++;
 674                 current_timeout <<= 1;
 675                 if (count >= 0xF)
 676                         break;
 677         }
 678
 679         if (count >= 0xF) {
 680                 pr_warning("%s: Too large timeout requested for CMD%d!\n",
 681                        mmc_hostname(host->mmc), cmd->opcode);
 682                 count = 0xE;
 683         }
 684
 685         return count;
 686 }
 687
 688 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 689 {
 690         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 691         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 692
 693         if (host->flags & SDHCI_REQ_USE_DMA)
 694                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 695         else
 696                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 697 }
 698
 699 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 700 {
 701         u8 count;
 702         u8 ctrl;
 703         struct mmc_data *data = cmd->data;
 704         int ret;
 705
 706         WARN_ON(host->data);
 707
 708         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 709                 count = sdhci_calc_timeout(host, cmd);
 710                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 711         }
 712
 713         if (!data)
 714                 return;
 715
 716         /* Sanity checks */
 717         BUG_ON(data->blksz * data->blocks > 524288);
 718         BUG_ON(data->blksz > host->mmc->max_blk_size);
 719         BUG_ON(data->blocks > 65535);
 720
 721         host->data = data;
 722         host->data_early = 0;
 723         host->data->bytes_xfered = 0;
 724
 725         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 726                 host->flags |= SDHCI_REQ_USE_DMA;
 727
 728         /*
 729          * FIXME: This doesn't account for merging when mapping the
 730          * scatterlist.
 731          */
 732         if (host->flags & SDHCI_REQ_USE_DMA) {
 733                 int broken, i;
 734                 struct scatterlist *sg;
 735
 736                 broken = 0;
 737                 if (host->flags & SDHCI_USE_ADMA) {
 738                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 739                                 broken = 1;
 740                 } else {
 741                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 742                                 broken = 1;
 743                 }
 744
 745                 if (unlikely(broken)) {
 746                         for_each_sg(data->sg, sg, data->sg_len, i) {
 747                                 if (sg->length & 0x3) {
 748                                         DBG("Reverting to PIO because of "
 749                                                 "transfer size (%d)\n",
 750                                                 sg->length);
 751                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 752                                         break;
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         /*
 759          * The assumption here being that alignment is the same after
 760          * translation to device address space.
 761          */
 762         if (host->flags & SDHCI_REQ_USE_DMA) {
 763                 int broken, i;
 764                 struct scatterlist *sg;
 765
 766                 broken = 0;
 767                 if (host->flags & SDHCI_USE_ADMA) {
 768                         /*
 769                          * As we use 3 byte chunks to work around
 770                          * alignment problems, we need to check this
 771                          * quirk.
 772                          */
 773                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 774                                 broken = 1;
 775                 } else {
 776                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 777                                 broken = 1;
 778                 }
 779
 780                 if (unlikely(broken)) {
 781                         for_each_sg(data->sg, sg, data->sg_len, i) {
 782                                 if (sg->offset & 0x3) {
 783                                         DBG("Reverting to PIO because of "
 784                                                 "bad alignment\n");
 785                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 786                                         break;
 787                                 }
 788                         }
 789                 }
 790         }
 791
 792         if (host->flags & SDHCI_REQ_USE_DMA) {
 793                 if (host->flags & SDHCI_USE_ADMA) {
 794                         ret = sdhci_adma_table_pre(host, data);
 795                         if (ret) {
 796                                 /*
 797                                  * This only happens when someone fed
 798                                  * us an invalid request.
 799                                  */
 800                                 WARN_ON(1);
 801                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 802                         } else {
 803                                 sdhci_writel(host, host->adma_addr,
 804                                         SDHCI_ADMA_ADDRESS);
 805                         }
 806                 } else {
 807                         int sg_cnt;
 808
 809                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 810                                         data->sg, data->sg_len,
 811                                         (data->flags & MMC_DATA_READ) ?
 812                                                 DMA_FROM_DEVICE :
 813                                                 DMA_TO_DEVICE);
 814                         if (sg_cnt == 0) {
 815                                 /*
 816                                  * This only happens when someone fed
 817                                  * us an invalid request.
 818                                  */
 819                                 WARN_ON(1);
 820                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 821                         } else {
 822                                 WARN_ON(sg_cnt != 1);
 823                                 sdhci_writel(host, sg_dma_address(data->sg),
 824                                         SDHCI_DMA_ADDRESS);
 825                         }
 826                 }
 827         }
 828
 829         /*
 830          * Always adjust the DMA selection as some controllers
 831          * (e.g. JMicron) can't do PIO properly when the selection
 832          * is ADMA.
 833          */
 834         if (host->version >= SDHCI_SPEC_200) {
 835                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 836                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 837                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 838                         (host->flags & SDHCI_USE_ADMA))
 839                         ctrl |= SDHCI_CTRL_ADMA32;
 840                 else
 841                         ctrl |= SDHCI_CTRL_SDMA;
 842                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 843         }
 844
 845         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 846                 int flags;
 847
 848                 flags = SG_MITER_ATOMIC;
 849                 if (host->data->flags & MMC_DATA_READ)
 850                         flags |= SG_MITER_TO_SG;
 851                 else
 852                         flags |= SG_MITER_FROM_SG;
 853                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 854                 host->blocks = data->blocks;
 855         }
 856
 857         sdhci_set_transfer_irqs(host);
 858
 859         /* Set the DMA boundary value and block size */
 860         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 861                 data->blksz), SDHCI_BLOCK_SIZE);
 862         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 863 }
 864
 865 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 866         struct mmc_command *cmd)
 867 {
 868         u16 mode;
 869         struct mmc_data *data = cmd->data;
 870
 871         if (data == NULL)
 872                 return;
 873
 874         WARN_ON(!host->data);
 875
 876         mode = SDHCI_TRNS_BLK_CNT_EN;
 877         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 878                 mode |= SDHCI_TRNS_MULTI;
 879                 /*
 880                  * If we are sending CMD23, CMD12 never gets sent
 881                  * on successful completion (so no Auto-CMD12).
 882                  */
 883                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 884                         mode |= SDHCI_TRNS_AUTO_CMD12;
 885                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 886                         mode |= SDHCI_TRNS_AUTO_CMD23;
 887                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 888                 }
 889         }
 890
 891         if (data->flags & MMC_DATA_READ)
 892                 mode |= SDHCI_TRNS_READ;
 893         if (host->flags & SDHCI_REQ_USE_DMA)
 894                 mode |= SDHCI_TRNS_DMA;
 895
 896         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 897 }
 898
 899 static void sdhci_finish_data(struct sdhci_host *host)
 900 {
 901         struct mmc_data *data;
 902
 903         BUG_ON(!host->data);
 904
 905         data = host->data;
 906         host->data = NULL;
 907
 908         if (host->flags & SDHCI_REQ_USE_DMA) {
 909                 if (host->flags & SDHCI_USE_ADMA)
 910                         sdhci_adma_table_post(host, data);
 911                 else {
 912                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 913                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 914                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 915                 }
 916         }
 917
 918         /*
 919          * The specification states that the block count register must
 920          * be updated, but it does not specify at what point in the
 921          * data flow. That makes the register entirely useless to read
 922          * back so we have to assume that nothing made it to the card
 923          * in the event of an error.
 924          */
 925         if (data->error)
 926                 data->bytes_xfered = 0;
 927         else
 928                 data->bytes_xfered = data->blksz * data->blocks;
 929
 930         /*
 931          * Need to send CMD12 if -
 932          * a) open-ended multiblock transfer (no CMD23)
 933          * b) error in multiblock transfer
 934          */
 935         if (data->stop &&
 936             (data->error ||
 937              !host->mrq->sbc)) {
 938
 939                 /*
 940                  * The controller needs a reset of internal state machines
 941                  * upon error conditions.
 942                  */
 943                 if (data->error) {
 944                         sdhci_reset(host, SDHCI_RESET_CMD);
 945                         sdhci_reset(host, SDHCI_RESET_DATA);
 946                 }
 947
 948                 sdhci_send_command(host, data->stop);
 949         } else
 950                 tasklet_schedule(&host->finish_tasklet);
 951 }
 952
 953 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 954 {
 955         int flags;
 956         u32 mask;
 957         unsigned long timeout;
 958
 959         WARN_ON(host->cmd);
 960
 961         /* Wait max 10 ms */
 962         timeout = 10;
 963
 964         mask = SDHCI_CMD_INHIBIT;
 965         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 966                 mask |= SDHCI_DATA_INHIBIT;
 967
 968         /* We shouldn't wait for data inihibit for stop commands, even
 969            though they might use busy signaling */
 970         if (host->mrq->data && (cmd == host->mrq->data->stop))
 971                 mask &= ~SDHCI_DATA_INHIBIT;
 972
 973         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 974                 if (timeout == 0) {
 975                         pr_err("%s: Controller never released "
 976                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 977                         sdhci_dumpregs(host);
 978                         cmd->error = -EIO;
 979                         tasklet_schedule(&host->finish_tasklet);
 980                         return;
 981                 }
 982                 timeout--;
 983                 mdelay(1);
 984         }
 985
 986         mod_timer(&host->timer, jiffies + 10 * HZ);
 987
 988         host->cmd = cmd;
 989
 990         sdhci_prepare_data(host, cmd);
 991
 992         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 993
 994         sdhci_set_transfer_mode(host, cmd);
 995
 996         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 997                 pr_err("%s: Unsupported response type!\n",
 998                         mmc_hostname(host->mmc));
 999                 cmd->error = -EINVAL;
1000                 tasklet_schedule(&host->finish_tasklet);
1001                 return;
1002         }
1003
1004         if (!(cmd->flags & MMC_RSP_PRESENT))
1005                 flags = SDHCI_CMD_RESP_NONE;
1006         else if (cmd->flags & MMC_RSP_136)
1007                 flags = SDHCI_CMD_RESP_LONG;
1008         else if (cmd->flags & MMC_RSP_BUSY)
1009                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1010         else
1011                 flags = SDHCI_CMD_RESP_SHORT;
1012
1013         if (cmd->flags & MMC_RSP_CRC)
1014                 flags |= SDHCI_CMD_CRC;
1015         if (cmd->flags & MMC_RSP_OPCODE)
1016                 flags |= SDHCI_CMD_INDEX;
1017
1018         /* CMD19 is special in that the Data Present Select should be set */
1019         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
1020                 flags |= SDHCI_CMD_DATA;
1021
1022         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1023 }
1024
1025 static void sdhci_finish_command(struct sdhci_host *host)
1026 {
1027         int i;
1028
1029         BUG_ON(host->cmd == NULL);
1030
1031         if (host->cmd->flags & MMC_RSP_PRESENT) {
1032                 if (host->cmd->flags & MMC_RSP_136) {
1033                         /* CRC is stripped so we need to do some shifting. */
1034                         for (i = 0;i < 4;i++) {
1035                                 host->cmd->resp[i] = sdhci_readl(host,
1036                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1037                                 if (i != 3)
1038                                         host->cmd->resp[i] |=
1039                                                 sdhci_readb(host,
1040                                                 SDHCI_RESPONSE + (3-i)*4-1);
1041                         }
1042                 } else {
1043                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1044                 }
1045         }
1046
1047         host->cmd->error = 0;
1048
1049         /* Finished CMD23, now send actual command. */
1050         if (host->cmd == host->mrq->sbc) {
1051                 host->cmd = NULL;
1052                 sdhci_send_command(host, host->mrq->cmd);
1053         } else {
1054
1055                 /* Processed actual command. */
1056                 if (host->data && host->data_early)
1057                         sdhci_finish_data(host);
1058
1059                 if (!host->cmd->data)
1060                         tasklet_schedule(&host->finish_tasklet);
1061
1062                 host->cmd = NULL;
1063         }
1064 }
1065
1066 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1067 {
1068         int div = 0; /* Initialized for compiler warning */
1069         u16 clk = 0;
1070         unsigned long timeout;
1071
1072         if (clock == host->clock)
1073                 return;
1074
1075         if (host->ops->set_clock) {
1076                 host->ops->set_clock(host, clock);
1077                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1078                         return;
1079         }
1080
1081         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1082
1083         if (clock == 0)
1084                 goto out;
1085
1086         if (host->version >= SDHCI_SPEC_300) {
1087                 /*
1088                  * Check if the Host Controller supports Programmable Clock
1089                  * Mode.
1090                  */
1091                 if (host->clk_mul) {
1092                         u16 ctrl;
1093
1094                         /*
1095                          * We need to figure out whether the Host Driver needs
1096                          * to select Programmable Clock Mode, or the value can
1097                          * be set automatically by the Host Controller based on
1098                          * the Preset Value registers.
1099                          */
1100                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1101                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1102                                 for (div = 1; div <= 1024; div++) {
1103                                         if (((host->max_clk * host->clk_mul) /
1104                                               div) <= clock)
1105                                                 break;
1106                                 }
1107                                 /*
1108                                  * Set Programmable Clock Mode in the Clock
1109                                  * Control register.
1110                                  */
1111                                 clk = SDHCI_PROG_CLOCK_MODE;
1112                                 div--;
1113                         }
1114                 } else {
1115                         /* Version 3.00 divisors must be a multiple of 2. */
1116                         if (host->max_clk <= clock)
1117                                 div = 1;
1118                         else {
1119                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1120                                      div += 2) {
1121                                         if ((host->max_clk / div) <= clock)
1122                                                 break;
1123                                 }
1124                         }
1125                         div >>= 1;
1126                 }
1127         } else {
1128                 /* Version 2.00 divisors must be a power of 2. */
1129                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1130                         if ((host->max_clk / div) <= clock)
1131                                 break;
1132                 }
1133                 div >>= 1;
1134         }
1135
1136         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1137         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1138                 << SDHCI_DIVIDER_HI_SHIFT;
1139         clk |= SDHCI_CLOCK_INT_EN;
1140         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1141
1142         /* Wait max 20 ms */
1143         timeout = 20;
1144         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1145                 & SDHCI_CLOCK_INT_STABLE)) {
1146                 if (timeout == 0) {
1147                         pr_err("%s: Internal clock never "
1148                                 "stabilised.\n", mmc_hostname(host->mmc));
1149                         sdhci_dumpregs(host);
1150                         return;
1151                 }
1152                 timeout--;
1153                 spin_unlock_irq(&host->lock);
1154                 usleep_range(900, 1100);
1155                 spin_lock_irq(&host->lock);
1156         }
1157
1158         clk |= SDHCI_CLOCK_CARD_EN;
1159         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1160
1161 out:
1162         host->clock = clock;
1163 }
1164
1165 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1166 {
1167         u8 pwr = 0;
1168
1169         if (power != (unsigned short)-1) {
1170                 switch (1 << power) {
1171                 case MMC_VDD_165_195:
1172                         pwr = SDHCI_POWER_180;
1173                         break;
1174                 case MMC_VDD_29_30:
1175                 case MMC_VDD_30_31:
1176                         pwr = SDHCI_POWER_300;
1177                         break;
1178                 case MMC_VDD_32_33:
1179                 case MMC_VDD_33_34:
1180                         pwr = SDHCI_POWER_330;
1181                         break;
1182                 default:
1183                         BUG();
1184                 }
1185         }
1186
1187         if (host->pwr == pwr)
1188                 return;
1189
1190         host->pwr = pwr;
1191
1192         if (pwr == 0) {
1193                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1194                 return;
1195         }
1196
1197         /*
1198          * Spec says that we should clear the power reg before setting
1199          * a new value. Some controllers don't seem to like this though.
1200          */
1201         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1202                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1203
1204         /*
1205          * At least the Marvell CaFe chip gets confused if we set the voltage
1206          * and set turn on power at the same time, so set the voltage first.
1207          */
1208         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1209                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1210
1211         pwr |= SDHCI_POWER_ON;
1212
1213         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1214
1215         /*
1216          * Some controllers need an extra 10ms delay of 10ms before they
1217          * can apply clock after applying power
1218          */
1219         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1220                 mdelay(10);
1221 }
1222
1223 /*****************************************************************************\
1224  *                                                                           *
1225  * MMC callbacks                                                             *
1226  *                                                                           *
1227 \*****************************************************************************/
1228
1229 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1230 {
1231         struct sdhci_host *host;
1232         bool present;
1233         unsigned long flags;
1234
1235         host = mmc_priv(mmc);
1236
1237         sdhci_runtime_pm_get(host);
1238
1239         spin_lock_irqsave(&host->lock, flags);
1240
1241         WARN_ON(host->mrq != NULL);
1242
1243 #ifndef SDHCI_USE_LEDS_CLASS
1244         sdhci_activate_led(host);
1245 #endif
1246
1247         /*
1248          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1249          * requests if Auto-CMD12 is enabled.
1250          */
1251         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1252                 if (mrq->stop) {
1253                         mrq->data->stop = NULL;
1254                         mrq->stop = NULL;
1255                 }
1256         }
1257
1258         host->mrq = mrq;
1259
1260         /* If polling, assume that the card is always present. */
1261         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1262                 present = true;
1263         else
1264                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1265                                 SDHCI_CARD_PRESENT;
1266
1267         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1268                 host->mrq->cmd->error = -ENOMEDIUM;
1269                 tasklet_schedule(&host->finish_tasklet);
1270         } else {
1271                 u32 present_state;
1272
1273                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1274                 /*
1275                  * Check if the re-tuning timer has already expired and there
1276                  * is no on-going data transfer. If so, we need to execute
1277                  * tuning procedure before sending command.
1278                  */
1279                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1280                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1281                         spin_unlock_irqrestore(&host->lock, flags);
1282                         sdhci_execute_tuning(mmc);
1283                         spin_lock_irqsave(&host->lock, flags);
1284
1285                         /* Restore original mmc_request structure */
1286                         host->mrq = mrq;
1287                 }
1288
1289                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1290                         sdhci_send_command(host, mrq->sbc);
1291                 else
1292                         sdhci_send_command(host, mrq->cmd);
1293         }
1294
1295         mmiowb();
1296         spin_unlock_irqrestore(&host->lock, flags);
1297 }
1298
1299 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1300 {
1301         unsigned long flags;
1302         u8 ctrl;
1303
1304         spin_lock_irqsave(&host->lock, flags);
1305
1306         if (host->flags & SDHCI_DEVICE_DEAD)
1307                 goto out;
1308
1309         /*
1310          * Reset the chip on each power off.
1311          * Should clear out any weird states.
1312          */
1313         if (ios->power_mode == MMC_POWER_OFF) {
1314                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1315                 sdhci_reinit(host);
1316         }
1317
1318         sdhci_set_clock(host, ios->clock);
1319
1320         if (ios->power_mode == MMC_POWER_OFF)
1321                 sdhci_set_power(host, -1);
1322         else
1323                 sdhci_set_power(host, ios->vdd);
1324
1325         if (host->ops->platform_send_init_74_clocks)
1326                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1327
1328         /*
1329          * If your platform has 8-bit width support but is not a v3 controller,
1330          * or if it requires special setup code, you should implement that in
1331          * platform_8bit_width().
1332          */
1333         if (host->ops->platform_8bit_width)
1334                 host->ops->platform_8bit_width(host, ios->bus_width);
1335         else {
1336                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1337                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1338                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1339                         if (host->version >= SDHCI_SPEC_300)
1340                                 ctrl |= SDHCI_CTRL_8BITBUS;
1341                 } else {
1342                         if (host->version >= SDHCI_SPEC_300)
1343                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1344                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1345                                 ctrl |= SDHCI_CTRL_4BITBUS;
1346                         else
1347                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1348                 }
1349                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1350         }
1351
1352         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1353
1354         if ((ios->timing == MMC_TIMING_SD_HS ||
1355              ios->timing == MMC_TIMING_MMC_HS)
1356             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1357                 ctrl |= SDHCI_CTRL_HISPD;
1358         else
1359                 ctrl &= ~SDHCI_CTRL_HISPD;
1360
1361         if (host->version >= SDHCI_SPEC_300) {
1362                 u16 clk, ctrl_2;
1363                 unsigned int clock;
1364
1365                 /* In case of UHS-I modes, set High Speed Enable */
1366                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1367                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1368                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1369                     (ios->timing == MMC_TIMING_UHS_SDR25))
1370                         ctrl |= SDHCI_CTRL_HISPD;
1371
1372                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1373                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1374                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1375                         /*
1376                          * We only need to set Driver Strength if the
1377                          * preset value enable is not set.
1378                          */
1379                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1380                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1381                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1382                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1383                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1384
1385                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1386                 } else {
1387                         /*
1388                          * According to SDHC Spec v3.00, if the Preset Value
1389                          * Enable in the Host Control 2 register is set, we
1390                          * need to reset SD Clock Enable before changing High
1391                          * Speed Enable to avoid generating clock gliches.
1392                          */
1393
1394                         /* Reset SD Clock Enable */
1395                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1396                         clk &= ~SDHCI_CLOCK_CARD_EN;
1397                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1398
1399                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1400
1401                         /* Re-enable SD Clock */
1402                         clock = host->clock;
1403                         host->clock = 0;
1404                         sdhci_set_clock(host, clock);
1405                 }
1406
1407
1408                 /* Reset SD Clock Enable */
1409                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1410                 clk &= ~SDHCI_CLOCK_CARD_EN;
1411                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1412
1413                 if (host->ops->set_uhs_signaling)
1414                         host->ops->set_uhs_signaling(host, ios->timing);
1415                 else {
1416                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1417                         /* Select Bus Speed Mode for host */
1418                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1419                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1420                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1421                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1422                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1423                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1424                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1425                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1426                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1427                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1428                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1429                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1430                 }
1431
1432                 /* Re-enable SD Clock */
1433                 clock = host->clock;
1434                 host->clock = 0;
1435                 sdhci_set_clock(host, clock);
1436         } else
1437                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1438
1439         /*
1440          * Some (ENE) controllers go apeshit on some ios operation,
1441          * signalling timeout and CRC errors even on CMD0. Resetting
1442          * it on each ios seems to solve the problem.
1443          */
1444         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1445                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1446
1447 out:
1448         mmiowb();
1449         spin_unlock_irqrestore(&host->lock, flags);
1450 }
1451
1452 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1453 {
1454         struct sdhci_host *host = mmc_priv(mmc);
1455
1456         sdhci_runtime_pm_get(host);
1457         sdhci_do_set_ios(host, ios);
1458         sdhci_runtime_pm_put(host);
1459 }
1460
1461 static int sdhci_check_ro(struct sdhci_host *host)
1462 {
1463         unsigned long flags;
1464         int is_readonly;
1465
1466         spin_lock_irqsave(&host->lock, flags);
1467
1468         if (host->flags & SDHCI_DEVICE_DEAD)
1469                 is_readonly = 0;
1470         else if (host->ops->get_ro)
1471                 is_readonly = host->ops->get_ro(host);
1472         else
1473                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1474                                 & SDHCI_WRITE_PROTECT);
1475
1476         spin_unlock_irqrestore(&host->lock, flags);
1477
1478         /* This quirk needs to be replaced by a callback-function later */
1479         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1480                 !is_readonly : is_readonly;
1481 }
1482
1483 #define SAMPLE_COUNT    5
1484
1485 static int sdhci_do_get_ro(struct sdhci_host *host)
1486 {
1487         int i, ro_count;
1488
1489         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1490                 return sdhci_check_ro(host);
1491
1492         ro_count = 0;
1493         for (i = 0; i < SAMPLE_COUNT; i++) {
1494                 if (sdhci_check_ro(host)) {
1495                         if (++ro_count > SAMPLE_COUNT / 2)
1496                                 return 1;
1497                 }
1498                 msleep(30);
1499         }
1500         return 0;
1501 }
1502
1503 static void sdhci_hw_reset(struct mmc_host *mmc)
1504 {
1505         struct sdhci_host *host = mmc_priv(mmc);
1506
1507         if (host->ops && host->ops->hw_reset)
1508                 host->ops->hw_reset(host);
1509 }
1510
1511 static int sdhci_get_ro(struct mmc_host *mmc)
1512 {
1513         struct sdhci_host *host = mmc_priv(mmc);
1514         int ret;
1515
1516         sdhci_runtime_pm_get(host);
1517         ret = sdhci_do_get_ro(host);
1518         sdhci_runtime_pm_put(host);
1519         return ret;
1520 }
1521
1522 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1523 {
1524         if (host->flags & SDHCI_DEVICE_DEAD)
1525                 goto out;
1526
1527         if (enable)
1528                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1529         else
1530                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1531
1532         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1533         if (host->runtime_suspended)
1534                 goto out;
1535
1536         if (enable)
1537                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1538         else
1539                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1540 out:
1541         mmiowb();
1542 }
1543
1544 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1545 {
1546         struct sdhci_host *host = mmc_priv(mmc);
1547         unsigned long flags;
1548
1549         if (enable)
1550                 pm_runtime_get_noresume(host->mmc->parent);
1551
1552         spin_lock_irqsave(&host->lock, flags);
1553         sdhci_enable_sdio_irq_nolock(host, enable);
1554         spin_unlock_irqrestore(&host->lock, flags);
1555
1556         if (!enable)
1557                 pm_runtime_put_noidle(host->mmc->parent);
1558 }
1559
1560 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1561                                                 struct mmc_ios *ios)
1562 {
1563         u8 pwr;
1564         u16 clk, ctrl;
1565         u32 present_state;
1566
1567         /*
1568          * Signal Voltage Switching is only applicable for Host Controllers
1569          * v3.00 and above.
1570          */
1571         if (host->version < SDHCI_SPEC_300)
1572                 return 0;
1573
1574         /*
1575          * We first check whether the request is to set signalling voltage
1576          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1577          */
1578         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1579         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1580                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1581                 ctrl &= ~SDHCI_CTRL_VDD_180;
1582                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1583
1584                 /* Wait for 5ms */
1585                 usleep_range(5000, 5500);
1586
1587                 /* 3.3V regulator output should be stable within 5 ms */
1588                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1589                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1590                         return 0;
1591                 else {
1592                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1593                                 "signalling voltage failed\n");
1594                         return -EIO;
1595                 }
1596         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1597                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1598                 /* Stop SDCLK */
1599                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1600                 clk &= ~SDHCI_CLOCK_CARD_EN;
1601                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1602
1603                 /* Check whether DAT[3:0] is 0000 */
1604                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1605                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1606                        SDHCI_DATA_LVL_SHIFT)) {
1607                         /*
1608                          * Enable 1.8V Signal Enable in the Host Control2
1609                          * register
1610                          */
1611                         ctrl |= SDHCI_CTRL_VDD_180;
1612                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1613
1614                         /* Wait for 5ms */
1615                         usleep_range(5000, 5500);
1616
1617                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1618                         if (ctrl & SDHCI_CTRL_VDD_180) {
1619                                 /* Provide SDCLK again and wait for 1ms*/
1620                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1621                                 clk |= SDHCI_CLOCK_CARD_EN;
1622                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1623                                 usleep_range(1000, 1500);
1624
1625                                 /*
1626                                  * If DAT[3:0] level is 1111b, then the card
1627                                  * was successfully switched to 1.8V signaling.
1628                                  */
1629                                 present_state = sdhci_readl(host,
1630                                                         SDHCI_PRESENT_STATE);
1631                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1632                                      SDHCI_DATA_LVL_MASK)
1633                                         return 0;
1634                         }
1635                 }
1636
1637                 /*
1638                  * If we are here, that means the switch to 1.8V signaling
1639                  * failed. We power cycle the card, and retry initialization
1640                  * sequence by setting S18R to 0.
1641                  */
1642                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1643                 pwr &= ~SDHCI_POWER_ON;
1644                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1645
1646                 /* Wait for 1ms as per the spec */
1647                 usleep_range(1000, 1500);
1648                 pwr |= SDHCI_POWER_ON;
1649                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1650
1651                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1652                         "voltage failed, retrying with S18R set to 0\n");
1653                 return -EAGAIN;
1654         } else
1655                 /* No signal voltage switch required */
1656                 return 0;
1657 }
1658
1659 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1660         struct mmc_ios *ios)
1661 {
1662         struct sdhci_host *host = mmc_priv(mmc);
1663         int err;
1664
1665         if (host->version < SDHCI_SPEC_300)
1666                 return 0;
1667         sdhci_runtime_pm_get(host);
1668         err = sdhci_do_start_signal_voltage_switch(host, ios);
1669         sdhci_runtime_pm_put(host);
1670         return err;
1671 }
1672
1673 static int sdhci_execute_tuning(struct mmc_host *mmc)
1674 {
1675         struct sdhci_host *host;
1676         u16 ctrl;
1677         u32 ier;
1678         int tuning_loop_counter = MAX_TUNING_LOOP;
1679         unsigned long timeout;
1680         int err = 0;
1681         unsigned long flags;
1682
1683         host = mmc_priv(mmc);
1684
1685         sdhci_runtime_pm_get(host);
1686         spin_lock_irqsave(&host->lock, flags);
1687
1688         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1689
1690         /*
1691          * Host Controller needs tuning only in case of SDR104 mode
1692          * and for SDR50 mode when Use Tuning for SDR50 is set in
1693          * Capabilities register.
1694          */
1695         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1696             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1697             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1698                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1699         else {
1700                 spin_unlock_irqrestore(&host->lock, flags);
1701                 sdhci_runtime_pm_put(host);
1702                 return 0;
1703         }
1704
1705         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1706
1707         /*
1708          * As per the Host Controller spec v3.00, tuning command
1709          * generates Buffer Read Ready interrupt, so enable that.
1710          *
1711          * Note: The spec clearly says that when tuning sequence
1712          * is being performed, the controller does not generate
1713          * interrupts other than Buffer Read Ready interrupt. But
1714          * to make sure we don't hit a controller bug, we _only_
1715          * enable Buffer Read Ready interrupt here.
1716          */
1717         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1718         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1719
1720         /*
1721          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1722          * of loops reaches 40 times or a timeout of 150ms occurs.
1723          */
1724         timeout = 150;
1725         do {
1726                 struct mmc_command cmd = {0};
1727                 struct mmc_request mrq = {NULL};
1728
1729                 if (!tuning_loop_counter && !timeout)
1730                         break;
1731
1732                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1733                 cmd.arg = 0;
1734                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1735                 cmd.retries = 0;
1736                 cmd.data = NULL;
1737                 cmd.error = 0;
1738
1739                 mrq.cmd = &cmd;
1740                 host->mrq = &mrq;
1741
1742                 /*
1743                  * In response to CMD19, the card sends 64 bytes of tuning
1744                  * block to the Host Controller. So we set the block size
1745                  * to 64 here.
1746                  */
1747                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1748
1749                 /*
1750                  * The tuning block is sent by the card to the host controller.
1751                  * So we set the TRNS_READ bit in the Transfer Mode register.
1752                  * This also takes care of setting DMA Enable and Multi Block
1753                  * Select in the same register to 0.
1754                  */
1755                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1756
1757                 sdhci_send_command(host, &cmd);
1758
1759                 host->cmd = NULL;
1760                 host->mrq = NULL;
1761
1762                 spin_unlock_irqrestore(&host->lock, flags);
1763                 /* Wait for Buffer Read Ready interrupt */
1764                 wait_event_interruptible_timeout(host->buf_ready_int,
1765                                         (host->tuning_done == 1),
1766                                         msecs_to_jiffies(50));
1767                 spin_lock_irqsave(&host->lock, flags);
1768
1769                 if (!host->tuning_done) {
1770                         pr_info(DRIVER_NAME ": Timeout waiting for "
1771                                 "Buffer Read Ready interrupt during tuning "
1772                                 "procedure, falling back to fixed sampling "
1773                                 "clock\n");
1774                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1776                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1777                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1778
1779                         err = -EIO;
1780                         goto out;
1781                 }
1782
1783                 host->tuning_done = 0;
1784
1785                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1786                 tuning_loop_counter--;
1787                 timeout--;
1788                 mdelay(1);
1789         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1790
1791         /*
1792          * The Host Driver has exhausted the maximum number of loops allowed,
1793          * so use fixed sampling frequency.
1794          */
1795         if (!tuning_loop_counter || !timeout) {
1796                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1797                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1798         } else {
1799                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1800                         pr_info(DRIVER_NAME ": Tuning procedure"
1801                                 " failed, falling back to fixed sampling"
1802                                 " clock\n");
1803                         err = -EIO;
1804                 }
1805         }
1806
1807 out:
1808         /*
1809          * If this is the very first time we are here, we start the retuning
1810          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1811          * flag won't be set, we check this condition before actually starting
1812          * the timer.
1813          */
1814         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1815             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1816                 mod_timer(&host->tuning_timer, jiffies +
1817                         host->tuning_count * HZ);
1818                 /* Tuning mode 1 limits the maximum data length to 4MB */
1819                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1820         } else {
1821                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1822                 /* Reload the new initial value for timer */
1823                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1824                         mod_timer(&host->tuning_timer, jiffies +
1825                                 host->tuning_count * HZ);
1826         }
1827
1828         /*
1829          * In case tuning fails, host controllers which support re-tuning can
1830          * try tuning again at a later time, when the re-tuning timer expires.
1831          * So for these controllers, we return 0. Since there might be other
1832          * controllers who do not have this capability, we return error for
1833          * them.
1834          */
1835         if (err && host->tuning_count &&
1836             host->tuning_mode == SDHCI_TUNING_MODE_1)
1837                 err = 0;
1838
1839         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1840         spin_unlock_irqrestore(&host->lock, flags);
1841         sdhci_runtime_pm_put(host);
1842
1843         return err;
1844 }
1845
1846 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1847 {
1848         u16 ctrl;
1849         unsigned long flags;
1850
1851         /* Host Controller v3.00 defines preset value registers */
1852         if (host->version < SDHCI_SPEC_300)
1853                 return;
1854
1855         spin_lock_irqsave(&host->lock, flags);
1856
1857         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1858
1859         /*
1860          * We only enable or disable Preset Value if they are not already
1861          * enabled or disabled respectively. Otherwise, we bail out.
1862          */
1863         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1864                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1865                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1866                 host->flags |= SDHCI_PV_ENABLED;
1867         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1868                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1869                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1870                 host->flags &= ~SDHCI_PV_ENABLED;
1871         }
1872
1873         spin_unlock_irqrestore(&host->lock, flags);
1874 }
1875
1876 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1877 {
1878         struct sdhci_host *host = mmc_priv(mmc);
1879
1880         sdhci_runtime_pm_get(host);
1881         sdhci_do_enable_preset_value(host, enable);
1882         sdhci_runtime_pm_put(host);
1883 }
1884
1885 static const struct mmc_host_ops sdhci_ops = {
1886         .request        = sdhci_request,
1887         .set_ios        = sdhci_set_ios,
1888         .get_ro         = sdhci_get_ro,
1889         .hw_reset       = sdhci_hw_reset,
1890         .enable_sdio_irq = sdhci_enable_sdio_irq,
1891         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1892         .execute_tuning                 = sdhci_execute_tuning,
1893         .enable_preset_value            = sdhci_enable_preset_value,
1894 };
1895
1896 /*****************************************************************************\
1897  *                                                                           *
1898  * Tasklets                                                                  *
1899  *                                                                           *
1900 \*****************************************************************************/
1901
1902 static void sdhci_tasklet_card(unsigned long param)
1903 {
1904         struct sdhci_host *host;
1905         unsigned long flags;
1906
1907         host = (struct sdhci_host*)param;
1908
1909         spin_lock_irqsave(&host->lock, flags);
1910
1911         /* Check host->mrq first in case we are runtime suspended */
1912         if (host->mrq &&
1913             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1914                 pr_err("%s: Card removed during transfer!\n",
1915                         mmc_hostname(host->mmc));
1916                 pr_err("%s: Resetting controller.\n",
1917                         mmc_hostname(host->mmc));
1918
1919                 sdhci_reset(host, SDHCI_RESET_CMD);
1920                 sdhci_reset(host, SDHCI_RESET_DATA);
1921
1922                 host->mrq->cmd->error = -ENOMEDIUM;
1923                 tasklet_schedule(&host->finish_tasklet);
1924         }
1925
1926         spin_unlock_irqrestore(&host->lock, flags);
1927
1928         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1929 }
1930
1931 static void sdhci_tasklet_finish(unsigned long param)
1932 {
1933         struct sdhci_host *host;
1934         unsigned long flags;
1935         struct mmc_request *mrq;
1936
1937         host = (struct sdhci_host*)param;
1938
1939         spin_lock_irqsave(&host->lock, flags);
1940
1941         /*
1942          * If this tasklet gets rescheduled while running, it will
1943          * be run again afterwards but without any active request.
1944          */
1945         if (!host->mrq) {
1946                 spin_unlock_irqrestore(&host->lock, flags);
1947                 return;
1948         }
1949
1950         del_timer(&host->timer);
1951
1952         mrq = host->mrq;
1953
1954         /*
1955          * The controller needs a reset of internal state machines
1956          * upon error conditions.
1957          */
1958         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1959             ((mrq->cmd && mrq->cmd->error) ||
1960                  (mrq->data && (mrq->data->error ||
1961                   (mrq->data->stop && mrq->data->stop->error))) ||
1962                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1963
1964                 /* Some controllers need this kick or reset won't work here */
1965                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1966                         unsigned int clock;
1967
1968                         /* This is to force an update */
1969                         clock = host->clock;
1970                         host->clock = 0;
1971                         sdhci_set_clock(host, clock);
1972                 }
1973
1974                 /* Spec says we should do both at the same time, but Ricoh
1975                    controllers do not like that. */
1976                 sdhci_reset(host, SDHCI_RESET_CMD);
1977                 sdhci_reset(host, SDHCI_RESET_DATA);
1978         }
1979
1980         host->mrq = NULL;
1981         host->cmd = NULL;
1982         host->data = NULL;
1983
1984 #ifndef SDHCI_USE_LEDS_CLASS
1985         sdhci_deactivate_led(host);
1986 #endif
1987
1988         mmiowb();
1989         spin_unlock_irqrestore(&host->lock, flags);
1990
1991         mmc_request_done(host->mmc, mrq);
1992         sdhci_runtime_pm_put(host);
1993 }
1994
1995 static void sdhci_timeout_timer(unsigned long data)
1996 {
1997         struct sdhci_host *host;
1998         unsigned long flags;
1999
2000         host = (struct sdhci_host*)data;
2001
2002         spin_lock_irqsave(&host->lock, flags);
2003
2004         if (host->mrq) {
2005                 pr_err("%s: Timeout waiting for hardware "
2006                         "interrupt.\n", mmc_hostname(host->mmc));
2007                 sdhci_dumpregs(host);
2008
2009                 if (host->data) {
2010                         host->data->error = -ETIMEDOUT;
2011                         sdhci_finish_data(host);
2012                 } else {
2013                         if (host->cmd)
2014                                 host->cmd->error = -ETIMEDOUT;
2015                         else
2016                                 host->mrq->cmd->error = -ETIMEDOUT;
2017
2018                         tasklet_schedule(&host->finish_tasklet);
2019                 }
2020         }
2021
2022         mmiowb();
2023         spin_unlock_irqrestore(&host->lock, flags);
2024 }
2025
2026 static void sdhci_tuning_timer(unsigned long data)
2027 {
2028         struct sdhci_host *host;
2029         unsigned long flags;
2030
2031         host = (struct sdhci_host *)data;
2032
2033         spin_lock_irqsave(&host->lock, flags);
2034
2035         host->flags |= SDHCI_NEEDS_RETUNING;
2036
2037         spin_unlock_irqrestore(&host->lock, flags);
2038 }
2039
2040 /*****************************************************************************\
2041  *                                                                           *
2042  * Interrupt handling                                                        *
2043  *                                                                           *
2044 \*****************************************************************************/
2045
2046 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2047 {
2048         BUG_ON(intmask == 0);
2049
2050         if (!host->cmd) {
2051                 pr_err("%s: Got command interrupt 0x%08x even "
2052                         "though no command operation was in progress.\n",
2053                         mmc_hostname(host->mmc), (unsigned)intmask);
2054                 sdhci_dumpregs(host);
2055                 return;
2056         }
2057
2058         if (intmask & SDHCI_INT_TIMEOUT)
2059                 host->cmd->error = -ETIMEDOUT;
2060         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2061                         SDHCI_INT_INDEX))
2062                 host->cmd->error = -EILSEQ;
2063
2064         if (host->cmd->error) {
2065                 tasklet_schedule(&host->finish_tasklet);
2066                 return;
2067         }
2068
2069         /*
2070          * The host can send and interrupt when the busy state has
2071          * ended, allowing us to wait without wasting CPU cycles.
2072          * Unfortunately this is overloaded on the "data complete"
2073          * interrupt, so we need to take some care when handling
2074          * it.
2075          *
2076          * Note: The 1.0 specification is a bit ambiguous about this
2077          *       feature so there might be some problems with older
2078          *       controllers.
2079          */
2080         if (host->cmd->flags & MMC_RSP_BUSY) {
2081                 if (host->cmd->data)
2082                         DBG("Cannot wait for busy signal when also "
2083                                 "doing a data transfer");
2084                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2085                         return;
2086
2087                 /* The controller does not support the end-of-busy IRQ,
2088                  * fall through and take the SDHCI_INT_RESPONSE */
2089         }
2090
2091         if (intmask & SDHCI_INT_RESPONSE)
2092                 sdhci_finish_command(host);
2093 }
2094
2095 #ifdef CONFIG_MMC_DEBUG
2096 static void sdhci_show_adma_error(struct sdhci_host *host)
2097 {
2098         const char *name = mmc_hostname(host->mmc);
2099         u8 *desc = host->adma_desc;
2100         __le32 *dma;
2101         __le16 *len;
2102         u8 attr;
2103
2104         sdhci_dumpregs(host);
2105
2106         while (true) {
2107                 dma = (__le32 *)(desc + 4);
2108                 len = (__le16 *)(desc + 2);
2109                 attr = *desc;
2110
2111                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2112                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2113
2114                 desc += 8;
2115
2116                 if (attr & 2)
2117                         break;
2118         }
2119 }
2120 #else
2121 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2122 #endif
2123
2124 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2125 {
2126         BUG_ON(intmask == 0);
2127
2128         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2129         if (intmask & SDHCI_INT_DATA_AVAIL) {
2130                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2131                     MMC_SEND_TUNING_BLOCK) {
2132                         host->tuning_done = 1;
2133                         wake_up(&host->buf_ready_int);
2134                         return;
2135                 }
2136         }
2137
2138         if (!host->data) {
2139                 /*
2140                  * The "data complete" interrupt is also used to
2141                  * indicate that a busy state has ended. See comment
2142                  * above in sdhci_cmd_irq().
2143                  */
2144                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2145                         if (intmask & SDHCI_INT_DATA_END) {
2146                                 sdhci_finish_command(host);
2147                                 return;
2148                         }
2149                 }
2150
2151                 pr_err("%s: Got data interrupt 0x%08x even "
2152                         "though no data operation was in progress.\n",
2153                         mmc_hostname(host->mmc), (unsigned)intmask);
2154                 sdhci_dumpregs(host);
2155
2156                 return;
2157         }
2158
2159         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2160                 host->data->error = -ETIMEDOUT;
2161         else if (intmask & SDHCI_INT_DATA_END_BIT)
2162                 host->data->error = -EILSEQ;
2163         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2164                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2165                         != MMC_BUS_TEST_R)
2166                 host->data->error = -EILSEQ;
2167         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2168                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2169                 sdhci_show_adma_error(host);
2170                 host->data->error = -EIO;
2171         }
2172
2173         if (host->data->error)
2174                 sdhci_finish_data(host);
2175         else {
2176                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2177                         sdhci_transfer_pio(host);
2178
2179                 /*
2180                  * We currently don't do anything fancy with DMA
2181                  * boundaries, but as we can't disable the feature
2182                  * we need to at least restart the transfer.
2183                  *
2184                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2185                  * should return a valid address to continue from, but as
2186                  * some controllers are faulty, don't trust them.
2187                  */
2188                 if (intmask & SDHCI_INT_DMA_END) {
2189                         u32 dmastart, dmanow;
2190                         dmastart = sg_dma_address(host->data->sg);
2191                         dmanow = dmastart + host->data->bytes_xfered;
2192                         /*
2193                          * Force update to the next DMA block boundary.
2194                          */
2195                         dmanow = (dmanow &
2196                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2197                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2198                         host->data->bytes_xfered = dmanow - dmastart;
2199                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2200                                 " next 0x%08x\n",
2201                                 mmc_hostname(host->mmc), dmastart,
2202                                 host->data->bytes_xfered, dmanow);
2203                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2204                 }
2205
2206                 if (intmask & SDHCI_INT_DATA_END) {
2207                         if (host->cmd) {
2208                                 /*
2209                                  * Data managed to finish before the
2210                                  * command completed. Make sure we do
2211                                  * things in the proper order.
2212                                  */
2213                                 host->data_early = 1;
2214                         } else {
2215                                 sdhci_finish_data(host);
2216                         }
2217                 }
2218         }
2219 }
2220
2221 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2222 {
2223         irqreturn_t result;
2224         struct sdhci_host *host = dev_id;
2225         u32 intmask;
2226         int cardint = 0;
2227
2228         spin_lock(&host->lock);
2229
2230         if (host->runtime_suspended) {
2231                 spin_unlock(&host->lock);
2232                 pr_warning("%s: got irq while runtime suspended\n",
2233                        mmc_hostname(host->mmc));
2234                 return IRQ_HANDLED;
2235         }
2236
2237         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2238
2239         if (!intmask || intmask == 0xffffffff) {
2240                 result = IRQ_NONE;
2241                 goto out;
2242         }
2243
2244         DBG("*** %s got interrupt: 0x%08x\n",
2245                 mmc_hostname(host->mmc), intmask);
2246
2247         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2248                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2249                               SDHCI_CARD_PRESENT;
2250
2251                 /*
2252                  * There is a observation on i.mx esdhc.  INSERT bit will be
2253                  * immediately set again when it gets cleared, if a card is
2254                  * inserted.  We have to mask the irq to prevent interrupt
2255                  * storm which will freeze the system.  And the REMOVE gets
2256                  * the same situation.
2257                  *
2258                  * More testing are needed here to ensure it works for other
2259                  * platforms though.
2260                  */
2261                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2262                                                 SDHCI_INT_CARD_REMOVE);
2263                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2264                                                   SDHCI_INT_CARD_INSERT);
2265
2266                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2267                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2268                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2269                 tasklet_schedule(&host->card_tasklet);
2270         }
2271
2272         if (intmask & SDHCI_INT_CMD_MASK) {
2273                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2274                         SDHCI_INT_STATUS);
2275                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2276         }
2277
2278         if (intmask & SDHCI_INT_DATA_MASK) {
2279                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2280                         SDHCI_INT_STATUS);
2281                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2282         }
2283
2284         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2285
2286         intmask &= ~SDHCI_INT_ERROR;
2287
2288         if (intmask & SDHCI_INT_BUS_POWER) {
2289                 pr_err("%s: Card is consuming too much power!\n",
2290                         mmc_hostname(host->mmc));
2291                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2292         }
2293
2294         intmask &= ~SDHCI_INT_BUS_POWER;
2295
2296         if (intmask & SDHCI_INT_CARD_INT)
2297                 cardint = 1;
2298
2299         intmask &= ~SDHCI_INT_CARD_INT;
2300
2301         if (intmask) {
2302                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2303                         mmc_hostname(host->mmc), intmask);
2304                 sdhci_dumpregs(host);
2305
2306                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2307         }
2308
2309         result = IRQ_HANDLED;
2310
2311         mmiowb();
2312 out:
2313         spin_unlock(&host->lock);
2314
2315         /*
2316          * We have to delay this as it calls back into the driver.
2317          */
2318         if (cardint)
2319                 mmc_signal_sdio_irq(host->mmc);
2320
2321         return result;
2322 }
2323
2324 /*****************************************************************************\
2325  *                                                                           *
2326  * Suspend/resume                                                            *
2327  *                                                                           *
2328 \*****************************************************************************/
2329
2330 #ifdef CONFIG_PM
2331
2332 int sdhci_suspend_host(struct sdhci_host *host)
2333 {
2334         int ret;
2335
2336         sdhci_disable_card_detection(host);
2337
2338         /* Disable tuning since we are suspending */
2339         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2340             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2341                 del_timer_sync(&host->tuning_timer);
2342                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2343         }
2344
2345         ret = mmc_suspend_host(host->mmc);
2346         if (ret)
2347                 return ret;
2348
2349         free_irq(host->irq, host);
2350
2351         if (host->vmmc)
2352                 ret = regulator_disable(host->vmmc);
2353
2354         return ret;
2355 }
2356
2357 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2358
2359 int sdhci_resume_host(struct sdhci_host *host)
2360 {
2361         int ret;
2362
2363         if (host->vmmc) {
2364                 int ret = regulator_enable(host->vmmc);
2365                 if (ret)
2366                         return ret;
2367         }
2368
2369         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2370                 if (host->ops->enable_dma)
2371                         host->ops->enable_dma(host);
2372         }
2373
2374         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2375                           mmc_hostname(host->mmc), host);
2376         if (ret)
2377                 return ret;
2378
2379         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2380         mmiowb();
2381
2382         ret = mmc_resume_host(host->mmc);
2383         sdhci_enable_card_detection(host);
2384
2385         /* Set the re-tuning expiration flag */
2386         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2387             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2388                 host->flags |= SDHCI_NEEDS_RETUNING;
2389
2390         return ret;
2391 }
2392
2393 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2394
2395 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2396 {
2397         u8 val;
2398         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2399         val |= SDHCI_WAKE_ON_INT;
2400         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2401 }
2402
2403 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2404
2405 #endif /* CONFIG_PM */
2406
2407 #ifdef CONFIG_PM_RUNTIME
2408
2409 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2410 {
2411         return pm_runtime_get_sync(host->mmc->parent);
2412 }
2413
2414 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2415 {
2416         pm_runtime_mark_last_busy(host->mmc->parent);
2417         return pm_runtime_put_autosuspend(host->mmc->parent);
2418 }
2419
2420 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2421 {
2422         unsigned long flags;
2423         int ret = 0;
2424
2425         /* Disable tuning since we are suspending */
2426         if (host->version >= SDHCI_SPEC_300 &&
2427             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2428                 del_timer_sync(&host->tuning_timer);
2429                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2430         }
2431
2432         spin_lock_irqsave(&host->lock, flags);
2433         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2434         spin_unlock_irqrestore(&host->lock, flags);
2435
2436         synchronize_irq(host->irq);
2437
2438         spin_lock_irqsave(&host->lock, flags);
2439         host->runtime_suspended = true;
2440         spin_unlock_irqrestore(&host->lock, flags);
2441
2442         return ret;
2443 }
2444 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2445
2446 int sdhci_runtime_resume_host(struct sdhci_host *host)
2447 {
2448         unsigned long flags;
2449         int ret = 0, host_flags = host->flags;
2450
2451         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2452                 if (host->ops->enable_dma)
2453                         host->ops->enable_dma(host);
2454         }
2455
2456         sdhci_init(host, 0);
2457
2458         /* Force clock and power re-program */
2459         host->pwr = 0;
2460         host->clock = 0;
2461         sdhci_do_set_ios(host, &host->mmc->ios);
2462
2463         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2464         if (host_flags & SDHCI_PV_ENABLED)
2465                 sdhci_do_enable_preset_value(host, true);
2466
2467         /* Set the re-tuning expiration flag */
2468         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2469             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2470                 host->flags |= SDHCI_NEEDS_RETUNING;
2471
2472         spin_lock_irqsave(&host->lock, flags);
2473
2474         host->runtime_suspended = false;
2475
2476         /* Enable SDIO IRQ */
2477         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2478                 sdhci_enable_sdio_irq_nolock(host, true);
2479
2480         /* Enable Card Detection */
2481         sdhci_enable_card_detection(host);
2482
2483         spin_unlock_irqrestore(&host->lock, flags);
2484
2485         return ret;
2486 }
2487 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2488
2489 #endif
2490
2491 /*****************************************************************************\
2492  *                                                                           *
2493  * Device allocation/registration                                            *
2494  *                                                                           *
2495 \*****************************************************************************/
2496
2497 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2498         size_t priv_size)
2499 {
2500         struct mmc_host *mmc;
2501         struct sdhci_host *host;
2502
2503         WARN_ON(dev == NULL);
2504
2505         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2506         if (!mmc)
2507                 return ERR_PTR(-ENOMEM);
2508
2509         host = mmc_priv(mmc);
2510         host->mmc = mmc;
2511
2512         return host;
2513 }
2514
2515 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2516
2517 int sdhci_add_host(struct sdhci_host *host)
2518 {
2519         struct mmc_host *mmc;
2520         u32 caps[2];
2521         u32 max_current_caps;
2522         unsigned int ocr_avail;
2523         int ret;
2524
2525         WARN_ON(host == NULL);
2526         if (host == NULL)
2527                 return -EINVAL;
2528
2529         mmc = host->mmc;
2530
2531         if (debug_quirks)
2532                 host->quirks = debug_quirks;
2533         if (debug_quirks2)
2534                 host->quirks2 = debug_quirks2;
2535
2536         sdhci_reset(host, SDHCI_RESET_ALL);
2537
2538         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2539         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2540                                 >> SDHCI_SPEC_VER_SHIFT;
2541         if (host->version > SDHCI_SPEC_300) {
2542                 pr_err("%s: Unknown controller version (%d). "
2543                         "You may experience problems.\n", mmc_hostname(mmc),
2544                         host->version);
2545         }
2546
2547         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2548                 sdhci_readl(host, SDHCI_CAPABILITIES);
2549
2550         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2551                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2552
2553         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2554                 host->flags |= SDHCI_USE_SDMA;
2555         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2556                 DBG("Controller doesn't have SDMA capability\n");
2557         else
2558                 host->flags |= SDHCI_USE_SDMA;
2559
2560         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2561                 (host->flags & SDHCI_USE_SDMA)) {
2562                 DBG("Disabling DMA as it is marked broken\n");
2563                 host->flags &= ~SDHCI_USE_SDMA;
2564         }
2565
2566         if ((host->version >= SDHCI_SPEC_200) &&
2567                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2568                 host->flags |= SDHCI_USE_ADMA;
2569
2570         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2571                 (host->flags & SDHCI_USE_ADMA)) {
2572                 DBG("Disabling ADMA as it is marked broken\n");
2573                 host->flags &= ~SDHCI_USE_ADMA;
2574         }
2575
2576         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2577                 if (host->ops->enable_dma) {
2578                         if (host->ops->enable_dma(host)) {
2579                                 pr_warning("%s: No suitable DMA "
2580                                         "available. Falling back to PIO.\n",
2581                                         mmc_hostname(mmc));
2582                                 host->flags &=
2583                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2584                         }
2585                 }
2586         }
2587
2588         if (host->flags & SDHCI_USE_ADMA) {
2589                 /*
2590                  * We need to allocate descriptors for all sg entries
2591                  * (128) and potentially one alignment transfer for
2592                  * each of those entries.
2593                  */
2594                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2595                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2596                 if (!host->adma_desc || !host->align_buffer) {
2597                         kfree(host->adma_desc);
2598                         kfree(host->align_buffer);
2599                         pr_warning("%s: Unable to allocate ADMA "
2600                                 "buffers. Falling back to standard DMA.\n",
2601                                 mmc_hostname(mmc));
2602                         host->flags &= ~SDHCI_USE_ADMA;
2603                 }
2604         }
2605
2606         /*
2607          * If we use DMA, then it's up to the caller to set the DMA
2608          * mask, but PIO does not need the hw shim so we set a new
2609          * mask here in that case.
2610          */
2611         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2612                 host->dma_mask = DMA_BIT_MASK(64);
2613                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2614         }
2615
2616         if (host->version >= SDHCI_SPEC_300)
2617                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2618                         >> SDHCI_CLOCK_BASE_SHIFT;
2619         else
2620                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2621                         >> SDHCI_CLOCK_BASE_SHIFT;
2622
2623         host->max_clk *= 1000000;
2624         if (host->max_clk == 0 || host->quirks &
2625                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2626                 if (!host->ops->get_max_clock) {
2627                         pr_err("%s: Hardware doesn't specify base clock "
2628                                "frequency.\n", mmc_hostname(mmc));
2629                         return -ENODEV;
2630                 }
2631                 host->max_clk = host->ops->get_max_clock(host);
2632         }
2633
2634         /*
2635          * In case of Host Controller v3.00, find out whether clock
2636          * multiplier is supported.
2637          */
2638         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2639                         SDHCI_CLOCK_MUL_SHIFT;
2640
2641         /*
2642          * In case the value in Clock Multiplier is 0, then programmable
2643          * clock mode is not supported, otherwise the actual clock
2644          * multiplier is one more than the value of Clock Multiplier
2645          * in the Capabilities Register.
2646          */
2647         if (host->clk_mul)
2648                 host->clk_mul += 1;
2649
2650         /*
2651          * Set host parameters.
2652          */
2653         mmc->ops = &sdhci_ops;
2654         mmc->f_max = host->max_clk;
2655         if (host->ops->get_min_clock)
2656                 mmc->f_min = host->ops->get_min_clock(host);
2657         else if (host->version >= SDHCI_SPEC_300) {
2658                 if (host->clk_mul) {
2659                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2660                         mmc->f_max = host->max_clk * host->clk_mul;
2661                 } else
2662                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2663         } else
2664                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2665
2666         host->timeout_clk =
2667                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2668         if (host->timeout_clk == 0) {
2669                 if (host->ops->get_timeout_clock) {
2670                         host->timeout_clk = host->ops->get_timeout_clock(host);
2671                 } else if (!(host->quirks &
2672                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2673                         pr_err("%s: Hardware doesn't specify timeout clock "
2674                                "frequency.\n", mmc_hostname(mmc));
2675                         return -ENODEV;
2676                 }
2677         }
2678         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2679                 host->timeout_clk *= 1000;
2680
2681         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2682                 host->timeout_clk = mmc->f_max / 1000;
2683
2684         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2685
2686         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2687
2688         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2689                 host->flags |= SDHCI_AUTO_CMD12;
2690
2691         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2692         if ((host->version >= SDHCI_SPEC_300) &&
2693             ((host->flags & SDHCI_USE_ADMA) ||
2694              !(host->flags & SDHCI_USE_SDMA))) {
2695                 host->flags |= SDHCI_AUTO_CMD23;
2696                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2697         } else {
2698                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2699         }
2700
2701         /*
2702          * A controller may support 8-bit width, but the board itself
2703          * might not have the pins brought out.  Boards that support
2704          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2705          * their platform code before calling sdhci_add_host(), and we
2706          * won't assume 8-bit width for hosts without that CAP.
2707          */
2708         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2709                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2710
2711         if (caps[0] & SDHCI_CAN_DO_HISPD)
2712                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2713
2714         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2715             mmc_card_is_removable(mmc))
2716                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2717
2718         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2719         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2720                        SDHCI_SUPPORT_DDR50))
2721                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2722
2723         /* SDR104 supports also implies SDR50 support */
2724         if (caps[1] & SDHCI_SUPPORT_SDR104)
2725                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2726         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2727                 mmc->caps |= MMC_CAP_UHS_SDR50;
2728
2729         if (caps[1] & SDHCI_SUPPORT_DDR50)
2730                 mmc->caps |= MMC_CAP_UHS_DDR50;
2731
2732         /* Does the host needs tuning for SDR50? */
2733         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2734                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2735
2736         /* Driver Type(s) (A, C, D) supported by the host */
2737         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2738                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2739         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2740                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2741         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2742                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2743
2744         /*
2745          * If Power Off Notify capability is enabled by the host,
2746          * set notify to short power off notify timeout value.
2747          */
2748         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2749                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2750         else
2751                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2752
2753         /* Initial value for re-tuning timer count */
2754         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2755                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2756
2757         /*
2758          * In case Re-tuning Timer is not disabled, the actual value of
2759          * re-tuning timer will be 2 ^ (n - 1).
2760          */
2761         if (host->tuning_count)
2762                 host->tuning_count = 1 << (host->tuning_count - 1);
2763
2764         /* Re-tuning mode supported by the Host Controller */
2765         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2766                              SDHCI_RETUNING_MODE_SHIFT;
2767
2768         ocr_avail = 0;
2769         /*
2770          * According to SD Host Controller spec v3.00, if the Host System
2771          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2772          * the value is meaningful only if Voltage Support in the Capabilities
2773          * register is set. The actual current value is 4 times the register
2774          * value.
2775          */
2776         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2777
2778         if (caps[0] & SDHCI_CAN_VDD_330) {
2779                 int max_current_330;
2780
2781                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2782
2783                 max_current_330 = ((max_current_caps &
2784                                    SDHCI_MAX_CURRENT_330_MASK) >>
2785                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2786                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2787
2788                 if (max_current_330 > 150)
2789                         mmc->caps |= MMC_CAP_SET_XPC_330;
2790         }
2791         if (caps[0] & SDHCI_CAN_VDD_300) {
2792                 int max_current_300;
2793
2794                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2795
2796                 max_current_300 = ((max_current_caps &
2797                                    SDHCI_MAX_CURRENT_300_MASK) >>
2798                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2799                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2800
2801                 if (max_current_300 > 150)
2802                         mmc->caps |= MMC_CAP_SET_XPC_300;
2803         }
2804         if (caps[0] & SDHCI_CAN_VDD_180) {
2805                 int max_current_180;
2806
2807                 ocr_avail |= MMC_VDD_165_195;
2808
2809                 max_current_180 = ((max_current_caps &
2810                                    SDHCI_MAX_CURRENT_180_MASK) >>
2811                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2812                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2813
2814                 if (max_current_180 > 150)
2815                         mmc->caps |= MMC_CAP_SET_XPC_180;
2816
2817                 /* Maximum current capabilities of the host at 1.8V */
2818                 if (max_current_180 >= 800)
2819                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2820                 else if (max_current_180 >= 600)
2821                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2822                 else if (max_current_180 >= 400)
2823                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2824                 else
2825                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2826         }
2827
2828         mmc->ocr_avail = ocr_avail;
2829         mmc->ocr_avail_sdio = ocr_avail;
2830         if (host->ocr_avail_sdio)
2831                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2832         mmc->ocr_avail_sd = ocr_avail;
2833         if (host->ocr_avail_sd)
2834                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2835         else /* normal SD controllers don't support 1.8V */
2836                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2837         mmc->ocr_avail_mmc = ocr_avail;
2838         if (host->ocr_avail_mmc)
2839                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2840
2841         if (mmc->ocr_avail == 0) {
2842                 pr_err("%s: Hardware doesn't report any "
2843                         "support voltages.\n", mmc_hostname(mmc));
2844                 return -ENODEV;
2845         }
2846
2847         spin_lock_init(&host->lock);
2848
2849         /*
2850          * Maximum number of segments. Depends on if the hardware
2851          * can do scatter/gather or not.
2852          */
2853         if (host->flags & SDHCI_USE_ADMA)
2854                 mmc->max_segs = 128;
2855         else if (host->flags & SDHCI_USE_SDMA)
2856                 mmc->max_segs = 1;
2857         else /* PIO */
2858                 mmc->max_segs = 128;
2859
2860         /*
2861          * Maximum number of sectors in one transfer. Limited by DMA boundary
2862          * size (512KiB).
2863          */
2864         mmc->max_req_size = 524288;
2865
2866         /*
2867          * Maximum segment size. Could be one segment with the maximum number
2868          * of bytes. When doing hardware scatter/gather, each entry cannot
2869          * be larger than 64 KiB though.
2870          */
2871         if (host->flags & SDHCI_USE_ADMA) {
2872                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2873                         mmc->max_seg_size = 65535;
2874                 else
2875                         mmc->max_seg_size = 65536;
2876         } else {
2877                 mmc->max_seg_size = mmc->max_req_size;
2878         }
2879
2880         /*
2881          * Maximum block size. This varies from controller to controller and
2882          * is specified in the capabilities register.
2883          */
2884         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2885                 mmc->max_blk_size = 2;
2886         } else {
2887                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2888                                 SDHCI_MAX_BLOCK_SHIFT;
2889                 if (mmc->max_blk_size >= 3) {
2890                         pr_warning("%s: Invalid maximum block size, "
2891                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2892                         mmc->max_blk_size = 0;
2893                 }
2894         }
2895
2896         mmc->max_blk_size = 512 << mmc->max_blk_size;
2897
2898         /*
2899          * Maximum block count.
2900          */
2901         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2902
2903         /*
2904          * Init tasklets.
2905          */
2906         tasklet_init(&host->card_tasklet,
2907                 sdhci_tasklet_card, (unsigned long)host);
2908         tasklet_init(&host->finish_tasklet,
2909                 sdhci_tasklet_finish, (unsigned long)host);
2910
2911         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2912
2913         if (host->version >= SDHCI_SPEC_300) {
2914                 init_waitqueue_head(&host->buf_ready_int);
2915
2916                 /* Initialize re-tuning timer */
2917                 init_timer(&host->tuning_timer);
2918                 host->tuning_timer.data = (unsigned long)host;
2919                 host->tuning_timer.function = sdhci_tuning_timer;
2920         }
2921
2922         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2923                 mmc_hostname(mmc), host);
2924         if (ret)
2925                 goto untasklet;
2926
2927         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2928         if (IS_ERR(host->vmmc)) {
2929                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2930                 host->vmmc = NULL;
2931         } else {
2932                 regulator_enable(host->vmmc);
2933         }
2934
2935         sdhci_init(host, 0);
2936
2937 #ifdef CONFIG_MMC_DEBUG
2938         sdhci_dumpregs(host);
2939 #endif
2940
2941 #ifdef SDHCI_USE_LEDS_CLASS
2942         snprintf(host->led_name, sizeof(host->led_name),
2943                 "%s::", mmc_hostname(mmc));
2944         host->led.name = host->led_name;
2945         host->led.brightness = LED_OFF;
2946         host->led.default_trigger = mmc_hostname(mmc);
2947         host->led.brightness_set = sdhci_led_control;
2948
2949         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2950         if (ret)
2951                 goto reset;
2952 #endif
2953
2954         mmiowb();
2955
2956         mmc_add_host(mmc);
2957
2958         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2959                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2960                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2961                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2962
2963         sdhci_enable_card_detection(host);
2964
2965         return 0;
2966
2967 #ifdef SDHCI_USE_LEDS_CLASS
2968 reset:
2969         sdhci_reset(host, SDHCI_RESET_ALL);
2970         free_irq(host->irq, host);
2971 #endif
2972 untasklet:
2973         tasklet_kill(&host->card_tasklet);
2974         tasklet_kill(&host->finish_tasklet);
2975
2976         return ret;
2977 }
2978
2979 EXPORT_SYMBOL_GPL(sdhci_add_host);
2980
2981 void sdhci_remove_host(struct sdhci_host *host, int dead)
2982 {
2983         unsigned long flags;
2984
2985         if (dead) {
2986                 spin_lock_irqsave(&host->lock, flags);
2987
2988                 host->flags |= SDHCI_DEVICE_DEAD;
2989
2990                 if (host->mrq) {
2991                         pr_err("%s: Controller removed during "
2992                                 " transfer!\n", mmc_hostname(host->mmc));
2993
2994                         host->mrq->cmd->error = -ENOMEDIUM;
2995                         tasklet_schedule(&host->finish_tasklet);
2996                 }
2997
2998                 spin_unlock_irqrestore(&host->lock, flags);
2999         }
3000
3001         sdhci_disable_card_detection(host);
3002
3003         mmc_remove_host(host->mmc);
3004
3005 #ifdef SDHCI_USE_LEDS_CLASS
3006         led_classdev_unregister(&host->led);
3007 #endif
3008
3009         if (!dead)
3010                 sdhci_reset(host, SDHCI_RESET_ALL);
3011
3012         free_irq(host->irq, host);
3013
3014         del_timer_sync(&host->timer);
3015         if (host->version >= SDHCI_SPEC_300)
3016                 del_timer_sync(&host->tuning_timer);
3017
3018         tasklet_kill(&host->card_tasklet);
3019         tasklet_kill(&host->finish_tasklet);
3020
3021         if (host->vmmc) {
3022                 regulator_disable(host->vmmc);
3023                 regulator_put(host->vmmc);
3024         }
3025
3026         kfree(host->adma_desc);
3027         kfree(host->align_buffer);
3028
3029         host->adma_desc = NULL;
3030         host->align_buffer = NULL;
3031 }
3032
3033 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3034
3035 void sdhci_free_host(struct sdhci_host *host)
3036 {
3037         mmc_free_host(host->mmc);
3038 }
3039
3040 EXPORT_SYMBOL_GPL(sdhci_free_host);
3041
3042 /*****************************************************************************\
3043  *                                                                           *
3044  * Driver init/exit                                                          *
3045  *                                                                           *
3046 \*****************************************************************************/
3047
3048 static int __init sdhci_drv_init(void)
3049 {
3050         pr_info(DRIVER_NAME
3051                 ": Secure Digital Host Controller Interface driver\n");
3052         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3053
3054         return 0;
3055 }
3056
3057 static void __exit sdhci_drv_exit(void)
3058 {
3059 }
3060
3061 module_init(sdhci_drv_init);
3062 module_exit(sdhci_drv_exit);
3063
3064 module_param(debug_quirks, uint, 0444);
3065 module_param(debug_quirks2, uint, 0444);
3066
3067 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3068 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3069 MODULE_LICENSE("GPL");
3070
3071 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3072 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");