drivers/media/video/ov6650.c

   1 /*
   2  * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
   3  *
   4  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
   5  *
   6  * Based on OmniVision OV96xx Camera Driver
   7  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
   8  *
   9  * Based on ov772x camera driver:
  10  * Copyright (C) 2008 Renesas Solutions Corp.
  11  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  12  *
  13  * Based on ov7670 and soc_camera_platform driver,
  14  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  15  * Copyright (C) 2008 Magnus Damm
  16  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  17  *
  18  * Hardware specific bits initialy based on former work by Matt Callow
  19  * drivers/media/video/omap/sensor_ov6650.c
  20  * Copyright (C) 2006 Matt Callow
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  */
  26
  27 #include <linux/bitops.h>
  28 #include <linux/delay.h>
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31
  32 #include <media/soc_camera.h>
  33 #include <media/soc_mediabus.h>
  34 #include <media/v4l2-chip-ident.h>
  35 #include <media/v4l2-ctrls.h>
  36
  37 /* Register definitions */
  38 #define REG_GAIN                0x00    /* range 00 - 3F */
  39 #define REG_BLUE                0x01
  40 #define REG_RED                 0x02
  41 #define REG_SAT                 0x03    /* [7:4] saturation [0:3] reserved */
  42 #define REG_HUE                 0x04    /* [7:6] rsrvd [5] hue en [4:0] hue */
  43
  44 #define REG_BRT                 0x06
  45
  46 #define REG_PIDH                0x0a
  47 #define REG_PIDL                0x0b
  48
  49 #define REG_AECH                0x10
  50 #define REG_CLKRC               0x11    /* Data Format and Internal Clock */
  51                                         /* [7:6] Input system clock (MHz)*/
  52                                         /*   00=8, 01=12, 10=16, 11=24 */
  53                                         /* [5:0]: Internal Clock Pre-Scaler */
  54 #define REG_COMA                0x12    /* [7] Reset */
  55 #define REG_COMB                0x13
  56 #define REG_COMC                0x14
  57 #define REG_COMD                0x15
  58 #define REG_COML                0x16
  59 #define REG_HSTRT               0x17
  60 #define REG_HSTOP               0x18
  61 #define REG_VSTRT               0x19
  62 #define REG_VSTOP               0x1a
  63 #define REG_PSHFT               0x1b
  64 #define REG_MIDH                0x1c
  65 #define REG_MIDL                0x1d
  66 #define REG_HSYNS               0x1e
  67 #define REG_HSYNE               0x1f
  68 #define REG_COME                0x20
  69 #define REG_YOFF                0x21
  70 #define REG_UOFF                0x22
  71 #define REG_VOFF                0x23
  72 #define REG_AEW                 0x24
  73 #define REG_AEB                 0x25
  74 #define REG_COMF                0x26
  75 #define REG_COMG                0x27
  76 #define REG_COMH                0x28
  77 #define REG_COMI                0x29
  78
  79 #define REG_FRARL               0x2b
  80 #define REG_COMJ                0x2c
  81 #define REG_COMK                0x2d
  82 #define REG_AVGY                0x2e
  83 #define REG_REF0                0x2f
  84 #define REG_REF1                0x30
  85 #define REG_REF2                0x31
  86 #define REG_FRAJH               0x32
  87 #define REG_FRAJL               0x33
  88 #define REG_FACT                0x34
  89 #define REG_L1AEC               0x35
  90 #define REG_AVGU                0x36
  91 #define REG_AVGV                0x37
  92
  93 #define REG_SPCB                0x60
  94 #define REG_SPCC                0x61
  95 #define REG_GAM1                0x62
  96 #define REG_GAM2                0x63
  97 #define REG_GAM3                0x64
  98 #define REG_SPCD                0x65
  99
 100 #define REG_SPCE                0x68
 101 #define REG_ADCL                0x69
 102
 103 #define REG_RMCO                0x6c
 104 #define REG_GMCO                0x6d
 105 #define REG_BMCO                0x6e
 106
 107
 108 /* Register bits, values, etc. */
 109 #define OV6650_PIDH             0x66    /* high byte of product ID number */
 110 #define OV6650_PIDL             0x50    /* low byte of product ID number */
 111 #define OV6650_MIDH             0x7F    /* high byte of mfg ID */
 112 #define OV6650_MIDL             0xA2    /* low byte of mfg ID */
 113
 114 #define DEF_GAIN                0x00
 115 #define DEF_BLUE                0x80
 116 #define DEF_RED                 0x80
 117
 118 #define SAT_SHIFT               4
 119 #define SAT_MASK                (0xf << SAT_SHIFT)
 120 #define SET_SAT(x)              (((x) << SAT_SHIFT) & SAT_MASK)
 121
 122 #define HUE_EN                  BIT(5)
 123 #define HUE_MASK                0x1f
 124 #define DEF_HUE                 0x10
 125 #define SET_HUE(x)              (HUE_EN | ((x) & HUE_MASK))
 126
 127 #define DEF_AECH                0x4D
 128
 129 #define CLKRC_6MHz              0x00
 130 #define CLKRC_12MHz             0x40
 131 #define CLKRC_16MHz             0x80
 132 #define CLKRC_24MHz             0xc0
 133 #define CLKRC_DIV_MASK          0x3f
 134 #define GET_CLKRC_DIV(x)        (((x) & CLKRC_DIV_MASK) + 1)
 135
 136 #define COMA_RESET              BIT(7)
 137 #define COMA_QCIF               BIT(5)
 138 #define COMA_RAW_RGB            BIT(4)
 139 #define COMA_RGB                BIT(3)
 140 #define COMA_BW                 BIT(2)
 141 #define COMA_WORD_SWAP          BIT(1)
 142 #define COMA_BYTE_SWAP          BIT(0)
 143 #define DEF_COMA                0x00
 144
 145 #define COMB_FLIP_V             BIT(7)
 146 #define COMB_FLIP_H             BIT(5)
 147 #define COMB_BAND_FILTER        BIT(4)
 148 #define COMB_AWB                BIT(2)
 149 #define COMB_AGC                BIT(1)
 150 #define COMB_AEC                BIT(0)
 151 #define DEF_COMB                0x5f
 152
 153 #define COML_ONE_CHANNEL        BIT(7)
 154
 155 #define DEF_HSTRT               0x24
 156 #define DEF_HSTOP               0xd4
 157 #define DEF_VSTRT               0x04
 158 #define DEF_VSTOP               0x94
 159
 160 #define COMF_HREF_LOW           BIT(4)
 161
 162 #define COMJ_PCLK_RISING        BIT(4)
 163 #define COMJ_VSYNC_HIGH         BIT(0)
 164
 165 /* supported resolutions */
 166 #define W_QCIF                  (DEF_HSTOP - DEF_HSTRT)
 167 #define W_CIF                   (W_QCIF << 1)
 168 #define H_QCIF                  (DEF_VSTOP - DEF_VSTRT)
 169 #define H_CIF                   (H_QCIF << 1)
 170
 171 #define FRAME_RATE_MAX          30
 172
 173
 174 struct ov6650_reg {
 175         u8      reg;
 176         u8      val;
 177 };
 178
 179 struct ov6650 {
 180         struct v4l2_subdev      subdev;
 181         struct v4l2_ctrl_handler hdl;
 182         struct {
 183                 /* exposure/autoexposure cluster */
 184                 struct v4l2_ctrl *autoexposure;
 185                 struct v4l2_ctrl *exposure;
 186         };
 187         struct {
 188                 /* gain/autogain cluster */
 189                 struct v4l2_ctrl *autogain;
 190                 struct v4l2_ctrl *gain;
 191         };
 192         struct {
 193                 /* blue/red/autowhitebalance cluster */
 194                 struct v4l2_ctrl *autowb;
 195                 struct v4l2_ctrl *blue;
 196                 struct v4l2_ctrl *red;
 197         };
 198         bool                    half_scale;     /* scale down output by 2 */
 199         struct v4l2_rect        rect;           /* sensor cropping window */
 200         unsigned long           pclk_limit;     /* from host */
 201         unsigned long           pclk_max;       /* from resolution and format */
 202         struct v4l2_fract       tpf;            /* as requested with s_parm */
 203         enum v4l2_mbus_pixelcode code;
 204         enum v4l2_colorspace    colorspace;
 205 };
 206
 207
 208 static enum v4l2_mbus_pixelcode ov6650_codes[] = {
 209         V4L2_MBUS_FMT_YUYV8_2X8,
 210         V4L2_MBUS_FMT_UYVY8_2X8,
 211         V4L2_MBUS_FMT_YVYU8_2X8,
 212         V4L2_MBUS_FMT_VYUY8_2X8,
 213         V4L2_MBUS_FMT_SBGGR8_1X8,
 214         V4L2_MBUS_FMT_Y8_1X8,
 215 };
 216
 217 /* read a register */
 218 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
 219 {
 220         int ret;
 221         u8 data = reg;
 222         struct i2c_msg msg = {
 223                 .addr   = client->addr,
 224                 .flags  = 0,
 225                 .len    = 1,
 226                 .buf    = &data,
 227         };
 228
 229         ret = i2c_transfer(client->adapter, &msg, 1);
 230         if (ret < 0)
 231                 goto err;
 232
 233         msg.flags = I2C_M_RD;
 234         ret = i2c_transfer(client->adapter, &msg, 1);
 235         if (ret < 0)
 236                 goto err;
 237
 238         *val = data;
 239         return 0;
 240
 241 err:
 242         dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
 243         return ret;
 244 }
 245
 246 /* write a register */
 247 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
 248 {
 249         int ret;
 250         unsigned char data[2] = { reg, val };
 251         struct i2c_msg msg = {
 252                 .addr   = client->addr,
 253                 .flags  = 0,
 254                 .len    = 2,
 255                 .buf    = data,
 256         };
 257
 258         ret = i2c_transfer(client->adapter, &msg, 1);
 259         udelay(100);
 260
 261         if (ret < 0) {
 262                 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
 263                 return ret;
 264         }
 265         return 0;
 266 }
 267
 268
 269 /* Read a register, alter its bits, write it back */
 270 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
 271 {
 272         u8 val;
 273         int ret;
 274
 275         ret = ov6650_reg_read(client, reg, &val);
 276         if (ret) {
 277                 dev_err(&client->dev,
 278                         "[Read]-Modify-Write of register 0x%02x failed!\n",
 279                         reg);
 280                 return ret;
 281         }
 282
 283         val &= ~mask;
 284         val |= set;
 285
 286         ret = ov6650_reg_write(client, reg, val);
 287         if (ret)
 288                 dev_err(&client->dev,
 289                         "Read-Modify-[Write] of register 0x%02x failed!\n",
 290                         reg);
 291
 292         return ret;
 293 }
 294
 295 static struct ov6650 *to_ov6650(const struct i2c_client *client)
 296 {
 297         return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
 298 }
 299
 300 /* Start/Stop streaming from the device */
 301 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
 302 {
 303         return 0;
 304 }
 305
 306 /* Get status of additional camera capabilities */
 307 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 308 {
 309         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 310         struct v4l2_subdev *sd = &priv->subdev;
 311         struct i2c_client *client = v4l2_get_subdevdata(sd);
 312         uint8_t reg, reg2;
 313         int ret = 0;
 314
 315         switch (ctrl->id) {
 316         case V4L2_CID_AUTOGAIN:
 317                 ret = ov6650_reg_read(client, REG_GAIN, &reg);
 318                 if (!ret)
 319                         priv->gain->val = reg;
 320                 return ret;
 321         case V4L2_CID_AUTO_WHITE_BALANCE:
 322                 ret = ov6650_reg_read(client, REG_BLUE, &reg);
 323                 if (!ret)
 324                         ret = ov6650_reg_read(client, REG_RED, &reg2);
 325                 if (!ret) {
 326                         priv->blue->val = reg;
 327                         priv->red->val = reg2;
 328                 }
 329                 return ret;
 330         case V4L2_CID_EXPOSURE_AUTO:
 331                 ret = ov6650_reg_read(client, REG_AECH, &reg);
 332                 if (!ret)
 333                         priv->exposure->val = reg;
 334                 return ret;
 335         }
 336         return -EINVAL;
 337 }
 338
 339 /* Set status of additional camera capabilities */
 340 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
 341 {
 342         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 343         struct v4l2_subdev *sd = &priv->subdev;
 344         struct i2c_client *client = v4l2_get_subdevdata(sd);
 345         int ret = 0;
 346
 347         switch (ctrl->id) {
 348         case V4L2_CID_AUTOGAIN:
 349                 ret = ov6650_reg_rmw(client, REG_COMB,
 350                                 ctrl->val ? COMB_AGC : 0, COMB_AGC);
 351                 if (!ret && !ctrl->val)
 352                         ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
 353                 return ret;
 354         case V4L2_CID_AUTO_WHITE_BALANCE:
 355                 ret = ov6650_reg_rmw(client, REG_COMB,
 356                                 ctrl->val ? COMB_AWB : 0, COMB_AWB);
 357                 if (!ret && !ctrl->val) {
 358                         ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
 359                         if (!ret)
 360                                 ret = ov6650_reg_write(client, REG_RED,
 361                                                         priv->red->val);
 362                 }
 363                 return ret;
 364         case V4L2_CID_SATURATION:
 365                 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
 366                                 SAT_MASK);
 367         case V4L2_CID_HUE:
 368                 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
 369                                 HUE_MASK);
 370         case V4L2_CID_BRIGHTNESS:
 371                 return ov6650_reg_write(client, REG_BRT, ctrl->val);
 372         case V4L2_CID_EXPOSURE_AUTO:
 373                 if (ctrl->val == V4L2_EXPOSURE_AUTO)
 374                         ret = ov6650_reg_rmw(client, REG_COMB, COMB_AEC, 0);
 375                 else
 376                         ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_AEC);
 377                 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
 378                         ret = ov6650_reg_write(client, REG_AECH,
 379                                                 priv->exposure->val);
 380                 return ret;
 381         case V4L2_CID_GAMMA:
 382                 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
 383         case V4L2_CID_VFLIP:
 384                 return ov6650_reg_rmw(client, REG_COMB,
 385                                 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
 386         case V4L2_CID_HFLIP:
 387                 return ov6650_reg_rmw(client, REG_COMB,
 388                                 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
 389         }
 390
 391         return -EINVAL;
 392 }
 393
 394 /* Get chip identification */
 395 static int ov6650_g_chip_ident(struct v4l2_subdev *sd,
 396                                 struct v4l2_dbg_chip_ident *id)
 397 {
 398         id->ident       = V4L2_IDENT_OV6650;
 399         id->revision    = 0;
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_VIDEO_ADV_DEBUG
 405 static int ov6650_get_register(struct v4l2_subdev *sd,
 406                                 struct v4l2_dbg_register *reg)
 407 {
 408         struct i2c_client *client = v4l2_get_subdevdata(sd);
 409         int ret;
 410         u8 val;
 411
 412         if (reg->reg & ~0xff)
 413                 return -EINVAL;
 414
 415         reg->size = 1;
 416
 417         ret = ov6650_reg_read(client, reg->reg, &val);
 418         if (!ret)
 419                 reg->val = (__u64)val;
 420
 421         return ret;
 422 }
 423
 424 static int ov6650_set_register(struct v4l2_subdev *sd,
 425                                 struct v4l2_dbg_register *reg)
 426 {
 427         struct i2c_client *client = v4l2_get_subdevdata(sd);
 428
 429         if (reg->reg & ~0xff || reg->val & ~0xff)
 430                 return -EINVAL;
 431
 432         return ov6650_reg_write(client, reg->reg, reg->val);
 433 }
 434 #endif
 435
 436 static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 437 {
 438         struct i2c_client *client = v4l2_get_subdevdata(sd);
 439         struct ov6650 *priv = to_ov6650(client);
 440
 441         a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 442         a->c = priv->rect;
 443
 444         return 0;
 445 }
 446
 447 static int ov6650_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 448 {
 449         struct i2c_client *client = v4l2_get_subdevdata(sd);
 450         struct ov6650 *priv = to_ov6650(client);
 451         struct v4l2_rect *rect = &a->c;
 452         int ret;
 453
 454         if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 455                 return -EINVAL;
 456
 457         rect->left   = ALIGN(rect->left,   2);
 458         rect->width  = ALIGN(rect->width,  2);
 459         rect->top    = ALIGN(rect->top,    2);
 460         rect->height = ALIGN(rect->height, 2);
 461         soc_camera_limit_side(&rect->left, &rect->width,
 462                         DEF_HSTRT << 1, 2, W_CIF);
 463         soc_camera_limit_side(&rect->top, &rect->height,
 464                         DEF_VSTRT << 1, 2, H_CIF);
 465
 466         ret = ov6650_reg_write(client, REG_HSTRT, rect->left >> 1);
 467         if (!ret) {
 468                 priv->rect.left = rect->left;
 469                 ret = ov6650_reg_write(client, REG_HSTOP,
 470                                 (rect->left + rect->width) >> 1);
 471         }
 472         if (!ret) {
 473                 priv->rect.width = rect->width;
 474                 ret = ov6650_reg_write(client, REG_VSTRT, rect->top >> 1);
 475         }
 476         if (!ret) {
 477                 priv->rect.top = rect->top;
 478                 ret = ov6650_reg_write(client, REG_VSTOP,
 479                                 (rect->top + rect->height) >> 1);
 480         }
 481         if (!ret)
 482                 priv->rect.height = rect->height;
 483
 484         return ret;
 485 }
 486
 487 static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
 488 {
 489         if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 490                 return -EINVAL;
 491
 492         a->bounds.left                  = DEF_HSTRT << 1;
 493         a->bounds.top                   = DEF_VSTRT << 1;
 494         a->bounds.width                 = W_CIF;
 495         a->bounds.height                = H_CIF;
 496         a->defrect                      = a->bounds;
 497         a->pixelaspect.numerator        = 1;
 498         a->pixelaspect.denominator      = 1;
 499
 500         return 0;
 501 }
 502
 503 static int ov6650_g_fmt(struct v4l2_subdev *sd,
 504                          struct v4l2_mbus_framefmt *mf)
 505 {
 506         struct i2c_client *client = v4l2_get_subdevdata(sd);
 507         struct ov6650 *priv = to_ov6650(client);
 508
 509         mf->width       = priv->rect.width >> priv->half_scale;
 510         mf->height      = priv->rect.height >> priv->half_scale;
 511         mf->code        = priv->code;
 512         mf->colorspace  = priv->colorspace;
 513         mf->field       = V4L2_FIELD_NONE;
 514
 515         return 0;
 516 }
 517
 518 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
 519 {
 520         return width > rect->width >> 1 || height > rect->height >> 1;
 521 }
 522
 523 static u8 to_clkrc(struct v4l2_fract *timeperframe,
 524                 unsigned long pclk_limit, unsigned long pclk_max)
 525 {
 526         unsigned long pclk;
 527
 528         if (timeperframe->numerator && timeperframe->denominator)
 529                 pclk = pclk_max * timeperframe->denominator /
 530                                 (FRAME_RATE_MAX * timeperframe->numerator);
 531         else
 532                 pclk = pclk_max;
 533
 534         if (pclk_limit && pclk_limit < pclk)
 535                 pclk = pclk_limit;
 536
 537         return (pclk_max - 1) / pclk;
 538 }
 539
 540 /* set the format we will capture in */
 541 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
 542 {
 543         struct i2c_client *client = v4l2_get_subdevdata(sd);
 544         struct soc_camera_device *icd = client->dev.platform_data;
 545         struct soc_camera_sense *sense = icd->sense;
 546         struct ov6650 *priv = to_ov6650(client);
 547         bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
 548         struct v4l2_crop a = {
 549                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
 550                 .c = {
 551                         .left   = priv->rect.left + (priv->rect.width >> 1) -
 552                                         (mf->width >> (1 - half_scale)),
 553                         .top    = priv->rect.top + (priv->rect.height >> 1) -
 554                                         (mf->height >> (1 - half_scale)),
 555                         .width  = mf->width << half_scale,
 556                         .height = mf->height << half_scale,
 557                 },
 558         };
 559         enum v4l2_mbus_pixelcode code = mf->code;
 560         unsigned long mclk, pclk;
 561         u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
 562         int ret;
 563
 564         /* select color matrix configuration for given color encoding */
 565         switch (code) {
 566         case V4L2_MBUS_FMT_Y8_1X8:
 567                 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
 568                 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
 569                 coma_set |= COMA_BW;
 570                 break;
 571         case V4L2_MBUS_FMT_YUYV8_2X8:
 572                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
 573                 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
 574                 coma_set |= COMA_WORD_SWAP;
 575                 break;
 576         case V4L2_MBUS_FMT_YVYU8_2X8:
 577                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
 578                 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
 579                                 COMA_BYTE_SWAP;
 580                 break;
 581         case V4L2_MBUS_FMT_UYVY8_2X8:
 582                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
 583                 if (half_scale) {
 584                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 585                         coma_set |= COMA_BYTE_SWAP;
 586                 } else {
 587                         coma_mask |= COMA_RGB | COMA_BW;
 588                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 589                 }
 590                 break;
 591         case V4L2_MBUS_FMT_VYUY8_2X8:
 592                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
 593                 if (half_scale) {
 594                         coma_mask |= COMA_RGB | COMA_BW;
 595                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 596                 } else {
 597                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 598                         coma_set |= COMA_BYTE_SWAP;
 599                 }
 600                 break;
 601         case V4L2_MBUS_FMT_SBGGR8_1X8:
 602                 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
 603                 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
 604                 coma_set |= COMA_RAW_RGB | COMA_RGB;
 605                 break;
 606         default:
 607                 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
 608                 return -EINVAL;
 609         }
 610         priv->code = code;
 611
 612         if (code == V4L2_MBUS_FMT_Y8_1X8 ||
 613                         code == V4L2_MBUS_FMT_SBGGR8_1X8) {
 614                 coml_mask = COML_ONE_CHANNEL;
 615                 coml_set = 0;
 616                 priv->pclk_max = 4000000;
 617         } else {
 618                 coml_mask = 0;
 619                 coml_set = COML_ONE_CHANNEL;
 620                 priv->pclk_max = 8000000;
 621         }
 622
 623         if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
 624                 priv->colorspace = V4L2_COLORSPACE_SRGB;
 625         else if (code != 0)
 626                 priv->colorspace = V4L2_COLORSPACE_JPEG;
 627
 628         if (half_scale) {
 629                 dev_dbg(&client->dev, "max resolution: QCIF\n");
 630                 coma_set |= COMA_QCIF;
 631                 priv->pclk_max /= 2;
 632         } else {
 633                 dev_dbg(&client->dev, "max resolution: CIF\n");
 634                 coma_mask |= COMA_QCIF;
 635         }
 636         priv->half_scale = half_scale;
 637
 638         if (sense) {
 639                 if (sense->master_clock == 8000000) {
 640                         dev_dbg(&client->dev, "8MHz input clock\n");
 641                         clkrc = CLKRC_6MHz;
 642                 } else if (sense->master_clock == 12000000) {
 643                         dev_dbg(&client->dev, "12MHz input clock\n");
 644                         clkrc = CLKRC_12MHz;
 645                 } else if (sense->master_clock == 16000000) {
 646                         dev_dbg(&client->dev, "16MHz input clock\n");
 647                         clkrc = CLKRC_16MHz;
 648                 } else if (sense->master_clock == 24000000) {
 649                         dev_dbg(&client->dev, "24MHz input clock\n");
 650                         clkrc = CLKRC_24MHz;
 651                 } else {
 652                         dev_err(&client->dev,
 653                                 "unspported input clock, check platform data\n");
 654                         return -EINVAL;
 655                 }
 656                 mclk = sense->master_clock;
 657                 priv->pclk_limit = sense->pixel_clock_max;
 658         } else {
 659                 clkrc = CLKRC_24MHz;
 660                 mclk = 24000000;
 661                 priv->pclk_limit = 0;
 662                 dev_dbg(&client->dev, "using default 24MHz input clock\n");
 663         }
 664
 665         clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 666
 667         pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
 668         dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
 669                         mclk / pclk, 10 * mclk % pclk / pclk);
 670
 671         ret = ov6650_s_crop(sd, &a);
 672         if (!ret)
 673                 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
 674         if (!ret)
 675                 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
 676         if (!ret)
 677                 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
 678
 679         if (!ret) {
 680                 mf->colorspace  = priv->colorspace;
 681                 mf->width = priv->rect.width >> half_scale;
 682                 mf->height = priv->rect.height >> half_scale;
 683         }
 684
 685         return ret;
 686 }
 687
 688 static int ov6650_try_fmt(struct v4l2_subdev *sd,
 689                           struct v4l2_mbus_framefmt *mf)
 690 {
 691         struct i2c_client *client = v4l2_get_subdevdata(sd);
 692         struct ov6650 *priv = to_ov6650(client);
 693
 694         if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
 695                 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
 696                                 &mf->height, 2, H_CIF, 1, 0);
 697
 698         mf->field = V4L2_FIELD_NONE;
 699
 700         switch (mf->code) {
 701         case V4L2_MBUS_FMT_Y10_1X10:
 702                 mf->code = V4L2_MBUS_FMT_Y8_1X8;
 703         case V4L2_MBUS_FMT_Y8_1X8:
 704         case V4L2_MBUS_FMT_YVYU8_2X8:
 705         case V4L2_MBUS_FMT_YUYV8_2X8:
 706         case V4L2_MBUS_FMT_VYUY8_2X8:
 707         case V4L2_MBUS_FMT_UYVY8_2X8:
 708                 mf->colorspace = V4L2_COLORSPACE_JPEG;
 709                 break;
 710         default:
 711                 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
 712         case V4L2_MBUS_FMT_SBGGR8_1X8:
 713                 mf->colorspace = V4L2_COLORSPACE_SRGB;
 714                 break;
 715         }
 716
 717         return 0;
 718 }
 719
 720 static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
 721                            enum v4l2_mbus_pixelcode *code)
 722 {
 723         if (index >= ARRAY_SIZE(ov6650_codes))
 724                 return -EINVAL;
 725
 726         *code = ov6650_codes[index];
 727         return 0;
 728 }
 729
 730 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
 731 {
 732         struct i2c_client *client = v4l2_get_subdevdata(sd);
 733         struct ov6650 *priv = to_ov6650(client);
 734         struct v4l2_captureparm *cp = &parms->parm.capture;
 735
 736         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 737                 return -EINVAL;
 738
 739         memset(cp, 0, sizeof(*cp));
 740         cp->capability = V4L2_CAP_TIMEPERFRAME;
 741         cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
 742                         priv->pclk_limit, priv->pclk_max));
 743         cp->timeperframe.denominator = FRAME_RATE_MAX;
 744
 745         dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
 746                 cp->timeperframe.numerator, cp->timeperframe.denominator);
 747
 748         return 0;
 749 }
 750
 751 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
 752 {
 753         struct i2c_client *client = v4l2_get_subdevdata(sd);
 754         struct ov6650 *priv = to_ov6650(client);
 755         struct v4l2_captureparm *cp = &parms->parm.capture;
 756         struct v4l2_fract *tpf = &cp->timeperframe;
 757         int div, ret;
 758         u8 clkrc;
 759
 760         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 761                 return -EINVAL;
 762
 763         if (cp->extendedmode != 0)
 764                 return -EINVAL;
 765
 766         if (tpf->numerator == 0 || tpf->denominator == 0)
 767                 div = 1;  /* Reset to full rate */
 768         else
 769                 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
 770
 771         if (div == 0)
 772                 div = 1;
 773         else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
 774                 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
 775
 776         /*
 777          * Keep result to be used as tpf limit
 778          * for subseqent clock divider calculations
 779          */
 780         priv->tpf.numerator = div;
 781         priv->tpf.denominator = FRAME_RATE_MAX;
 782
 783         clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 784
 785         ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
 786         if (!ret) {
 787                 tpf->numerator = GET_CLKRC_DIV(clkrc);
 788                 tpf->denominator = FRAME_RATE_MAX;
 789         }
 790
 791         return ret;
 792 }
 793
 794 /* Soft reset the camera. This has nothing to do with the RESET pin! */
 795 static int ov6650_reset(struct i2c_client *client)
 796 {
 797         int ret;
 798
 799         dev_dbg(&client->dev, "reset\n");
 800
 801         ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
 802         if (ret)
 803                 dev_err(&client->dev,
 804                         "An error occurred while entering soft reset!\n");
 805
 806         return ret;
 807 }
 808
 809 /* program default register values */
 810 static int ov6650_prog_dflt(struct i2c_client *client)
 811 {
 812         int ret;
 813
 814         dev_dbg(&client->dev, "initializing\n");
 815
 816         ret = ov6650_reg_write(client, REG_COMA, 0);    /* ~COMA_RESET */
 817         if (!ret)
 818                 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
 819
 820         return ret;
 821 }
 822
 823 static int ov6650_video_probe(struct soc_camera_device *icd,
 824                                 struct i2c_client *client)
 825 {
 826         u8              pidh, pidl, midh, midl;
 827         int             ret = 0;
 828
 829         /*
 830          * check and show product ID and manufacturer ID
 831          */
 832         ret = ov6650_reg_read(client, REG_PIDH, &pidh);
 833         if (!ret)
 834                 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
 835         if (!ret)
 836                 ret = ov6650_reg_read(client, REG_MIDH, &midh);
 837         if (!ret)
 838                 ret = ov6650_reg_read(client, REG_MIDL, &midl);
 839
 840         if (ret)
 841                 return ret;
 842
 843         if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
 844                 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
 845                                 pidh, pidl);
 846                 return -ENODEV;
 847         }
 848
 849         dev_info(&client->dev,
 850                 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
 851                 pidh, pidl, midh, midl);
 852
 853         ret = ov6650_reset(client);
 854         if (!ret)
 855                 ret = ov6650_prog_dflt(client);
 856
 857         return ret;
 858 }
 859
 860 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
 861         .g_volatile_ctrl = ov6550_g_volatile_ctrl,
 862         .s_ctrl = ov6550_s_ctrl,
 863 };
 864
 865 static struct v4l2_subdev_core_ops ov6650_core_ops = {
 866         .g_chip_ident           = ov6650_g_chip_ident,
 867 #ifdef CONFIG_VIDEO_ADV_DEBUG
 868         .g_register             = ov6650_get_register,
 869         .s_register             = ov6650_set_register,
 870 #endif
 871 };
 872
 873 /* Request bus settings on camera side */
 874 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
 875                                 struct v4l2_mbus_config *cfg)
 876 {
 877         struct i2c_client *client = v4l2_get_subdevdata(sd);
 878         struct soc_camera_device *icd = client->dev.platform_data;
 879         struct soc_camera_link *icl = to_soc_camera_link(icd);
 880
 881         cfg->flags = V4L2_MBUS_MASTER |
 882                 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
 883                 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
 884                 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
 885                 V4L2_MBUS_DATA_ACTIVE_HIGH;
 886         cfg->type = V4L2_MBUS_PARALLEL;
 887         cfg->flags = soc_camera_apply_board_flags(icl, cfg);
 888
 889         return 0;
 890 }
 891
 892 /* Alter bus settings on camera side */
 893 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
 894                                 const struct v4l2_mbus_config *cfg)
 895 {
 896         struct i2c_client *client = v4l2_get_subdevdata(sd);
 897         struct soc_camera_device *icd = client->dev.platform_data;
 898         struct soc_camera_link *icl = to_soc_camera_link(icd);
 899         unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
 900         int ret;
 901
 902         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 903                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
 904         else
 905                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
 906         if (ret)
 907                 return ret;
 908
 909         if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 910                 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
 911         else
 912                 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
 913         if (ret)
 914                 return ret;
 915
 916         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 917                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
 918         else
 919                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
 920
 921         return ret;
 922 }
 923
 924 static struct v4l2_subdev_video_ops ov6650_video_ops = {
 925         .s_stream       = ov6650_s_stream,
 926         .g_mbus_fmt     = ov6650_g_fmt,
 927         .s_mbus_fmt     = ov6650_s_fmt,
 928         .try_mbus_fmt   = ov6650_try_fmt,
 929         .enum_mbus_fmt  = ov6650_enum_fmt,
 930         .cropcap        = ov6650_cropcap,
 931         .g_crop         = ov6650_g_crop,
 932         .s_crop         = ov6650_s_crop,
 933         .g_parm         = ov6650_g_parm,
 934         .s_parm         = ov6650_s_parm,
 935         .g_mbus_config  = ov6650_g_mbus_config,
 936         .s_mbus_config  = ov6650_s_mbus_config,
 937 };
 938
 939 static struct v4l2_subdev_ops ov6650_subdev_ops = {
 940         .core   = &ov6650_core_ops,
 941         .video  = &ov6650_video_ops,
 942 };
 943
 944 /*
 945  * i2c_driver function
 946  */
 947 static int ov6650_probe(struct i2c_client *client,
 948                         const struct i2c_device_id *did)
 949 {
 950         struct ov6650 *priv;
 951         struct soc_camera_device *icd = client->dev.platform_data;
 952         struct soc_camera_link *icl;
 953         int ret;
 954
 955         if (!icd) {
 956                 dev_err(&client->dev, "Missing soc-camera data!\n");
 957                 return -EINVAL;
 958         }
 959
 960         icl = to_soc_camera_link(icd);
 961         if (!icl) {
 962                 dev_err(&client->dev, "Missing platform_data for driver\n");
 963                 return -EINVAL;
 964         }
 965
 966         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 967         if (!priv) {
 968                 dev_err(&client->dev,
 969                         "Failed to allocate memory for private data!\n");
 970                 return -ENOMEM;
 971         }
 972
 973         v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
 974         v4l2_ctrl_handler_init(&priv->hdl, 13);
 975         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 976                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 977         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 978                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 979         priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 980                         V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
 981         priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 982                         V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
 983         priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 984                         V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
 985         priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 986                         V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
 987         priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 988                         V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
 989         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 990                         V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
 991         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 992                         V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
 993         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 994                         V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
 995         priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
 996                         &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
 997                         V4L2_EXPOSURE_AUTO);
 998         priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 999                         V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1000         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1001                         V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1002
1003         priv->subdev.ctrl_handler = &priv->hdl;
1004         if (priv->hdl.error) {
1005                 int err = priv->hdl.error;
1006
1007                 kfree(priv);
1008                 return err;
1009         }
1010         v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1011         v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1012         v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1013                                 V4L2_EXPOSURE_MANUAL, true);
1014
1015         priv->rect.left   = DEF_HSTRT << 1;
1016         priv->rect.top    = DEF_VSTRT << 1;
1017         priv->rect.width  = W_CIF;
1018         priv->rect.height = H_CIF;
1019         priv->half_scale  = false;
1020         priv->code        = V4L2_MBUS_FMT_YUYV8_2X8;
1021         priv->colorspace  = V4L2_COLORSPACE_JPEG;
1022
1023         ret = ov6650_video_probe(icd, client);
1024         if (!ret)
1025                 ret = v4l2_ctrl_handler_setup(&priv->hdl);
1026
1027         if (ret) {
1028                 v4l2_ctrl_handler_free(&priv->hdl);
1029                 kfree(priv);
1030         }
1031
1032         return ret;
1033 }
1034
1035 static int ov6650_remove(struct i2c_client *client)
1036 {
1037         struct ov6650 *priv = to_ov6650(client);
1038
1039         v4l2_device_unregister_subdev(&priv->subdev);
1040         v4l2_ctrl_handler_free(&priv->hdl);
1041         kfree(priv);
1042         return 0;
1043 }
1044
1045 static const struct i2c_device_id ov6650_id[] = {
1046         { "ov6650", 0 },
1047         { }
1048 };
1049 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1050
1051 static struct i2c_driver ov6650_i2c_driver = {
1052         .driver = {
1053                 .name = "ov6650",
1054         },
1055         .probe    = ov6650_probe,
1056         .remove   = ov6650_remove,
1057         .id_table = ov6650_id,
1058 };
1059
1060 static int __init ov6650_module_init(void)
1061 {
1062         return i2c_add_driver(&ov6650_i2c_driver);
1063 }
1064
1065 static void __exit ov6650_module_exit(void)
1066 {
1067         i2c_del_driver(&ov6650_i2c_driver);
1068 }
1069
1070 module_init(ov6650_module_init);
1071 module_exit(ov6650_module_exit);
1072
1073 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1074 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1075 MODULE_LICENSE("GPL v2");