drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/time.h>
  27 #include <linux/sched.h>
  28 #include <linux/delay.h>
  29 #include <linux/errno.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/i2c-pxa.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/err.h>
  34 #include <linux/clk.h>
  35 #include <linux/slab.h>
  36 #include <linux/io.h>
  37
  38 #include <asm/irq.h>
  39 #include <plat/i2c.h>
  40
  41 /*
  42  * I2C register offsets will be shifted 0 or 1 bit left, depending on
  43  * different SoCs
  44  */
  45 #define REG_SHIFT_0     (0 << 0)
  46 #define REG_SHIFT_1     (1 << 0)
  47 #define REG_SHIFT(d)    ((d) & 0x1)
  48
  49 static const struct platform_device_id i2c_pxa_id_table[] = {
  50         { "pxa2xx-i2c",         REG_SHIFT_1 },
  51         { "pxa3xx-pwri2c",      REG_SHIFT_0 },
  52         { },
  53 };
  54 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
  55
  56 /*
  57  * I2C registers and bit definitions
  58  */
  59 #define IBMR            (0x00)
  60 #define IDBR            (0x08)
  61 #define ICR             (0x10)
  62 #define ISR             (0x18)
  63 #define ISAR            (0x20)
  64
  65 #define ICR_START       (1 << 0)           /* start bit */
  66 #define ICR_STOP        (1 << 1)           /* stop bit */
  67 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  68 #define ICR_TB          (1 << 3)           /* transfer byte bit */
  69 #define ICR_MA          (1 << 4)           /* master abort */
  70 #define ICR_SCLE        (1 << 5)           /* master clock enable */
  71 #define ICR_IUE         (1 << 6)           /* unit enable */
  72 #define ICR_GCD         (1 << 7)           /* general call disable */
  73 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
  74 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
  75 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
  76 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
  77 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
  78 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
  79 #define ICR_UR          (1 << 14)          /* unit reset */
  80 #define ICR_FM          (1 << 15)          /* fast mode */
  81
  82 #define ISR_RWM         (1 << 0)           /* read/write mode */
  83 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
  84 #define ISR_UB          (1 << 2)           /* unit busy */
  85 #define ISR_IBB         (1 << 3)           /* bus busy */
  86 #define ISR_SSD         (1 << 4)           /* slave stop detected */
  87 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
  88 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
  89 #define ISR_IRF         (1 << 7)           /* rx buffer full */
  90 #define ISR_GCAD        (1 << 8)           /* general call address detected */
  91 #define ISR_SAD         (1 << 9)           /* slave address detected */
  92 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
  93
  94 struct pxa_i2c {
  95         spinlock_t              lock;
  96         wait_queue_head_t       wait;
  97         struct i2c_msg          *msg;
  98         unsigned int            msg_num;
  99         unsigned int            msg_idx;
 100         unsigned int            msg_ptr;
 101         unsigned int            slave_addr;
 102
 103         struct i2c_adapter      adap;
 104         struct clk              *clk;
 105 #ifdef CONFIG_I2C_PXA_SLAVE
 106         struct i2c_slave_client *slave;
 107 #endif
 108
 109         unsigned int            irqlogidx;
 110         u32                     isrlog[32];
 111         u32                     icrlog[32];
 112
 113         void __iomem            *reg_base;
 114         unsigned int            reg_shift;
 115
 116         unsigned long           iobase;
 117         unsigned long           iosize;
 118
 119         int                     irq;
 120         unsigned int            use_pio :1;
 121         unsigned int            fast_mode :1;
 122 };
 123
 124 #define _IBMR(i2c)      ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
 125 #define _IDBR(i2c)      ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
 126 #define _ICR(i2c)       ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
 127 #define _ISR(i2c)       ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
 128 #define _ISAR(i2c)      ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
 129
 130 /*
 131  * I2C Slave mode address
 132  */
 133 #define I2C_PXA_SLAVE_ADDR      0x1
 134
 135 #ifdef DEBUG
 136
 137 struct bits {
 138         u32     mask;
 139         const char *set;
 140         const char *unset;
 141 };
 142 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 143
 144 static inline void
 145 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 146 {
 147         printk("%s %08x: ", prefix, val);
 148         while (num--) {
 149                 const char *str = val & bits->mask ? bits->set : bits->unset;
 150                 if (str)
 151                         printk("%s ", str);
 152                 bits++;
 153         }
 154 }
 155
 156 static const struct bits isr_bits[] = {
 157         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 158         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 159         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 160         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 161         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 162         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 163         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 164         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 165         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 166         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 167         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 168 };
 169
 170 static void decode_ISR(unsigned int val)
 171 {
 172         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 173         printk("\n");
 174 }
 175
 176 static const struct bits icr_bits[] = {
 177         PXA_BIT(ICR_START,  "START",    NULL),
 178         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 179         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 180         PXA_BIT(ICR_TB,     "TB",       NULL),
 181         PXA_BIT(ICR_MA,     "MA",       NULL),
 182         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 183         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 184         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 185         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 186         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 187         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 188         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 189         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 190         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 191         PXA_BIT(ICR_UR,     "UR",               "ur"),
 192 };
 193
 194 #ifdef CONFIG_I2C_PXA_SLAVE
 195 static void decode_ICR(unsigned int val)
 196 {
 197         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 198         printk("\n");
 199 }
 200 #endif
 201
 202 static unsigned int i2c_debug = DEBUG;
 203
 204 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 205 {
 206         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 207                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 208 }
 209
 210 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 211
 212 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 213 {
 214         unsigned int i;
 215         printk(KERN_ERR "i2c: error: %s\n", why);
 216         printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 217                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 218         printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
 219                readl(_ICR(i2c)), readl(_ISR(i2c)));
 220         printk(KERN_DEBUG "i2c: log: ");
 221         for (i = 0; i < i2c->irqlogidx; i++)
 222                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 223         printk("\n");
 224 }
 225
 226 #else /* ifdef DEBUG */
 227
 228 #define i2c_debug       0
 229
 230 #define show_state(i2c) do { } while (0)
 231 #define decode_ISR(val) do { } while (0)
 232 #define decode_ICR(val) do { } while (0)
 233 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 234
 235 #endif /* ifdef DEBUG / else */
 236
 237 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 238 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 239
 240 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 241 {
 242         return !(readl(_ICR(i2c)) & ICR_SCLE);
 243 }
 244
 245 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 246 {
 247         int i = 250;
 248
 249         if (i2c_pxa_is_slavemode(i2c)) {
 250                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 251                 return;
 252         }
 253
 254         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 255                 unsigned long icr = readl(_ICR(i2c));
 256
 257                 icr &= ~ICR_START;
 258                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 259
 260                 writel(icr, _ICR(i2c));
 261
 262                 show_state(i2c);
 263
 264                 mdelay(1);
 265                 i --;
 266         }
 267
 268         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 269                _ICR(i2c));
 270 }
 271
 272 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 273 {
 274         int timeout = DEF_TIMEOUT;
 275
 276         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 277                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 278                         timeout += 4;
 279
 280                 msleep(2);
 281                 show_state(i2c);
 282         }
 283
 284         if (timeout < 0)
 285                 show_state(i2c);
 286
 287         return timeout < 0 ? I2C_RETRY : 0;
 288 }
 289
 290 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 291 {
 292         unsigned long timeout = jiffies + HZ*4;
 293
 294         while (time_before(jiffies, timeout)) {
 295                 if (i2c_debug > 1)
 296                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 297                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 298
 299                 if (readl(_ISR(i2c)) & ISR_SAD) {
 300                         if (i2c_debug > 0)
 301                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 302                         goto out;
 303                 }
 304
 305                 /* wait for unit and bus being not busy, and we also do a
 306                  * quick check of the i2c lines themselves to ensure they've
 307                  * gone high...
 308                  */
 309                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 310                         if (i2c_debug > 0)
 311                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 312                         return 1;
 313                 }
 314
 315                 msleep(1);
 316         }
 317
 318         if (i2c_debug > 0)
 319                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 320  out:
 321         return 0;
 322 }
 323
 324 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 325 {
 326         if (i2c_debug)
 327                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 328
 329         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 330                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 331                 if (!i2c_pxa_wait_master(i2c)) {
 332                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 333                         return I2C_RETRY;
 334                 }
 335         }
 336
 337         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 338         return 0;
 339 }
 340
 341 #ifdef CONFIG_I2C_PXA_SLAVE
 342 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 343 {
 344         unsigned long timeout = jiffies + HZ*1;
 345
 346         /* wait for stop */
 347
 348         show_state(i2c);
 349
 350         while (time_before(jiffies, timeout)) {
 351                 if (i2c_debug > 1)
 352                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 353                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 354
 355                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 356                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 357                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 358                         if (i2c_debug > 1)
 359                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 360                         return 1;
 361                 }
 362
 363                 msleep(1);
 364         }
 365
 366         if (i2c_debug > 0)
 367                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 368         return 0;
 369 }
 370
 371 /*
 372  * clear the hold on the bus, and take of anything else
 373  * that has been configured
 374  */
 375 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 376 {
 377         show_state(i2c);
 378
 379         if (errcode < 0) {
 380                 udelay(100);   /* simple delay */
 381         } else {
 382                 /* we need to wait for the stop condition to end */
 383
 384                 /* if we where in stop, then clear... */
 385                 if (readl(_ICR(i2c)) & ICR_STOP) {
 386                         udelay(100);
 387                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 388                 }
 389
 390                 if (!i2c_pxa_wait_slave(i2c)) {
 391                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 392                                 __func__);
 393                         return;
 394                 }
 395         }
 396
 397         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 398         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 399
 400         if (i2c_debug) {
 401                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 402                 decode_ICR(readl(_ICR(i2c)));
 403         }
 404 }
 405 #else
 406 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 407 #endif
 408
 409 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 410 {
 411         pr_debug("Resetting I2C Controller Unit\n");
 412
 413         /* abort any transfer currently under way */
 414         i2c_pxa_abort(i2c);
 415
 416         /* reset according to 9.8 */
 417         writel(ICR_UR, _ICR(i2c));
 418         writel(I2C_ISR_INIT, _ISR(i2c));
 419         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 420
 421         writel(i2c->slave_addr, _ISAR(i2c));
 422
 423         /* set control register values */
 424         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 425
 426 #ifdef CONFIG_I2C_PXA_SLAVE
 427         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 428         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 429 #endif
 430
 431         i2c_pxa_set_slave(i2c, 0);
 432
 433         /* enable unit */
 434         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 435         udelay(100);
 436 }
 437
 438
 439 #ifdef CONFIG_I2C_PXA_SLAVE
 440 /*
 441  * PXA I2C Slave mode
 442  */
 443
 444 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 445 {
 446         if (isr & ISR_BED) {
 447                 /* what should we do here? */
 448         } else {
 449                 int ret = 0;
 450
 451                 if (i2c->slave != NULL)
 452                         ret = i2c->slave->read(i2c->slave->data);
 453
 454                 writel(ret, _IDBR(i2c));
 455                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 456         }
 457 }
 458
 459 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 460 {
 461         unsigned int byte = readl(_IDBR(i2c));
 462
 463         if (i2c->slave != NULL)
 464                 i2c->slave->write(i2c->slave->data, byte);
 465
 466         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 467 }
 468
 469 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 470 {
 471         int timeout;
 472
 473         if (i2c_debug > 0)
 474                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 475                        (isr & ISR_RWM) ? 'r' : 't');
 476
 477         if (i2c->slave != NULL)
 478                 i2c->slave->event(i2c->slave->data,
 479                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 480
 481         /*
 482          * slave could interrupt in the middle of us generating a
 483          * start condition... if this happens, we'd better back off
 484          * and stop holding the poor thing up
 485          */
 486         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 487         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 488
 489         timeout = 0x10000;
 490
 491         while (1) {
 492                 if ((readl(_IBMR(i2c)) & 2) == 2)
 493                         break;
 494
 495                 timeout--;
 496
 497                 if (timeout <= 0) {
 498                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 499                         break;
 500                 }
 501         }
 502
 503         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 504 }
 505
 506 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 507 {
 508         if (i2c_debug > 2)
 509                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 510
 511         if (i2c->slave != NULL)
 512                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 513
 514         if (i2c_debug > 2)
 515                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 516
 517         /*
 518          * If we have a master-mode message waiting,
 519          * kick it off now that the slave has completed.
 520          */
 521         if (i2c->msg)
 522                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 523 }
 524 #else
 525 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 526 {
 527         if (isr & ISR_BED) {
 528                 /* what should we do here? */
 529         } else {
 530                 writel(0, _IDBR(i2c));
 531                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 532         }
 533 }
 534
 535 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 536 {
 537         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 538 }
 539
 540 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 541 {
 542         int timeout;
 543
 544         /*
 545          * slave could interrupt in the middle of us generating a
 546          * start condition... if this happens, we'd better back off
 547          * and stop holding the poor thing up
 548          */
 549         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 550         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 551
 552         timeout = 0x10000;
 553
 554         while (1) {
 555                 if ((readl(_IBMR(i2c)) & 2) == 2)
 556                         break;
 557
 558                 timeout--;
 559
 560                 if (timeout <= 0) {
 561                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 562                         break;
 563                 }
 564         }
 565
 566         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 567 }
 568
 569 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 570 {
 571         if (i2c->msg)
 572                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 573 }
 574 #endif
 575
 576 /*
 577  * PXA I2C Master mode
 578  */
 579
 580 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 581 {
 582         unsigned int addr = (msg->addr & 0x7f) << 1;
 583
 584         if (msg->flags & I2C_M_RD)
 585                 addr |= 1;
 586
 587         return addr;
 588 }
 589
 590 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 591 {
 592         u32 icr;
 593
 594         /*
 595          * Step 1: target slave address into IDBR
 596          */
 597         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 598
 599         /*
 600          * Step 2: initiate the write.
 601          */
 602         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 603         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 604 }
 605
 606 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 607 {
 608         u32 icr;
 609
 610         /*
 611          * Clear the STOP and ACK flags
 612          */
 613         icr = readl(_ICR(i2c));
 614         icr &= ~(ICR_STOP | ICR_ACKNAK);
 615         writel(icr, _ICR(i2c));
 616 }
 617
 618 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 619 {
 620         /* make timeout the same as for interrupt based functions */
 621         long timeout = 2 * DEF_TIMEOUT;
 622
 623         /*
 624          * Wait for the bus to become free.
 625          */
 626         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 627                 udelay(1000);
 628                 show_state(i2c);
 629         }
 630
 631         if (timeout < 0) {
 632                 show_state(i2c);
 633                 dev_err(&i2c->adap.dev,
 634                         "i2c_pxa: timeout waiting for bus free\n");
 635                 return I2C_RETRY;
 636         }
 637
 638         /*
 639          * Set master mode.
 640          */
 641         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 642
 643         return 0;
 644 }
 645
 646 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 647                                struct i2c_msg *msg, int num)
 648 {
 649         unsigned long timeout = 500000; /* 5 seconds */
 650         int ret = 0;
 651
 652         ret = i2c_pxa_pio_set_master(i2c);
 653         if (ret)
 654                 goto out;
 655
 656         i2c->msg = msg;
 657         i2c->msg_num = num;
 658         i2c->msg_idx = 0;
 659         i2c->msg_ptr = 0;
 660         i2c->irqlogidx = 0;
 661
 662         i2c_pxa_start_message(i2c);
 663
 664         while (i2c->msg_num > 0 && --timeout) {
 665                 i2c_pxa_handler(0, i2c);
 666                 udelay(10);
 667         }
 668
 669         i2c_pxa_stop_message(i2c);
 670
 671         /*
 672          * We place the return code in i2c->msg_idx.
 673          */
 674         ret = i2c->msg_idx;
 675
 676 out:
 677         if (timeout == 0)
 678                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 679
 680         return ret;
 681 }
 682
 683 /*
 684  * We are protected by the adapter bus mutex.
 685  */
 686 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 687 {
 688         long timeout;
 689         int ret;
 690
 691         /*
 692          * Wait for the bus to become free.
 693          */
 694         ret = i2c_pxa_wait_bus_not_busy(i2c);
 695         if (ret) {
 696                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 697                 goto out;
 698         }
 699
 700         /*
 701          * Set master mode.
 702          */
 703         ret = i2c_pxa_set_master(i2c);
 704         if (ret) {
 705                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 706                 goto out;
 707         }
 708
 709         spin_lock_irq(&i2c->lock);
 710
 711         i2c->msg = msg;
 712         i2c->msg_num = num;
 713         i2c->msg_idx = 0;
 714         i2c->msg_ptr = 0;
 715         i2c->irqlogidx = 0;
 716
 717         i2c_pxa_start_message(i2c);
 718
 719         spin_unlock_irq(&i2c->lock);
 720
 721         /*
 722          * The rest of the processing occurs in the interrupt handler.
 723          */
 724         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 725         i2c_pxa_stop_message(i2c);
 726
 727         /*
 728          * We place the return code in i2c->msg_idx.
 729          */
 730         ret = i2c->msg_idx;
 731
 732         if (timeout == 0)
 733                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 734
 735  out:
 736         return ret;
 737 }
 738
 739 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 740                             struct i2c_msg msgs[], int num)
 741 {
 742         struct pxa_i2c *i2c = adap->algo_data;
 743         int ret, i;
 744
 745         /* If the I2C controller is disabled we need to reset it
 746           (probably due to a suspend/resume destroying state). We do
 747           this here as we can then avoid worrying about resuming the
 748           controller before its users. */
 749         if (!(readl(_ICR(i2c)) & ICR_IUE))
 750                 i2c_pxa_reset(i2c);
 751
 752         for (i = adap->retries; i >= 0; i--) {
 753                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 754                 if (ret != I2C_RETRY)
 755                         goto out;
 756
 757                 if (i2c_debug)
 758                         dev_dbg(&adap->dev, "Retrying transmission\n");
 759                 udelay(100);
 760         }
 761         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 762         ret = -EREMOTEIO;
 763  out:
 764         i2c_pxa_set_slave(i2c, ret);
 765         return ret;
 766 }
 767
 768 /*
 769  * i2c_pxa_master_complete - complete the message and wake up.
 770  */
 771 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 772 {
 773         i2c->msg_ptr = 0;
 774         i2c->msg = NULL;
 775         i2c->msg_idx ++;
 776         i2c->msg_num = 0;
 777         if (ret)
 778                 i2c->msg_idx = ret;
 779         if (!i2c->use_pio)
 780                 wake_up(&i2c->wait);
 781 }
 782
 783 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 784 {
 785         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 786
 787  again:
 788         /*
 789          * If ISR_ALD is set, we lost arbitration.
 790          */
 791         if (isr & ISR_ALD) {
 792                 /*
 793                  * Do we need to do anything here?  The PXA docs
 794                  * are vague about what happens.
 795                  */
 796                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 797
 798                 /*
 799                  * We ignore this error.  We seem to see spurious ALDs
 800                  * for seemingly no reason.  If we handle them as I think
 801                  * they should, we end up causing an I2C error, which
 802                  * is painful for some systems.
 803                  */
 804                 return; /* ignore */
 805         }
 806
 807         if (isr & ISR_BED) {
 808                 int ret = BUS_ERROR;
 809
 810                 /*
 811                  * I2C bus error - either the device NAK'd us, or
 812                  * something more serious happened.  If we were NAK'd
 813                  * on the initial address phase, we can retry.
 814                  */
 815                 if (isr & ISR_ACKNAK) {
 816                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 817                                 ret = I2C_RETRY;
 818                         else
 819                                 ret = XFER_NAKED;
 820                 }
 821                 i2c_pxa_master_complete(i2c, ret);
 822         } else if (isr & ISR_RWM) {
 823                 /*
 824                  * Read mode.  We have just sent the address byte, and
 825                  * now we must initiate the transfer.
 826                  */
 827                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 828                     i2c->msg_idx == i2c->msg_num - 1)
 829                         icr |= ICR_STOP | ICR_ACKNAK;
 830
 831                 icr |= ICR_ALDIE | ICR_TB;
 832         } else if (i2c->msg_ptr < i2c->msg->len) {
 833                 /*
 834                  * Write mode.  Write the next data byte.
 835                  */
 836                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 837
 838                 icr |= ICR_ALDIE | ICR_TB;
 839
 840                 /*
 841                  * If this is the last byte of the last message, send
 842                  * a STOP.
 843                  */
 844                 if (i2c->msg_ptr == i2c->msg->len &&
 845                     i2c->msg_idx == i2c->msg_num - 1)
 846                         icr |= ICR_STOP;
 847         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 848                 /*
 849                  * Next segment of the message.
 850                  */
 851                 i2c->msg_ptr = 0;
 852                 i2c->msg_idx ++;
 853                 i2c->msg++;
 854
 855                 /*
 856                  * If we aren't doing a repeated start and address,
 857                  * go back and try to send the next byte.  Note that
 858                  * we do not support switching the R/W direction here.
 859                  */
 860                 if (i2c->msg->flags & I2C_M_NOSTART)
 861                         goto again;
 862
 863                 /*
 864                  * Write the next address.
 865                  */
 866                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 867
 868                 /*
 869                  * And trigger a repeated start, and send the byte.
 870                  */
 871                 icr &= ~ICR_ALDIE;
 872                 icr |= ICR_START | ICR_TB;
 873         } else {
 874                 if (i2c->msg->len == 0) {
 875                         /*
 876                          * Device probes have a message length of zero
 877                          * and need the bus to be reset before it can
 878                          * be used again.
 879                          */
 880                         i2c_pxa_reset(i2c);
 881                 }
 882                 i2c_pxa_master_complete(i2c, 0);
 883         }
 884
 885         i2c->icrlog[i2c->irqlogidx-1] = icr;
 886
 887         writel(icr, _ICR(i2c));
 888         show_state(i2c);
 889 }
 890
 891 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 892 {
 893         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 894
 895         /*
 896          * Read the byte.
 897          */
 898         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 899
 900         if (i2c->msg_ptr < i2c->msg->len) {
 901                 /*
 902                  * If this is the last byte of the last
 903                  * message, send a STOP.
 904                  */
 905                 if (i2c->msg_ptr == i2c->msg->len - 1)
 906                         icr |= ICR_STOP | ICR_ACKNAK;
 907
 908                 icr |= ICR_ALDIE | ICR_TB;
 909         } else {
 910                 i2c_pxa_master_complete(i2c, 0);
 911         }
 912
 913         i2c->icrlog[i2c->irqlogidx-1] = icr;
 914
 915         writel(icr, _ICR(i2c));
 916 }
 917
 918 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 919 {
 920         struct pxa_i2c *i2c = dev_id;
 921         u32 isr = readl(_ISR(i2c));
 922
 923         if (i2c_debug > 2 && 0) {
 924                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 925                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 926                 decode_ISR(isr);
 927         }
 928
 929         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 930                 i2c->isrlog[i2c->irqlogidx++] = isr;
 931
 932         show_state(i2c);
 933
 934         /*
 935          * Always clear all pending IRQs.
 936          */
 937         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
 938
 939         if (isr & ISR_SAD)
 940                 i2c_pxa_slave_start(i2c, isr);
 941         if (isr & ISR_SSD)
 942                 i2c_pxa_slave_stop(i2c);
 943
 944         if (i2c_pxa_is_slavemode(i2c)) {
 945                 if (isr & ISR_ITE)
 946                         i2c_pxa_slave_txempty(i2c, isr);
 947                 if (isr & ISR_IRF)
 948                         i2c_pxa_slave_rxfull(i2c, isr);
 949         } else if (i2c->msg) {
 950                 if (isr & ISR_ITE)
 951                         i2c_pxa_irq_txempty(i2c, isr);
 952                 if (isr & ISR_IRF)
 953                         i2c_pxa_irq_rxfull(i2c, isr);
 954         } else {
 955                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 956         }
 957
 958         return IRQ_HANDLED;
 959 }
 960
 961
 962 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 963 {
 964         struct pxa_i2c *i2c = adap->algo_data;
 965         int ret, i;
 966
 967         for (i = adap->retries; i >= 0; i--) {
 968                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 969                 if (ret != I2C_RETRY)
 970                         goto out;
 971
 972                 if (i2c_debug)
 973                         dev_dbg(&adap->dev, "Retrying transmission\n");
 974                 udelay(100);
 975         }
 976         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 977         ret = -EREMOTEIO;
 978  out:
 979         i2c_pxa_set_slave(i2c, ret);
 980         return ret;
 981 }
 982
 983 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
 984 {
 985         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 986 }
 987
 988 static const struct i2c_algorithm i2c_pxa_algorithm = {
 989         .master_xfer    = i2c_pxa_xfer,
 990         .functionality  = i2c_pxa_functionality,
 991 };
 992
 993 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 994         .master_xfer    = i2c_pxa_pio_xfer,
 995         .functionality  = i2c_pxa_functionality,
 996 };
 997
 998 static int i2c_pxa_probe(struct platform_device *dev)
 999 {
1000         struct pxa_i2c *i2c;
1001         struct resource *res;
1002         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1003         const struct platform_device_id *id = platform_get_device_id(dev);
1004         int ret;
1005         int irq;
1006
1007         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1008         irq = platform_get_irq(dev, 0);
1009         if (res == NULL || irq < 0)
1010                 return -ENODEV;
1011
1012         if (!request_mem_region(res->start, resource_size(res), res->name))
1013                 return -ENOMEM;
1014
1015         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1016         if (!i2c) {
1017                 ret = -ENOMEM;
1018                 goto emalloc;
1019         }
1020
1021         i2c->adap.owner   = THIS_MODULE;
1022         i2c->adap.retries = 5;
1023
1024         spin_lock_init(&i2c->lock);
1025         init_waitqueue_head(&i2c->wait);
1026
1027         /*
1028          * If "dev->id" is negative we consider it as zero.
1029          * The reason to do so is to avoid sysfs names that only make
1030          * sense when there are multiple adapters.
1031          */
1032         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1033         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1034                  i2c->adap.nr);
1035
1036         i2c->clk = clk_get(&dev->dev, NULL);
1037         if (IS_ERR(i2c->clk)) {
1038                 ret = PTR_ERR(i2c->clk);
1039                 goto eclk;
1040         }
1041
1042         i2c->reg_base = ioremap(res->start, resource_size(res));
1043         if (!i2c->reg_base) {
1044                 ret = -EIO;
1045                 goto eremap;
1046         }
1047         i2c->reg_shift = REG_SHIFT(id->driver_data);
1048
1049         i2c->iobase = res->start;
1050         i2c->iosize = resource_size(res);
1051
1052         i2c->irq = irq;
1053
1054         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1055
1056 #ifdef CONFIG_I2C_PXA_SLAVE
1057         if (plat) {
1058                 i2c->slave_addr = plat->slave_addr;
1059                 i2c->slave = plat->slave;
1060         }
1061 #endif
1062
1063         clk_enable(i2c->clk);
1064
1065         if (plat) {
1066                 i2c->adap.class = plat->class;
1067                 i2c->use_pio = plat->use_pio;
1068                 i2c->fast_mode = plat->fast_mode;
1069         }
1070
1071         if (i2c->use_pio) {
1072                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1073         } else {
1074                 i2c->adap.algo = &i2c_pxa_algorithm;
1075                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1076                                   i2c->adap.name, i2c);
1077                 if (ret)
1078                         goto ereqirq;
1079         }
1080
1081         i2c_pxa_reset(i2c);
1082
1083         i2c->adap.algo_data = i2c;
1084         i2c->adap.dev.parent = &dev->dev;
1085
1086         ret = i2c_add_numbered_adapter(&i2c->adap);
1087         if (ret < 0) {
1088                 printk(KERN_INFO "I2C: Failed to add bus\n");
1089                 goto eadapt;
1090         }
1091
1092         platform_set_drvdata(dev, i2c);
1093
1094 #ifdef CONFIG_I2C_PXA_SLAVE
1095         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1096                dev_name(&i2c->adap.dev), i2c->slave_addr);
1097 #else
1098         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1099                dev_name(&i2c->adap.dev));
1100 #endif
1101         return 0;
1102
1103 eadapt:
1104         if (!i2c->use_pio)
1105                 free_irq(irq, i2c);
1106 ereqirq:
1107         clk_disable(i2c->clk);
1108         iounmap(i2c->reg_base);
1109 eremap:
1110         clk_put(i2c->clk);
1111 eclk:
1112         kfree(i2c);
1113 emalloc:
1114         release_mem_region(res->start, resource_size(res));
1115         return ret;
1116 }
1117
1118 static int __exit i2c_pxa_remove(struct platform_device *dev)
1119 {
1120         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1121
1122         platform_set_drvdata(dev, NULL);
1123
1124         i2c_del_adapter(&i2c->adap);
1125         if (!i2c->use_pio)
1126                 free_irq(i2c->irq, i2c);
1127
1128         clk_disable(i2c->clk);
1129         clk_put(i2c->clk);
1130
1131         iounmap(i2c->reg_base);
1132         release_mem_region(i2c->iobase, i2c->iosize);
1133         kfree(i2c);
1134
1135         return 0;
1136 }
1137
1138 #ifdef CONFIG_PM
1139 static int i2c_pxa_suspend_noirq(struct device *dev)
1140 {
1141         struct platform_device *pdev = to_platform_device(dev);
1142         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1143
1144         clk_disable(i2c->clk);
1145
1146         return 0;
1147 }
1148
1149 static int i2c_pxa_resume_noirq(struct device *dev)
1150 {
1151         struct platform_device *pdev = to_platform_device(dev);
1152         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1153
1154         clk_enable(i2c->clk);
1155         i2c_pxa_reset(i2c);
1156
1157         return 0;
1158 }
1159
1160 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1161         .suspend_noirq = i2c_pxa_suspend_noirq,
1162         .resume_noirq = i2c_pxa_resume_noirq,
1163 };
1164
1165 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1166 #else
1167 #define I2C_PXA_DEV_PM_OPS NULL
1168 #endif
1169
1170 static struct platform_driver i2c_pxa_driver = {
1171         .probe          = i2c_pxa_probe,
1172         .remove         = __exit_p(i2c_pxa_remove),
1173         .driver         = {
1174                 .name   = "pxa2xx-i2c",
1175                 .owner  = THIS_MODULE,
1176                 .pm     = I2C_PXA_DEV_PM_OPS,
1177         },
1178         .id_table       = i2c_pxa_id_table,
1179 };
1180
1181 static int __init i2c_adap_pxa_init(void)
1182 {
1183         return platform_driver_register(&i2c_pxa_driver);
1184 }
1185
1186 static void __exit i2c_adap_pxa_exit(void)
1187 {
1188         platform_driver_unregister(&i2c_pxa_driver);
1189 }
1190
1191 MODULE_LICENSE("GPL");
1192 MODULE_ALIAS("platform:pxa2xx-i2c");
1193
1194 subsys_initcall(i2c_adap_pxa_init);
1195 module_exit(i2c_adap_pxa_exit);