2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
54 Features supported by this driver:
58 Block process call transaction no
59 I2C block read transaction yes (doesn't use the block buffer)
62 See the file Documentation/i2c/busses/i2c-i801 for details.
65 #include <linux/module.h>
66 #include <linux/pci.h>
67 #include <linux/kernel.h>
68 #include <linux/stddef.h>
69 #include <linux/delay.h>
70 #include <linux/ioport.h>
71 #include <linux/init.h>
72 #include <linux/i2c.h>
73 #include <linux/acpi.h>
75 #include <linux/dmi.h>
76 #include <linux/slab.h>
78 /* I801 SMBus address offsets */
79 #define SMBHSTSTS(p) (0 + (p)->smba)
80 #define SMBHSTCNT(p) (2 + (p)->smba)
81 #define SMBHSTCMD(p) (3 + (p)->smba)
82 #define SMBHSTADD(p) (4 + (p)->smba)
83 #define SMBHSTDAT0(p) (5 + (p)->smba)
84 #define SMBHSTDAT1(p) (6 + (p)->smba)
85 #define SMBBLKDAT(p) (7 + (p)->smba)
86 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
87 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
88 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
90 /* PCI Address Constants */
92 #define SMBHSTCFG 0x040
94 /* Host configuration bits for SMBHSTCFG */
95 #define SMBHSTCFG_HST_EN 1
96 #define SMBHSTCFG_SMB_SMI_EN 2
97 #define SMBHSTCFG_I2C_EN 4
99 /* Auxiliary control register bits, ICH4+ only */
100 #define SMBAUXCTL_CRC 1
101 #define SMBAUXCTL_E32B 2
103 /* kill bit for SMBHSTCNT */
104 #define SMBHSTCNT_KILL 2
107 #define MAX_TIMEOUT 100
108 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
110 /* I801 command constants */
111 #define I801_QUICK 0x00
112 #define I801_BYTE 0x04
113 #define I801_BYTE_DATA 0x08
114 #define I801_WORD_DATA 0x0C
115 #define I801_PROC_CALL 0x10 /* unimplemented */
116 #define I801_BLOCK_DATA 0x14
117 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
118 #define I801_BLOCK_LAST 0x34
119 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
120 #define I801_START 0x40
121 #define I801_PEC_EN 0x80 /* ICH3 and later */
123 /* I801 Hosts Status register bits */
124 #define SMBHSTSTS_BYTE_DONE 0x80
125 #define SMBHSTSTS_INUSE_STS 0x40
126 #define SMBHSTSTS_SMBALERT_STS 0x20
127 #define SMBHSTSTS_FAILED 0x10
128 #define SMBHSTSTS_BUS_ERR 0x08
129 #define SMBHSTSTS_DEV_ERR 0x04
130 #define SMBHSTSTS_INTR 0x02
131 #define SMBHSTSTS_HOST_BUSY 0x01
133 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
134 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
137 /* Older devices have their ID defined in <linux/pci_ids.h> */
138 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
139 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
140 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
141 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
144 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
145 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
148 struct i2c_adapter adapter;
150 unsigned char original_hstcfg;
151 struct pci_dev *pci_dev;
152 unsigned int features;
155 static struct pci_driver i801_driver;
157 #define FEATURE_SMBUS_PEC (1 << 0)
158 #define FEATURE_BLOCK_BUFFER (1 << 1)
159 #define FEATURE_BLOCK_PROC (1 << 2)
160 #define FEATURE_I2C_BLOCK_READ (1 << 3)
162 static const char *i801_feature_names[] = {
165 "Block process call",
169 static unsigned int disable_features;
170 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
171 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
173 /* Make sure the SMBus host is ready to start transmitting.
174 Return 0 if it is, -EBUSY if it is not. */
175 static int i801_check_pre(struct i801_priv *priv)
179 status = inb_p(SMBHSTSTS(priv));
180 if (status & SMBHSTSTS_HOST_BUSY) {
181 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
185 status &= STATUS_FLAGS;
187 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
189 outb_p(status, SMBHSTSTS(priv));
190 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
192 dev_err(&priv->pci_dev->dev,
193 "Failed clearing status flags (%02x)\n",
202 /* Convert the status register to an error code, and clear it. */
203 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
207 /* If the SMBus is still busy, we give up */
209 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
210 /* try to stop the current command */
211 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
212 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
215 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
218 /* Check if it worked */
219 status = inb_p(SMBHSTSTS(priv));
220 if ((status & SMBHSTSTS_HOST_BUSY) ||
221 !(status & SMBHSTSTS_FAILED))
222 dev_err(&priv->pci_dev->dev,
223 "Failed terminating the transaction\n");
224 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
228 if (status & SMBHSTSTS_FAILED) {
230 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
232 if (status & SMBHSTSTS_DEV_ERR) {
234 dev_dbg(&priv->pci_dev->dev, "No response\n");
236 if (status & SMBHSTSTS_BUS_ERR) {
238 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
242 /* Clear error flags */
243 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
244 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
246 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
247 "flags at end of transaction (%02x)\n",
255 static int i801_transaction(struct i801_priv *priv, int xact)
261 result = i801_check_pre(priv);
265 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
266 * INTREN, SMBSCMD are passed in xact */
267 outb_p(xact | I801_START, SMBHSTCNT(priv));
269 /* We will always wait for a fraction of a second! */
272 status = inb_p(SMBHSTSTS(priv));
273 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
275 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
279 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
283 /* wait for INTR bit as advised by Intel */
284 static void i801_wait_hwpec(struct i801_priv *priv)
291 status = inb_p(SMBHSTSTS(priv));
292 } while ((!(status & SMBHSTSTS_INTR))
293 && (timeout++ < MAX_TIMEOUT));
295 if (timeout > MAX_TIMEOUT)
296 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
298 outb_p(status, SMBHSTSTS(priv));
301 static int i801_block_transaction_by_block(struct i801_priv *priv,
302 union i2c_smbus_data *data,
303 char read_write, int hwpec)
308 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
310 /* Use 32-byte buffer to process this transaction */
311 if (read_write == I2C_SMBUS_WRITE) {
312 len = data->block[0];
313 outb_p(len, SMBHSTDAT0(priv));
314 for (i = 0; i < len; i++)
315 outb_p(data->block[i+1], SMBBLKDAT(priv));
318 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
319 I801_PEC_EN * hwpec);
323 if (read_write == I2C_SMBUS_READ) {
324 len = inb_p(SMBHSTDAT0(priv));
325 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
328 data->block[0] = len;
329 for (i = 0; i < len; i++)
330 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
335 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
336 union i2c_smbus_data *data,
337 char read_write, int command,
346 result = i801_check_pre(priv);
350 len = data->block[0];
352 if (read_write == I2C_SMBUS_WRITE) {
353 outb_p(len, SMBHSTDAT0(priv));
354 outb_p(data->block[1], SMBBLKDAT(priv));
357 for (i = 1; i <= len; i++) {
358 if (i == len && read_write == I2C_SMBUS_READ) {
359 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
360 smbcmd = I801_I2C_BLOCK_LAST;
362 smbcmd = I801_BLOCK_LAST;
364 if (command == I2C_SMBUS_I2C_BLOCK_DATA
365 && read_write == I2C_SMBUS_READ)
366 smbcmd = I801_I2C_BLOCK_DATA;
368 smbcmd = I801_BLOCK_DATA;
370 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
373 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
376 /* We will always wait for a fraction of a second! */
380 status = inb_p(SMBHSTSTS(priv));
381 } while ((!(status & SMBHSTSTS_BYTE_DONE))
382 && (timeout++ < MAX_TIMEOUT));
384 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
388 if (i == 1 && read_write == I2C_SMBUS_READ
389 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
390 len = inb_p(SMBHSTDAT0(priv));
391 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
392 dev_err(&priv->pci_dev->dev,
393 "Illegal SMBus block read size %d\n",
396 while (inb_p(SMBHSTSTS(priv)) &
398 outb_p(SMBHSTSTS_BYTE_DONE,
400 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
403 data->block[0] = len;
406 /* Retrieve/store value in SMBBLKDAT */
407 if (read_write == I2C_SMBUS_READ)
408 data->block[i] = inb_p(SMBBLKDAT(priv));
409 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
410 outb_p(data->block[i+1], SMBBLKDAT(priv));
412 /* signals SMBBLKDAT ready */
413 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
419 static int i801_set_block_buffer_mode(struct i801_priv *priv)
421 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
422 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
427 /* Block transaction function */
428 static int i801_block_transaction(struct i801_priv *priv,
429 union i2c_smbus_data *data, char read_write,
430 int command, int hwpec)
435 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
436 if (read_write == I2C_SMBUS_WRITE) {
437 /* set I2C_EN bit in configuration register */
438 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
439 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
440 hostc | SMBHSTCFG_I2C_EN);
441 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
442 dev_err(&priv->pci_dev->dev,
443 "I2C block read is unsupported!\n");
448 if (read_write == I2C_SMBUS_WRITE
449 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
450 if (data->block[0] < 1)
452 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
453 data->block[0] = I2C_SMBUS_BLOCK_MAX;
455 data->block[0] = 32; /* max for SMBus block reads */
458 /* Experience has shown that the block buffer can only be used for
459 SMBus (not I2C) block transactions, even though the datasheet
460 doesn't mention this limitation. */
461 if ((priv->features & FEATURE_BLOCK_BUFFER)
462 && command != I2C_SMBUS_I2C_BLOCK_DATA
463 && i801_set_block_buffer_mode(priv) == 0)
464 result = i801_block_transaction_by_block(priv, data,
467 result = i801_block_transaction_byte_by_byte(priv, data,
471 if (result == 0 && hwpec)
472 i801_wait_hwpec(priv);
474 if (command == I2C_SMBUS_I2C_BLOCK_DATA
475 && read_write == I2C_SMBUS_WRITE) {
476 /* restore saved configuration register value */
477 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
482 /* Return negative errno on error. */
483 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
484 unsigned short flags, char read_write, u8 command,
485 int size, union i2c_smbus_data *data)
490 struct i801_priv *priv = i2c_get_adapdata(adap);
492 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
493 && size != I2C_SMBUS_QUICK
494 && size != I2C_SMBUS_I2C_BLOCK_DATA;
497 case I2C_SMBUS_QUICK:
498 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
503 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
505 if (read_write == I2C_SMBUS_WRITE)
506 outb_p(command, SMBHSTCMD(priv));
509 case I2C_SMBUS_BYTE_DATA:
510 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
512 outb_p(command, SMBHSTCMD(priv));
513 if (read_write == I2C_SMBUS_WRITE)
514 outb_p(data->byte, SMBHSTDAT0(priv));
515 xact = I801_BYTE_DATA;
517 case I2C_SMBUS_WORD_DATA:
518 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
520 outb_p(command, SMBHSTCMD(priv));
521 if (read_write == I2C_SMBUS_WRITE) {
522 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
523 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
525 xact = I801_WORD_DATA;
527 case I2C_SMBUS_BLOCK_DATA:
528 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
530 outb_p(command, SMBHSTCMD(priv));
533 case I2C_SMBUS_I2C_BLOCK_DATA:
534 /* NB: page 240 of ICH5 datasheet shows that the R/#W
535 * bit should be cleared here, even when reading */
536 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
537 if (read_write == I2C_SMBUS_READ) {
538 /* NB: page 240 of ICH5 datasheet also shows
539 * that DATA1 is the cmd field when reading */
540 outb_p(command, SMBHSTDAT1(priv));
542 outb_p(command, SMBHSTCMD(priv));
546 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
551 if (hwpec) /* enable/disable hardware PEC */
552 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
554 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
558 ret = i801_block_transaction(priv, data, read_write, size,
561 ret = i801_transaction(priv, xact | ENABLE_INT9);
563 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
564 time, so we forcibly disable it after every transaction. Turn off
565 E32B for the same reason. */
567 outb_p(inb_p(SMBAUXCTL(priv)) &
568 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
574 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
577 switch (xact & 0x7f) {
578 case I801_BYTE: /* Result put in SMBHSTDAT0 */
580 data->byte = inb_p(SMBHSTDAT0(priv));
583 data->word = inb_p(SMBHSTDAT0(priv)) +
584 (inb_p(SMBHSTDAT1(priv)) << 8);
591 static u32 i801_func(struct i2c_adapter *adapter)
593 struct i801_priv *priv = i2c_get_adapdata(adapter);
595 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
596 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
597 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
598 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
599 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
600 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
603 static const struct i2c_algorithm smbus_algorithm = {
604 .smbus_xfer = i801_access,
605 .functionality = i801_func,
608 static const struct pci_device_id i801_ids[] = {
609 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
610 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
634 MODULE_DEVICE_TABLE(pci, i801_ids);
636 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
637 static unsigned char apanel_addr;
639 /* Scan the system ROM for the signature "FJKEYINF" */
640 static __init const void __iomem *bios_signature(const void __iomem *bios)
643 const unsigned char signature[] = "FJKEYINF";
645 for (offset = 0; offset < 0x10000; offset += 0x10) {
646 if (check_signature(bios + offset, signature,
647 sizeof(signature)-1))
648 return bios + offset;
653 static void __init input_apanel_init(void)
656 const void __iomem *p;
658 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
659 p = bios_signature(bios);
661 /* just use the first address */
662 apanel_addr = readb(p + 8 + 3) >> 1;
667 static void __init input_apanel_init(void) {}
670 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
671 struct dmi_onboard_device_info {
674 unsigned short i2c_addr;
675 const char *i2c_type;
678 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
679 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
680 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
681 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
684 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
685 struct i2c_adapter *adap)
688 struct i2c_board_info info;
690 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
691 /* & ~0x80, ignore enabled/disabled bit */
692 if ((type & ~0x80) != dmi_devices[i].type)
694 if (strcasecmp(name, dmi_devices[i].name))
697 memset(&info, 0, sizeof(struct i2c_board_info));
698 info.addr = dmi_devices[i].i2c_addr;
699 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
700 i2c_new_device(adap, &info);
705 /* We use our own function to check for onboard devices instead of
706 dmi_find_device() as some buggy BIOS's have the devices we are interested
707 in marked as disabled */
708 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
716 count = (dm->length - sizeof(struct dmi_header)) / 2;
717 for (i = 0; i < count; i++) {
718 const u8 *d = (char *)(dm + 1) + (i * 2);
719 const char *name = ((char *) dm) + dm->length;
726 while (s > 0 && name[0]) {
727 name += strlen(name) + 1;
730 if (name[0] == 0) /* Bogus string reference */
733 dmi_check_onboard_device(type, name, adap);
738 static int __devinit i801_probe(struct pci_dev *dev,
739 const struct pci_device_id *id)
743 struct i801_priv *priv;
745 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
749 i2c_set_adapdata(&priv->adapter, priv);
750 priv->adapter.owner = THIS_MODULE;
751 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
752 priv->adapter.algo = &smbus_algorithm;
755 switch (dev->device) {
757 priv->features |= FEATURE_I2C_BLOCK_READ;
759 case PCI_DEVICE_ID_INTEL_82801DB_3:
760 priv->features |= FEATURE_SMBUS_PEC;
761 priv->features |= FEATURE_BLOCK_BUFFER;
763 case PCI_DEVICE_ID_INTEL_82801CA_3:
764 case PCI_DEVICE_ID_INTEL_82801BA_2:
765 case PCI_DEVICE_ID_INTEL_82801AB_3:
766 case PCI_DEVICE_ID_INTEL_82801AA_3:
770 /* Disable features on user request */
771 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
772 if (priv->features & disable_features & (1 << i))
773 dev_notice(&dev->dev, "%s disabled by user\n",
774 i801_feature_names[i]);
776 priv->features &= ~disable_features;
778 err = pci_enable_device(dev);
780 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
785 /* Determine the address of the SMBus area */
786 priv->smba = pci_resource_start(dev, SMBBAR);
788 dev_err(&dev->dev, "SMBus base address uninitialized, "
794 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
800 err = pci_request_region(dev, SMBBAR, i801_driver.name);
802 dev_err(&dev->dev, "Failed to request SMBus region "
803 "0x%lx-0x%Lx\n", priv->smba,
804 (unsigned long long)pci_resource_end(dev, SMBBAR));
808 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
809 priv->original_hstcfg = temp;
810 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
811 if (!(temp & SMBHSTCFG_HST_EN)) {
812 dev_info(&dev->dev, "Enabling SMBus device\n");
813 temp |= SMBHSTCFG_HST_EN;
815 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
817 if (temp & SMBHSTCFG_SMB_SMI_EN)
818 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
820 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
822 /* Clear special mode bits */
823 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
824 outb_p(inb_p(SMBAUXCTL(priv)) &
825 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
827 /* set up the sysfs linkage to our parent device */
828 priv->adapter.dev.parent = &dev->dev;
830 /* Retry up to 3 times on lost arbitration */
831 priv->adapter.retries = 3;
833 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
834 "SMBus I801 adapter at %04lx", priv->smba);
835 err = i2c_add_adapter(&priv->adapter);
837 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
841 /* Register optional slaves */
842 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
844 struct i2c_board_info info;
846 memset(&info, 0, sizeof(struct i2c_board_info));
847 info.addr = apanel_addr;
848 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
849 i2c_new_device(&priv->adapter, &info);
852 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
853 if (dmi_name_in_vendors("FUJITSU"))
854 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
857 pci_set_drvdata(dev, priv);
861 pci_release_region(dev, SMBBAR);
867 static void __devexit i801_remove(struct pci_dev *dev)
869 struct i801_priv *priv = pci_get_drvdata(dev);
871 i2c_del_adapter(&priv->adapter);
872 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
873 pci_release_region(dev, SMBBAR);
874 pci_set_drvdata(dev, NULL);
877 * do not call pci_disable_device(dev) since it can cause hard hangs on
878 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
883 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
885 struct i801_priv *priv = pci_get_drvdata(dev);
888 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
889 pci_set_power_state(dev, pci_choose_state(dev, mesg));
893 static int i801_resume(struct pci_dev *dev)
895 pci_set_power_state(dev, PCI_D0);
896 pci_restore_state(dev);
897 return pci_enable_device(dev);
900 #define i801_suspend NULL
901 #define i801_resume NULL
904 static struct pci_driver i801_driver = {
905 .name = "i801_smbus",
906 .id_table = i801_ids,
908 .remove = __devexit_p(i801_remove),
909 .suspend = i801_suspend,
910 .resume = i801_resume,
913 static int __init i2c_i801_init(void)
916 return pci_register_driver(&i801_driver);
919 static void __exit i2c_i801_exit(void)
921 pci_unregister_driver(&i801_driver);
924 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
925 "Jean Delvare <khali@linux-fr.org>");
926 MODULE_DESCRIPTION("I801 SMBus driver");
927 MODULE_LICENSE("GPL");
929 module_init(i2c_i801_init);
930 module_exit(i2c_i801_exit);