drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25  * Supports the following Intel I/O Controller Hubs (ICH):
  26  *
  27  *                                      I/O                     Block   I2C
  28  *                                      region  SMBus   Block   proc.   block
  29  * Chip name                    PCI ID  size    PEC     buffer  call    read
  30  * ---------------------------------------------------------------------------
  31  * 82801AA (ICH)                0x2413  16      no      no      no      no
  32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  44  * ICH10                        0x3a30  32      hard    yes     yes     yes
  45  * ICH10                        0x3a60  32      hard    yes     yes     yes
  46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  65  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  66  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  67  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  68  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  69  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  70  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  71  *
  72  * Features supported by this driver:
  73  * Software PEC                         no
  74  * Hardware PEC                         yes
  75  * Block buffer                         yes
  76  * Block process call transaction       no
  77  * I2C block read transaction           yes (doesn't use the block buffer)
  78  * Slave mode                           no
  79  *
  80  * See the file Documentation/i2c/busses/i2c-i801 for details.
  81  */
  82
  83 #include <linux/module.h>
  84 #include <linux/pci.h>
  85 #include <linux/kernel.h>
  86 #include <linux/stddef.h>
  87 #include <linux/delay.h>
  88 #include <linux/ioport.h>
  89 #include <linux/init.h>
  90 #include <linux/i2c.h>
  91 #include <linux/acpi.h>
  92 #include <linux/io.h>
  93 #include <linux/dmi.h>
  94 #include <linux/slab.h>
  95
  96 /* I801 SMBus address offsets */
  97 #define SMBHSTSTS(p)    (0 + (p)->smba)
  98 #define SMBHSTCNT(p)    (2 + (p)->smba)
  99 #define SMBHSTCMD(p)    (3 + (p)->smba)
 100 #define SMBHSTADD(p)    (4 + (p)->smba)
 101 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 102 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 103 #define SMBBLKDAT(p)    (7 + (p)->smba)
 104 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 105 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 106 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 107
 108 /* PCI Address Constants */
 109 #define SMBBAR          4
 110 #define SMBHSTCFG       0x040
 111
 112 /* Host configuration bits for SMBHSTCFG */
 113 #define SMBHSTCFG_HST_EN        1
 114 #define SMBHSTCFG_SMB_SMI_EN    2
 115 #define SMBHSTCFG_I2C_EN        4
 116
 117 /* Auxiliary control register bits, ICH4+ only */
 118 #define SMBAUXCTL_CRC           1
 119 #define SMBAUXCTL_E32B          2
 120
 121 /* kill bit for SMBHSTCNT */
 122 #define SMBHSTCNT_KILL          2
 123
 124 /* Other settings */
 125 #define MAX_TIMEOUT             100
 126 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 127
 128 /* I801 command constants */
 129 #define I801_QUICK              0x00
 130 #define I801_BYTE               0x04
 131 #define I801_BYTE_DATA          0x08
 132 #define I801_WORD_DATA          0x0C
 133 #define I801_PROC_CALL          0x10    /* unimplemented */
 134 #define I801_BLOCK_DATA         0x14
 135 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 136 #define I801_BLOCK_LAST         0x34
 137 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 138 #define I801_START              0x40
 139 #define I801_PEC_EN             0x80    /* ICH3 and later */
 140
 141 /* I801 Hosts Status register bits */
 142 #define SMBHSTSTS_BYTE_DONE     0x80
 143 #define SMBHSTSTS_INUSE_STS     0x40
 144 #define SMBHSTSTS_SMBALERT_STS  0x20
 145 #define SMBHSTSTS_FAILED        0x10
 146 #define SMBHSTSTS_BUS_ERR       0x08
 147 #define SMBHSTSTS_DEV_ERR       0x04
 148 #define SMBHSTSTS_INTR          0x02
 149 #define SMBHSTSTS_HOST_BUSY     0x01
 150
 151 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 152                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 153                                  SMBHSTSTS_INTR)
 154
 155 /* Older devices have their ID defined in <linux/pci_ids.h> */
 156 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 157 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 158 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 159 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 160 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 161 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 162 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 163 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 164 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 165 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 166 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 167 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 168 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 169 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 170 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 171 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 172 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 173 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 174 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 175 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 176 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 177 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 178 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 179 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 180 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 181 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 182 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 183
 184 struct i801_priv {
 185         struct i2c_adapter adapter;
 186         unsigned long smba;
 187         unsigned char original_hstcfg;
 188         struct pci_dev *pci_dev;
 189         unsigned int features;
 190 };
 191
 192 static struct pci_driver i801_driver;
 193
 194 #define FEATURE_SMBUS_PEC       (1 << 0)
 195 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 196 #define FEATURE_BLOCK_PROC      (1 << 2)
 197 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 198 /* Not really a feature, but it's convenient to handle it as such */
 199 #define FEATURE_IDF             (1 << 15)
 200
 201 static const char *i801_feature_names[] = {
 202         "SMBus PEC",
 203         "Block buffer",
 204         "Block process call",
 205         "I2C block read",
 206 };
 207
 208 static unsigned int disable_features;
 209 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 210 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 211
 212 /* Make sure the SMBus host is ready to start transmitting.
 213    Return 0 if it is, -EBUSY if it is not. */
 214 static int i801_check_pre(struct i801_priv *priv)
 215 {
 216         int status;
 217
 218         status = inb_p(SMBHSTSTS(priv));
 219         if (status & SMBHSTSTS_HOST_BUSY) {
 220                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 221                 return -EBUSY;
 222         }
 223
 224         status &= STATUS_FLAGS;
 225         if (status) {
 226                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 227                         status);
 228                 outb_p(status, SMBHSTSTS(priv));
 229                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 230                 if (status) {
 231                         dev_err(&priv->pci_dev->dev,
 232                                 "Failed clearing status flags (%02x)\n",
 233                                 status);
 234                         return -EBUSY;
 235                 }
 236         }
 237
 238         return 0;
 239 }
 240
 241 /* Convert the status register to an error code, and clear it. */
 242 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 243 {
 244         int result = 0;
 245
 246         /* If the SMBus is still busy, we give up */
 247         if (timeout) {
 248                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 249                 /* try to stop the current command */
 250                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 251                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 252                        SMBHSTCNT(priv));
 253                 msleep(1);
 254                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 255                        SMBHSTCNT(priv));
 256
 257                 /* Check if it worked */
 258                 status = inb_p(SMBHSTSTS(priv));
 259                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 260                     !(status & SMBHSTSTS_FAILED))
 261                         dev_err(&priv->pci_dev->dev,
 262                                 "Failed terminating the transaction\n");
 263                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 264                 return -ETIMEDOUT;
 265         }
 266
 267         if (status & SMBHSTSTS_FAILED) {
 268                 result = -EIO;
 269                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 270         }
 271         if (status & SMBHSTSTS_DEV_ERR) {
 272                 result = -ENXIO;
 273                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 274         }
 275         if (status & SMBHSTSTS_BUS_ERR) {
 276                 result = -EAGAIN;
 277                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 278         }
 279
 280         if (result) {
 281                 /* Clear error flags */
 282                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 283                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 284                 if (status) {
 285                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 286                                  "flags at end of transaction (%02x)\n",
 287                                  status);
 288                 }
 289         }
 290
 291         return result;
 292 }
 293
 294 static int i801_transaction(struct i801_priv *priv, int xact)
 295 {
 296         int status;
 297         int result;
 298         int timeout = 0;
 299
 300         result = i801_check_pre(priv);
 301         if (result < 0)
 302                 return result;
 303
 304         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 305          * INTREN, SMBSCMD are passed in xact */
 306         outb_p(xact | I801_START, SMBHSTCNT(priv));
 307
 308         /* We will always wait for a fraction of a second! */
 309         do {
 310                 msleep(1);
 311                 status = inb_p(SMBHSTSTS(priv));
 312         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 313
 314         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 315         if (result < 0)
 316                 return result;
 317
 318         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 319         return 0;
 320 }
 321
 322 /* wait for INTR bit as advised by Intel */
 323 static void i801_wait_hwpec(struct i801_priv *priv)
 324 {
 325         int timeout = 0;
 326         int status;
 327
 328         do {
 329                 msleep(1);
 330                 status = inb_p(SMBHSTSTS(priv));
 331         } while ((!(status & SMBHSTSTS_INTR))
 332                  && (timeout++ < MAX_TIMEOUT));
 333
 334         if (timeout > MAX_TIMEOUT)
 335                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 336
 337         outb_p(status, SMBHSTSTS(priv));
 338 }
 339
 340 static int i801_block_transaction_by_block(struct i801_priv *priv,
 341                                            union i2c_smbus_data *data,
 342                                            char read_write, int hwpec)
 343 {
 344         int i, len;
 345         int status;
 346
 347         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 348
 349         /* Use 32-byte buffer to process this transaction */
 350         if (read_write == I2C_SMBUS_WRITE) {
 351                 len = data->block[0];
 352                 outb_p(len, SMBHSTDAT0(priv));
 353                 for (i = 0; i < len; i++)
 354                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 355         }
 356
 357         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 358                                   I801_PEC_EN * hwpec);
 359         if (status)
 360                 return status;
 361
 362         if (read_write == I2C_SMBUS_READ) {
 363                 len = inb_p(SMBHSTDAT0(priv));
 364                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 365                         return -EPROTO;
 366
 367                 data->block[0] = len;
 368                 for (i = 0; i < len; i++)
 369                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 370         }
 371         return 0;
 372 }
 373
 374 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 375                                                union i2c_smbus_data *data,
 376                                                char read_write, int command,
 377                                                int hwpec)
 378 {
 379         int i, len;
 380         int smbcmd;
 381         int status;
 382         int result;
 383         int timeout;
 384
 385         result = i801_check_pre(priv);
 386         if (result < 0)
 387                 return result;
 388
 389         len = data->block[0];
 390
 391         if (read_write == I2C_SMBUS_WRITE) {
 392                 outb_p(len, SMBHSTDAT0(priv));
 393                 outb_p(data->block[1], SMBBLKDAT(priv));
 394         }
 395
 396         for (i = 1; i <= len; i++) {
 397                 if (i == len && read_write == I2C_SMBUS_READ) {
 398                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 399                                 smbcmd = I801_I2C_BLOCK_LAST;
 400                         else
 401                                 smbcmd = I801_BLOCK_LAST;
 402                 } else {
 403                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 404                          && read_write == I2C_SMBUS_READ)
 405                                 smbcmd = I801_I2C_BLOCK_DATA;
 406                         else
 407                                 smbcmd = I801_BLOCK_DATA;
 408                 }
 409                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 410
 411                 if (i == 1)
 412                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 413                                SMBHSTCNT(priv));
 414
 415                 /* We will always wait for a fraction of a second! */
 416                 timeout = 0;
 417                 do {
 418                         msleep(1);
 419                         status = inb_p(SMBHSTSTS(priv));
 420                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 421                          && (timeout++ < MAX_TIMEOUT));
 422
 423                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 424                 if (result < 0)
 425                         return result;
 426
 427                 if (i == 1 && read_write == I2C_SMBUS_READ
 428                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 429                         len = inb_p(SMBHSTDAT0(priv));
 430                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 431                                 dev_err(&priv->pci_dev->dev,
 432                                         "Illegal SMBus block read size %d\n",
 433                                         len);
 434                                 /* Recover */
 435                                 while (inb_p(SMBHSTSTS(priv)) &
 436                                        SMBHSTSTS_HOST_BUSY)
 437                                         outb_p(SMBHSTSTS_BYTE_DONE,
 438                                                SMBHSTSTS(priv));
 439                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 440                                 return -EPROTO;
 441                         }
 442                         data->block[0] = len;
 443                 }
 444
 445                 /* Retrieve/store value in SMBBLKDAT */
 446                 if (read_write == I2C_SMBUS_READ)
 447                         data->block[i] = inb_p(SMBBLKDAT(priv));
 448                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 449                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 450
 451                 /* signals SMBBLKDAT ready */
 452                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 459 {
 460         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 461         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 462                 return -EIO;
 463         return 0;
 464 }
 465
 466 /* Block transaction function */
 467 static int i801_block_transaction(struct i801_priv *priv,
 468                                   union i2c_smbus_data *data, char read_write,
 469                                   int command, int hwpec)
 470 {
 471         int result = 0;
 472         unsigned char hostc;
 473
 474         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 475                 if (read_write == I2C_SMBUS_WRITE) {
 476                         /* set I2C_EN bit in configuration register */
 477                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 478                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 479                                               hostc | SMBHSTCFG_I2C_EN);
 480                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 481                         dev_err(&priv->pci_dev->dev,
 482                                 "I2C block read is unsupported!\n");
 483                         return -EOPNOTSUPP;
 484                 }
 485         }
 486
 487         if (read_write == I2C_SMBUS_WRITE
 488          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 489                 if (data->block[0] < 1)
 490                         data->block[0] = 1;
 491                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 492                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 493         } else {
 494                 data->block[0] = 32;    /* max for SMBus block reads */
 495         }
 496
 497         /* Experience has shown that the block buffer can only be used for
 498            SMBus (not I2C) block transactions, even though the datasheet
 499            doesn't mention this limitation. */
 500         if ((priv->features & FEATURE_BLOCK_BUFFER)
 501          && command != I2C_SMBUS_I2C_BLOCK_DATA
 502          && i801_set_block_buffer_mode(priv) == 0)
 503                 result = i801_block_transaction_by_block(priv, data,
 504                                                          read_write, hwpec);
 505         else
 506                 result = i801_block_transaction_byte_by_byte(priv, data,
 507                                                              read_write,
 508                                                              command, hwpec);
 509
 510         if (result == 0 && hwpec)
 511                 i801_wait_hwpec(priv);
 512
 513         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 514          && read_write == I2C_SMBUS_WRITE) {
 515                 /* restore saved configuration register value */
 516                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 517         }
 518         return result;
 519 }
 520
 521 /* Return negative errno on error. */
 522 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 523                        unsigned short flags, char read_write, u8 command,
 524                        int size, union i2c_smbus_data *data)
 525 {
 526         int hwpec;
 527         int block = 0;
 528         int ret, xact = 0;
 529         struct i801_priv *priv = i2c_get_adapdata(adap);
 530
 531         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 532                 && size != I2C_SMBUS_QUICK
 533                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 534
 535         switch (size) {
 536         case I2C_SMBUS_QUICK:
 537                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 538                        SMBHSTADD(priv));
 539                 xact = I801_QUICK;
 540                 break;
 541         case I2C_SMBUS_BYTE:
 542                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 543                        SMBHSTADD(priv));
 544                 if (read_write == I2C_SMBUS_WRITE)
 545                         outb_p(command, SMBHSTCMD(priv));
 546                 xact = I801_BYTE;
 547                 break;
 548         case I2C_SMBUS_BYTE_DATA:
 549                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 550                        SMBHSTADD(priv));
 551                 outb_p(command, SMBHSTCMD(priv));
 552                 if (read_write == I2C_SMBUS_WRITE)
 553                         outb_p(data->byte, SMBHSTDAT0(priv));
 554                 xact = I801_BYTE_DATA;
 555                 break;
 556         case I2C_SMBUS_WORD_DATA:
 557                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 558                        SMBHSTADD(priv));
 559                 outb_p(command, SMBHSTCMD(priv));
 560                 if (read_write == I2C_SMBUS_WRITE) {
 561                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 562                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 563                 }
 564                 xact = I801_WORD_DATA;
 565                 break;
 566         case I2C_SMBUS_BLOCK_DATA:
 567                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 568                        SMBHSTADD(priv));
 569                 outb_p(command, SMBHSTCMD(priv));
 570                 block = 1;
 571                 break;
 572         case I2C_SMBUS_I2C_BLOCK_DATA:
 573                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 574                  * bit should be cleared here, even when reading */
 575                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 576                 if (read_write == I2C_SMBUS_READ) {
 577                         /* NB: page 240 of ICH5 datasheet also shows
 578                          * that DATA1 is the cmd field when reading */
 579                         outb_p(command, SMBHSTDAT1(priv));
 580                 } else
 581                         outb_p(command, SMBHSTCMD(priv));
 582                 block = 1;
 583                 break;
 584         default:
 585                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 586                         size);
 587                 return -EOPNOTSUPP;
 588         }
 589
 590         if (hwpec)      /* enable/disable hardware PEC */
 591                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 592         else
 593                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 594                        SMBAUXCTL(priv));
 595
 596         if (block)
 597                 ret = i801_block_transaction(priv, data, read_write, size,
 598                                              hwpec);
 599         else
 600                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 601
 602         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 603            time, so we forcibly disable it after every transaction. Turn off
 604            E32B for the same reason. */
 605         if (hwpec || block)
 606                 outb_p(inb_p(SMBAUXCTL(priv)) &
 607                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 608
 609         if (block)
 610                 return ret;
 611         if (ret)
 612                 return ret;
 613         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 614                 return 0;
 615
 616         switch (xact & 0x7f) {
 617         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 618         case I801_BYTE_DATA:
 619                 data->byte = inb_p(SMBHSTDAT0(priv));
 620                 break;
 621         case I801_WORD_DATA:
 622                 data->word = inb_p(SMBHSTDAT0(priv)) +
 623                              (inb_p(SMBHSTDAT1(priv)) << 8);
 624                 break;
 625         }
 626         return 0;
 627 }
 628
 629
 630 static u32 i801_func(struct i2c_adapter *adapter)
 631 {
 632         struct i801_priv *priv = i2c_get_adapdata(adapter);
 633
 634         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 635                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 636                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 637                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 638                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 639                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 640 }
 641
 642 static const struct i2c_algorithm smbus_algorithm = {
 643         .smbus_xfer     = i801_access,
 644         .functionality  = i801_func,
 645 };
 646
 647 static const struct pci_device_id i801_ids[] = {
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 663         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 664         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 665         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 666         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 667         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 668         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 669         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 670         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 671         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 672         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 673         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 674         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 675         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 676         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 677         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 678         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 679         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 680         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 681         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 682         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 683         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 684         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
 685         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
 686         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
 687         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
 688         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
 689         { 0, }
 690 };
 691
 692 MODULE_DEVICE_TABLE(pci, i801_ids);
 693
 694 #if defined CONFIG_X86 && defined CONFIG_DMI
 695 static unsigned char apanel_addr;
 696
 697 /* Scan the system ROM for the signature "FJKEYINF" */
 698 static __init const void __iomem *bios_signature(const void __iomem *bios)
 699 {
 700         ssize_t offset;
 701         const unsigned char signature[] = "FJKEYINF";
 702
 703         for (offset = 0; offset < 0x10000; offset += 0x10) {
 704                 if (check_signature(bios + offset, signature,
 705                                     sizeof(signature)-1))
 706                         return bios + offset;
 707         }
 708         return NULL;
 709 }
 710
 711 static void __init input_apanel_init(void)
 712 {
 713         void __iomem *bios;
 714         const void __iomem *p;
 715
 716         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 717         p = bios_signature(bios);
 718         if (p) {
 719                 /* just use the first address */
 720                 apanel_addr = readb(p + 8 + 3) >> 1;
 721         }
 722         iounmap(bios);
 723 }
 724
 725 struct dmi_onboard_device_info {
 726         const char *name;
 727         u8 type;
 728         unsigned short i2c_addr;
 729         const char *i2c_type;
 730 };
 731
 732 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 733         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 734         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 735         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 736 };
 737
 738 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 739                                                struct i2c_adapter *adap)
 740 {
 741         int i;
 742         struct i2c_board_info info;
 743
 744         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 745                 /* & ~0x80, ignore enabled/disabled bit */
 746                 if ((type & ~0x80) != dmi_devices[i].type)
 747                         continue;
 748                 if (strcasecmp(name, dmi_devices[i].name))
 749                         continue;
 750
 751                 memset(&info, 0, sizeof(struct i2c_board_info));
 752                 info.addr = dmi_devices[i].i2c_addr;
 753                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 754                 i2c_new_device(adap, &info);
 755                 break;
 756         }
 757 }
 758
 759 /* We use our own function to check for onboard devices instead of
 760    dmi_find_device() as some buggy BIOS's have the devices we are interested
 761    in marked as disabled */
 762 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 763                                                 void *adap)
 764 {
 765         int i, count;
 766
 767         if (dm->type != 10)
 768                 return;
 769
 770         count = (dm->length - sizeof(struct dmi_header)) / 2;
 771         for (i = 0; i < count; i++) {
 772                 const u8 *d = (char *)(dm + 1) + (i * 2);
 773                 const char *name = ((char *) dm) + dm->length;
 774                 u8 type = d[0];
 775                 u8 s = d[1];
 776
 777                 if (!s)
 778                         continue;
 779                 s--;
 780                 while (s > 0 && name[0]) {
 781                         name += strlen(name) + 1;
 782                         s--;
 783                 }
 784                 if (name[0] == 0) /* Bogus string reference */
 785                         continue;
 786
 787                 dmi_check_onboard_device(type, name, adap);
 788         }
 789 }
 790
 791 /* Register optional slaves */
 792 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 793 {
 794         /* Only register slaves on main SMBus channel */
 795         if (priv->features & FEATURE_IDF)
 796                 return;
 797
 798         if (apanel_addr) {
 799                 struct i2c_board_info info;
 800
 801                 memset(&info, 0, sizeof(struct i2c_board_info));
 802                 info.addr = apanel_addr;
 803                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 804                 i2c_new_device(&priv->adapter, &info);
 805         }
 806
 807         if (dmi_name_in_vendors("FUJITSU"))
 808                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 809 }
 810 #else
 811 static void __init input_apanel_init(void) {}
 812 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 813 #endif  /* CONFIG_X86 && CONFIG_DMI */
 814
 815 static int __devinit i801_probe(struct pci_dev *dev,
 816                                 const struct pci_device_id *id)
 817 {
 818         unsigned char temp;
 819         int err, i;
 820         struct i801_priv *priv;
 821
 822         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 823         if (!priv)
 824                 return -ENOMEM;
 825
 826         i2c_set_adapdata(&priv->adapter, priv);
 827         priv->adapter.owner = THIS_MODULE;
 828         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 829         priv->adapter.algo = &smbus_algorithm;
 830
 831         priv->pci_dev = dev;
 832         switch (dev->device) {
 833         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 834         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 835         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 836         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 837         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 838         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 839                 priv->features |= FEATURE_IDF;
 840                 /* fall through */
 841         default:
 842                 priv->features |= FEATURE_I2C_BLOCK_READ;
 843                 /* fall through */
 844         case PCI_DEVICE_ID_INTEL_82801DB_3:
 845                 priv->features |= FEATURE_SMBUS_PEC;
 846                 priv->features |= FEATURE_BLOCK_BUFFER;
 847                 /* fall through */
 848         case PCI_DEVICE_ID_INTEL_82801CA_3:
 849         case PCI_DEVICE_ID_INTEL_82801BA_2:
 850         case PCI_DEVICE_ID_INTEL_82801AB_3:
 851         case PCI_DEVICE_ID_INTEL_82801AA_3:
 852                 break;
 853         }
 854
 855         /* Disable features on user request */
 856         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 857                 if (priv->features & disable_features & (1 << i))
 858                         dev_notice(&dev->dev, "%s disabled by user\n",
 859                                    i801_feature_names[i]);
 860         }
 861         priv->features &= ~disable_features;
 862
 863         err = pci_enable_device(dev);
 864         if (err) {
 865                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 866                         err);
 867                 goto exit;
 868         }
 869
 870         /* Determine the address of the SMBus area */
 871         priv->smba = pci_resource_start(dev, SMBBAR);
 872         if (!priv->smba) {
 873                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 874                         "upgrade BIOS\n");
 875                 err = -ENODEV;
 876                 goto exit;
 877         }
 878
 879         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 880         if (err) {
 881                 err = -ENODEV;
 882                 goto exit;
 883         }
 884
 885         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 886         if (err) {
 887                 dev_err(&dev->dev, "Failed to request SMBus region "
 888                         "0x%lx-0x%Lx\n", priv->smba,
 889                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 890                 goto exit;
 891         }
 892
 893         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 894         priv->original_hstcfg = temp;
 895         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 896         if (!(temp & SMBHSTCFG_HST_EN)) {
 897                 dev_info(&dev->dev, "Enabling SMBus device\n");
 898                 temp |= SMBHSTCFG_HST_EN;
 899         }
 900         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 901
 902         if (temp & SMBHSTCFG_SMB_SMI_EN)
 903                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 904         else
 905                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 906
 907         /* Clear special mode bits */
 908         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 909                 outb_p(inb_p(SMBAUXCTL(priv)) &
 910                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 911
 912         /* set up the sysfs linkage to our parent device */
 913         priv->adapter.dev.parent = &dev->dev;
 914
 915         /* Retry up to 3 times on lost arbitration */
 916         priv->adapter.retries = 3;
 917
 918         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 919                 "SMBus I801 adapter at %04lx", priv->smba);
 920         err = i2c_add_adapter(&priv->adapter);
 921         if (err) {
 922                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 923                 goto exit_release;
 924         }
 925
 926         i801_probe_optional_slaves(priv);
 927
 928         pci_set_drvdata(dev, priv);
 929         return 0;
 930
 931 exit_release:
 932         pci_release_region(dev, SMBBAR);
 933 exit:
 934         kfree(priv);
 935         return err;
 936 }
 937
 938 static void __devexit i801_remove(struct pci_dev *dev)
 939 {
 940         struct i801_priv *priv = pci_get_drvdata(dev);
 941
 942         i2c_del_adapter(&priv->adapter);
 943         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 944         pci_release_region(dev, SMBBAR);
 945         pci_set_drvdata(dev, NULL);
 946         kfree(priv);
 947         /*
 948          * do not call pci_disable_device(dev) since it can cause hard hangs on
 949          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 950          */
 951 }
 952
 953 #ifdef CONFIG_PM
 954 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 955 {
 956         struct i801_priv *priv = pci_get_drvdata(dev);
 957
 958         pci_save_state(dev);
 959         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 960         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 961         return 0;
 962 }
 963
 964 static int i801_resume(struct pci_dev *dev)
 965 {
 966         pci_set_power_state(dev, PCI_D0);
 967         pci_restore_state(dev);
 968         return pci_enable_device(dev);
 969 }
 970 #else
 971 #define i801_suspend NULL
 972 #define i801_resume NULL
 973 #endif
 974
 975 static struct pci_driver i801_driver = {
 976         .name           = "i801_smbus",
 977         .id_table       = i801_ids,
 978         .probe          = i801_probe,
 979         .remove         = __devexit_p(i801_remove),
 980         .suspend        = i801_suspend,
 981         .resume         = i801_resume,
 982 };
 983
 984 static int __init i2c_i801_init(void)
 985 {
 986         if (dmi_name_in_vendors("FUJITSU"))
 987                 input_apanel_init();
 988         return pci_register_driver(&i801_driver);
 989 }
 990
 991 static void __exit i2c_i801_exit(void)
 992 {
 993         pci_unregister_driver(&i801_driver);
 994 }
 995
 996 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 997               "Jean Delvare <khali@linux-fr.org>");
 998 MODULE_DESCRIPTION("I801 SMBus driver");
 999 MODULE_LICENSE("GPL");
1000
1001 module_init(i2c_i801_init);
1002 module_exit(i2c_i801_exit);