drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  47 {
  48         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  49         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  50
  51         /* Lock the graphics update lock */
  52         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  53         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  54
  55         /* update the scanout addresses */
  56         if (radeon_crtc->crtc_id) {
  57                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  58                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  59         } else {
  60                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  61                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  62         }
  63         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  64                (u32)crtc_base);
  65         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  66                (u32)crtc_base);
  67
  68         /* Wait for update_pending to go high. */
  69         while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
  70         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  71
  72         /* Unlock the lock, so double-buffering can take place inside vblank */
  73         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  74         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* Return current update_pending status: */
  77         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  78 }
  79
  80 /* get temperature in millidegrees */
  81 u32 rv770_get_temp(struct radeon_device *rdev)
  82 {
  83         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  84                 ASIC_T_SHIFT;
  85         u32 actual_temp = 0;
  86
  87         if ((temp >> 9) & 1)
  88                 actual_temp = 0;
  89         else
  90                 actual_temp = (temp >> 1) & 0xff;
  91
  92         return actual_temp * 1000;
  93 }
  94
  95 void rv770_pm_misc(struct radeon_device *rdev)
  96 {
  97         int req_ps_idx = rdev->pm.requested_power_state_index;
  98         int req_cm_idx = rdev->pm.requested_clock_mode_index;
  99         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 100         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 101
 102         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 103                 if (voltage->voltage != rdev->pm.current_vddc) {
 104                         radeon_atom_set_voltage(rdev, voltage->voltage);
 105                         rdev->pm.current_vddc = voltage->voltage;
 106                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 107                 }
 108         }
 109 }
 110
 111 /*
 112  * GART
 113  */
 114 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 115 {
 116         u32 tmp;
 117         int r, i;
 118
 119         if (rdev->gart.table.vram.robj == NULL) {
 120                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 121                 return -EINVAL;
 122         }
 123         r = radeon_gart_table_vram_pin(rdev);
 124         if (r)
 125                 return r;
 126         radeon_gart_restore(rdev);
 127         /* Setup L2 cache */
 128         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 129                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 130                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 131         WREG32(VM_L2_CNTL2, 0);
 132         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 133         /* Setup TLB control */
 134         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 135                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 136                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 137                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 138         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 139         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 140         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 141         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 142         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 143         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 144         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 145         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 146         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 147         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 148         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 149                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 150         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 151                         (u32)(rdev->dummy_page.addr >> 12));
 152         for (i = 1; i < 7; i++)
 153                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 154
 155         r600_pcie_gart_tlb_flush(rdev);
 156         rdev->gart.ready = true;
 157         return 0;
 158 }
 159
 160 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 161 {
 162         u32 tmp;
 163         int i, r;
 164
 165         /* Disable all tables */
 166         for (i = 0; i < 7; i++)
 167                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 168
 169         /* Setup L2 cache */
 170         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 171                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 172         WREG32(VM_L2_CNTL2, 0);
 173         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 174         /* Setup TLB control */
 175         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 176         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 177         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 178         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 179         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 180         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 181         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 182         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 183         if (rdev->gart.table.vram.robj) {
 184                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 185                 if (likely(r == 0)) {
 186                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 187                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 188                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 189                 }
 190         }
 191 }
 192
 193 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 194 {
 195         radeon_gart_fini(rdev);
 196         rv770_pcie_gart_disable(rdev);
 197         radeon_gart_table_vram_free(rdev);
 198 }
 199
 200
 201 void rv770_agp_enable(struct radeon_device *rdev)
 202 {
 203         u32 tmp;
 204         int i;
 205
 206         /* Setup L2 cache */
 207         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 208                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 209                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 210         WREG32(VM_L2_CNTL2, 0);
 211         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 212         /* Setup TLB control */
 213         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 214                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 215                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 216                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 217         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 218         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 219         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 220         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 221         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 222         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 223         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 224         for (i = 0; i < 7; i++)
 225                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 226 }
 227
 228 static void rv770_mc_program(struct radeon_device *rdev)
 229 {
 230         struct rv515_mc_save save;
 231         u32 tmp;
 232         int i, j;
 233
 234         /* Initialize HDP */
 235         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 236                 WREG32((0x2c14 + j), 0x00000000);
 237                 WREG32((0x2c18 + j), 0x00000000);
 238                 WREG32((0x2c1c + j), 0x00000000);
 239                 WREG32((0x2c20 + j), 0x00000000);
 240                 WREG32((0x2c24 + j), 0x00000000);
 241         }
 242         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 243          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 244          */
 245         tmp = RREG32(HDP_DEBUG1);
 246
 247         rv515_mc_stop(rdev, &save);
 248         if (r600_mc_wait_for_idle(rdev)) {
 249                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 250         }
 251         /* Lockout access through VGA aperture*/
 252         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 253         /* Update configuration */
 254         if (rdev->flags & RADEON_IS_AGP) {
 255                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 256                         /* VRAM before AGP */
 257                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 258                                 rdev->mc.vram_start >> 12);
 259                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 260                                 rdev->mc.gtt_end >> 12);
 261                 } else {
 262                         /* VRAM after AGP */
 263                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 264                                 rdev->mc.gtt_start >> 12);
 265                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 266                                 rdev->mc.vram_end >> 12);
 267                 }
 268         } else {
 269                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 270                         rdev->mc.vram_start >> 12);
 271                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 272                         rdev->mc.vram_end >> 12);
 273         }
 274         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 275         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 276         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 277         WREG32(MC_VM_FB_LOCATION, tmp);
 278         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 279         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 280         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 281         if (rdev->flags & RADEON_IS_AGP) {
 282                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 283                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 284                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 285         } else {
 286                 WREG32(MC_VM_AGP_BASE, 0);
 287                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 288                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 289         }
 290         if (r600_mc_wait_for_idle(rdev)) {
 291                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 292         }
 293         rv515_mc_resume(rdev, &save);
 294         /* we need to own VRAM, so turn off the VGA renderer here
 295          * to stop it overwriting our objects */
 296         rv515_vga_render_disable(rdev);
 297 }
 298
 299
 300 /*
 301  * CP.
 302  */
 303 void r700_cp_stop(struct radeon_device *rdev)
 304 {
 305         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 306         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 307         WREG32(SCRATCH_UMSK, 0);
 308 }
 309
 310 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 311 {
 312         const __be32 *fw_data;
 313         int i;
 314
 315         if (!rdev->me_fw || !rdev->pfp_fw)
 316                 return -EINVAL;
 317
 318         r700_cp_stop(rdev);
 319         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 320
 321         /* Reset cp */
 322         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 323         RREG32(GRBM_SOFT_RESET);
 324         mdelay(15);
 325         WREG32(GRBM_SOFT_RESET, 0);
 326
 327         fw_data = (const __be32 *)rdev->pfp_fw->data;
 328         WREG32(CP_PFP_UCODE_ADDR, 0);
 329         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 330                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 331         WREG32(CP_PFP_UCODE_ADDR, 0);
 332
 333         fw_data = (const __be32 *)rdev->me_fw->data;
 334         WREG32(CP_ME_RAM_WADDR, 0);
 335         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 336                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 337
 338         WREG32(CP_PFP_UCODE_ADDR, 0);
 339         WREG32(CP_ME_RAM_WADDR, 0);
 340         WREG32(CP_ME_RAM_RADDR, 0);
 341         return 0;
 342 }
 343
 344 void r700_cp_fini(struct radeon_device *rdev)
 345 {
 346         r700_cp_stop(rdev);
 347         radeon_ring_fini(rdev);
 348 }
 349
 350 /*
 351  * Core functions
 352  */
 353 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 354                                              u32 num_tile_pipes,
 355                                              u32 num_backends,
 356                                              u32 backend_disable_mask)
 357 {
 358         u32 backend_map = 0;
 359         u32 enabled_backends_mask;
 360         u32 enabled_backends_count;
 361         u32 cur_pipe;
 362         u32 swizzle_pipe[R7XX_MAX_PIPES];
 363         u32 cur_backend;
 364         u32 i;
 365         bool force_no_swizzle;
 366
 367         if (num_tile_pipes > R7XX_MAX_PIPES)
 368                 num_tile_pipes = R7XX_MAX_PIPES;
 369         if (num_tile_pipes < 1)
 370                 num_tile_pipes = 1;
 371         if (num_backends > R7XX_MAX_BACKENDS)
 372                 num_backends = R7XX_MAX_BACKENDS;
 373         if (num_backends < 1)
 374                 num_backends = 1;
 375
 376         enabled_backends_mask = 0;
 377         enabled_backends_count = 0;
 378         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 379                 if (((backend_disable_mask >> i) & 1) == 0) {
 380                         enabled_backends_mask |= (1 << i);
 381                         ++enabled_backends_count;
 382                 }
 383                 if (enabled_backends_count == num_backends)
 384                         break;
 385         }
 386
 387         if (enabled_backends_count == 0) {
 388                 enabled_backends_mask = 1;
 389                 enabled_backends_count = 1;
 390         }
 391
 392         if (enabled_backends_count != num_backends)
 393                 num_backends = enabled_backends_count;
 394
 395         switch (rdev->family) {
 396         case CHIP_RV770:
 397         case CHIP_RV730:
 398                 force_no_swizzle = false;
 399                 break;
 400         case CHIP_RV710:
 401         case CHIP_RV740:
 402         default:
 403                 force_no_swizzle = true;
 404                 break;
 405         }
 406
 407         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 408         switch (num_tile_pipes) {
 409         case 1:
 410                 swizzle_pipe[0] = 0;
 411                 break;
 412         case 2:
 413                 swizzle_pipe[0] = 0;
 414                 swizzle_pipe[1] = 1;
 415                 break;
 416         case 3:
 417                 if (force_no_swizzle) {
 418                         swizzle_pipe[0] = 0;
 419                         swizzle_pipe[1] = 1;
 420                         swizzle_pipe[2] = 2;
 421                 } else {
 422                         swizzle_pipe[0] = 0;
 423                         swizzle_pipe[1] = 2;
 424                         swizzle_pipe[2] = 1;
 425                 }
 426                 break;
 427         case 4:
 428                 if (force_no_swizzle) {
 429                         swizzle_pipe[0] = 0;
 430                         swizzle_pipe[1] = 1;
 431                         swizzle_pipe[2] = 2;
 432                         swizzle_pipe[3] = 3;
 433                 } else {
 434                         swizzle_pipe[0] = 0;
 435                         swizzle_pipe[1] = 2;
 436                         swizzle_pipe[2] = 3;
 437                         swizzle_pipe[3] = 1;
 438                 }
 439                 break;
 440         case 5:
 441                 if (force_no_swizzle) {
 442                         swizzle_pipe[0] = 0;
 443                         swizzle_pipe[1] = 1;
 444                         swizzle_pipe[2] = 2;
 445                         swizzle_pipe[3] = 3;
 446                         swizzle_pipe[4] = 4;
 447                 } else {
 448                         swizzle_pipe[0] = 0;
 449                         swizzle_pipe[1] = 2;
 450                         swizzle_pipe[2] = 4;
 451                         swizzle_pipe[3] = 1;
 452                         swizzle_pipe[4] = 3;
 453                 }
 454                 break;
 455         case 6:
 456                 if (force_no_swizzle) {
 457                         swizzle_pipe[0] = 0;
 458                         swizzle_pipe[1] = 1;
 459                         swizzle_pipe[2] = 2;
 460                         swizzle_pipe[3] = 3;
 461                         swizzle_pipe[4] = 4;
 462                         swizzle_pipe[5] = 5;
 463                 } else {
 464                         swizzle_pipe[0] = 0;
 465                         swizzle_pipe[1] = 2;
 466                         swizzle_pipe[2] = 4;
 467                         swizzle_pipe[3] = 5;
 468                         swizzle_pipe[4] = 3;
 469                         swizzle_pipe[5] = 1;
 470                 }
 471                 break;
 472         case 7:
 473                 if (force_no_swizzle) {
 474                         swizzle_pipe[0] = 0;
 475                         swizzle_pipe[1] = 1;
 476                         swizzle_pipe[2] = 2;
 477                         swizzle_pipe[3] = 3;
 478                         swizzle_pipe[4] = 4;
 479                         swizzle_pipe[5] = 5;
 480                         swizzle_pipe[6] = 6;
 481                 } else {
 482                         swizzle_pipe[0] = 0;
 483                         swizzle_pipe[1] = 2;
 484                         swizzle_pipe[2] = 4;
 485                         swizzle_pipe[3] = 6;
 486                         swizzle_pipe[4] = 3;
 487                         swizzle_pipe[5] = 1;
 488                         swizzle_pipe[6] = 5;
 489                 }
 490                 break;
 491         case 8:
 492                 if (force_no_swizzle) {
 493                         swizzle_pipe[0] = 0;
 494                         swizzle_pipe[1] = 1;
 495                         swizzle_pipe[2] = 2;
 496                         swizzle_pipe[3] = 3;
 497                         swizzle_pipe[4] = 4;
 498                         swizzle_pipe[5] = 5;
 499                         swizzle_pipe[6] = 6;
 500                         swizzle_pipe[7] = 7;
 501                 } else {
 502                         swizzle_pipe[0] = 0;
 503                         swizzle_pipe[1] = 2;
 504                         swizzle_pipe[2] = 4;
 505                         swizzle_pipe[3] = 6;
 506                         swizzle_pipe[4] = 3;
 507                         swizzle_pipe[5] = 1;
 508                         swizzle_pipe[6] = 7;
 509                         swizzle_pipe[7] = 5;
 510                 }
 511                 break;
 512         }
 513
 514         cur_backend = 0;
 515         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 516                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 517                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 518
 519                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 520
 521                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 522         }
 523
 524         return backend_map;
 525 }
 526
 527 static void rv770_program_channel_remap(struct radeon_device *rdev)
 528 {
 529         u32 tcp_chan_steer, mc_shared_chremap, tmp;
 530         bool force_no_swizzle;
 531
 532         switch (rdev->family) {
 533         case CHIP_RV770:
 534         case CHIP_RV730:
 535                 force_no_swizzle = false;
 536                 break;
 537         case CHIP_RV710:
 538         case CHIP_RV740:
 539         default:
 540                 force_no_swizzle = true;
 541                 break;
 542         }
 543
 544         tmp = RREG32(MC_SHARED_CHMAP);
 545         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 546         case 0:
 547         case 1:
 548         default:
 549                 /* default mapping */
 550                 mc_shared_chremap = 0x00fac688;
 551                 break;
 552         case 2:
 553         case 3:
 554                 if (force_no_swizzle)
 555                         mc_shared_chremap = 0x00fac688;
 556                 else
 557                         mc_shared_chremap = 0x00bbc298;
 558                 break;
 559         }
 560
 561         if (rdev->family == CHIP_RV740)
 562                 tcp_chan_steer = 0x00ef2a60;
 563         else
 564                 tcp_chan_steer = 0x00fac688;
 565
 566         WREG32(TCP_CHAN_STEER, tcp_chan_steer);
 567         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
 568 }
 569
 570 static void rv770_gpu_init(struct radeon_device *rdev)
 571 {
 572         int i, j, num_qd_pipes;
 573         u32 ta_aux_cntl;
 574         u32 sx_debug_1;
 575         u32 smx_dc_ctl0;
 576         u32 db_debug3;
 577         u32 num_gs_verts_per_thread;
 578         u32 vgt_gs_per_es;
 579         u32 gs_prim_buffer_depth = 0;
 580         u32 sq_ms_fifo_sizes;
 581         u32 sq_config;
 582         u32 sq_thread_resource_mgmt;
 583         u32 hdp_host_path_cntl;
 584         u32 sq_dyn_gpr_size_simd_ab_0;
 585         u32 backend_map;
 586         u32 gb_tiling_config = 0;
 587         u32 cc_rb_backend_disable = 0;
 588         u32 cc_gc_shader_pipe_config = 0;
 589         u32 mc_arb_ramcfg;
 590         u32 db_debug4;
 591
 592         /* setup chip specs */
 593         switch (rdev->family) {
 594         case CHIP_RV770:
 595                 rdev->config.rv770.max_pipes = 4;
 596                 rdev->config.rv770.max_tile_pipes = 8;
 597                 rdev->config.rv770.max_simds = 10;
 598                 rdev->config.rv770.max_backends = 4;
 599                 rdev->config.rv770.max_gprs = 256;
 600                 rdev->config.rv770.max_threads = 248;
 601                 rdev->config.rv770.max_stack_entries = 512;
 602                 rdev->config.rv770.max_hw_contexts = 8;
 603                 rdev->config.rv770.max_gs_threads = 16 * 2;
 604                 rdev->config.rv770.sx_max_export_size = 128;
 605                 rdev->config.rv770.sx_max_export_pos_size = 16;
 606                 rdev->config.rv770.sx_max_export_smx_size = 112;
 607                 rdev->config.rv770.sq_num_cf_insts = 2;
 608
 609                 rdev->config.rv770.sx_num_of_sets = 7;
 610                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 611                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 612                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 613                 break;
 614         case CHIP_RV730:
 615                 rdev->config.rv770.max_pipes = 2;
 616                 rdev->config.rv770.max_tile_pipes = 4;
 617                 rdev->config.rv770.max_simds = 8;
 618                 rdev->config.rv770.max_backends = 2;
 619                 rdev->config.rv770.max_gprs = 128;
 620                 rdev->config.rv770.max_threads = 248;
 621                 rdev->config.rv770.max_stack_entries = 256;
 622                 rdev->config.rv770.max_hw_contexts = 8;
 623                 rdev->config.rv770.max_gs_threads = 16 * 2;
 624                 rdev->config.rv770.sx_max_export_size = 256;
 625                 rdev->config.rv770.sx_max_export_pos_size = 32;
 626                 rdev->config.rv770.sx_max_export_smx_size = 224;
 627                 rdev->config.rv770.sq_num_cf_insts = 2;
 628
 629                 rdev->config.rv770.sx_num_of_sets = 7;
 630                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 631                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 632                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 633                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 634                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 635                         rdev->config.rv770.sx_max_export_smx_size += 16;
 636                 }
 637                 break;
 638         case CHIP_RV710:
 639                 rdev->config.rv770.max_pipes = 2;
 640                 rdev->config.rv770.max_tile_pipes = 2;
 641                 rdev->config.rv770.max_simds = 2;
 642                 rdev->config.rv770.max_backends = 1;
 643                 rdev->config.rv770.max_gprs = 256;
 644                 rdev->config.rv770.max_threads = 192;
 645                 rdev->config.rv770.max_stack_entries = 256;
 646                 rdev->config.rv770.max_hw_contexts = 4;
 647                 rdev->config.rv770.max_gs_threads = 8 * 2;
 648                 rdev->config.rv770.sx_max_export_size = 128;
 649                 rdev->config.rv770.sx_max_export_pos_size = 16;
 650                 rdev->config.rv770.sx_max_export_smx_size = 112;
 651                 rdev->config.rv770.sq_num_cf_insts = 1;
 652
 653                 rdev->config.rv770.sx_num_of_sets = 7;
 654                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 655                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 656                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 657                 break;
 658         case CHIP_RV740:
 659                 rdev->config.rv770.max_pipes = 4;
 660                 rdev->config.rv770.max_tile_pipes = 4;
 661                 rdev->config.rv770.max_simds = 8;
 662                 rdev->config.rv770.max_backends = 4;
 663                 rdev->config.rv770.max_gprs = 256;
 664                 rdev->config.rv770.max_threads = 248;
 665                 rdev->config.rv770.max_stack_entries = 512;
 666                 rdev->config.rv770.max_hw_contexts = 8;
 667                 rdev->config.rv770.max_gs_threads = 16 * 2;
 668                 rdev->config.rv770.sx_max_export_size = 256;
 669                 rdev->config.rv770.sx_max_export_pos_size = 32;
 670                 rdev->config.rv770.sx_max_export_smx_size = 224;
 671                 rdev->config.rv770.sq_num_cf_insts = 2;
 672
 673                 rdev->config.rv770.sx_num_of_sets = 7;
 674                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 675                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 676                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 677
 678                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 679                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 680                         rdev->config.rv770.sx_max_export_smx_size += 16;
 681                 }
 682                 break;
 683         default:
 684                 break;
 685         }
 686
 687         /* Initialize HDP */
 688         j = 0;
 689         for (i = 0; i < 32; i++) {
 690                 WREG32((0x2c14 + j), 0x00000000);
 691                 WREG32((0x2c18 + j), 0x00000000);
 692                 WREG32((0x2c1c + j), 0x00000000);
 693                 WREG32((0x2c20 + j), 0x00000000);
 694                 WREG32((0x2c24 + j), 0x00000000);
 695                 j += 0x18;
 696         }
 697
 698         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 699
 700         /* setup tiling, simd, pipe config */
 701         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 702
 703         switch (rdev->config.rv770.max_tile_pipes) {
 704         case 1:
 705         default:
 706                 gb_tiling_config |= PIPE_TILING(0);
 707                 break;
 708         case 2:
 709                 gb_tiling_config |= PIPE_TILING(1);
 710                 break;
 711         case 4:
 712                 gb_tiling_config |= PIPE_TILING(2);
 713                 break;
 714         case 8:
 715                 gb_tiling_config |= PIPE_TILING(3);
 716                 break;
 717         }
 718         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 719
 720         if (rdev->family == CHIP_RV770)
 721                 gb_tiling_config |= BANK_TILING(1);
 722         else
 723                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 724         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 725         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 726         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 727                 rdev->config.rv770.tiling_group_size = 512;
 728         else
 729                 rdev->config.rv770.tiling_group_size = 256;
 730         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 731                 gb_tiling_config |= ROW_TILING(3);
 732                 gb_tiling_config |= SAMPLE_SPLIT(3);
 733         } else {
 734                 gb_tiling_config |=
 735                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 736                 gb_tiling_config |=
 737                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 738         }
 739
 740         gb_tiling_config |= BANK_SWAPS(1);
 741
 742         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 743         cc_rb_backend_disable |=
 744                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 745
 746         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 747         cc_gc_shader_pipe_config |=
 748                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 749         cc_gc_shader_pipe_config |=
 750                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 751
 752         if (rdev->family == CHIP_RV740)
 753                 backend_map = 0x28;
 754         else
 755                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 756                                                                 rdev->config.rv770.max_tile_pipes,
 757                                                                 (R7XX_MAX_BACKENDS -
 758                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 759                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 760                                                                 (cc_rb_backend_disable >> 16));
 761
 762         rdev->config.rv770.tile_config = gb_tiling_config;
 763         gb_tiling_config |= BACKEND_MAP(backend_map);
 764
 765         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 766         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 767         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 768
 769         rv770_program_channel_remap(rdev);
 770
 771         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 772         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 773         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 774         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 775
 776         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 777         WREG32(CGTS_TCC_DISABLE, 0);
 778         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 779         WREG32(CGTS_USER_TCC_DISABLE, 0);
 780
 781         num_qd_pipes =
 782                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 783         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 784         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 785
 786         /* set HW defaults for 3D engine */
 787         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 788                                      ROQ_IB2_START(0x2b)));
 789
 790         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 791
 792         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 793         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 794
 795         sx_debug_1 = RREG32(SX_DEBUG_1);
 796         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 797         WREG32(SX_DEBUG_1, sx_debug_1);
 798
 799         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 800         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 801         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 802         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 803
 804         if (rdev->family != CHIP_RV740)
 805                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 806                                        GS_FLUSH_CTL(4) |
 807                                        ACK_FLUSH_CTL(3) |
 808                                        SYNC_FLUSH_CTL));
 809
 810         db_debug3 = RREG32(DB_DEBUG3);
 811         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 812         switch (rdev->family) {
 813         case CHIP_RV770:
 814         case CHIP_RV740:
 815                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 816                 break;
 817         case CHIP_RV710:
 818         case CHIP_RV730:
 819         default:
 820                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 821                 break;
 822         }
 823         WREG32(DB_DEBUG3, db_debug3);
 824
 825         if (rdev->family != CHIP_RV770) {
 826                 db_debug4 = RREG32(DB_DEBUG4);
 827                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 828                 WREG32(DB_DEBUG4, db_debug4);
 829         }
 830
 831         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 832                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 833                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 834
 835         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 836                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 837                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 838
 839         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 840
 841         WREG32(VGT_NUM_INSTANCES, 1);
 842
 843         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 844
 845         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 846
 847         WREG32(CP_PERFMON_CNTL, 0);
 848
 849         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 850                             DONE_FIFO_HIWATER(0xe0) |
 851                             ALU_UPDATE_FIFO_HIWATER(0x8));
 852         switch (rdev->family) {
 853         case CHIP_RV770:
 854         case CHIP_RV730:
 855         case CHIP_RV710:
 856                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 857                 break;
 858         case CHIP_RV740:
 859         default:
 860                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 861                 break;
 862         }
 863         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 864
 865         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 866          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 867          */
 868         sq_config = RREG32(SQ_CONFIG);
 869         sq_config &= ~(PS_PRIO(3) |
 870                        VS_PRIO(3) |
 871                        GS_PRIO(3) |
 872                        ES_PRIO(3));
 873         sq_config |= (DX9_CONSTS |
 874                       VC_ENABLE |
 875                       EXPORT_SRC_C |
 876                       PS_PRIO(0) |
 877                       VS_PRIO(1) |
 878                       GS_PRIO(2) |
 879                       ES_PRIO(3));
 880         if (rdev->family == CHIP_RV710)
 881                 /* no vertex cache */
 882                 sq_config &= ~VC_ENABLE;
 883
 884         WREG32(SQ_CONFIG, sq_config);
 885
 886         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 887                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 888                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 889
 890         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 891                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 892
 893         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 894                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 895                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 896         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 897                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 898         else
 899                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 900         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 901
 902         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 903                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 904
 905         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 906                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 907
 908         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 909                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 910                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 911                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 912
 913         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 914         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 915         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 916         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 917         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 918         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 919         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 920         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 921
 922         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 923                                           FORCE_EOV_MAX_REZ_CNT(255)));
 924
 925         if (rdev->family == CHIP_RV710)
 926                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 927                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 928         else
 929                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 930                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 931
 932         switch (rdev->family) {
 933         case CHIP_RV770:
 934         case CHIP_RV730:
 935         case CHIP_RV740:
 936                 gs_prim_buffer_depth = 384;
 937                 break;
 938         case CHIP_RV710:
 939                 gs_prim_buffer_depth = 128;
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 946         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 947         /* Max value for this is 256 */
 948         if (vgt_gs_per_es > 256)
 949                 vgt_gs_per_es = 256;
 950
 951         WREG32(VGT_ES_PER_GS, 128);
 952         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 953         WREG32(VGT_GS_PER_VS, 2);
 954
 955         /* more default values. 2D/3D driver should adjust as needed */
 956         WREG32(VGT_GS_VERTEX_REUSE, 16);
 957         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 958         WREG32(VGT_STRMOUT_EN, 0);
 959         WREG32(SX_MISC, 0);
 960         WREG32(PA_SC_MODE_CNTL, 0);
 961         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 962         WREG32(PA_SC_AA_CONFIG, 0);
 963         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 964         WREG32(PA_SC_LINE_STIPPLE, 0);
 965         WREG32(SPI_INPUT_Z, 0);
 966         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 967         WREG32(CB_COLOR7_FRAG, 0);
 968
 969         /* clear render buffer base addresses */
 970         WREG32(CB_COLOR0_BASE, 0);
 971         WREG32(CB_COLOR1_BASE, 0);
 972         WREG32(CB_COLOR2_BASE, 0);
 973         WREG32(CB_COLOR3_BASE, 0);
 974         WREG32(CB_COLOR4_BASE, 0);
 975         WREG32(CB_COLOR5_BASE, 0);
 976         WREG32(CB_COLOR6_BASE, 0);
 977         WREG32(CB_COLOR7_BASE, 0);
 978
 979         WREG32(TCP_CNTL, 0);
 980
 981         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 982         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 983
 984         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 985
 986         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 987                                           NUM_CLIP_SEQ(3)));
 988
 989 }
 990
 991 static int rv770_vram_scratch_init(struct radeon_device *rdev)
 992 {
 993         int r;
 994         u64 gpu_addr;
 995
 996         if (rdev->vram_scratch.robj == NULL) {
 997                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
 998                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 999                                      &rdev->vram_scratch.robj);
1000                 if (r) {
1001                         return r;
1002                 }
1003         }
1004
1005         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1006         if (unlikely(r != 0))
1007                 return r;
1008         r = radeon_bo_pin(rdev->vram_scratch.robj,
1009                           RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
1010         if (r) {
1011                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1012                 return r;
1013         }
1014         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1015                                 (void **)&rdev->vram_scratch.ptr);
1016         if (r)
1017                 radeon_bo_unpin(rdev->vram_scratch.robj);
1018         radeon_bo_unreserve(rdev->vram_scratch.robj);
1019
1020         return r;
1021 }
1022
1023 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
1024 {
1025         int r;
1026
1027         if (rdev->vram_scratch.robj == NULL) {
1028                 return;
1029         }
1030         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1031         if (likely(r == 0)) {
1032                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1033                 radeon_bo_unpin(rdev->vram_scratch.robj);
1034                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1035         }
1036         radeon_bo_unref(&rdev->vram_scratch.robj);
1037 }
1038
1039 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1040 {
1041         u64 size_bf, size_af;
1042
1043         if (mc->mc_vram_size > 0xE0000000) {
1044                 /* leave room for at least 512M GTT */
1045                 dev_warn(rdev->dev, "limiting VRAM\n");
1046                 mc->real_vram_size = 0xE0000000;
1047                 mc->mc_vram_size = 0xE0000000;
1048         }
1049         if (rdev->flags & RADEON_IS_AGP) {
1050                 size_bf = mc->gtt_start;
1051                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1052                 if (size_bf > size_af) {
1053                         if (mc->mc_vram_size > size_bf) {
1054                                 dev_warn(rdev->dev, "limiting VRAM\n");
1055                                 mc->real_vram_size = size_bf;
1056                                 mc->mc_vram_size = size_bf;
1057                         }
1058                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1059                 } else {
1060                         if (mc->mc_vram_size > size_af) {
1061                                 dev_warn(rdev->dev, "limiting VRAM\n");
1062                                 mc->real_vram_size = size_af;
1063                                 mc->mc_vram_size = size_af;
1064                         }
1065                         mc->vram_start = mc->gtt_end;
1066                 }
1067                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1068                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1069                                 mc->mc_vram_size >> 20, mc->vram_start,
1070                                 mc->vram_end, mc->real_vram_size >> 20);
1071         } else {
1072                 radeon_vram_location(rdev, &rdev->mc, 0);
1073                 rdev->mc.gtt_base_align = 0;
1074                 radeon_gtt_location(rdev, mc);
1075         }
1076 }
1077
1078 int rv770_mc_init(struct radeon_device *rdev)
1079 {
1080         u32 tmp;
1081         int chansize, numchan;
1082
1083         /* Get VRAM informations */
1084         rdev->mc.vram_is_ddr = true;
1085         tmp = RREG32(MC_ARB_RAMCFG);
1086         if (tmp & CHANSIZE_OVERRIDE) {
1087                 chansize = 16;
1088         } else if (tmp & CHANSIZE_MASK) {
1089                 chansize = 64;
1090         } else {
1091                 chansize = 32;
1092         }
1093         tmp = RREG32(MC_SHARED_CHMAP);
1094         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1095         case 0:
1096         default:
1097                 numchan = 1;
1098                 break;
1099         case 1:
1100                 numchan = 2;
1101                 break;
1102         case 2:
1103                 numchan = 4;
1104                 break;
1105         case 3:
1106                 numchan = 8;
1107                 break;
1108         }
1109         rdev->mc.vram_width = numchan * chansize;
1110         /* Could aper size report 0 ? */
1111         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1112         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1113         /* Setup GPU memory space */
1114         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1115         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1116         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1117         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1118         r700_vram_gtt_location(rdev, &rdev->mc);
1119         radeon_update_bandwidth_info(rdev);
1120
1121         return 0;
1122 }
1123
1124 static int rv770_startup(struct radeon_device *rdev)
1125 {
1126         int r;
1127
1128         /* enable pcie gen2 link */
1129         rv770_pcie_gen2_enable(rdev);
1130
1131         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1132                 r = r600_init_microcode(rdev);
1133                 if (r) {
1134                         DRM_ERROR("Failed to load firmware!\n");
1135                         return r;
1136                 }
1137         }
1138
1139         rv770_mc_program(rdev);
1140         if (rdev->flags & RADEON_IS_AGP) {
1141                 rv770_agp_enable(rdev);
1142         } else {
1143                 r = rv770_pcie_gart_enable(rdev);
1144                 if (r)
1145                         return r;
1146         }
1147         r = rv770_vram_scratch_init(rdev);
1148         if (r)
1149                 return r;
1150         rv770_gpu_init(rdev);
1151         r = r600_blit_init(rdev);
1152         if (r) {
1153                 r600_blit_fini(rdev);
1154                 rdev->asic->copy = NULL;
1155                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1156         }
1157
1158         /* allocate wb buffer */
1159         r = radeon_wb_init(rdev);
1160         if (r)
1161                 return r;
1162
1163         /* Enable IRQ */
1164         r = r600_irq_init(rdev);
1165         if (r) {
1166                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1167                 radeon_irq_kms_fini(rdev);
1168                 return r;
1169         }
1170         r600_irq_set(rdev);
1171
1172         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1173         if (r)
1174                 return r;
1175         r = rv770_cp_load_microcode(rdev);
1176         if (r)
1177                 return r;
1178         r = r600_cp_resume(rdev);
1179         if (r)
1180                 return r;
1181
1182         return 0;
1183 }
1184
1185 int rv770_resume(struct radeon_device *rdev)
1186 {
1187         int r;
1188
1189         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1190          * posting will perform necessary task to bring back GPU into good
1191          * shape.
1192          */
1193         /* post card */
1194         atom_asic_init(rdev->mode_info.atom_context);
1195
1196         r = rv770_startup(rdev);
1197         if (r) {
1198                 DRM_ERROR("r600 startup failed on resume\n");
1199                 return r;
1200         }
1201
1202         r = r600_ib_test(rdev);
1203         if (r) {
1204                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1205                 return r;
1206         }
1207
1208         r = r600_audio_init(rdev);
1209         if (r) {
1210                 dev_err(rdev->dev, "radeon: audio init failed\n");
1211                 return r;
1212         }
1213
1214         return r;
1215
1216 }
1217
1218 int rv770_suspend(struct radeon_device *rdev)
1219 {
1220         int r;
1221
1222         r600_audio_fini(rdev);
1223         /* FIXME: we should wait for ring to be empty */
1224         r700_cp_stop(rdev);
1225         rdev->cp.ready = false;
1226         r600_irq_suspend(rdev);
1227         radeon_wb_disable(rdev);
1228         rv770_pcie_gart_disable(rdev);
1229         /* unpin shaders bo */
1230         if (rdev->r600_blit.shader_obj) {
1231                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1232                 if (likely(r == 0)) {
1233                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1234                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1235                 }
1236         }
1237         return 0;
1238 }
1239
1240 /* Plan is to move initialization in that function and use
1241  * helper function so that radeon_device_init pretty much
1242  * do nothing more than calling asic specific function. This
1243  * should also allow to remove a bunch of callback function
1244  * like vram_info.
1245  */
1246 int rv770_init(struct radeon_device *rdev)
1247 {
1248         int r;
1249
1250         r = radeon_dummy_page_init(rdev);
1251         if (r)
1252                 return r;
1253         /* This don't do much */
1254         r = radeon_gem_init(rdev);
1255         if (r)
1256                 return r;
1257         /* Read BIOS */
1258         if (!radeon_get_bios(rdev)) {
1259                 if (ASIC_IS_AVIVO(rdev))
1260                         return -EINVAL;
1261         }
1262         /* Must be an ATOMBIOS */
1263         if (!rdev->is_atom_bios) {
1264                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1265                 return -EINVAL;
1266         }
1267         r = radeon_atombios_init(rdev);
1268         if (r)
1269                 return r;
1270         /* Post card if necessary */
1271         if (!r600_card_posted(rdev)) {
1272                 if (!rdev->bios) {
1273                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1274                         return -EINVAL;
1275                 }
1276                 DRM_INFO("GPU not posted. posting now...\n");
1277                 atom_asic_init(rdev->mode_info.atom_context);
1278         }
1279         /* Initialize scratch registers */
1280         r600_scratch_init(rdev);
1281         /* Initialize surface registers */
1282         radeon_surface_init(rdev);
1283         /* Initialize clocks */
1284         radeon_get_clock_info(rdev->ddev);
1285         /* Fence driver */
1286         r = radeon_fence_driver_init(rdev);
1287         if (r)
1288                 return r;
1289         /* initialize AGP */
1290         if (rdev->flags & RADEON_IS_AGP) {
1291                 r = radeon_agp_init(rdev);
1292                 if (r)
1293                         radeon_agp_disable(rdev);
1294         }
1295         r = rv770_mc_init(rdev);
1296         if (r)
1297                 return r;
1298         /* Memory manager */
1299         r = radeon_bo_init(rdev);
1300         if (r)
1301                 return r;
1302
1303         r = radeon_irq_kms_init(rdev);
1304         if (r)
1305                 return r;
1306
1307         rdev->cp.ring_obj = NULL;
1308         r600_ring_init(rdev, 1024 * 1024);
1309
1310         rdev->ih.ring_obj = NULL;
1311         r600_ih_ring_init(rdev, 64 * 1024);
1312
1313         r = r600_pcie_gart_init(rdev);
1314         if (r)
1315                 return r;
1316
1317         rdev->accel_working = true;
1318         r = rv770_startup(rdev);
1319         if (r) {
1320                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1321                 r700_cp_fini(rdev);
1322                 r600_irq_fini(rdev);
1323                 radeon_wb_fini(rdev);
1324                 radeon_irq_kms_fini(rdev);
1325                 rv770_pcie_gart_fini(rdev);
1326                 rdev->accel_working = false;
1327         }
1328         if (rdev->accel_working) {
1329                 r = radeon_ib_pool_init(rdev);
1330                 if (r) {
1331                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1332                         rdev->accel_working = false;
1333                 } else {
1334                         r = r600_ib_test(rdev);
1335                         if (r) {
1336                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1337                                 rdev->accel_working = false;
1338                         }
1339                 }
1340         }
1341
1342         r = r600_audio_init(rdev);
1343         if (r) {
1344                 dev_err(rdev->dev, "radeon: audio init failed\n");
1345                 return r;
1346         }
1347
1348         return 0;
1349 }
1350
1351 void rv770_fini(struct radeon_device *rdev)
1352 {
1353         r600_blit_fini(rdev);
1354         r700_cp_fini(rdev);
1355         r600_irq_fini(rdev);
1356         radeon_wb_fini(rdev);
1357         radeon_irq_kms_fini(rdev);
1358         rv770_pcie_gart_fini(rdev);
1359         rv770_vram_scratch_fini(rdev);
1360         radeon_gem_fini(rdev);
1361         radeon_fence_driver_fini(rdev);
1362         radeon_agp_fini(rdev);
1363         radeon_bo_fini(rdev);
1364         radeon_atombios_fini(rdev);
1365         kfree(rdev->bios);
1366         rdev->bios = NULL;
1367         radeon_dummy_page_fini(rdev);
1368 }
1369
1370 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1371 {
1372         u32 link_width_cntl, lanes, speed_cntl, tmp;
1373         u16 link_cntl2;
1374
1375         if (rdev->flags & RADEON_IS_IGP)
1376                 return;
1377
1378         if (!(rdev->flags & RADEON_IS_PCIE))
1379                 return;
1380
1381         /* x2 cards have a special sequence */
1382         if (ASIC_IS_X2(rdev))
1383                 return;
1384
1385         /* advertise upconfig capability */
1386         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1387         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1388         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1389         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1390         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1391                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1392                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1393                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
1394                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1395                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1396                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1397         } else {
1398                 link_width_cntl |= LC_UPCONFIGURE_DIS;
1399                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1400         }
1401
1402         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1403         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1404             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1405
1406                 tmp = RREG32(0x541c);
1407                 WREG32(0x541c, tmp | 0x8);
1408                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1409                 link_cntl2 = RREG16(0x4088);
1410                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1411                 link_cntl2 |= 0x2;
1412                 WREG16(0x4088, link_cntl2);
1413                 WREG32(MM_CFGREGS_CNTL, 0);
1414
1415                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1416                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1417                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1418
1419                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1420                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1421                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1422
1423                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1424                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1425                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1426
1427                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1428                 speed_cntl |= LC_GEN2_EN_STRAP;
1429                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1430
1431         } else {
1432                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1433                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1434                 if (1)
1435                         link_width_cntl |= LC_UPCONFIGURE_DIS;
1436                 else
1437                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1438                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1439         }
1440 }