drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  47 {
  48         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  49         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  50         int i;
  51
  52         /* Lock the graphics update lock */
  53         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  54         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  55
  56         /* update the scanout addresses */
  57         if (radeon_crtc->crtc_id) {
  58                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  59                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  60         } else {
  61                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  62                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  63         }
  64         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  65                (u32)crtc_base);
  66         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  67                (u32)crtc_base);
  68
  69         /* Wait for update_pending to go high. */
  70         for (i = 0; i < rdev->usec_timeout; i++) {
  71                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
  72                         break;
  73                 udelay(1);
  74         }
  75         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  76
  77         /* Unlock the lock, so double-buffering can take place inside vblank */
  78         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  79         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  80
  81         /* Return current update_pending status: */
  82         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  83 }
  84
  85 /* get temperature in millidegrees */
  86 int rv770_get_temp(struct radeon_device *rdev)
  87 {
  88         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  89                 ASIC_T_SHIFT;
  90         int actual_temp;
  91
  92         if (temp & 0x400)
  93                 actual_temp = -256;
  94         else if (temp & 0x200)
  95                 actual_temp = 255;
  96         else if (temp & 0x100) {
  97                 actual_temp = temp & 0x1ff;
  98                 actual_temp |= ~0x1ff;
  99         } else
 100                 actual_temp = temp & 0xff;
 101
 102         return (actual_temp * 1000) / 2;
 103 }
 104
 105 void rv770_pm_misc(struct radeon_device *rdev)
 106 {
 107         int req_ps_idx = rdev->pm.requested_power_state_index;
 108         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 109         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 110         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 111
 112         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 113                 /* 0xff01 is a flag rather then an actual voltage */
 114                 if (voltage->voltage == 0xff01)
 115                         return;
 116                 if (voltage->voltage != rdev->pm.current_vddc) {
 117                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 118                         rdev->pm.current_vddc = voltage->voltage;
 119                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 120                 }
 121         }
 122 }
 123
 124 /*
 125  * GART
 126  */
 127 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 128 {
 129         u32 tmp;
 130         int r, i;
 131
 132         if (rdev->gart.robj == NULL) {
 133                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 134                 return -EINVAL;
 135         }
 136         r = radeon_gart_table_vram_pin(rdev);
 137         if (r)
 138                 return r;
 139         radeon_gart_restore(rdev);
 140         /* Setup L2 cache */
 141         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 142                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 143                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 144         WREG32(VM_L2_CNTL2, 0);
 145         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 146         /* Setup TLB control */
 147         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 148                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 149                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 150                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 151         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 152         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 153         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 154         if (rdev->family == CHIP_RV740)
 155                 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
 156         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 157         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 158         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 159         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 160         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 161         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 162         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 163         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 164                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 165         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 166                         (u32)(rdev->dummy_page.addr >> 12));
 167         for (i = 1; i < 7; i++)
 168                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 169
 170         r600_pcie_gart_tlb_flush(rdev);
 171         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 172                  (unsigned)(rdev->mc.gtt_size >> 20),
 173                  (unsigned long long)rdev->gart.table_addr);
 174         rdev->gart.ready = true;
 175         return 0;
 176 }
 177
 178 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 179 {
 180         u32 tmp;
 181         int i;
 182
 183         /* Disable all tables */
 184         for (i = 0; i < 7; i++)
 185                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 186
 187         /* Setup L2 cache */
 188         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 189                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 190         WREG32(VM_L2_CNTL2, 0);
 191         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 192         /* Setup TLB control */
 193         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 194         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 195         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 196         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 197         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 198         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 199         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 200         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 201         radeon_gart_table_vram_unpin(rdev);
 202 }
 203
 204 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 205 {
 206         radeon_gart_fini(rdev);
 207         rv770_pcie_gart_disable(rdev);
 208         radeon_gart_table_vram_free(rdev);
 209 }
 210
 211
 212 void rv770_agp_enable(struct radeon_device *rdev)
 213 {
 214         u32 tmp;
 215         int i;
 216
 217         /* Setup L2 cache */
 218         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 219                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 220                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 221         WREG32(VM_L2_CNTL2, 0);
 222         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 223         /* Setup TLB control */
 224         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 225                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 226                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 227                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 228         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 229         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 230         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 231         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 232         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 233         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 234         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 235         for (i = 0; i < 7; i++)
 236                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 237 }
 238
 239 static void rv770_mc_program(struct radeon_device *rdev)
 240 {
 241         struct rv515_mc_save save;
 242         u32 tmp;
 243         int i, j;
 244
 245         /* Initialize HDP */
 246         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 247                 WREG32((0x2c14 + j), 0x00000000);
 248                 WREG32((0x2c18 + j), 0x00000000);
 249                 WREG32((0x2c1c + j), 0x00000000);
 250                 WREG32((0x2c20 + j), 0x00000000);
 251                 WREG32((0x2c24 + j), 0x00000000);
 252         }
 253         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 254          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 255          */
 256         tmp = RREG32(HDP_DEBUG1);
 257
 258         rv515_mc_stop(rdev, &save);
 259         if (r600_mc_wait_for_idle(rdev)) {
 260                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 261         }
 262         /* Lockout access through VGA aperture*/
 263         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 264         /* Update configuration */
 265         if (rdev->flags & RADEON_IS_AGP) {
 266                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 267                         /* VRAM before AGP */
 268                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 269                                 rdev->mc.vram_start >> 12);
 270                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 271                                 rdev->mc.gtt_end >> 12);
 272                 } else {
 273                         /* VRAM after AGP */
 274                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 275                                 rdev->mc.gtt_start >> 12);
 276                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 277                                 rdev->mc.vram_end >> 12);
 278                 }
 279         } else {
 280                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 281                         rdev->mc.vram_start >> 12);
 282                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 283                         rdev->mc.vram_end >> 12);
 284         }
 285         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
 286         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 287         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 288         WREG32(MC_VM_FB_LOCATION, tmp);
 289         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 290         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 291         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 292         if (rdev->flags & RADEON_IS_AGP) {
 293                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 294                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 295                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 296         } else {
 297                 WREG32(MC_VM_AGP_BASE, 0);
 298                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 299                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 300         }
 301         if (r600_mc_wait_for_idle(rdev)) {
 302                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 303         }
 304         rv515_mc_resume(rdev, &save);
 305         /* we need to own VRAM, so turn off the VGA renderer here
 306          * to stop it overwriting our objects */
 307         rv515_vga_render_disable(rdev);
 308 }
 309
 310
 311 /*
 312  * CP.
 313  */
 314 void r700_cp_stop(struct radeon_device *rdev)
 315 {
 316         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 317         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 318         WREG32(SCRATCH_UMSK, 0);
 319 }
 320
 321 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 322 {
 323         const __be32 *fw_data;
 324         int i;
 325
 326         if (!rdev->me_fw || !rdev->pfp_fw)
 327                 return -EINVAL;
 328
 329         r700_cp_stop(rdev);
 330         WREG32(CP_RB_CNTL,
 331 #ifdef __BIG_ENDIAN
 332                BUF_SWAP_32BIT |
 333 #endif
 334                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
 335
 336         /* Reset cp */
 337         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 338         RREG32(GRBM_SOFT_RESET);
 339         mdelay(15);
 340         WREG32(GRBM_SOFT_RESET, 0);
 341
 342         fw_data = (const __be32 *)rdev->pfp_fw->data;
 343         WREG32(CP_PFP_UCODE_ADDR, 0);
 344         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 345                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 346         WREG32(CP_PFP_UCODE_ADDR, 0);
 347
 348         fw_data = (const __be32 *)rdev->me_fw->data;
 349         WREG32(CP_ME_RAM_WADDR, 0);
 350         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 351                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 352
 353         WREG32(CP_PFP_UCODE_ADDR, 0);
 354         WREG32(CP_ME_RAM_WADDR, 0);
 355         WREG32(CP_ME_RAM_RADDR, 0);
 356         return 0;
 357 }
 358
 359 void r700_cp_fini(struct radeon_device *rdev)
 360 {
 361         r700_cp_stop(rdev);
 362         radeon_ring_fini(rdev);
 363 }
 364
 365 /*
 366  * Core functions
 367  */
 368 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 369                                              u32 num_tile_pipes,
 370                                              u32 num_backends,
 371                                              u32 backend_disable_mask)
 372 {
 373         u32 backend_map = 0;
 374         u32 enabled_backends_mask;
 375         u32 enabled_backends_count;
 376         u32 cur_pipe;
 377         u32 swizzle_pipe[R7XX_MAX_PIPES];
 378         u32 cur_backend;
 379         u32 i;
 380         bool force_no_swizzle;
 381
 382         if (num_tile_pipes > R7XX_MAX_PIPES)
 383                 num_tile_pipes = R7XX_MAX_PIPES;
 384         if (num_tile_pipes < 1)
 385                 num_tile_pipes = 1;
 386         if (num_backends > R7XX_MAX_BACKENDS)
 387                 num_backends = R7XX_MAX_BACKENDS;
 388         if (num_backends < 1)
 389                 num_backends = 1;
 390
 391         enabled_backends_mask = 0;
 392         enabled_backends_count = 0;
 393         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 394                 if (((backend_disable_mask >> i) & 1) == 0) {
 395                         enabled_backends_mask |= (1 << i);
 396                         ++enabled_backends_count;
 397                 }
 398                 if (enabled_backends_count == num_backends)
 399                         break;
 400         }
 401
 402         if (enabled_backends_count == 0) {
 403                 enabled_backends_mask = 1;
 404                 enabled_backends_count = 1;
 405         }
 406
 407         if (enabled_backends_count != num_backends)
 408                 num_backends = enabled_backends_count;
 409
 410         switch (rdev->family) {
 411         case CHIP_RV770:
 412         case CHIP_RV730:
 413                 force_no_swizzle = false;
 414                 break;
 415         case CHIP_RV710:
 416         case CHIP_RV740:
 417         default:
 418                 force_no_swizzle = true;
 419                 break;
 420         }
 421
 422         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 423         switch (num_tile_pipes) {
 424         case 1:
 425                 swizzle_pipe[0] = 0;
 426                 break;
 427         case 2:
 428                 swizzle_pipe[0] = 0;
 429                 swizzle_pipe[1] = 1;
 430                 break;
 431         case 3:
 432                 if (force_no_swizzle) {
 433                         swizzle_pipe[0] = 0;
 434                         swizzle_pipe[1] = 1;
 435                         swizzle_pipe[2] = 2;
 436                 } else {
 437                         swizzle_pipe[0] = 0;
 438                         swizzle_pipe[1] = 2;
 439                         swizzle_pipe[2] = 1;
 440                 }
 441                 break;
 442         case 4:
 443                 if (force_no_swizzle) {
 444                         swizzle_pipe[0] = 0;
 445                         swizzle_pipe[1] = 1;
 446                         swizzle_pipe[2] = 2;
 447                         swizzle_pipe[3] = 3;
 448                 } else {
 449                         swizzle_pipe[0] = 0;
 450                         swizzle_pipe[1] = 2;
 451                         swizzle_pipe[2] = 3;
 452                         swizzle_pipe[3] = 1;
 453                 }
 454                 break;
 455         case 5:
 456                 if (force_no_swizzle) {
 457                         swizzle_pipe[0] = 0;
 458                         swizzle_pipe[1] = 1;
 459                         swizzle_pipe[2] = 2;
 460                         swizzle_pipe[3] = 3;
 461                         swizzle_pipe[4] = 4;
 462                 } else {
 463                         swizzle_pipe[0] = 0;
 464                         swizzle_pipe[1] = 2;
 465                         swizzle_pipe[2] = 4;
 466                         swizzle_pipe[3] = 1;
 467                         swizzle_pipe[4] = 3;
 468                 }
 469                 break;
 470         case 6:
 471                 if (force_no_swizzle) {
 472                         swizzle_pipe[0] = 0;
 473                         swizzle_pipe[1] = 1;
 474                         swizzle_pipe[2] = 2;
 475                         swizzle_pipe[3] = 3;
 476                         swizzle_pipe[4] = 4;
 477                         swizzle_pipe[5] = 5;
 478                 } else {
 479                         swizzle_pipe[0] = 0;
 480                         swizzle_pipe[1] = 2;
 481                         swizzle_pipe[2] = 4;
 482                         swizzle_pipe[3] = 5;
 483                         swizzle_pipe[4] = 3;
 484                         swizzle_pipe[5] = 1;
 485                 }
 486                 break;
 487         case 7:
 488                 if (force_no_swizzle) {
 489                         swizzle_pipe[0] = 0;
 490                         swizzle_pipe[1] = 1;
 491                         swizzle_pipe[2] = 2;
 492                         swizzle_pipe[3] = 3;
 493                         swizzle_pipe[4] = 4;
 494                         swizzle_pipe[5] = 5;
 495                         swizzle_pipe[6] = 6;
 496                 } else {
 497                         swizzle_pipe[0] = 0;
 498                         swizzle_pipe[1] = 2;
 499                         swizzle_pipe[2] = 4;
 500                         swizzle_pipe[3] = 6;
 501                         swizzle_pipe[4] = 3;
 502                         swizzle_pipe[5] = 1;
 503                         swizzle_pipe[6] = 5;
 504                 }
 505                 break;
 506         case 8:
 507                 if (force_no_swizzle) {
 508                         swizzle_pipe[0] = 0;
 509                         swizzle_pipe[1] = 1;
 510                         swizzle_pipe[2] = 2;
 511                         swizzle_pipe[3] = 3;
 512                         swizzle_pipe[4] = 4;
 513                         swizzle_pipe[5] = 5;
 514                         swizzle_pipe[6] = 6;
 515                         swizzle_pipe[7] = 7;
 516                 } else {
 517                         swizzle_pipe[0] = 0;
 518                         swizzle_pipe[1] = 2;
 519                         swizzle_pipe[2] = 4;
 520                         swizzle_pipe[3] = 6;
 521                         swizzle_pipe[4] = 3;
 522                         swizzle_pipe[5] = 1;
 523                         swizzle_pipe[6] = 7;
 524                         swizzle_pipe[7] = 5;
 525                 }
 526                 break;
 527         }
 528
 529         cur_backend = 0;
 530         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 531                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 532                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 533
 534                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 535
 536                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 537         }
 538
 539         return backend_map;
 540 }
 541
 542 static void rv770_gpu_init(struct radeon_device *rdev)
 543 {
 544         int i, j, num_qd_pipes;
 545         u32 ta_aux_cntl;
 546         u32 sx_debug_1;
 547         u32 smx_dc_ctl0;
 548         u32 db_debug3;
 549         u32 num_gs_verts_per_thread;
 550         u32 vgt_gs_per_es;
 551         u32 gs_prim_buffer_depth = 0;
 552         u32 sq_ms_fifo_sizes;
 553         u32 sq_config;
 554         u32 sq_thread_resource_mgmt;
 555         u32 hdp_host_path_cntl;
 556         u32 sq_dyn_gpr_size_simd_ab_0;
 557         u32 backend_map;
 558         u32 gb_tiling_config = 0;
 559         u32 cc_rb_backend_disable = 0;
 560         u32 cc_gc_shader_pipe_config = 0;
 561         u32 mc_arb_ramcfg;
 562         u32 db_debug4;
 563
 564         /* setup chip specs */
 565         switch (rdev->family) {
 566         case CHIP_RV770:
 567                 rdev->config.rv770.max_pipes = 4;
 568                 rdev->config.rv770.max_tile_pipes = 8;
 569                 rdev->config.rv770.max_simds = 10;
 570                 rdev->config.rv770.max_backends = 4;
 571                 rdev->config.rv770.max_gprs = 256;
 572                 rdev->config.rv770.max_threads = 248;
 573                 rdev->config.rv770.max_stack_entries = 512;
 574                 rdev->config.rv770.max_hw_contexts = 8;
 575                 rdev->config.rv770.max_gs_threads = 16 * 2;
 576                 rdev->config.rv770.sx_max_export_size = 128;
 577                 rdev->config.rv770.sx_max_export_pos_size = 16;
 578                 rdev->config.rv770.sx_max_export_smx_size = 112;
 579                 rdev->config.rv770.sq_num_cf_insts = 2;
 580
 581                 rdev->config.rv770.sx_num_of_sets = 7;
 582                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 583                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 584                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 585                 break;
 586         case CHIP_RV730:
 587                 rdev->config.rv770.max_pipes = 2;
 588                 rdev->config.rv770.max_tile_pipes = 4;
 589                 rdev->config.rv770.max_simds = 8;
 590                 rdev->config.rv770.max_backends = 2;
 591                 rdev->config.rv770.max_gprs = 128;
 592                 rdev->config.rv770.max_threads = 248;
 593                 rdev->config.rv770.max_stack_entries = 256;
 594                 rdev->config.rv770.max_hw_contexts = 8;
 595                 rdev->config.rv770.max_gs_threads = 16 * 2;
 596                 rdev->config.rv770.sx_max_export_size = 256;
 597                 rdev->config.rv770.sx_max_export_pos_size = 32;
 598                 rdev->config.rv770.sx_max_export_smx_size = 224;
 599                 rdev->config.rv770.sq_num_cf_insts = 2;
 600
 601                 rdev->config.rv770.sx_num_of_sets = 7;
 602                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 603                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 604                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 605                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 606                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 607                         rdev->config.rv770.sx_max_export_smx_size += 16;
 608                 }
 609                 break;
 610         case CHIP_RV710:
 611                 rdev->config.rv770.max_pipes = 2;
 612                 rdev->config.rv770.max_tile_pipes = 2;
 613                 rdev->config.rv770.max_simds = 2;
 614                 rdev->config.rv770.max_backends = 1;
 615                 rdev->config.rv770.max_gprs = 256;
 616                 rdev->config.rv770.max_threads = 192;
 617                 rdev->config.rv770.max_stack_entries = 256;
 618                 rdev->config.rv770.max_hw_contexts = 4;
 619                 rdev->config.rv770.max_gs_threads = 8 * 2;
 620                 rdev->config.rv770.sx_max_export_size = 128;
 621                 rdev->config.rv770.sx_max_export_pos_size = 16;
 622                 rdev->config.rv770.sx_max_export_smx_size = 112;
 623                 rdev->config.rv770.sq_num_cf_insts = 1;
 624
 625                 rdev->config.rv770.sx_num_of_sets = 7;
 626                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 627                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 628                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 629                 break;
 630         case CHIP_RV740:
 631                 rdev->config.rv770.max_pipes = 4;
 632                 rdev->config.rv770.max_tile_pipes = 4;
 633                 rdev->config.rv770.max_simds = 8;
 634                 rdev->config.rv770.max_backends = 4;
 635                 rdev->config.rv770.max_gprs = 256;
 636                 rdev->config.rv770.max_threads = 248;
 637                 rdev->config.rv770.max_stack_entries = 512;
 638                 rdev->config.rv770.max_hw_contexts = 8;
 639                 rdev->config.rv770.max_gs_threads = 16 * 2;
 640                 rdev->config.rv770.sx_max_export_size = 256;
 641                 rdev->config.rv770.sx_max_export_pos_size = 32;
 642                 rdev->config.rv770.sx_max_export_smx_size = 224;
 643                 rdev->config.rv770.sq_num_cf_insts = 2;
 644
 645                 rdev->config.rv770.sx_num_of_sets = 7;
 646                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 647                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 648                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 649
 650                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 651                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 652                         rdev->config.rv770.sx_max_export_smx_size += 16;
 653                 }
 654                 break;
 655         default:
 656                 break;
 657         }
 658
 659         /* Initialize HDP */
 660         j = 0;
 661         for (i = 0; i < 32; i++) {
 662                 WREG32((0x2c14 + j), 0x00000000);
 663                 WREG32((0x2c18 + j), 0x00000000);
 664                 WREG32((0x2c1c + j), 0x00000000);
 665                 WREG32((0x2c20 + j), 0x00000000);
 666                 WREG32((0x2c24 + j), 0x00000000);
 667                 j += 0x18;
 668         }
 669
 670         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 671
 672         /* setup tiling, simd, pipe config */
 673         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 674
 675         switch (rdev->config.rv770.max_tile_pipes) {
 676         case 1:
 677         default:
 678                 gb_tiling_config |= PIPE_TILING(0);
 679                 break;
 680         case 2:
 681                 gb_tiling_config |= PIPE_TILING(1);
 682                 break;
 683         case 4:
 684                 gb_tiling_config |= PIPE_TILING(2);
 685                 break;
 686         case 8:
 687                 gb_tiling_config |= PIPE_TILING(3);
 688                 break;
 689         }
 690         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 691
 692         if (rdev->family == CHIP_RV770)
 693                 gb_tiling_config |= BANK_TILING(1);
 694         else {
 695                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
 696                         gb_tiling_config |= BANK_TILING(1);
 697                 else
 698                         gb_tiling_config |= BANK_TILING(0);
 699         }
 700         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 701         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 702         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 703                 rdev->config.rv770.tiling_group_size = 512;
 704         else
 705                 rdev->config.rv770.tiling_group_size = 256;
 706         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 707                 gb_tiling_config |= ROW_TILING(3);
 708                 gb_tiling_config |= SAMPLE_SPLIT(3);
 709         } else {
 710                 gb_tiling_config |=
 711                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 712                 gb_tiling_config |=
 713                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 714         }
 715
 716         gb_tiling_config |= BANK_SWAPS(1);
 717
 718         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 719         cc_rb_backend_disable |=
 720                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 721
 722         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 723         cc_gc_shader_pipe_config |=
 724                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 725         cc_gc_shader_pipe_config |=
 726                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 727
 728         if (rdev->family == CHIP_RV740)
 729                 backend_map = 0x28;
 730         else
 731                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 732                                                                 rdev->config.rv770.max_tile_pipes,
 733                                                                 (R7XX_MAX_BACKENDS -
 734                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 735                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 736                                                                 (cc_rb_backend_disable >> 16));
 737
 738         rdev->config.rv770.tile_config = gb_tiling_config;
 739         rdev->config.rv770.backend_map = backend_map;
 740         gb_tiling_config |= BACKEND_MAP(backend_map);
 741
 742         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 743         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 744         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 745
 746         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 747         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 748         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 749         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 750
 751         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 752         WREG32(CGTS_TCC_DISABLE, 0);
 753         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 754         WREG32(CGTS_USER_TCC_DISABLE, 0);
 755
 756         num_qd_pipes =
 757                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 758         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 759         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 760
 761         /* set HW defaults for 3D engine */
 762         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 763                                      ROQ_IB2_START(0x2b)));
 764
 765         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 766
 767         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 768         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 769
 770         sx_debug_1 = RREG32(SX_DEBUG_1);
 771         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 772         WREG32(SX_DEBUG_1, sx_debug_1);
 773
 774         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 775         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 776         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 777         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 778
 779         if (rdev->family != CHIP_RV740)
 780                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 781                                        GS_FLUSH_CTL(4) |
 782                                        ACK_FLUSH_CTL(3) |
 783                                        SYNC_FLUSH_CTL));
 784
 785         if (rdev->family != CHIP_RV770)
 786                 WREG32(SMX_SAR_CTL0, 0x00003f3f);
 787
 788         db_debug3 = RREG32(DB_DEBUG3);
 789         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 790         switch (rdev->family) {
 791         case CHIP_RV770:
 792         case CHIP_RV740:
 793                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 794                 break;
 795         case CHIP_RV710:
 796         case CHIP_RV730:
 797         default:
 798                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 799                 break;
 800         }
 801         WREG32(DB_DEBUG3, db_debug3);
 802
 803         if (rdev->family != CHIP_RV770) {
 804                 db_debug4 = RREG32(DB_DEBUG4);
 805                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 806                 WREG32(DB_DEBUG4, db_debug4);
 807         }
 808
 809         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 810                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 811                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 812
 813         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 814                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 815                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 816
 817         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 818
 819         WREG32(VGT_NUM_INSTANCES, 1);
 820
 821         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 822
 823         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 824
 825         WREG32(CP_PERFMON_CNTL, 0);
 826
 827         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 828                             DONE_FIFO_HIWATER(0xe0) |
 829                             ALU_UPDATE_FIFO_HIWATER(0x8));
 830         switch (rdev->family) {
 831         case CHIP_RV770:
 832         case CHIP_RV730:
 833         case CHIP_RV710:
 834                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 835                 break;
 836         case CHIP_RV740:
 837         default:
 838                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 839                 break;
 840         }
 841         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 842
 843         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 844          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 845          */
 846         sq_config = RREG32(SQ_CONFIG);
 847         sq_config &= ~(PS_PRIO(3) |
 848                        VS_PRIO(3) |
 849                        GS_PRIO(3) |
 850                        ES_PRIO(3));
 851         sq_config |= (DX9_CONSTS |
 852                       VC_ENABLE |
 853                       EXPORT_SRC_C |
 854                       PS_PRIO(0) |
 855                       VS_PRIO(1) |
 856                       GS_PRIO(2) |
 857                       ES_PRIO(3));
 858         if (rdev->family == CHIP_RV710)
 859                 /* no vertex cache */
 860                 sq_config &= ~VC_ENABLE;
 861
 862         WREG32(SQ_CONFIG, sq_config);
 863
 864         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 865                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 866                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 867
 868         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 869                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 870
 871         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 872                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 873                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 874         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 875                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 876         else
 877                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 878         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 879
 880         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 881                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 882
 883         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 884                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 885
 886         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 887                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 888                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 889                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 890
 891         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 892         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 893         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 894         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 895         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 896         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 897         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 898         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 899
 900         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 901                                           FORCE_EOV_MAX_REZ_CNT(255)));
 902
 903         if (rdev->family == CHIP_RV710)
 904                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 905                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 906         else
 907                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 908                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 909
 910         switch (rdev->family) {
 911         case CHIP_RV770:
 912         case CHIP_RV730:
 913         case CHIP_RV740:
 914                 gs_prim_buffer_depth = 384;
 915                 break;
 916         case CHIP_RV710:
 917                 gs_prim_buffer_depth = 128;
 918                 break;
 919         default:
 920                 break;
 921         }
 922
 923         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 924         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 925         /* Max value for this is 256 */
 926         if (vgt_gs_per_es > 256)
 927                 vgt_gs_per_es = 256;
 928
 929         WREG32(VGT_ES_PER_GS, 128);
 930         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 931         WREG32(VGT_GS_PER_VS, 2);
 932
 933         /* more default values. 2D/3D driver should adjust as needed */
 934         WREG32(VGT_GS_VERTEX_REUSE, 16);
 935         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 936         WREG32(VGT_STRMOUT_EN, 0);
 937         WREG32(SX_MISC, 0);
 938         WREG32(PA_SC_MODE_CNTL, 0);
 939         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 940         WREG32(PA_SC_AA_CONFIG, 0);
 941         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 942         WREG32(PA_SC_LINE_STIPPLE, 0);
 943         WREG32(SPI_INPUT_Z, 0);
 944         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 945         WREG32(CB_COLOR7_FRAG, 0);
 946
 947         /* clear render buffer base addresses */
 948         WREG32(CB_COLOR0_BASE, 0);
 949         WREG32(CB_COLOR1_BASE, 0);
 950         WREG32(CB_COLOR2_BASE, 0);
 951         WREG32(CB_COLOR3_BASE, 0);
 952         WREG32(CB_COLOR4_BASE, 0);
 953         WREG32(CB_COLOR5_BASE, 0);
 954         WREG32(CB_COLOR6_BASE, 0);
 955         WREG32(CB_COLOR7_BASE, 0);
 956
 957         WREG32(TCP_CNTL, 0);
 958
 959         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 960         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 961
 962         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 963
 964         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 965                                           NUM_CLIP_SEQ(3)));
 966         WREG32(VC_ENHANCE, 0);
 967 }
 968
 969 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 970 {
 971         u64 size_bf, size_af;
 972
 973         if (mc->mc_vram_size > 0xE0000000) {
 974                 /* leave room for at least 512M GTT */
 975                 dev_warn(rdev->dev, "limiting VRAM\n");
 976                 mc->real_vram_size = 0xE0000000;
 977                 mc->mc_vram_size = 0xE0000000;
 978         }
 979         if (rdev->flags & RADEON_IS_AGP) {
 980                 size_bf = mc->gtt_start;
 981                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 982                 if (size_bf > size_af) {
 983                         if (mc->mc_vram_size > size_bf) {
 984                                 dev_warn(rdev->dev, "limiting VRAM\n");
 985                                 mc->real_vram_size = size_bf;
 986                                 mc->mc_vram_size = size_bf;
 987                         }
 988                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 989                 } else {
 990                         if (mc->mc_vram_size > size_af) {
 991                                 dev_warn(rdev->dev, "limiting VRAM\n");
 992                                 mc->real_vram_size = size_af;
 993                                 mc->mc_vram_size = size_af;
 994                         }
 995                         mc->vram_start = mc->gtt_end;
 996                 }
 997                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 998                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 999                                 mc->mc_vram_size >> 20, mc->vram_start,
1000                                 mc->vram_end, mc->real_vram_size >> 20);
1001         } else {
1002                 radeon_vram_location(rdev, &rdev->mc, 0);
1003                 rdev->mc.gtt_base_align = 0;
1004                 radeon_gtt_location(rdev, mc);
1005         }
1006 }
1007
1008 int rv770_mc_init(struct radeon_device *rdev)
1009 {
1010         u32 tmp;
1011         int chansize, numchan;
1012
1013         /* Get VRAM informations */
1014         rdev->mc.vram_is_ddr = true;
1015         tmp = RREG32(MC_ARB_RAMCFG);
1016         if (tmp & CHANSIZE_OVERRIDE) {
1017                 chansize = 16;
1018         } else if (tmp & CHANSIZE_MASK) {
1019                 chansize = 64;
1020         } else {
1021                 chansize = 32;
1022         }
1023         tmp = RREG32(MC_SHARED_CHMAP);
1024         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1025         case 0:
1026         default:
1027                 numchan = 1;
1028                 break;
1029         case 1:
1030                 numchan = 2;
1031                 break;
1032         case 2:
1033                 numchan = 4;
1034                 break;
1035         case 3:
1036                 numchan = 8;
1037                 break;
1038         }
1039         rdev->mc.vram_width = numchan * chansize;
1040         /* Could aper size report 0 ? */
1041         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1042         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1043         /* Setup GPU memory space */
1044         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1045         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1046         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1047         r700_vram_gtt_location(rdev, &rdev->mc);
1048         radeon_update_bandwidth_info(rdev);
1049
1050         return 0;
1051 }
1052
1053 static int rv770_startup(struct radeon_device *rdev)
1054 {
1055         int r;
1056
1057         /* enable pcie gen2 link */
1058         rv770_pcie_gen2_enable(rdev);
1059
1060         rv770_mc_program(rdev);
1061
1062         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1063                 r = r600_init_microcode(rdev);
1064                 if (r) {
1065                         DRM_ERROR("Failed to load firmware!\n");
1066                         return r;
1067                 }
1068         }
1069
1070         r = r600_vram_scratch_init(rdev);
1071         if (r)
1072                 return r;
1073
1074         if (rdev->flags & RADEON_IS_AGP) {
1075                 rv770_agp_enable(rdev);
1076         } else {
1077                 r = rv770_pcie_gart_enable(rdev);
1078                 if (r)
1079                         return r;
1080         }
1081
1082         rv770_gpu_init(rdev);
1083         r = r600_blit_init(rdev);
1084         if (r) {
1085                 r600_blit_fini(rdev);
1086                 rdev->asic->copy = NULL;
1087                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1088         }
1089
1090         /* allocate wb buffer */
1091         r = radeon_wb_init(rdev);
1092         if (r)
1093                 return r;
1094
1095         /* Enable IRQ */
1096         if (!rdev->irq.installed) {
1097                 r = radeon_irq_kms_init(rdev);
1098                 if (r)
1099                         return r;
1100         }
1101
1102         r = r600_irq_init(rdev);
1103         if (r) {
1104                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1105                 radeon_irq_kms_fini(rdev);
1106                 return r;
1107         }
1108         r600_irq_set(rdev);
1109
1110         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1111         if (r)
1112                 return r;
1113         r = rv770_cp_load_microcode(rdev);
1114         if (r)
1115                 return r;
1116         r = r600_cp_resume(rdev);
1117         if (r)
1118                 return r;
1119
1120         return 0;
1121 }
1122
1123 int rv770_resume(struct radeon_device *rdev)
1124 {
1125         int r;
1126
1127         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1128          * posting will perform necessary task to bring back GPU into good
1129          * shape.
1130          */
1131         /* post card */
1132         atom_asic_init(rdev->mode_info.atom_context);
1133
1134         r = rv770_startup(rdev);
1135         if (r) {
1136                 DRM_ERROR("r600 startup failed on resume\n");
1137                 return r;
1138         }
1139
1140         r = r600_ib_test(rdev);
1141         if (r) {
1142                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1143                 return r;
1144         }
1145
1146         r = r600_audio_init(rdev);
1147         if (r) {
1148                 dev_err(rdev->dev, "radeon: audio init failed\n");
1149                 return r;
1150         }
1151
1152         return r;
1153
1154 }
1155
1156 int rv770_suspend(struct radeon_device *rdev)
1157 {
1158         r600_audio_fini(rdev);
1159         /* FIXME: we should wait for ring to be empty */
1160         r700_cp_stop(rdev);
1161         rdev->cp.ready = false;
1162         r600_irq_suspend(rdev);
1163         radeon_wb_disable(rdev);
1164         rv770_pcie_gart_disable(rdev);
1165         r600_blit_suspend(rdev);
1166
1167         return 0;
1168 }
1169
1170 /* Plan is to move initialization in that function and use
1171  * helper function so that radeon_device_init pretty much
1172  * do nothing more than calling asic specific function. This
1173  * should also allow to remove a bunch of callback function
1174  * like vram_info.
1175  */
1176 int rv770_init(struct radeon_device *rdev)
1177 {
1178         int r;
1179
1180         /* This don't do much */
1181         r = radeon_gem_init(rdev);
1182         if (r)
1183                 return r;
1184         /* Read BIOS */
1185         if (!radeon_get_bios(rdev)) {
1186                 if (ASIC_IS_AVIVO(rdev))
1187                         return -EINVAL;
1188         }
1189         /* Must be an ATOMBIOS */
1190         if (!rdev->is_atom_bios) {
1191                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1192                 return -EINVAL;
1193         }
1194         r = radeon_atombios_init(rdev);
1195         if (r)
1196                 return r;
1197         /* Post card if necessary */
1198         if (!radeon_card_posted(rdev)) {
1199                 if (!rdev->bios) {
1200                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1201                         return -EINVAL;
1202                 }
1203                 DRM_INFO("GPU not posted. posting now...\n");
1204                 atom_asic_init(rdev->mode_info.atom_context);
1205         }
1206         /* Initialize scratch registers */
1207         r600_scratch_init(rdev);
1208         /* Initialize surface registers */
1209         radeon_surface_init(rdev);
1210         /* Initialize clocks */
1211         radeon_get_clock_info(rdev->ddev);
1212         /* Fence driver */
1213         r = radeon_fence_driver_init(rdev);
1214         if (r)
1215                 return r;
1216         /* initialize AGP */
1217         if (rdev->flags & RADEON_IS_AGP) {
1218                 r = radeon_agp_init(rdev);
1219                 if (r)
1220                         radeon_agp_disable(rdev);
1221         }
1222         r = rv770_mc_init(rdev);
1223         if (r)
1224                 return r;
1225         /* Memory manager */
1226         r = radeon_bo_init(rdev);
1227         if (r)
1228                 return r;
1229
1230         rdev->cp.ring_obj = NULL;
1231         r600_ring_init(rdev, 1024 * 1024);
1232
1233         rdev->ih.ring_obj = NULL;
1234         r600_ih_ring_init(rdev, 64 * 1024);
1235
1236         r = r600_pcie_gart_init(rdev);
1237         if (r)
1238                 return r;
1239
1240         rdev->accel_working = true;
1241         r = rv770_startup(rdev);
1242         if (r) {
1243                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1244                 r700_cp_fini(rdev);
1245                 r600_irq_fini(rdev);
1246                 radeon_wb_fini(rdev);
1247                 radeon_irq_kms_fini(rdev);
1248                 rv770_pcie_gart_fini(rdev);
1249                 rdev->accel_working = false;
1250         }
1251         if (rdev->accel_working) {
1252                 r = radeon_ib_pool_init(rdev);
1253                 if (r) {
1254                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1255                         rdev->accel_working = false;
1256                 } else {
1257                         r = r600_ib_test(rdev);
1258                         if (r) {
1259                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1260                                 rdev->accel_working = false;
1261                         }
1262                 }
1263         }
1264
1265         r = r600_audio_init(rdev);
1266         if (r) {
1267                 dev_err(rdev->dev, "radeon: audio init failed\n");
1268                 return r;
1269         }
1270
1271         return 0;
1272 }
1273
1274 void rv770_fini(struct radeon_device *rdev)
1275 {
1276         r600_blit_fini(rdev);
1277         r700_cp_fini(rdev);
1278         r600_irq_fini(rdev);
1279         radeon_wb_fini(rdev);
1280         radeon_ib_pool_fini(rdev);
1281         radeon_irq_kms_fini(rdev);
1282         rv770_pcie_gart_fini(rdev);
1283         r600_vram_scratch_fini(rdev);
1284         radeon_gem_fini(rdev);
1285         radeon_fence_driver_fini(rdev);
1286         radeon_agp_fini(rdev);
1287         radeon_bo_fini(rdev);
1288         radeon_atombios_fini(rdev);
1289         kfree(rdev->bios);
1290         rdev->bios = NULL;
1291 }
1292
1293 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1294 {
1295         u32 link_width_cntl, lanes, speed_cntl, tmp;
1296         u16 link_cntl2;
1297
1298         if (radeon_pcie_gen2 == 0)
1299                 return;
1300
1301         if (rdev->flags & RADEON_IS_IGP)
1302                 return;
1303
1304         if (!(rdev->flags & RADEON_IS_PCIE))
1305                 return;
1306
1307         /* x2 cards have a special sequence */
1308         if (ASIC_IS_X2(rdev))
1309                 return;
1310
1311         /* advertise upconfig capability */
1312         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1313         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1314         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1315         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1316         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1317                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1318                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1319                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
1320                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1321                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1322                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1323         } else {
1324                 link_width_cntl |= LC_UPCONFIGURE_DIS;
1325                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1326         }
1327
1328         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1329         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1330             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1331
1332                 tmp = RREG32(0x541c);
1333                 WREG32(0x541c, tmp | 0x8);
1334                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1335                 link_cntl2 = RREG16(0x4088);
1336                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1337                 link_cntl2 |= 0x2;
1338                 WREG16(0x4088, link_cntl2);
1339                 WREG32(MM_CFGREGS_CNTL, 0);
1340
1341                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1342                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1343                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1344
1345                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1346                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1347                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1348
1349                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1350                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1351                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1352
1353                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1354                 speed_cntl |= LC_GEN2_EN_STRAP;
1355                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1356
1357         } else {
1358                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1359                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1360                 if (1)
1361                         link_width_cntl |= LC_UPCONFIGURE_DIS;
1362                 else
1363                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1364                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1365         }
1366 }