drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  47 {
  48         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  49         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  50
  51         /* Lock the graphics update lock */
  52         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  53         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  54
  55         /* update the scanout addresses */
  56         if (radeon_crtc->crtc_id) {
  57                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  58                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  59         } else {
  60                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  61                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  62         }
  63         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  64                (u32)crtc_base);
  65         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  66                (u32)crtc_base);
  67
  68         /* Wait for update_pending to go high. */
  69         while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
  70         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  71
  72         /* Unlock the lock, so double-buffering can take place inside vblank */
  73         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  74         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* Return current update_pending status: */
  77         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  78 }
  79
  80 /* get temperature in millidegrees */
  81 int rv770_get_temp(struct radeon_device *rdev)
  82 {
  83         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  84                 ASIC_T_SHIFT;
  85         int actual_temp;
  86
  87         if (temp & 0x400)
  88                 actual_temp = -256;
  89         else if (temp & 0x200)
  90                 actual_temp = 255;
  91         else if (temp & 0x100) {
  92                 actual_temp = temp & 0x1ff;
  93                 actual_temp |= ~0x1ff;
  94         } else
  95                 actual_temp = temp & 0xff;
  96
  97         return (actual_temp * 1000) / 2;
  98 }
  99
 100 void rv770_pm_misc(struct radeon_device *rdev)
 101 {
 102         int req_ps_idx = rdev->pm.requested_power_state_index;
 103         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 104         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 105         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 106
 107         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 108                 if (voltage->voltage != rdev->pm.current_vddc) {
 109                         radeon_atom_set_voltage(rdev, voltage->voltage);
 110                         rdev->pm.current_vddc = voltage->voltage;
 111                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 112                 }
 113         }
 114 }
 115
 116 /*
 117  * GART
 118  */
 119 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 120 {
 121         u32 tmp;
 122         int r, i;
 123
 124         if (rdev->gart.table.vram.robj == NULL) {
 125                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 126                 return -EINVAL;
 127         }
 128         r = radeon_gart_table_vram_pin(rdev);
 129         if (r)
 130                 return r;
 131         radeon_gart_restore(rdev);
 132         /* Setup L2 cache */
 133         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 134                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 135                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 136         WREG32(VM_L2_CNTL2, 0);
 137         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 138         /* Setup TLB control */
 139         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 140                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 141                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 142                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 143         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 144         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 145         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 146         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 147         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 148         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 149         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 150         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 151         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 152         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 153         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 154                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 155         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 156                         (u32)(rdev->dummy_page.addr >> 12));
 157         for (i = 1; i < 7; i++)
 158                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 159
 160         r600_pcie_gart_tlb_flush(rdev);
 161         rdev->gart.ready = true;
 162         return 0;
 163 }
 164
 165 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 166 {
 167         u32 tmp;
 168         int i, r;
 169
 170         /* Disable all tables */
 171         for (i = 0; i < 7; i++)
 172                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 173
 174         /* Setup L2 cache */
 175         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 176                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 177         WREG32(VM_L2_CNTL2, 0);
 178         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 179         /* Setup TLB control */
 180         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 181         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 182         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 183         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 184         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 185         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 186         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 187         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 188         if (rdev->gart.table.vram.robj) {
 189                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 190                 if (likely(r == 0)) {
 191                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 192                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 193                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 194                 }
 195         }
 196 }
 197
 198 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 199 {
 200         radeon_gart_fini(rdev);
 201         rv770_pcie_gart_disable(rdev);
 202         radeon_gart_table_vram_free(rdev);
 203 }
 204
 205
 206 void rv770_agp_enable(struct radeon_device *rdev)
 207 {
 208         u32 tmp;
 209         int i;
 210
 211         /* Setup L2 cache */
 212         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 213                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 214                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 215         WREG32(VM_L2_CNTL2, 0);
 216         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 217         /* Setup TLB control */
 218         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 219                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 220                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 221                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 222         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 223         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 224         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 225         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 226         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 227         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 228         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 229         for (i = 0; i < 7; i++)
 230                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 231 }
 232
 233 static void rv770_mc_program(struct radeon_device *rdev)
 234 {
 235         struct rv515_mc_save save;
 236         u32 tmp;
 237         int i, j;
 238
 239         /* Initialize HDP */
 240         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 241                 WREG32((0x2c14 + j), 0x00000000);
 242                 WREG32((0x2c18 + j), 0x00000000);
 243                 WREG32((0x2c1c + j), 0x00000000);
 244                 WREG32((0x2c20 + j), 0x00000000);
 245                 WREG32((0x2c24 + j), 0x00000000);
 246         }
 247         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 248          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 249          */
 250         tmp = RREG32(HDP_DEBUG1);
 251
 252         rv515_mc_stop(rdev, &save);
 253         if (r600_mc_wait_for_idle(rdev)) {
 254                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 255         }
 256         /* Lockout access through VGA aperture*/
 257         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 258         /* Update configuration */
 259         if (rdev->flags & RADEON_IS_AGP) {
 260                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 261                         /* VRAM before AGP */
 262                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 263                                 rdev->mc.vram_start >> 12);
 264                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 265                                 rdev->mc.gtt_end >> 12);
 266                 } else {
 267                         /* VRAM after AGP */
 268                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 269                                 rdev->mc.gtt_start >> 12);
 270                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 271                                 rdev->mc.vram_end >> 12);
 272                 }
 273         } else {
 274                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 275                         rdev->mc.vram_start >> 12);
 276                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 277                         rdev->mc.vram_end >> 12);
 278         }
 279         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 280         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 281         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 282         WREG32(MC_VM_FB_LOCATION, tmp);
 283         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 284         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 285         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 286         if (rdev->flags & RADEON_IS_AGP) {
 287                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 288                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 289                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 290         } else {
 291                 WREG32(MC_VM_AGP_BASE, 0);
 292                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 293                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 294         }
 295         if (r600_mc_wait_for_idle(rdev)) {
 296                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 297         }
 298         rv515_mc_resume(rdev, &save);
 299         /* we need to own VRAM, so turn off the VGA renderer here
 300          * to stop it overwriting our objects */
 301         rv515_vga_render_disable(rdev);
 302 }
 303
 304
 305 /*
 306  * CP.
 307  */
 308 void r700_cp_stop(struct radeon_device *rdev)
 309 {
 310         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 311         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 312         WREG32(SCRATCH_UMSK, 0);
 313 }
 314
 315 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 316 {
 317         const __be32 *fw_data;
 318         int i;
 319
 320         if (!rdev->me_fw || !rdev->pfp_fw)
 321                 return -EINVAL;
 322
 323         r700_cp_stop(rdev);
 324         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 325
 326         /* Reset cp */
 327         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 328         RREG32(GRBM_SOFT_RESET);
 329         mdelay(15);
 330         WREG32(GRBM_SOFT_RESET, 0);
 331
 332         fw_data = (const __be32 *)rdev->pfp_fw->data;
 333         WREG32(CP_PFP_UCODE_ADDR, 0);
 334         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 335                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 336         WREG32(CP_PFP_UCODE_ADDR, 0);
 337
 338         fw_data = (const __be32 *)rdev->me_fw->data;
 339         WREG32(CP_ME_RAM_WADDR, 0);
 340         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 341                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 342
 343         WREG32(CP_PFP_UCODE_ADDR, 0);
 344         WREG32(CP_ME_RAM_WADDR, 0);
 345         WREG32(CP_ME_RAM_RADDR, 0);
 346         return 0;
 347 }
 348
 349 void r700_cp_fini(struct radeon_device *rdev)
 350 {
 351         r700_cp_stop(rdev);
 352         radeon_ring_fini(rdev);
 353 }
 354
 355 /*
 356  * Core functions
 357  */
 358 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 359                                              u32 num_tile_pipes,
 360                                              u32 num_backends,
 361                                              u32 backend_disable_mask)
 362 {
 363         u32 backend_map = 0;
 364         u32 enabled_backends_mask;
 365         u32 enabled_backends_count;
 366         u32 cur_pipe;
 367         u32 swizzle_pipe[R7XX_MAX_PIPES];
 368         u32 cur_backend;
 369         u32 i;
 370         bool force_no_swizzle;
 371
 372         if (num_tile_pipes > R7XX_MAX_PIPES)
 373                 num_tile_pipes = R7XX_MAX_PIPES;
 374         if (num_tile_pipes < 1)
 375                 num_tile_pipes = 1;
 376         if (num_backends > R7XX_MAX_BACKENDS)
 377                 num_backends = R7XX_MAX_BACKENDS;
 378         if (num_backends < 1)
 379                 num_backends = 1;
 380
 381         enabled_backends_mask = 0;
 382         enabled_backends_count = 0;
 383         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 384                 if (((backend_disable_mask >> i) & 1) == 0) {
 385                         enabled_backends_mask |= (1 << i);
 386                         ++enabled_backends_count;
 387                 }
 388                 if (enabled_backends_count == num_backends)
 389                         break;
 390         }
 391
 392         if (enabled_backends_count == 0) {
 393                 enabled_backends_mask = 1;
 394                 enabled_backends_count = 1;
 395         }
 396
 397         if (enabled_backends_count != num_backends)
 398                 num_backends = enabled_backends_count;
 399
 400         switch (rdev->family) {
 401         case CHIP_RV770:
 402         case CHIP_RV730:
 403                 force_no_swizzle = false;
 404                 break;
 405         case CHIP_RV710:
 406         case CHIP_RV740:
 407         default:
 408                 force_no_swizzle = true;
 409                 break;
 410         }
 411
 412         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 413         switch (num_tile_pipes) {
 414         case 1:
 415                 swizzle_pipe[0] = 0;
 416                 break;
 417         case 2:
 418                 swizzle_pipe[0] = 0;
 419                 swizzle_pipe[1] = 1;
 420                 break;
 421         case 3:
 422                 if (force_no_swizzle) {
 423                         swizzle_pipe[0] = 0;
 424                         swizzle_pipe[1] = 1;
 425                         swizzle_pipe[2] = 2;
 426                 } else {
 427                         swizzle_pipe[0] = 0;
 428                         swizzle_pipe[1] = 2;
 429                         swizzle_pipe[2] = 1;
 430                 }
 431                 break;
 432         case 4:
 433                 if (force_no_swizzle) {
 434                         swizzle_pipe[0] = 0;
 435                         swizzle_pipe[1] = 1;
 436                         swizzle_pipe[2] = 2;
 437                         swizzle_pipe[3] = 3;
 438                 } else {
 439                         swizzle_pipe[0] = 0;
 440                         swizzle_pipe[1] = 2;
 441                         swizzle_pipe[2] = 3;
 442                         swizzle_pipe[3] = 1;
 443                 }
 444                 break;
 445         case 5:
 446                 if (force_no_swizzle) {
 447                         swizzle_pipe[0] = 0;
 448                         swizzle_pipe[1] = 1;
 449                         swizzle_pipe[2] = 2;
 450                         swizzle_pipe[3] = 3;
 451                         swizzle_pipe[4] = 4;
 452                 } else {
 453                         swizzle_pipe[0] = 0;
 454                         swizzle_pipe[1] = 2;
 455                         swizzle_pipe[2] = 4;
 456                         swizzle_pipe[3] = 1;
 457                         swizzle_pipe[4] = 3;
 458                 }
 459                 break;
 460         case 6:
 461                 if (force_no_swizzle) {
 462                         swizzle_pipe[0] = 0;
 463                         swizzle_pipe[1] = 1;
 464                         swizzle_pipe[2] = 2;
 465                         swizzle_pipe[3] = 3;
 466                         swizzle_pipe[4] = 4;
 467                         swizzle_pipe[5] = 5;
 468                 } else {
 469                         swizzle_pipe[0] = 0;
 470                         swizzle_pipe[1] = 2;
 471                         swizzle_pipe[2] = 4;
 472                         swizzle_pipe[3] = 5;
 473                         swizzle_pipe[4] = 3;
 474                         swizzle_pipe[5] = 1;
 475                 }
 476                 break;
 477         case 7:
 478                 if (force_no_swizzle) {
 479                         swizzle_pipe[0] = 0;
 480                         swizzle_pipe[1] = 1;
 481                         swizzle_pipe[2] = 2;
 482                         swizzle_pipe[3] = 3;
 483                         swizzle_pipe[4] = 4;
 484                         swizzle_pipe[5] = 5;
 485                         swizzle_pipe[6] = 6;
 486                 } else {
 487                         swizzle_pipe[0] = 0;
 488                         swizzle_pipe[1] = 2;
 489                         swizzle_pipe[2] = 4;
 490                         swizzle_pipe[3] = 6;
 491                         swizzle_pipe[4] = 3;
 492                         swizzle_pipe[5] = 1;
 493                         swizzle_pipe[6] = 5;
 494                 }
 495                 break;
 496         case 8:
 497                 if (force_no_swizzle) {
 498                         swizzle_pipe[0] = 0;
 499                         swizzle_pipe[1] = 1;
 500                         swizzle_pipe[2] = 2;
 501                         swizzle_pipe[3] = 3;
 502                         swizzle_pipe[4] = 4;
 503                         swizzle_pipe[5] = 5;
 504                         swizzle_pipe[6] = 6;
 505                         swizzle_pipe[7] = 7;
 506                 } else {
 507                         swizzle_pipe[0] = 0;
 508                         swizzle_pipe[1] = 2;
 509                         swizzle_pipe[2] = 4;
 510                         swizzle_pipe[3] = 6;
 511                         swizzle_pipe[4] = 3;
 512                         swizzle_pipe[5] = 1;
 513                         swizzle_pipe[6] = 7;
 514                         swizzle_pipe[7] = 5;
 515                 }
 516                 break;
 517         }
 518
 519         cur_backend = 0;
 520         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 521                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 522                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 523
 524                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 525
 526                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 527         }
 528
 529         return backend_map;
 530 }
 531
 532 static void rv770_program_channel_remap(struct radeon_device *rdev)
 533 {
 534         u32 tcp_chan_steer, mc_shared_chremap, tmp;
 535         bool force_no_swizzle;
 536
 537         switch (rdev->family) {
 538         case CHIP_RV770:
 539         case CHIP_RV730:
 540                 force_no_swizzle = false;
 541                 break;
 542         case CHIP_RV710:
 543         case CHIP_RV740:
 544         default:
 545                 force_no_swizzle = true;
 546                 break;
 547         }
 548
 549         tmp = RREG32(MC_SHARED_CHMAP);
 550         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 551         case 0:
 552         case 1:
 553         default:
 554                 /* default mapping */
 555                 mc_shared_chremap = 0x00fac688;
 556                 break;
 557         case 2:
 558         case 3:
 559                 if (force_no_swizzle)
 560                         mc_shared_chremap = 0x00fac688;
 561                 else
 562                         mc_shared_chremap = 0x00bbc298;
 563                 break;
 564         }
 565
 566         if (rdev->family == CHIP_RV740)
 567                 tcp_chan_steer = 0x00ef2a60;
 568         else
 569                 tcp_chan_steer = 0x00fac688;
 570
 571         WREG32(TCP_CHAN_STEER, tcp_chan_steer);
 572         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
 573 }
 574
 575 static void rv770_gpu_init(struct radeon_device *rdev)
 576 {
 577         int i, j, num_qd_pipes;
 578         u32 ta_aux_cntl;
 579         u32 sx_debug_1;
 580         u32 smx_dc_ctl0;
 581         u32 db_debug3;
 582         u32 num_gs_verts_per_thread;
 583         u32 vgt_gs_per_es;
 584         u32 gs_prim_buffer_depth = 0;
 585         u32 sq_ms_fifo_sizes;
 586         u32 sq_config;
 587         u32 sq_thread_resource_mgmt;
 588         u32 hdp_host_path_cntl;
 589         u32 sq_dyn_gpr_size_simd_ab_0;
 590         u32 backend_map;
 591         u32 gb_tiling_config = 0;
 592         u32 cc_rb_backend_disable = 0;
 593         u32 cc_gc_shader_pipe_config = 0;
 594         u32 mc_arb_ramcfg;
 595         u32 db_debug4;
 596
 597         /* setup chip specs */
 598         switch (rdev->family) {
 599         case CHIP_RV770:
 600                 rdev->config.rv770.max_pipes = 4;
 601                 rdev->config.rv770.max_tile_pipes = 8;
 602                 rdev->config.rv770.max_simds = 10;
 603                 rdev->config.rv770.max_backends = 4;
 604                 rdev->config.rv770.max_gprs = 256;
 605                 rdev->config.rv770.max_threads = 248;
 606                 rdev->config.rv770.max_stack_entries = 512;
 607                 rdev->config.rv770.max_hw_contexts = 8;
 608                 rdev->config.rv770.max_gs_threads = 16 * 2;
 609                 rdev->config.rv770.sx_max_export_size = 128;
 610                 rdev->config.rv770.sx_max_export_pos_size = 16;
 611                 rdev->config.rv770.sx_max_export_smx_size = 112;
 612                 rdev->config.rv770.sq_num_cf_insts = 2;
 613
 614                 rdev->config.rv770.sx_num_of_sets = 7;
 615                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 616                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 617                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 618                 break;
 619         case CHIP_RV730:
 620                 rdev->config.rv770.max_pipes = 2;
 621                 rdev->config.rv770.max_tile_pipes = 4;
 622                 rdev->config.rv770.max_simds = 8;
 623                 rdev->config.rv770.max_backends = 2;
 624                 rdev->config.rv770.max_gprs = 128;
 625                 rdev->config.rv770.max_threads = 248;
 626                 rdev->config.rv770.max_stack_entries = 256;
 627                 rdev->config.rv770.max_hw_contexts = 8;
 628                 rdev->config.rv770.max_gs_threads = 16 * 2;
 629                 rdev->config.rv770.sx_max_export_size = 256;
 630                 rdev->config.rv770.sx_max_export_pos_size = 32;
 631                 rdev->config.rv770.sx_max_export_smx_size = 224;
 632                 rdev->config.rv770.sq_num_cf_insts = 2;
 633
 634                 rdev->config.rv770.sx_num_of_sets = 7;
 635                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 636                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 637                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 638                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 639                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 640                         rdev->config.rv770.sx_max_export_smx_size += 16;
 641                 }
 642                 break;
 643         case CHIP_RV710:
 644                 rdev->config.rv770.max_pipes = 2;
 645                 rdev->config.rv770.max_tile_pipes = 2;
 646                 rdev->config.rv770.max_simds = 2;
 647                 rdev->config.rv770.max_backends = 1;
 648                 rdev->config.rv770.max_gprs = 256;
 649                 rdev->config.rv770.max_threads = 192;
 650                 rdev->config.rv770.max_stack_entries = 256;
 651                 rdev->config.rv770.max_hw_contexts = 4;
 652                 rdev->config.rv770.max_gs_threads = 8 * 2;
 653                 rdev->config.rv770.sx_max_export_size = 128;
 654                 rdev->config.rv770.sx_max_export_pos_size = 16;
 655                 rdev->config.rv770.sx_max_export_smx_size = 112;
 656                 rdev->config.rv770.sq_num_cf_insts = 1;
 657
 658                 rdev->config.rv770.sx_num_of_sets = 7;
 659                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 660                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 661                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 662                 break;
 663         case CHIP_RV740:
 664                 rdev->config.rv770.max_pipes = 4;
 665                 rdev->config.rv770.max_tile_pipes = 4;
 666                 rdev->config.rv770.max_simds = 8;
 667                 rdev->config.rv770.max_backends = 4;
 668                 rdev->config.rv770.max_gprs = 256;
 669                 rdev->config.rv770.max_threads = 248;
 670                 rdev->config.rv770.max_stack_entries = 512;
 671                 rdev->config.rv770.max_hw_contexts = 8;
 672                 rdev->config.rv770.max_gs_threads = 16 * 2;
 673                 rdev->config.rv770.sx_max_export_size = 256;
 674                 rdev->config.rv770.sx_max_export_pos_size = 32;
 675                 rdev->config.rv770.sx_max_export_smx_size = 224;
 676                 rdev->config.rv770.sq_num_cf_insts = 2;
 677
 678                 rdev->config.rv770.sx_num_of_sets = 7;
 679                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 680                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 681                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 682
 683                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 684                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 685                         rdev->config.rv770.sx_max_export_smx_size += 16;
 686                 }
 687                 break;
 688         default:
 689                 break;
 690         }
 691
 692         /* Initialize HDP */
 693         j = 0;
 694         for (i = 0; i < 32; i++) {
 695                 WREG32((0x2c14 + j), 0x00000000);
 696                 WREG32((0x2c18 + j), 0x00000000);
 697                 WREG32((0x2c1c + j), 0x00000000);
 698                 WREG32((0x2c20 + j), 0x00000000);
 699                 WREG32((0x2c24 + j), 0x00000000);
 700                 j += 0x18;
 701         }
 702
 703         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 704
 705         /* setup tiling, simd, pipe config */
 706         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 707
 708         switch (rdev->config.rv770.max_tile_pipes) {
 709         case 1:
 710         default:
 711                 gb_tiling_config |= PIPE_TILING(0);
 712                 break;
 713         case 2:
 714                 gb_tiling_config |= PIPE_TILING(1);
 715                 break;
 716         case 4:
 717                 gb_tiling_config |= PIPE_TILING(2);
 718                 break;
 719         case 8:
 720                 gb_tiling_config |= PIPE_TILING(3);
 721                 break;
 722         }
 723         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 724
 725         if (rdev->family == CHIP_RV770)
 726                 gb_tiling_config |= BANK_TILING(1);
 727         else
 728                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 729         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 730         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 731         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 732                 rdev->config.rv770.tiling_group_size = 512;
 733         else
 734                 rdev->config.rv770.tiling_group_size = 256;
 735         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 736                 gb_tiling_config |= ROW_TILING(3);
 737                 gb_tiling_config |= SAMPLE_SPLIT(3);
 738         } else {
 739                 gb_tiling_config |=
 740                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 741                 gb_tiling_config |=
 742                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 743         }
 744
 745         gb_tiling_config |= BANK_SWAPS(1);
 746
 747         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 748         cc_rb_backend_disable |=
 749                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 750
 751         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 752         cc_gc_shader_pipe_config |=
 753                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 754         cc_gc_shader_pipe_config |=
 755                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 756
 757         if (rdev->family == CHIP_RV740)
 758                 backend_map = 0x28;
 759         else
 760                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 761                                                                 rdev->config.rv770.max_tile_pipes,
 762                                                                 (R7XX_MAX_BACKENDS -
 763                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 764                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 765                                                                 (cc_rb_backend_disable >> 16));
 766
 767         rdev->config.rv770.tile_config = gb_tiling_config;
 768         gb_tiling_config |= BACKEND_MAP(backend_map);
 769
 770         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 771         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 772         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 773
 774         rv770_program_channel_remap(rdev);
 775
 776         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 777         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 778         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 779         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 780
 781         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 782         WREG32(CGTS_TCC_DISABLE, 0);
 783         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 784         WREG32(CGTS_USER_TCC_DISABLE, 0);
 785
 786         num_qd_pipes =
 787                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 788         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 789         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 790
 791         /* set HW defaults for 3D engine */
 792         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 793                                      ROQ_IB2_START(0x2b)));
 794
 795         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 796
 797         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 798         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 799
 800         sx_debug_1 = RREG32(SX_DEBUG_1);
 801         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 802         WREG32(SX_DEBUG_1, sx_debug_1);
 803
 804         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 805         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 806         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 807         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 808
 809         if (rdev->family != CHIP_RV740)
 810                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 811                                        GS_FLUSH_CTL(4) |
 812                                        ACK_FLUSH_CTL(3) |
 813                                        SYNC_FLUSH_CTL));
 814
 815         db_debug3 = RREG32(DB_DEBUG3);
 816         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 817         switch (rdev->family) {
 818         case CHIP_RV770:
 819         case CHIP_RV740:
 820                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 821                 break;
 822         case CHIP_RV710:
 823         case CHIP_RV730:
 824         default:
 825                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 826                 break;
 827         }
 828         WREG32(DB_DEBUG3, db_debug3);
 829
 830         if (rdev->family != CHIP_RV770) {
 831                 db_debug4 = RREG32(DB_DEBUG4);
 832                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 833                 WREG32(DB_DEBUG4, db_debug4);
 834         }
 835
 836         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 837                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 838                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 839
 840         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 841                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 842                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 843
 844         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 845
 846         WREG32(VGT_NUM_INSTANCES, 1);
 847
 848         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 849
 850         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 851
 852         WREG32(CP_PERFMON_CNTL, 0);
 853
 854         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 855                             DONE_FIFO_HIWATER(0xe0) |
 856                             ALU_UPDATE_FIFO_HIWATER(0x8));
 857         switch (rdev->family) {
 858         case CHIP_RV770:
 859         case CHIP_RV730:
 860         case CHIP_RV710:
 861                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 862                 break;
 863         case CHIP_RV740:
 864         default:
 865                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 866                 break;
 867         }
 868         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 869
 870         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 871          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 872          */
 873         sq_config = RREG32(SQ_CONFIG);
 874         sq_config &= ~(PS_PRIO(3) |
 875                        VS_PRIO(3) |
 876                        GS_PRIO(3) |
 877                        ES_PRIO(3));
 878         sq_config |= (DX9_CONSTS |
 879                       VC_ENABLE |
 880                       EXPORT_SRC_C |
 881                       PS_PRIO(0) |
 882                       VS_PRIO(1) |
 883                       GS_PRIO(2) |
 884                       ES_PRIO(3));
 885         if (rdev->family == CHIP_RV710)
 886                 /* no vertex cache */
 887                 sq_config &= ~VC_ENABLE;
 888
 889         WREG32(SQ_CONFIG, sq_config);
 890
 891         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 892                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 893                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 894
 895         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 896                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 897
 898         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 899                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 900                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 901         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 902                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 903         else
 904                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 905         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 906
 907         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 908                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 909
 910         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 911                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 912
 913         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 914                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 915                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 916                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 917
 918         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 919         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 920         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 921         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 922         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 923         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 924         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 925         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 926
 927         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 928                                           FORCE_EOV_MAX_REZ_CNT(255)));
 929
 930         if (rdev->family == CHIP_RV710)
 931                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 932                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 933         else
 934                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 935                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 936
 937         switch (rdev->family) {
 938         case CHIP_RV770:
 939         case CHIP_RV730:
 940         case CHIP_RV740:
 941                 gs_prim_buffer_depth = 384;
 942                 break;
 943         case CHIP_RV710:
 944                 gs_prim_buffer_depth = 128;
 945                 break;
 946         default:
 947                 break;
 948         }
 949
 950         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 951         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 952         /* Max value for this is 256 */
 953         if (vgt_gs_per_es > 256)
 954                 vgt_gs_per_es = 256;
 955
 956         WREG32(VGT_ES_PER_GS, 128);
 957         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 958         WREG32(VGT_GS_PER_VS, 2);
 959
 960         /* more default values. 2D/3D driver should adjust as needed */
 961         WREG32(VGT_GS_VERTEX_REUSE, 16);
 962         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 963         WREG32(VGT_STRMOUT_EN, 0);
 964         WREG32(SX_MISC, 0);
 965         WREG32(PA_SC_MODE_CNTL, 0);
 966         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 967         WREG32(PA_SC_AA_CONFIG, 0);
 968         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 969         WREG32(PA_SC_LINE_STIPPLE, 0);
 970         WREG32(SPI_INPUT_Z, 0);
 971         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 972         WREG32(CB_COLOR7_FRAG, 0);
 973
 974         /* clear render buffer base addresses */
 975         WREG32(CB_COLOR0_BASE, 0);
 976         WREG32(CB_COLOR1_BASE, 0);
 977         WREG32(CB_COLOR2_BASE, 0);
 978         WREG32(CB_COLOR3_BASE, 0);
 979         WREG32(CB_COLOR4_BASE, 0);
 980         WREG32(CB_COLOR5_BASE, 0);
 981         WREG32(CB_COLOR6_BASE, 0);
 982         WREG32(CB_COLOR7_BASE, 0);
 983
 984         WREG32(TCP_CNTL, 0);
 985
 986         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 987         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 988
 989         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 990
 991         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 992                                           NUM_CLIP_SEQ(3)));
 993
 994 }
 995
 996 static int rv770_vram_scratch_init(struct radeon_device *rdev)
 997 {
 998         int r;
 999         u64 gpu_addr;
1000
1001         if (rdev->vram_scratch.robj == NULL) {
1002                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
1003                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1004                                      &rdev->vram_scratch.robj);
1005                 if (r) {
1006                         return r;
1007                 }
1008         }
1009
1010         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1011         if (unlikely(r != 0))
1012                 return r;
1013         r = radeon_bo_pin(rdev->vram_scratch.robj,
1014                           RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
1015         if (r) {
1016                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1017                 return r;
1018         }
1019         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1020                                 (void **)&rdev->vram_scratch.ptr);
1021         if (r)
1022                 radeon_bo_unpin(rdev->vram_scratch.robj);
1023         radeon_bo_unreserve(rdev->vram_scratch.robj);
1024
1025         return r;
1026 }
1027
1028 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
1029 {
1030         int r;
1031
1032         if (rdev->vram_scratch.robj == NULL) {
1033                 return;
1034         }
1035         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1036         if (likely(r == 0)) {
1037                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1038                 radeon_bo_unpin(rdev->vram_scratch.robj);
1039                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1040         }
1041         radeon_bo_unref(&rdev->vram_scratch.robj);
1042 }
1043
1044 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1045 {
1046         u64 size_bf, size_af;
1047
1048         if (mc->mc_vram_size > 0xE0000000) {
1049                 /* leave room for at least 512M GTT */
1050                 dev_warn(rdev->dev, "limiting VRAM\n");
1051                 mc->real_vram_size = 0xE0000000;
1052                 mc->mc_vram_size = 0xE0000000;
1053         }
1054         if (rdev->flags & RADEON_IS_AGP) {
1055                 size_bf = mc->gtt_start;
1056                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1057                 if (size_bf > size_af) {
1058                         if (mc->mc_vram_size > size_bf) {
1059                                 dev_warn(rdev->dev, "limiting VRAM\n");
1060                                 mc->real_vram_size = size_bf;
1061                                 mc->mc_vram_size = size_bf;
1062                         }
1063                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1064                 } else {
1065                         if (mc->mc_vram_size > size_af) {
1066                                 dev_warn(rdev->dev, "limiting VRAM\n");
1067                                 mc->real_vram_size = size_af;
1068                                 mc->mc_vram_size = size_af;
1069                         }
1070                         mc->vram_start = mc->gtt_end;
1071                 }
1072                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1073                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1074                                 mc->mc_vram_size >> 20, mc->vram_start,
1075                                 mc->vram_end, mc->real_vram_size >> 20);
1076         } else {
1077                 radeon_vram_location(rdev, &rdev->mc, 0);
1078                 rdev->mc.gtt_base_align = 0;
1079                 radeon_gtt_location(rdev, mc);
1080         }
1081 }
1082
1083 int rv770_mc_init(struct radeon_device *rdev)
1084 {
1085         u32 tmp;
1086         int chansize, numchan;
1087
1088         /* Get VRAM informations */
1089         rdev->mc.vram_is_ddr = true;
1090         tmp = RREG32(MC_ARB_RAMCFG);
1091         if (tmp & CHANSIZE_OVERRIDE) {
1092                 chansize = 16;
1093         } else if (tmp & CHANSIZE_MASK) {
1094                 chansize = 64;
1095         } else {
1096                 chansize = 32;
1097         }
1098         tmp = RREG32(MC_SHARED_CHMAP);
1099         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1100         case 0:
1101         default:
1102                 numchan = 1;
1103                 break;
1104         case 1:
1105                 numchan = 2;
1106                 break;
1107         case 2:
1108                 numchan = 4;
1109                 break;
1110         case 3:
1111                 numchan = 8;
1112                 break;
1113         }
1114         rdev->mc.vram_width = numchan * chansize;
1115         /* Could aper size report 0 ? */
1116         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1117         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1118         /* Setup GPU memory space */
1119         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1120         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1121         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1122         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1123         r700_vram_gtt_location(rdev, &rdev->mc);
1124         radeon_update_bandwidth_info(rdev);
1125
1126         return 0;
1127 }
1128
1129 static int rv770_startup(struct radeon_device *rdev)
1130 {
1131         int r;
1132
1133         /* enable pcie gen2 link */
1134         rv770_pcie_gen2_enable(rdev);
1135
1136         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1137                 r = r600_init_microcode(rdev);
1138                 if (r) {
1139                         DRM_ERROR("Failed to load firmware!\n");
1140                         return r;
1141                 }
1142         }
1143
1144         rv770_mc_program(rdev);
1145         if (rdev->flags & RADEON_IS_AGP) {
1146                 rv770_agp_enable(rdev);
1147         } else {
1148                 r = rv770_pcie_gart_enable(rdev);
1149                 if (r)
1150                         return r;
1151         }
1152         r = rv770_vram_scratch_init(rdev);
1153         if (r)
1154                 return r;
1155         rv770_gpu_init(rdev);
1156         r = r600_blit_init(rdev);
1157         if (r) {
1158                 r600_blit_fini(rdev);
1159                 rdev->asic->copy = NULL;
1160                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1161         }
1162
1163         /* allocate wb buffer */
1164         r = radeon_wb_init(rdev);
1165         if (r)
1166                 return r;
1167
1168         /* Enable IRQ */
1169         r = r600_irq_init(rdev);
1170         if (r) {
1171                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1172                 radeon_irq_kms_fini(rdev);
1173                 return r;
1174         }
1175         r600_irq_set(rdev);
1176
1177         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1178         if (r)
1179                 return r;
1180         r = rv770_cp_load_microcode(rdev);
1181         if (r)
1182                 return r;
1183         r = r600_cp_resume(rdev);
1184         if (r)
1185                 return r;
1186
1187         return 0;
1188 }
1189
1190 int rv770_resume(struct radeon_device *rdev)
1191 {
1192         int r;
1193
1194         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1195          * posting will perform necessary task to bring back GPU into good
1196          * shape.
1197          */
1198         /* post card */
1199         atom_asic_init(rdev->mode_info.atom_context);
1200
1201         r = rv770_startup(rdev);
1202         if (r) {
1203                 DRM_ERROR("r600 startup failed on resume\n");
1204                 return r;
1205         }
1206
1207         r = r600_ib_test(rdev);
1208         if (r) {
1209                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1210                 return r;
1211         }
1212
1213         r = r600_audio_init(rdev);
1214         if (r) {
1215                 dev_err(rdev->dev, "radeon: audio init failed\n");
1216                 return r;
1217         }
1218
1219         return r;
1220
1221 }
1222
1223 int rv770_suspend(struct radeon_device *rdev)
1224 {
1225         int r;
1226
1227         r600_audio_fini(rdev);
1228         /* FIXME: we should wait for ring to be empty */
1229         r700_cp_stop(rdev);
1230         rdev->cp.ready = false;
1231         r600_irq_suspend(rdev);
1232         radeon_wb_disable(rdev);
1233         rv770_pcie_gart_disable(rdev);
1234         /* unpin shaders bo */
1235         if (rdev->r600_blit.shader_obj) {
1236                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1237                 if (likely(r == 0)) {
1238                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1239                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1240                 }
1241         }
1242         return 0;
1243 }
1244
1245 /* Plan is to move initialization in that function and use
1246  * helper function so that radeon_device_init pretty much
1247  * do nothing more than calling asic specific function. This
1248  * should also allow to remove a bunch of callback function
1249  * like vram_info.
1250  */
1251 int rv770_init(struct radeon_device *rdev)
1252 {
1253         int r;
1254
1255         r = radeon_dummy_page_init(rdev);
1256         if (r)
1257                 return r;
1258         /* This don't do much */
1259         r = radeon_gem_init(rdev);
1260         if (r)
1261                 return r;
1262         /* Read BIOS */
1263         if (!radeon_get_bios(rdev)) {
1264                 if (ASIC_IS_AVIVO(rdev))
1265                         return -EINVAL;
1266         }
1267         /* Must be an ATOMBIOS */
1268         if (!rdev->is_atom_bios) {
1269                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1270                 return -EINVAL;
1271         }
1272         r = radeon_atombios_init(rdev);
1273         if (r)
1274                 return r;
1275         /* Post card if necessary */
1276         if (!radeon_card_posted(rdev)) {
1277                 if (!rdev->bios) {
1278                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1279                         return -EINVAL;
1280                 }
1281                 DRM_INFO("GPU not posted. posting now...\n");
1282                 atom_asic_init(rdev->mode_info.atom_context);
1283         }
1284         /* Initialize scratch registers */
1285         r600_scratch_init(rdev);
1286         /* Initialize surface registers */
1287         radeon_surface_init(rdev);
1288         /* Initialize clocks */
1289         radeon_get_clock_info(rdev->ddev);
1290         /* Fence driver */
1291         r = radeon_fence_driver_init(rdev);
1292         if (r)
1293                 return r;
1294         /* initialize AGP */
1295         if (rdev->flags & RADEON_IS_AGP) {
1296                 r = radeon_agp_init(rdev);
1297                 if (r)
1298                         radeon_agp_disable(rdev);
1299         }
1300         r = rv770_mc_init(rdev);
1301         if (r)
1302                 return r;
1303         /* Memory manager */
1304         r = radeon_bo_init(rdev);
1305         if (r)
1306                 return r;
1307
1308         r = radeon_irq_kms_init(rdev);
1309         if (r)
1310                 return r;
1311
1312         rdev->cp.ring_obj = NULL;
1313         r600_ring_init(rdev, 1024 * 1024);
1314
1315         rdev->ih.ring_obj = NULL;
1316         r600_ih_ring_init(rdev, 64 * 1024);
1317
1318         r = r600_pcie_gart_init(rdev);
1319         if (r)
1320                 return r;
1321
1322         rdev->accel_working = true;
1323         r = rv770_startup(rdev);
1324         if (r) {
1325                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1326                 r700_cp_fini(rdev);
1327                 r600_irq_fini(rdev);
1328                 radeon_wb_fini(rdev);
1329                 radeon_irq_kms_fini(rdev);
1330                 rv770_pcie_gart_fini(rdev);
1331                 rdev->accel_working = false;
1332         }
1333         if (rdev->accel_working) {
1334                 r = radeon_ib_pool_init(rdev);
1335                 if (r) {
1336                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1337                         rdev->accel_working = false;
1338                 } else {
1339                         r = r600_ib_test(rdev);
1340                         if (r) {
1341                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1342                                 rdev->accel_working = false;
1343                         }
1344                 }
1345         }
1346
1347         r = r600_audio_init(rdev);
1348         if (r) {
1349                 dev_err(rdev->dev, "radeon: audio init failed\n");
1350                 return r;
1351         }
1352
1353         return 0;
1354 }
1355
1356 void rv770_fini(struct radeon_device *rdev)
1357 {
1358         r600_blit_fini(rdev);
1359         r700_cp_fini(rdev);
1360         r600_irq_fini(rdev);
1361         radeon_wb_fini(rdev);
1362         radeon_irq_kms_fini(rdev);
1363         rv770_pcie_gart_fini(rdev);
1364         rv770_vram_scratch_fini(rdev);
1365         radeon_gem_fini(rdev);
1366         radeon_fence_driver_fini(rdev);
1367         radeon_agp_fini(rdev);
1368         radeon_bo_fini(rdev);
1369         radeon_atombios_fini(rdev);
1370         kfree(rdev->bios);
1371         rdev->bios = NULL;
1372         radeon_dummy_page_fini(rdev);
1373 }
1374
1375 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1376 {
1377         u32 link_width_cntl, lanes, speed_cntl, tmp;
1378         u16 link_cntl2;
1379
1380         if (radeon_pcie_gen2 == 0)
1381                 return;
1382
1383         if (rdev->flags & RADEON_IS_IGP)
1384                 return;
1385
1386         if (!(rdev->flags & RADEON_IS_PCIE))
1387                 return;
1388
1389         /* x2 cards have a special sequence */
1390         if (ASIC_IS_X2(rdev))
1391                 return;
1392
1393         /* advertise upconfig capability */
1394         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1395         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1396         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1397         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1398         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1399                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1400                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1401                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
1402                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1403                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1404                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1405         } else {
1406                 link_width_cntl |= LC_UPCONFIGURE_DIS;
1407                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1408         }
1409
1410         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1411         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1412             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1413
1414                 tmp = RREG32(0x541c);
1415                 WREG32(0x541c, tmp | 0x8);
1416                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1417                 link_cntl2 = RREG16(0x4088);
1418                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1419                 link_cntl2 |= 0x2;
1420                 WREG16(0x4088, link_cntl2);
1421                 WREG32(MM_CFGREGS_CNTL, 0);
1422
1423                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1424                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1425                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1426
1427                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1428                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1429                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1430
1431                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1432                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1433                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1434
1435                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1436                 speed_cntl |= LC_GEN2_EN_STRAP;
1437                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1438
1439         } else {
1440                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1441                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1442                 if (1)
1443                         link_width_cntl |= LC_UPCONFIGURE_DIS;
1444                 else
1445                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1446                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1447         }
1448 }