drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30
  31 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  32 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  33 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  34 static void radeon_pm_idle_work_handler(struct work_struct *work);
  35 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  36
  37 static const char *pm_state_names[4] = {
  38         "PM_STATE_DISABLED",
  39         "PM_STATE_MINIMUM",
  40         "PM_STATE_PAUSED",
  41         "PM_STATE_ACTIVE"
  42 };
  43
  44 static const char *pm_state_types[5] = {
  45         "Default",
  46         "Powersave",
  47         "Battery",
  48         "Balanced",
  49         "Performance",
  50 };
  51
  52 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  53 {
  54         int i, j;
  55         bool is_default;
  56
  57         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  58         for (i = 0; i < rdev->pm.num_power_states; i++) {
  59                 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  60                         is_default = true;
  61                 else
  62                         is_default = false;
  63                 DRM_INFO("State %d %s %s\n", i,
  64                          pm_state_types[rdev->pm.power_state[i].type],
  65                          is_default ? "(default)" : "");
  66                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  67                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  68                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  69                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  70                         if (rdev->flags & RADEON_IS_IGP)
  71                                 DRM_INFO("\t\t%d engine: %d\n",
  72                                          j,
  73                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  74                         else
  75                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  76                                          j,
  77                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  78                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  79                 }
  80         }
  81 }
  82
  83 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  84                                                            enum radeon_pm_state_type type)
  85 {
  86         int i, j;
  87         enum radeon_pm_state_type wanted_types[2];
  88         int wanted_count;
  89
  90         switch (type) {
  91         case POWER_STATE_TYPE_DEFAULT:
  92         default:
  93                 return rdev->pm.default_power_state;
  94         case POWER_STATE_TYPE_POWERSAVE:
  95                 if (rdev->flags & RADEON_IS_MOBILITY) {
  96                         wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
  97                         wanted_types[1] = POWER_STATE_TYPE_BATTERY;
  98                         wanted_count = 2;
  99                 } else {
 100                         wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
 101                         wanted_count = 1;
 102                 }
 103                 break;
 104         case POWER_STATE_TYPE_BATTERY:
 105                 if (rdev->flags & RADEON_IS_MOBILITY) {
 106                         wanted_types[0] = POWER_STATE_TYPE_BATTERY;
 107                         wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
 108                         wanted_count = 2;
 109                 } else {
 110                         wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
 111                         wanted_count = 1;
 112                 }
 113                 break;
 114         case POWER_STATE_TYPE_BALANCED:
 115         case POWER_STATE_TYPE_PERFORMANCE:
 116                 wanted_types[0] = type;
 117                 wanted_count = 1;
 118                 break;
 119         }
 120
 121         for (i = 0; i < wanted_count; i++) {
 122                 for (j = 0; j < rdev->pm.num_power_states; j++) {
 123                         if (rdev->pm.power_state[j].type == wanted_types[i])
 124                                 return &rdev->pm.power_state[j];
 125                 }
 126         }
 127
 128         return rdev->pm.default_power_state;
 129 }
 130
 131 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
 132                                                             struct radeon_power_state *power_state,
 133                                                             enum radeon_pm_clock_mode_type type)
 134 {
 135         switch (type) {
 136         case POWER_MODE_TYPE_DEFAULT:
 137         default:
 138                 return power_state->default_clock_mode;
 139         case POWER_MODE_TYPE_LOW:
 140                 return &power_state->clock_info[0];
 141         case POWER_MODE_TYPE_MID:
 142                 if (power_state->num_clock_modes > 2)
 143                         return &power_state->clock_info[1];
 144                 else
 145                         return &power_state->clock_info[0];
 146                 break;
 147         case POWER_MODE_TYPE_HIGH:
 148                 return &power_state->clock_info[power_state->num_clock_modes - 1];
 149         }
 150
 151 }
 152
 153 static void radeon_get_power_state(struct radeon_device *rdev,
 154                                    enum radeon_pm_action action)
 155 {
 156         switch (action) {
 157         case PM_ACTION_MINIMUM:
 158                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
 159                 rdev->pm.requested_clock_mode =
 160                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
 161                 break;
 162         case PM_ACTION_DOWNCLOCK:
 163                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
 164                 rdev->pm.requested_clock_mode =
 165                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
 166                 break;
 167         case PM_ACTION_UPCLOCK:
 168                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
 169                 rdev->pm.requested_clock_mode =
 170                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
 171                 break;
 172         case PM_ACTION_NONE:
 173         default:
 174                 DRM_ERROR("Requested mode for not defined action\n");
 175                 return;
 176         }
 177         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 178                  rdev->pm.requested_clock_mode->sclk,
 179                  rdev->pm.requested_clock_mode->mclk,
 180                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 181 }
 182
 183 static inline void radeon_sync_with_vblank(struct radeon_device *rdev)
 184 {
 185         if (rdev->pm.active_crtcs) {
 186                 rdev->pm.vblank_sync = false;
 187                 wait_event_timeout(
 188                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 189                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 190         }
 191 }
 192
 193 static void radeon_set_power_state(struct radeon_device *rdev)
 194 {
 195         /* if *_clock_mode are the same, *_power_state are as well */
 196         if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode)
 197                 return;
 198
 199         DRM_INFO("Setting: e: %d m: %d p: %d\n",
 200                  rdev->pm.requested_clock_mode->sclk,
 201                  rdev->pm.requested_clock_mode->mclk,
 202                  rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
 203
 204         /* set pcie lanes */
 205         /* TODO */
 206
 207         /* set voltage */
 208         /* TODO */
 209
 210         /* set engine clock */
 211         radeon_sync_with_vblank(rdev);
 212         radeon_pm_debug_check_in_vbl(rdev, false);
 213         radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk);
 214         radeon_pm_debug_check_in_vbl(rdev, true);
 215
 216 #if 0
 217         /* set memory clock */
 218         if (rdev->asic->set_memory_clock) {
 219                 radeon_sync_with_vblank(rdev);
 220                 radeon_pm_debug_check_in_vbl(rdev, false);
 221                 radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk);
 222                 radeon_pm_debug_check_in_vbl(rdev, true);
 223         }
 224 #endif
 225
 226         rdev->pm.current_power_state = rdev->pm.requested_power_state;
 227         rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode;
 228 }
 229
 230 int radeon_pm_init(struct radeon_device *rdev)
 231 {
 232         rdev->pm.state = PM_STATE_DISABLED;
 233         rdev->pm.planned_action = PM_ACTION_NONE;
 234         rdev->pm.downclocked = false;
 235
 236         if (rdev->bios) {
 237                 if (rdev->is_atom_bios)
 238                         radeon_atombios_get_power_modes(rdev);
 239                 else
 240                         radeon_combios_get_power_modes(rdev);
 241                 radeon_print_power_mode_info(rdev);
 242         }
 243
 244         if (radeon_debugfs_pm_init(rdev)) {
 245                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 246         }
 247
 248         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 249
 250         if (radeon_dynpm != -1 && radeon_dynpm) {
 251                 rdev->pm.state = PM_STATE_PAUSED;
 252                 DRM_INFO("radeon: dynamic power management enabled\n");
 253         }
 254
 255         DRM_INFO("radeon: power management initialized\n");
 256
 257         return 0;
 258 }
 259
 260 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 261 {
 262         struct drm_device *ddev = rdev->ddev;
 263         struct drm_connector *connector;
 264         struct radeon_crtc *radeon_crtc;
 265         int count = 0;
 266
 267         if (rdev->pm.state == PM_STATE_DISABLED)
 268                 return;
 269
 270         mutex_lock(&rdev->pm.mutex);
 271
 272         rdev->pm.active_crtcs = 0;
 273         list_for_each_entry(connector,
 274                 &ddev->mode_config.connector_list, head) {
 275                 if (connector->encoder &&
 276                         connector->dpms != DRM_MODE_DPMS_OFF) {
 277                         radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
 278                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 279                         ++count;
 280                 }
 281         }
 282
 283         if (count > 1) {
 284                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 285                         cancel_delayed_work(&rdev->pm.idle_work);
 286
 287                         rdev->pm.state = PM_STATE_PAUSED;
 288                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 289                         if (rdev->pm.downclocked)
 290                                 radeon_pm_set_clocks(rdev);
 291
 292                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 293                 }
 294         } else if (count == 1) {
 295                 /* TODO: Increase clocks if needed for current mode */
 296
 297                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 298                         rdev->pm.state = PM_STATE_ACTIVE;
 299                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 300                         radeon_pm_set_clocks(rdev);
 301
 302                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 303                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 304                 }
 305                 else if (rdev->pm.state == PM_STATE_PAUSED) {
 306                         rdev->pm.state = PM_STATE_ACTIVE;
 307                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 308                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 309                         DRM_DEBUG("radeon: dynamic power management activated\n");
 310                 }
 311         }
 312         else { /* count == 0 */
 313                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 314                         cancel_delayed_work(&rdev->pm.idle_work);
 315
 316                         rdev->pm.state = PM_STATE_MINIMUM;
 317                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 318                         radeon_pm_set_clocks(rdev);
 319                 }
 320         }
 321
 322         mutex_unlock(&rdev->pm.mutex);
 323 }
 324
 325 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 326 {
 327         u32 stat_crtc1 = 0, stat_crtc2 = 0;
 328         bool in_vbl = true;
 329
 330         if (ASIC_IS_AVIVO(rdev)) {
 331                 if (rdev->pm.active_crtcs & (1 << 0)) {
 332                         stat_crtc1 = RREG32(D1CRTC_STATUS);
 333                         if (!(stat_crtc1 & 1))
 334                                 in_vbl = false;
 335                 }
 336                 if (rdev->pm.active_crtcs & (1 << 1)) {
 337                         stat_crtc2 = RREG32(D2CRTC_STATUS);
 338                         if (!(stat_crtc2 & 1))
 339                                 in_vbl = false;
 340                 }
 341         }
 342         if (in_vbl == false)
 343                 DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1,
 344                          stat_crtc2, finish ? "exit" : "entry");
 345         return in_vbl;
 346 }
 347 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 348 {
 349         /*radeon_fence_wait_last(rdev);*/
 350         switch (rdev->pm.planned_action) {
 351         case PM_ACTION_UPCLOCK:
 352                 rdev->pm.downclocked = false;
 353                 break;
 354         case PM_ACTION_DOWNCLOCK:
 355                 rdev->pm.downclocked = true;
 356                 break;
 357         case PM_ACTION_MINIMUM:
 358                 break;
 359         case PM_ACTION_NONE:
 360                 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
 361                 break;
 362         }
 363
 364         radeon_set_power_state(rdev);
 365         rdev->pm.planned_action = PM_ACTION_NONE;
 366 }
 367
 368 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 369 {
 370         radeon_get_power_state(rdev, rdev->pm.planned_action);
 371         mutex_lock(&rdev->cp.mutex);
 372
 373         if (rdev->pm.active_crtcs & (1 << 0)) {
 374                 rdev->pm.req_vblank |= (1 << 0);
 375                 drm_vblank_get(rdev->ddev, 0);
 376         }
 377         if (rdev->pm.active_crtcs & (1 << 1)) {
 378                 rdev->pm.req_vblank |= (1 << 1);
 379                 drm_vblank_get(rdev->ddev, 1);
 380         }
 381         radeon_pm_set_clocks_locked(rdev);
 382         if (rdev->pm.req_vblank & (1 << 0)) {
 383                 rdev->pm.req_vblank &= ~(1 << 0);
 384                 drm_vblank_put(rdev->ddev, 0);
 385         }
 386         if (rdev->pm.req_vblank & (1 << 1)) {
 387                 rdev->pm.req_vblank &= ~(1 << 1);
 388                 drm_vblank_put(rdev->ddev, 1);
 389         }
 390
 391         mutex_unlock(&rdev->cp.mutex);
 392 }
 393
 394 static void radeon_pm_idle_work_handler(struct work_struct *work)
 395 {
 396         struct radeon_device *rdev;
 397         rdev = container_of(work, struct radeon_device,
 398                                 pm.idle_work.work);
 399
 400         mutex_lock(&rdev->pm.mutex);
 401         if (rdev->pm.state == PM_STATE_ACTIVE) {
 402                 unsigned long irq_flags;
 403                 int not_processed = 0;
 404
 405                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 406                 if (!list_empty(&rdev->fence_drv.emited)) {
 407                         struct list_head *ptr;
 408                         list_for_each(ptr, &rdev->fence_drv.emited) {
 409                                 /* count up to 3, that's enought info */
 410                                 if (++not_processed >= 3)
 411                                         break;
 412                         }
 413                 }
 414                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 415
 416                 if (not_processed >= 3) { /* should upclock */
 417                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 418                                 rdev->pm.planned_action = PM_ACTION_NONE;
 419                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 420                                 rdev->pm.downclocked) {
 421                                 rdev->pm.planned_action =
 422                                         PM_ACTION_UPCLOCK;
 423                                 rdev->pm.action_timeout = jiffies +
 424                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 425                         }
 426                 } else if (not_processed == 0) { /* should downclock */
 427                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 428                                 rdev->pm.planned_action = PM_ACTION_NONE;
 429                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 430                                 !rdev->pm.downclocked) {
 431                                 rdev->pm.planned_action =
 432                                         PM_ACTION_DOWNCLOCK;
 433                                 rdev->pm.action_timeout = jiffies +
 434                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 435                         }
 436                 }
 437
 438                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 439                     jiffies > rdev->pm.action_timeout) {
 440                         radeon_pm_set_clocks(rdev);
 441                 }
 442         }
 443         mutex_unlock(&rdev->pm.mutex);
 444
 445         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 446                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 447 }
 448
 449 /*
 450  * Debugfs info
 451  */
 452 #if defined(CONFIG_DEBUG_FS)
 453
 454 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 455 {
 456         struct drm_info_node *node = (struct drm_info_node *) m->private;
 457         struct drm_device *dev = node->minor->dev;
 458         struct radeon_device *rdev = dev->dev_private;
 459
 460         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 461         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 462         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 463         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 464         if (rdev->asic->get_memory_clock)
 465                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 466         if (rdev->asic->get_pcie_lanes)
 467                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 468
 469         return 0;
 470 }
 471
 472 static struct drm_info_list radeon_pm_info_list[] = {
 473         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 474 };
 475 #endif
 476
 477 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 478 {
 479 #if defined(CONFIG_DEBUG_FS)
 480         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 481 #else
 482         return 0;
 483 #endif
 484 }