2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/acpi.h>
30 #include <linux/power_supply.h>
31 #include <linux/hwmon.h>
32 #include <linux/hwmon-sysfs.h>
34 #define RADEON_IDLE_LOOP_MS 100
35 #define RADEON_RECLOCK_DELAY_MS 200
36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
37 #define RADEON_WAIT_IDLE_TIMEOUT 200
39 static const char *radeon_pm_state_type_name[5] = {
47 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51 static void radeon_pm_update_profile(struct radeon_device *rdev);
52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
54 #define ACPI_AC_CLASS "ac_adapter"
56 int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
61 int found_instance = -1;
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
66 if (found_instance == instance)
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
75 static int radeon_acpi_event(struct notifier_block *nb,
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
84 DRM_DEBUG_DRIVER("pm: AC\n");
86 DRM_DEBUG_DRIVER("pm: DC\n");
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
102 static void radeon_pm_update_profile(struct radeon_device *rdev)
104 switch (rdev->pm.profile) {
105 case PM_PROFILE_DEFAULT:
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
108 case PM_PROFILE_AUTO:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
133 case PM_PROFILE_HIGH:
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
154 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
156 struct radeon_bo *bo, *n;
158 if (list_empty(&rdev->gem.objects))
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
163 ttm_bo_unmap_virtual(&bo->tbo);
167 static void radeon_sync_with_vblank(struct radeon_device *rdev)
169 if (rdev->pm.active_crtcs) {
170 rdev->pm.vblank_sync = false;
172 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
177 static void radeon_set_power_state(struct radeon_device *rdev)
180 bool misc_after = false;
182 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
183 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
186 if (radeon_gui_idle(rdev)) {
187 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188 clock_info[rdev->pm.requested_clock_mode_index].sclk;
189 if (sclk > rdev->pm.default_sclk)
190 sclk = rdev->pm.default_sclk;
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
201 radeon_sync_with_vblank(rdev);
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
208 radeon_pm_prepare(rdev);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
223 /* set memory clock */
224 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
236 radeon_pm_finish(rdev);
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex);
255 mutex_lock(&rdev->cp.mutex);
257 /* gui idle int has issues on older chips it seems */
258 if (rdev->family >= CHIP_R600) {
259 if (rdev->irq.installed) {
260 /* wait for GPU idle */
261 rdev->pm.gui_idle = false;
262 rdev->irq.gui_idle = true;
263 radeon_irq_set(rdev);
264 wait_event_interruptible_timeout(
265 rdev->irq.idle_queue, rdev->pm.gui_idle,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
267 rdev->irq.gui_idle = false;
268 radeon_irq_set(rdev);
271 if (rdev->cp.ready) {
272 struct radeon_fence *fence;
273 radeon_ring_alloc(rdev, 64);
274 radeon_fence_create(rdev, &fence);
275 radeon_fence_emit(rdev, fence);
276 radeon_ring_commit(rdev);
277 radeon_fence_wait(fence, false);
278 radeon_fence_unref(&fence);
281 radeon_unmap_vram_bos(rdev);
283 if (rdev->irq.installed) {
284 for (i = 0; i < rdev->num_crtc; i++) {
285 if (rdev->pm.active_crtcs & (1 << i)) {
286 rdev->pm.req_vblank |= (1 << i);
287 drm_vblank_get(rdev->ddev, i);
292 radeon_set_power_state(rdev);
294 if (rdev->irq.installed) {
295 for (i = 0; i < rdev->num_crtc; i++) {
296 if (rdev->pm.req_vblank & (1 << i)) {
297 rdev->pm.req_vblank &= ~(1 << i);
298 drm_vblank_put(rdev->ddev, i);
303 /* update display watermarks based on new power state */
304 radeon_update_bandwidth_info(rdev);
305 if (rdev->pm.active_crtc_count)
306 radeon_bandwidth_update(rdev);
308 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
310 mutex_unlock(&rdev->cp.mutex);
311 mutex_unlock(&rdev->vram_mutex);
312 mutex_unlock(&rdev->ddev->struct_mutex);
315 static void radeon_pm_print_states(struct radeon_device *rdev)
318 struct radeon_power_state *power_state;
319 struct radeon_pm_clock_info *clock_info;
321 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
322 for (i = 0; i < rdev->pm.num_power_states; i++) {
323 power_state = &rdev->pm.power_state[i];
324 DRM_DEBUG_DRIVER("State %d: %s\n", i,
325 radeon_pm_state_type_name[power_state->type]);
326 if (i == rdev->pm.default_power_state_index)
327 DRM_DEBUG_DRIVER("\tDefault");
328 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
329 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
330 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
331 DRM_DEBUG_DRIVER("\tSingle display only\n");
332 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
333 for (j = 0; j < power_state->num_clock_modes; j++) {
334 clock_info = &(power_state->clock_info[j]);
335 if (rdev->flags & RADEON_IS_IGP)
336 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
338 clock_info->sclk * 10,
339 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
341 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
343 clock_info->sclk * 10,
344 clock_info->mclk * 10,
345 clock_info->voltage.voltage,
346 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
351 static ssize_t radeon_get_pm_profile(struct device *dev,
352 struct device_attribute *attr,
355 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
356 struct radeon_device *rdev = ddev->dev_private;
357 int cp = rdev->pm.profile;
359 return snprintf(buf, PAGE_SIZE, "%s\n",
360 (cp == PM_PROFILE_AUTO) ? "auto" :
361 (cp == PM_PROFILE_LOW) ? "low" :
362 (cp == PM_PROFILE_MID) ? "mid" :
363 (cp == PM_PROFILE_HIGH) ? "high" : "default");
366 static ssize_t radeon_set_pm_profile(struct device *dev,
367 struct device_attribute *attr,
371 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
372 struct radeon_device *rdev = ddev->dev_private;
374 mutex_lock(&rdev->pm.mutex);
375 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
376 if (strncmp("default", buf, strlen("default")) == 0)
377 rdev->pm.profile = PM_PROFILE_DEFAULT;
378 else if (strncmp("auto", buf, strlen("auto")) == 0)
379 rdev->pm.profile = PM_PROFILE_AUTO;
380 else if (strncmp("low", buf, strlen("low")) == 0)
381 rdev->pm.profile = PM_PROFILE_LOW;
382 else if (strncmp("mid", buf, strlen("mid")) == 0)
383 rdev->pm.profile = PM_PROFILE_MID;
384 else if (strncmp("high", buf, strlen("high")) == 0)
385 rdev->pm.profile = PM_PROFILE_HIGH;
390 radeon_pm_update_profile(rdev);
391 radeon_pm_set_clocks(rdev);
396 mutex_unlock(&rdev->pm.mutex);
401 static ssize_t radeon_get_pm_method(struct device *dev,
402 struct device_attribute *attr,
405 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
406 struct radeon_device *rdev = ddev->dev_private;
407 int pm = rdev->pm.pm_method;
409 return snprintf(buf, PAGE_SIZE, "%s\n",
410 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
413 static ssize_t radeon_set_pm_method(struct device *dev,
414 struct device_attribute *attr,
418 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
419 struct radeon_device *rdev = ddev->dev_private;
422 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
423 mutex_lock(&rdev->pm.mutex);
424 rdev->pm.pm_method = PM_METHOD_DYNPM;
425 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
426 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
427 mutex_unlock(&rdev->pm.mutex);
428 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
429 mutex_lock(&rdev->pm.mutex);
431 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
432 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
433 rdev->pm.pm_method = PM_METHOD_PROFILE;
434 mutex_unlock(&rdev->pm.mutex);
435 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
440 radeon_pm_compute_clocks(rdev);
445 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
446 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
448 static ssize_t radeon_hwmon_show_temp(struct device *dev,
449 struct device_attribute *attr,
452 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
453 struct radeon_device *rdev = ddev->dev_private;
456 switch (rdev->pm.int_thermal_type) {
457 case THERMAL_TYPE_RV6XX:
458 temp = rv6xx_get_temp(rdev);
460 case THERMAL_TYPE_RV770:
461 temp = rv770_get_temp(rdev);
463 case THERMAL_TYPE_EVERGREEN:
464 case THERMAL_TYPE_NI:
465 temp = evergreen_get_temp(rdev);
467 case THERMAL_TYPE_SUMO:
468 temp = sumo_get_temp(rdev);
475 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
478 static ssize_t radeon_hwmon_show_name(struct device *dev,
479 struct device_attribute *attr,
482 return sprintf(buf, "radeon\n");
485 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
486 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
488 static struct attribute *hwmon_attributes[] = {
489 &sensor_dev_attr_temp1_input.dev_attr.attr,
490 &sensor_dev_attr_name.dev_attr.attr,
494 static const struct attribute_group hwmon_attrgroup = {
495 .attrs = hwmon_attributes,
498 static int radeon_hwmon_init(struct radeon_device *rdev)
502 rdev->pm.int_hwmon_dev = NULL;
504 switch (rdev->pm.int_thermal_type) {
505 case THERMAL_TYPE_RV6XX:
506 case THERMAL_TYPE_RV770:
507 case THERMAL_TYPE_EVERGREEN:
508 case THERMAL_TYPE_NI:
509 case THERMAL_TYPE_SUMO:
510 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
511 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
512 err = PTR_ERR(rdev->pm.int_hwmon_dev);
514 "Unable to register hwmon device: %d\n", err);
517 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
518 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
522 "Unable to create hwmon sysfs file: %d\n", err);
523 hwmon_device_unregister(rdev->dev);
533 static void radeon_hwmon_fini(struct radeon_device *rdev)
535 if (rdev->pm.int_hwmon_dev) {
536 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
537 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
541 void radeon_pm_suspend(struct radeon_device *rdev)
543 mutex_lock(&rdev->pm.mutex);
544 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
545 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
546 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
548 mutex_unlock(&rdev->pm.mutex);
550 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
553 void radeon_pm_resume(struct radeon_device *rdev)
555 /* set up the default clocks if the MC ucode is loaded */
556 if ((rdev->family >= CHIP_BARTS) &&
557 (rdev->family <= CHIP_CAYMAN) &&
559 if (rdev->pm.default_vddc)
560 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
561 SET_VOLTAGE_TYPE_ASIC_VDDC);
562 if (rdev->pm.default_vddci)
563 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
564 SET_VOLTAGE_TYPE_ASIC_VDDCI);
565 if (rdev->pm.default_sclk)
566 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
567 if (rdev->pm.default_mclk)
568 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
570 /* asic init will reset the default power state */
571 mutex_lock(&rdev->pm.mutex);
572 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
573 rdev->pm.current_clock_mode_index = 0;
574 rdev->pm.current_sclk = rdev->pm.default_sclk;
575 rdev->pm.current_mclk = rdev->pm.default_mclk;
576 if (rdev->pm.power_state) {
577 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
578 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
580 if (rdev->pm.pm_method == PM_METHOD_DYNPM
581 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
582 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
583 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
584 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
586 mutex_unlock(&rdev->pm.mutex);
587 radeon_pm_compute_clocks(rdev);
590 int radeon_pm_init(struct radeon_device *rdev)
594 /* default to profile method */
595 rdev->pm.pm_method = PM_METHOD_PROFILE;
596 rdev->pm.profile = PM_PROFILE_DEFAULT;
597 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
598 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
599 rdev->pm.dynpm_can_upclock = true;
600 rdev->pm.dynpm_can_downclock = true;
601 rdev->pm.default_sclk = rdev->clock.default_sclk;
602 rdev->pm.default_mclk = rdev->clock.default_mclk;
603 rdev->pm.current_sclk = rdev->clock.default_sclk;
604 rdev->pm.current_mclk = rdev->clock.default_mclk;
605 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
608 if (rdev->is_atom_bios)
609 radeon_atombios_get_power_modes(rdev);
611 radeon_combios_get_power_modes(rdev);
612 radeon_pm_print_states(rdev);
613 radeon_pm_init_profile(rdev);
614 /* set up the default clocks if the MC ucode is loaded */
615 if ((rdev->family >= CHIP_BARTS) &&
616 (rdev->family <= CHIP_CAYMAN) &&
618 if (rdev->pm.default_vddc)
619 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
620 SET_VOLTAGE_TYPE_ASIC_VDDC);
621 if (rdev->pm.default_vddci)
622 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
623 SET_VOLTAGE_TYPE_ASIC_VDDCI);
624 if (rdev->pm.default_sclk)
625 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
626 if (rdev->pm.default_mclk)
627 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
631 /* set up the internal thermal sensor if applicable */
632 ret = radeon_hwmon_init(rdev);
636 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
638 if (rdev->pm.num_power_states > 1) {
639 /* where's the best place to put these? */
640 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
642 DRM_ERROR("failed to create device file for power profile\n");
643 ret = device_create_file(rdev->dev, &dev_attr_power_method);
645 DRM_ERROR("failed to create device file for power method\n");
648 rdev->acpi_nb.notifier_call = radeon_acpi_event;
649 register_acpi_notifier(&rdev->acpi_nb);
651 if (radeon_debugfs_pm_init(rdev)) {
652 DRM_ERROR("Failed to register debugfs file for PM!\n");
655 DRM_INFO("radeon: power management initialized\n");
661 void radeon_pm_fini(struct radeon_device *rdev)
663 if (rdev->pm.num_power_states > 1) {
664 mutex_lock(&rdev->pm.mutex);
665 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
666 rdev->pm.profile = PM_PROFILE_DEFAULT;
667 radeon_pm_update_profile(rdev);
668 radeon_pm_set_clocks(rdev);
669 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
670 /* reset default clocks */
671 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
672 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
673 radeon_pm_set_clocks(rdev);
675 mutex_unlock(&rdev->pm.mutex);
677 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
679 device_remove_file(rdev->dev, &dev_attr_power_profile);
680 device_remove_file(rdev->dev, &dev_attr_power_method);
682 unregister_acpi_notifier(&rdev->acpi_nb);
686 if (rdev->pm.power_state)
687 kfree(rdev->pm.power_state);
689 radeon_hwmon_fini(rdev);
692 void radeon_pm_compute_clocks(struct radeon_device *rdev)
694 struct drm_device *ddev = rdev->ddev;
695 struct drm_crtc *crtc;
696 struct radeon_crtc *radeon_crtc;
698 if (rdev->pm.num_power_states < 2)
701 mutex_lock(&rdev->pm.mutex);
703 rdev->pm.active_crtcs = 0;
704 rdev->pm.active_crtc_count = 0;
705 list_for_each_entry(crtc,
706 &ddev->mode_config.crtc_list, head) {
707 radeon_crtc = to_radeon_crtc(crtc);
708 if (radeon_crtc->enabled) {
709 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
710 rdev->pm.active_crtc_count++;
714 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
715 radeon_pm_update_profile(rdev);
716 radeon_pm_set_clocks(rdev);
717 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
718 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
719 if (rdev->pm.active_crtc_count > 1) {
720 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
721 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
723 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
724 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
725 radeon_pm_get_dynpm_state(rdev);
726 radeon_pm_set_clocks(rdev);
728 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
730 } else if (rdev->pm.active_crtc_count == 1) {
731 /* TODO: Increase clocks if needed for current mode */
733 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
734 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
735 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
736 radeon_pm_get_dynpm_state(rdev);
737 radeon_pm_set_clocks(rdev);
739 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
740 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
741 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
742 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
743 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
744 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
745 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
747 } else { /* count == 0 */
748 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
749 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
751 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
752 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
753 radeon_pm_get_dynpm_state(rdev);
754 radeon_pm_set_clocks(rdev);
760 mutex_unlock(&rdev->pm.mutex);
763 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
765 int crtc, vpos, hpos, vbl_status;
768 /* Iterate over all active crtc's. All crtc's must be in vblank,
769 * otherwise return in_vbl == false.
771 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
772 if (rdev->pm.active_crtcs & (1 << crtc)) {
773 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
774 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
775 !(vbl_status & DRM_SCANOUTPOS_INVBL))
783 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
786 bool in_vbl = radeon_pm_in_vbl(rdev);
789 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
790 finish ? "exit" : "entry");
794 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
796 struct radeon_device *rdev;
798 rdev = container_of(work, struct radeon_device,
799 pm.dynpm_idle_work.work);
801 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
802 mutex_lock(&rdev->pm.mutex);
803 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
804 unsigned long irq_flags;
805 int not_processed = 0;
807 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
808 if (!list_empty(&rdev->fence_drv.emited)) {
809 struct list_head *ptr;
810 list_for_each(ptr, &rdev->fence_drv.emited) {
811 /* count up to 3, that's enought info */
812 if (++not_processed >= 3)
816 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
818 if (not_processed >= 3) { /* should upclock */
819 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
820 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
821 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
822 rdev->pm.dynpm_can_upclock) {
823 rdev->pm.dynpm_planned_action =
824 DYNPM_ACTION_UPCLOCK;
825 rdev->pm.dynpm_action_timeout = jiffies +
826 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
828 } else if (not_processed == 0) { /* should downclock */
829 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
830 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
831 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
832 rdev->pm.dynpm_can_downclock) {
833 rdev->pm.dynpm_planned_action =
834 DYNPM_ACTION_DOWNCLOCK;
835 rdev->pm.dynpm_action_timeout = jiffies +
836 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
840 /* Note, radeon_pm_set_clocks is called with static_switch set
841 * to false since we want to wait for vbl to avoid flicker.
843 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
844 jiffies > rdev->pm.dynpm_action_timeout) {
845 radeon_pm_get_dynpm_state(rdev);
846 radeon_pm_set_clocks(rdev);
849 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
850 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
852 mutex_unlock(&rdev->pm.mutex);
853 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
859 #if defined(CONFIG_DEBUG_FS)
861 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
863 struct drm_info_node *node = (struct drm_info_node *) m->private;
864 struct drm_device *dev = node->minor->dev;
865 struct radeon_device *rdev = dev->dev_private;
867 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
868 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
869 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
870 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
872 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
873 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
874 if (rdev->asic->get_memory_clock)
875 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
876 if (rdev->pm.current_vddc)
877 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
878 if (rdev->asic->get_pcie_lanes)
879 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
884 static struct drm_info_list radeon_pm_info_list[] = {
885 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
889 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
891 #if defined(CONFIG_DEBUG_FS)
892 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));