drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  71                 mutex_lock(&rdev->pm.mutex);
  72                 if (power_supply_is_system_supplied() > 0)
  73                         rdev->pm.dpm.ac_power = true;
  74                 else
  75                         rdev->pm.dpm.ac_power = false;
  76                 if (rdev->asic->dpm.enable_bapm)
  77                         radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
  78                 mutex_unlock(&rdev->pm.mutex);
  79         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  80                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  81                         mutex_lock(&rdev->pm.mutex);
  82                         radeon_pm_update_profile(rdev);
  83                         radeon_pm_set_clocks(rdev);
  84                         mutex_unlock(&rdev->pm.mutex);
  85                 }
  86         }
  87 }
  88
  89 static void radeon_pm_update_profile(struct radeon_device *rdev)
  90 {
  91         switch (rdev->pm.profile) {
  92         case PM_PROFILE_DEFAULT:
  93                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  94                 break;
  95         case PM_PROFILE_AUTO:
  96                 if (power_supply_is_system_supplied() > 0) {
  97                         if (rdev->pm.active_crtc_count > 1)
  98                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  99                         else
 100                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 101                 } else {
 102                         if (rdev->pm.active_crtc_count > 1)
 103                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 104                         else
 105                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 106                 }
 107                 break;
 108         case PM_PROFILE_LOW:
 109                 if (rdev->pm.active_crtc_count > 1)
 110                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 111                 else
 112                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 113                 break;
 114         case PM_PROFILE_MID:
 115                 if (rdev->pm.active_crtc_count > 1)
 116                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 117                 else
 118                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 119                 break;
 120         case PM_PROFILE_HIGH:
 121                 if (rdev->pm.active_crtc_count > 1)
 122                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 123                 else
 124                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 125                 break;
 126         }
 127
 128         if (rdev->pm.active_crtc_count == 0) {
 129                 rdev->pm.requested_power_state_index =
 130                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 131                 rdev->pm.requested_clock_mode_index =
 132                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 133         } else {
 134                 rdev->pm.requested_power_state_index =
 135                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 136                 rdev->pm.requested_clock_mode_index =
 137                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 138         }
 139 }
 140
 141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 142 {
 143         struct radeon_bo *bo, *n;
 144
 145         if (list_empty(&rdev->gem.objects))
 146                 return;
 147
 148         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 149                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 150                         ttm_bo_unmap_virtual(&bo->tbo);
 151         }
 152 }
 153
 154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 155 {
 156         if (rdev->pm.active_crtcs) {
 157                 rdev->pm.vblank_sync = false;
 158                 wait_event_timeout(
 159                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 160                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 161         }
 162 }
 163
 164 static void radeon_set_power_state(struct radeon_device *rdev)
 165 {
 166         u32 sclk, mclk;
 167         bool misc_after = false;
 168
 169         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 170             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 171                 return;
 172
 173         if (radeon_gui_idle(rdev)) {
 174                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 175                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 176                 if (sclk > rdev->pm.default_sclk)
 177                         sclk = rdev->pm.default_sclk;
 178
 179                 /* starting with BTC, there is one state that is used for both
 180                  * MH and SH.  Difference is that we always use the high clock index for
 181                  * mclk and vddci.
 182                  */
 183                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 184                     (rdev->family >= CHIP_BARTS) &&
 185                     rdev->pm.active_crtc_count &&
 186                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 187                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 188                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 189                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 190                 else
 191                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 192                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 193
 194                 if (mclk > rdev->pm.default_mclk)
 195                         mclk = rdev->pm.default_mclk;
 196
 197                 /* upvolt before raising clocks, downvolt after lowering clocks */
 198                 if (sclk < rdev->pm.current_sclk)
 199                         misc_after = true;
 200
 201                 radeon_sync_with_vblank(rdev);
 202
 203                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 204                         if (!radeon_pm_in_vbl(rdev))
 205                                 return;
 206                 }
 207
 208                 radeon_pm_prepare(rdev);
 209
 210                 if (!misc_after)
 211                         /* voltage, pcie lanes, etc.*/
 212                         radeon_pm_misc(rdev);
 213
 214                 /* set engine clock */
 215                 if (sclk != rdev->pm.current_sclk) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_engine_clock(rdev, sclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_sclk = sclk;
 220                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 221                 }
 222
 223                 /* set memory clock */
 224                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 225                         radeon_pm_debug_check_in_vbl(rdev, false);
 226                         radeon_set_memory_clock(rdev, mclk);
 227                         radeon_pm_debug_check_in_vbl(rdev, true);
 228                         rdev->pm.current_mclk = mclk;
 229                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 230                 }
 231
 232                 if (misc_after)
 233                         /* voltage, pcie lanes, etc.*/
 234                         radeon_pm_misc(rdev);
 235
 236                 radeon_pm_finish(rdev);
 237
 238                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 239                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 240         } else
 241                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 242 }
 243
 244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 245 {
 246         int i, r;
 247
 248         /* no need to take locks, etc. if nothing's going to change */
 249         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 250             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 251                 return;
 252
 253         mutex_lock(&rdev->ddev->struct_mutex);
 254         down_write(&rdev->pm.mclk_lock);
 255         mutex_lock(&rdev->ring_lock);
 256
 257         /* wait for the rings to drain */
 258         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 259                 struct radeon_ring *ring = &rdev->ring[i];
 260                 if (!ring->ready) {
 261                         continue;
 262                 }
 263                 r = radeon_fence_wait_empty(rdev, i);
 264                 if (r) {
 265                         /* needs a GPU reset dont reset here */
 266                         mutex_unlock(&rdev->ring_lock);
 267                         up_write(&rdev->pm.mclk_lock);
 268                         mutex_unlock(&rdev->ddev->struct_mutex);
 269                         return;
 270                 }
 271         }
 272
 273         radeon_unmap_vram_bos(rdev);
 274
 275         if (rdev->irq.installed) {
 276                 for (i = 0; i < rdev->num_crtc; i++) {
 277                         if (rdev->pm.active_crtcs & (1 << i)) {
 278                                 rdev->pm.req_vblank |= (1 << i);
 279                                 drm_vblank_get(rdev->ddev, i);
 280                         }
 281                 }
 282         }
 283
 284         radeon_set_power_state(rdev);
 285
 286         if (rdev->irq.installed) {
 287                 for (i = 0; i < rdev->num_crtc; i++) {
 288                         if (rdev->pm.req_vblank & (1 << i)) {
 289                                 rdev->pm.req_vblank &= ~(1 << i);
 290                                 drm_vblank_put(rdev->ddev, i);
 291                         }
 292                 }
 293         }
 294
 295         /* update display watermarks based on new power state */
 296         radeon_update_bandwidth_info(rdev);
 297         if (rdev->pm.active_crtc_count)
 298                 radeon_bandwidth_update(rdev);
 299
 300         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 301
 302         mutex_unlock(&rdev->ring_lock);
 303         up_write(&rdev->pm.mclk_lock);
 304         mutex_unlock(&rdev->ddev->struct_mutex);
 305 }
 306
 307 static void radeon_pm_print_states(struct radeon_device *rdev)
 308 {
 309         int i, j;
 310         struct radeon_power_state *power_state;
 311         struct radeon_pm_clock_info *clock_info;
 312
 313         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 314         for (i = 0; i < rdev->pm.num_power_states; i++) {
 315                 power_state = &rdev->pm.power_state[i];
 316                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 317                         radeon_pm_state_type_name[power_state->type]);
 318                 if (i == rdev->pm.default_power_state_index)
 319                         DRM_DEBUG_DRIVER("\tDefault");
 320                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 321                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 322                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 323                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 324                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 325                 for (j = 0; j < power_state->num_clock_modes; j++) {
 326                         clock_info = &(power_state->clock_info[j]);
 327                         if (rdev->flags & RADEON_IS_IGP)
 328                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 329                                                  j,
 330                                                  clock_info->sclk * 10);
 331                         else
 332                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 333                                                  j,
 334                                                  clock_info->sclk * 10,
 335                                                  clock_info->mclk * 10,
 336                                                  clock_info->voltage.voltage);
 337                 }
 338         }
 339 }
 340
 341 static ssize_t radeon_get_pm_profile(struct device *dev,
 342                                      struct device_attribute *attr,
 343                                      char *buf)
 344 {
 345         struct drm_device *ddev = dev_get_drvdata(dev);
 346         struct radeon_device *rdev = ddev->dev_private;
 347         int cp = rdev->pm.profile;
 348
 349         return snprintf(buf, PAGE_SIZE, "%s\n",
 350                         (cp == PM_PROFILE_AUTO) ? "auto" :
 351                         (cp == PM_PROFILE_LOW) ? "low" :
 352                         (cp == PM_PROFILE_MID) ? "mid" :
 353                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 354 }
 355
 356 static ssize_t radeon_set_pm_profile(struct device *dev,
 357                                      struct device_attribute *attr,
 358                                      const char *buf,
 359                                      size_t count)
 360 {
 361         struct drm_device *ddev = dev_get_drvdata(dev);
 362         struct radeon_device *rdev = ddev->dev_private;
 363
 364         /* Can't set profile when the card is off */
 365         if  ((rdev->flags & RADEON_IS_PX) &&
 366              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 367                 return -EINVAL;
 368
 369         mutex_lock(&rdev->pm.mutex);
 370         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 371                 if (strncmp("default", buf, strlen("default")) == 0)
 372                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 373                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 374                         rdev->pm.profile = PM_PROFILE_AUTO;
 375                 else if (strncmp("low", buf, strlen("low")) == 0)
 376                         rdev->pm.profile = PM_PROFILE_LOW;
 377                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 378                         rdev->pm.profile = PM_PROFILE_MID;
 379                 else if (strncmp("high", buf, strlen("high")) == 0)
 380                         rdev->pm.profile = PM_PROFILE_HIGH;
 381                 else {
 382                         count = -EINVAL;
 383                         goto fail;
 384                 }
 385                 radeon_pm_update_profile(rdev);
 386                 radeon_pm_set_clocks(rdev);
 387         } else
 388                 count = -EINVAL;
 389
 390 fail:
 391         mutex_unlock(&rdev->pm.mutex);
 392
 393         return count;
 394 }
 395
 396 static ssize_t radeon_get_pm_method(struct device *dev,
 397                                     struct device_attribute *attr,
 398                                     char *buf)
 399 {
 400         struct drm_device *ddev = dev_get_drvdata(dev);
 401         struct radeon_device *rdev = ddev->dev_private;
 402         int pm = rdev->pm.pm_method;
 403
 404         return snprintf(buf, PAGE_SIZE, "%s\n",
 405                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 406                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 407 }
 408
 409 static ssize_t radeon_set_pm_method(struct device *dev,
 410                                     struct device_attribute *attr,
 411                                     const char *buf,
 412                                     size_t count)
 413 {
 414         struct drm_device *ddev = dev_get_drvdata(dev);
 415         struct radeon_device *rdev = ddev->dev_private;
 416
 417         /* Can't set method when the card is off */
 418         if  ((rdev->flags & RADEON_IS_PX) &&
 419              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
 420                 count = -EINVAL;
 421                 goto fail;
 422         }
 423
 424         /* we don't support the legacy modes with dpm */
 425         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 426                 count = -EINVAL;
 427                 goto fail;
 428         }
 429
 430         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 431                 mutex_lock(&rdev->pm.mutex);
 432                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 433                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 434                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 435                 mutex_unlock(&rdev->pm.mutex);
 436         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 437                 mutex_lock(&rdev->pm.mutex);
 438                 /* disable dynpm */
 439                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 440                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 441                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 442                 mutex_unlock(&rdev->pm.mutex);
 443                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 444         } else {
 445                 count = -EINVAL;
 446                 goto fail;
 447         }
 448         radeon_pm_compute_clocks(rdev);
 449 fail:
 450         return count;
 451 }
 452
 453 static ssize_t radeon_get_dpm_state(struct device *dev,
 454                                     struct device_attribute *attr,
 455                                     char *buf)
 456 {
 457         struct drm_device *ddev = dev_get_drvdata(dev);
 458         struct radeon_device *rdev = ddev->dev_private;
 459         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 460
 461         if  ((rdev->flags & RADEON_IS_PX) &&
 462              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 463                 return snprintf(buf, PAGE_SIZE, "off\n");
 464
 465         return snprintf(buf, PAGE_SIZE, "%s\n",
 466                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 467                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 468 }
 469
 470 static ssize_t radeon_set_dpm_state(struct device *dev,
 471                                     struct device_attribute *attr,
 472                                     const char *buf,
 473                                     size_t count)
 474 {
 475         struct drm_device *ddev = dev_get_drvdata(dev);
 476         struct radeon_device *rdev = ddev->dev_private;
 477
 478         /* Can't set dpm state when the card is off */
 479         if  ((rdev->flags & RADEON_IS_PX) &&
 480              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 481                 return -EINVAL;
 482
 483         mutex_lock(&rdev->pm.mutex);
 484         if (strncmp("battery", buf, strlen("battery")) == 0)
 485                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 486         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 487                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 488         else if (strncmp("performance", buf, strlen("performance")) == 0)
 489                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 490         else {
 491                 mutex_unlock(&rdev->pm.mutex);
 492                 count = -EINVAL;
 493                 goto fail;
 494         }
 495         mutex_unlock(&rdev->pm.mutex);
 496         radeon_pm_compute_clocks(rdev);
 497 fail:
 498         return count;
 499 }
 500
 501 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 502                                                        struct device_attribute *attr,
 503                                                        char *buf)
 504 {
 505         struct drm_device *ddev = dev_get_drvdata(dev);
 506         struct radeon_device *rdev = ddev->dev_private;
 507         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 508
 509         if  ((rdev->flags & RADEON_IS_PX) &&
 510              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 511                 return snprintf(buf, PAGE_SIZE, "off\n");
 512
 513         return snprintf(buf, PAGE_SIZE, "%s\n",
 514                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 515                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 516 }
 517
 518 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 519                                                        struct device_attribute *attr,
 520                                                        const char *buf,
 521                                                        size_t count)
 522 {
 523         struct drm_device *ddev = dev_get_drvdata(dev);
 524         struct radeon_device *rdev = ddev->dev_private;
 525         enum radeon_dpm_forced_level level;
 526         int ret = 0;
 527
 528         /* Can't force performance level when the card is off */
 529         if  ((rdev->flags & RADEON_IS_PX) &&
 530              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 531                 return -EINVAL;
 532
 533         mutex_lock(&rdev->pm.mutex);
 534         if (strncmp("low", buf, strlen("low")) == 0) {
 535                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 536         } else if (strncmp("high", buf, strlen("high")) == 0) {
 537                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 538         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 539                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 540         } else {
 541                 count = -EINVAL;
 542                 goto fail;
 543         }
 544         if (rdev->asic->dpm.force_performance_level) {
 545                 if (rdev->pm.dpm.thermal_active) {
 546                         count = -EINVAL;
 547                         goto fail;
 548                 }
 549                 ret = radeon_dpm_force_performance_level(rdev, level);
 550                 if (ret)
 551                         count = -EINVAL;
 552         }
 553 fail:
 554         mutex_unlock(&rdev->pm.mutex);
 555
 556         return count;
 557 }
 558
 559 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 560 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 561 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 562 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 563                    radeon_get_dpm_forced_performance_level,
 564                    radeon_set_dpm_forced_performance_level);
 565
 566 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 567                                       struct device_attribute *attr,
 568                                       char *buf)
 569 {
 570         struct radeon_device *rdev = dev_get_drvdata(dev);
 571         struct drm_device *ddev = rdev->ddev;
 572         int temp;
 573
 574         /* Can't get temperature when the card is off */
 575         if  ((rdev->flags & RADEON_IS_PX) &&
 576              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 577                 return -EINVAL;
 578
 579         if (rdev->asic->pm.get_temperature)
 580                 temp = radeon_get_temperature(rdev);
 581         else
 582                 temp = 0;
 583
 584         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 585 }
 586
 587 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
 588                                              struct device_attribute *attr,
 589                                              char *buf)
 590 {
 591         struct radeon_device *rdev = dev_get_drvdata(dev);
 592         int hyst = to_sensor_dev_attr(attr)->index;
 593         int temp;
 594
 595         if (hyst)
 596                 temp = rdev->pm.dpm.thermal.min_temp;
 597         else
 598                 temp = rdev->pm.dpm.thermal.max_temp;
 599
 600         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 601 }
 602
 603 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 604 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
 605 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
 606
 607 static struct attribute *hwmon_attributes[] = {
 608         &sensor_dev_attr_temp1_input.dev_attr.attr,
 609         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 610         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 611         NULL
 612 };
 613
 614 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 615                                         struct attribute *attr, int index)
 616 {
 617         struct device *dev = container_of(kobj, struct device, kobj);
 618         struct radeon_device *rdev = dev_get_drvdata(dev);
 619
 620         /* Skip limit attributes if DPM is not enabled */
 621         if (rdev->pm.pm_method != PM_METHOD_DPM &&
 622             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 623              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
 624                 return 0;
 625
 626         return attr->mode;
 627 }
 628
 629 static const struct attribute_group hwmon_attrgroup = {
 630         .attrs = hwmon_attributes,
 631         .is_visible = hwmon_attributes_visible,
 632 };
 633
 634 static const struct attribute_group *hwmon_groups[] = {
 635         &hwmon_attrgroup,
 636         NULL
 637 };
 638
 639 static int radeon_hwmon_init(struct radeon_device *rdev)
 640 {
 641         int err = 0;
 642
 643         switch (rdev->pm.int_thermal_type) {
 644         case THERMAL_TYPE_RV6XX:
 645         case THERMAL_TYPE_RV770:
 646         case THERMAL_TYPE_EVERGREEN:
 647         case THERMAL_TYPE_NI:
 648         case THERMAL_TYPE_SUMO:
 649         case THERMAL_TYPE_SI:
 650         case THERMAL_TYPE_CI:
 651         case THERMAL_TYPE_KV:
 652                 if (rdev->asic->pm.get_temperature == NULL)
 653                         return err;
 654                 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
 655                                                                            "radeon", rdev,
 656                                                                            hwmon_groups);
 657                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 658                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 659                         dev_err(rdev->dev,
 660                                 "Unable to register hwmon device: %d\n", err);
 661                 }
 662                 break;
 663         default:
 664                 break;
 665         }
 666
 667         return err;
 668 }
 669
 670 static void radeon_hwmon_fini(struct radeon_device *rdev)
 671 {
 672         if (rdev->pm.int_hwmon_dev)
 673                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 674 }
 675
 676 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 677 {
 678         struct radeon_device *rdev =
 679                 container_of(work, struct radeon_device,
 680                              pm.dpm.thermal.work);
 681         /* switch to the thermal state */
 682         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 683
 684         if (!rdev->pm.dpm_enabled)
 685                 return;
 686
 687         if (rdev->asic->pm.get_temperature) {
 688                 int temp = radeon_get_temperature(rdev);
 689
 690                 if (temp < rdev->pm.dpm.thermal.min_temp)
 691                         /* switch back the user state */
 692                         dpm_state = rdev->pm.dpm.user_state;
 693         } else {
 694                 if (rdev->pm.dpm.thermal.high_to_low)
 695                         /* switch back the user state */
 696                         dpm_state = rdev->pm.dpm.user_state;
 697         }
 698         mutex_lock(&rdev->pm.mutex);
 699         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 700                 rdev->pm.dpm.thermal_active = true;
 701         else
 702                 rdev->pm.dpm.thermal_active = false;
 703         rdev->pm.dpm.state = dpm_state;
 704         mutex_unlock(&rdev->pm.mutex);
 705
 706         radeon_pm_compute_clocks(rdev);
 707 }
 708
 709 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 710                                                      enum radeon_pm_state_type dpm_state)
 711 {
 712         int i;
 713         struct radeon_ps *ps;
 714         u32 ui_class;
 715         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 716                 true : false;
 717
 718         /* check if the vblank period is too short to adjust the mclk */
 719         if (single_display && rdev->asic->dpm.vblank_too_short) {
 720                 if (radeon_dpm_vblank_too_short(rdev))
 721                         single_display = false;
 722         }
 723
 724         /* certain older asics have a separare 3D performance state,
 725          * so try that first if the user selected performance
 726          */
 727         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 728                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 729         /* balanced states don't exist at the moment */
 730         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 731                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 732
 733 restart_search:
 734         /* Pick the best power state based on current conditions */
 735         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 736                 ps = &rdev->pm.dpm.ps[i];
 737                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 738                 switch (dpm_state) {
 739                 /* user states */
 740                 case POWER_STATE_TYPE_BATTERY:
 741                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 742                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 743                                         if (single_display)
 744                                                 return ps;
 745                                 } else
 746                                         return ps;
 747                         }
 748                         break;
 749                 case POWER_STATE_TYPE_BALANCED:
 750                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 751                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 752                                         if (single_display)
 753                                                 return ps;
 754                                 } else
 755                                         return ps;
 756                         }
 757                         break;
 758                 case POWER_STATE_TYPE_PERFORMANCE:
 759                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 760                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 761                                         if (single_display)
 762                                                 return ps;
 763                                 } else
 764                                         return ps;
 765                         }
 766                         break;
 767                 /* internal states */
 768                 case POWER_STATE_TYPE_INTERNAL_UVD:
 769                         if (rdev->pm.dpm.uvd_ps)
 770                                 return rdev->pm.dpm.uvd_ps;
 771                         else
 772                                 break;
 773                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 774                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 775                                 return ps;
 776                         break;
 777                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 778                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 779                                 return ps;
 780                         break;
 781                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 782                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 783                                 return ps;
 784                         break;
 785                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 786                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 787                                 return ps;
 788                         break;
 789                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 790                         return rdev->pm.dpm.boot_ps;
 791                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 792                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 793                                 return ps;
 794                         break;
 795                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 796                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 797                                 return ps;
 798                         break;
 799                 case POWER_STATE_TYPE_INTERNAL_ULV:
 800                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 801                                 return ps;
 802                         break;
 803                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 804                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 805                                 return ps;
 806                         break;
 807                 default:
 808                         break;
 809                 }
 810         }
 811         /* use a fallback state if we didn't match */
 812         switch (dpm_state) {
 813         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 814                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 815                 goto restart_search;
 816         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 817         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 818         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 819                 if (rdev->pm.dpm.uvd_ps) {
 820                         return rdev->pm.dpm.uvd_ps;
 821                 } else {
 822                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 823                         goto restart_search;
 824                 }
 825         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 826                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 827                 goto restart_search;
 828         case POWER_STATE_TYPE_INTERNAL_ACPI:
 829                 dpm_state = POWER_STATE_TYPE_BATTERY;
 830                 goto restart_search;
 831         case POWER_STATE_TYPE_BATTERY:
 832         case POWER_STATE_TYPE_BALANCED:
 833         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 834                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 835                 goto restart_search;
 836         default:
 837                 break;
 838         }
 839
 840         return NULL;
 841 }
 842
 843 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 844 {
 845         int i;
 846         struct radeon_ps *ps;
 847         enum radeon_pm_state_type dpm_state;
 848         int ret;
 849
 850         /* if dpm init failed */
 851         if (!rdev->pm.dpm_enabled)
 852                 return;
 853
 854         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 855                 /* add other state override checks here */
 856                 if ((!rdev->pm.dpm.thermal_active) &&
 857                     (!rdev->pm.dpm.uvd_active))
 858                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 859         }
 860         dpm_state = rdev->pm.dpm.state;
 861
 862         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 863         if (ps)
 864                 rdev->pm.dpm.requested_ps = ps;
 865         else
 866                 return;
 867
 868         /* no need to reprogram if nothing changed unless we are on BTC+ */
 869         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 870                 /* vce just modifies an existing state so force a change */
 871                 if (ps->vce_active != rdev->pm.dpm.vce_active)
 872                         goto force;
 873                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 874                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 875                          * all we need to do is update the display configuration.
 876                          */
 877                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 878                                 /* update display watermarks based on new power state */
 879                                 radeon_bandwidth_update(rdev);
 880                                 /* update displays */
 881                                 radeon_dpm_display_configuration_changed(rdev);
 882                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 883                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 884                         }
 885                         return;
 886                 } else {
 887                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 888                          * nothing to do, if the num crtcs is > 1 and state is the same,
 889                          * update display configuration.
 890                          */
 891                         if (rdev->pm.dpm.new_active_crtcs ==
 892                             rdev->pm.dpm.current_active_crtcs) {
 893                                 return;
 894                         } else {
 895                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 896                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 897                                         /* update display watermarks based on new power state */
 898                                         radeon_bandwidth_update(rdev);
 899                                         /* update displays */
 900                                         radeon_dpm_display_configuration_changed(rdev);
 901                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 902                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 903                                         return;
 904                                 }
 905                         }
 906                 }
 907         }
 908
 909 force:
 910         if (radeon_dpm == 1) {
 911                 printk("switching from power state:\n");
 912                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 913                 printk("switching to power state:\n");
 914                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 915         }
 916
 917         mutex_lock(&rdev->ddev->struct_mutex);
 918         down_write(&rdev->pm.mclk_lock);
 919         mutex_lock(&rdev->ring_lock);
 920
 921         /* update whether vce is active */
 922         ps->vce_active = rdev->pm.dpm.vce_active;
 923
 924         ret = radeon_dpm_pre_set_power_state(rdev);
 925         if (ret)
 926                 goto done;
 927
 928         /* update display watermarks based on new power state */
 929         radeon_bandwidth_update(rdev);
 930         /* update displays */
 931         radeon_dpm_display_configuration_changed(rdev);
 932
 933         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 934         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 935
 936         /* wait for the rings to drain */
 937         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 938                 struct radeon_ring *ring = &rdev->ring[i];
 939                 if (ring->ready)
 940                         radeon_fence_wait_empty(rdev, i);
 941         }
 942
 943         /* program the new power state */
 944         radeon_dpm_set_power_state(rdev);
 945
 946         /* update current power state */
 947         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 948
 949         radeon_dpm_post_set_power_state(rdev);
 950
 951         if (rdev->asic->dpm.force_performance_level) {
 952                 if (rdev->pm.dpm.thermal_active) {
 953                         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 954                         /* force low perf level for thermal */
 955                         radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
 956                         /* save the user's level */
 957                         rdev->pm.dpm.forced_level = level;
 958                 } else {
 959                         /* otherwise, user selected level */
 960                         radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
 961                 }
 962         }
 963
 964 done:
 965         mutex_unlock(&rdev->ring_lock);
 966         up_write(&rdev->pm.mclk_lock);
 967         mutex_unlock(&rdev->ddev->struct_mutex);
 968 }
 969
 970 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
 971 {
 972         enum radeon_pm_state_type dpm_state;
 973
 974         if (rdev->asic->dpm.powergate_uvd) {
 975                 mutex_lock(&rdev->pm.mutex);
 976                 /* don't powergate anything if we
 977                    have active but pause streams */
 978                 enable |= rdev->pm.dpm.sd > 0;
 979                 enable |= rdev->pm.dpm.hd > 0;
 980                 /* enable/disable UVD */
 981                 radeon_dpm_powergate_uvd(rdev, !enable);
 982                 mutex_unlock(&rdev->pm.mutex);
 983         } else {
 984                 if (enable) {
 985                         mutex_lock(&rdev->pm.mutex);
 986                         rdev->pm.dpm.uvd_active = true;
 987                         if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
 988                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
 989                         else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
 990                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 991                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
 992                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 993                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
 994                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
 995                         else
 996                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
 997                         rdev->pm.dpm.state = dpm_state;
 998                         mutex_unlock(&rdev->pm.mutex);
 999                 } else {
1000                         mutex_lock(&rdev->pm.mutex);
1001                         rdev->pm.dpm.uvd_active = false;
1002                         mutex_unlock(&rdev->pm.mutex);
1003                 }
1004
1005                 radeon_pm_compute_clocks(rdev);
1006         }
1007 }
1008
1009 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1010 {
1011         if (enable) {
1012                 mutex_lock(&rdev->pm.mutex);
1013                 rdev->pm.dpm.vce_active = true;
1014                 /* XXX select vce level based on ring/task */
1015                 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1016                 mutex_unlock(&rdev->pm.mutex);
1017         } else {
1018                 mutex_lock(&rdev->pm.mutex);
1019                 rdev->pm.dpm.vce_active = false;
1020                 mutex_unlock(&rdev->pm.mutex);
1021         }
1022
1023         radeon_pm_compute_clocks(rdev);
1024 }
1025
1026 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1027 {
1028         mutex_lock(&rdev->pm.mutex);
1029         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1030                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1031                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1032         }
1033         mutex_unlock(&rdev->pm.mutex);
1034
1035         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1036 }
1037
1038 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1039 {
1040         mutex_lock(&rdev->pm.mutex);
1041         /* disable dpm */
1042         radeon_dpm_disable(rdev);
1043         /* reset the power state */
1044         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1045         rdev->pm.dpm_enabled = false;
1046         mutex_unlock(&rdev->pm.mutex);
1047 }
1048
1049 void radeon_pm_suspend(struct radeon_device *rdev)
1050 {
1051         if (rdev->pm.pm_method == PM_METHOD_DPM)
1052                 radeon_pm_suspend_dpm(rdev);
1053         else
1054                 radeon_pm_suspend_old(rdev);
1055 }
1056
1057 static void radeon_pm_resume_old(struct radeon_device *rdev)
1058 {
1059         /* set up the default clocks if the MC ucode is loaded */
1060         if ((rdev->family >= CHIP_BARTS) &&
1061             (rdev->family <= CHIP_CAYMAN) &&
1062             rdev->mc_fw) {
1063                 if (rdev->pm.default_vddc)
1064                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1065                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1066                 if (rdev->pm.default_vddci)
1067                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1068                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1069                 if (rdev->pm.default_sclk)
1070                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1071                 if (rdev->pm.default_mclk)
1072                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1073         }
1074         /* asic init will reset the default power state */
1075         mutex_lock(&rdev->pm.mutex);
1076         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1077         rdev->pm.current_clock_mode_index = 0;
1078         rdev->pm.current_sclk = rdev->pm.default_sclk;
1079         rdev->pm.current_mclk = rdev->pm.default_mclk;
1080         if (rdev->pm.power_state) {
1081                 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1082                 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1083         }
1084         if (rdev->pm.pm_method == PM_METHOD_DYNPM
1085             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1086                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1087                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1088                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1089         }
1090         mutex_unlock(&rdev->pm.mutex);
1091         radeon_pm_compute_clocks(rdev);
1092 }
1093
1094 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1095 {
1096         int ret;
1097
1098         /* asic init will reset to the boot state */
1099         mutex_lock(&rdev->pm.mutex);
1100         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1101         radeon_dpm_setup_asic(rdev);
1102         ret = radeon_dpm_enable(rdev);
1103         mutex_unlock(&rdev->pm.mutex);
1104         if (ret)
1105                 goto dpm_resume_fail;
1106         rdev->pm.dpm_enabled = true;
1107         radeon_pm_compute_clocks(rdev);
1108         return;
1109
1110 dpm_resume_fail:
1111         DRM_ERROR("radeon: dpm resume failed\n");
1112         if ((rdev->family >= CHIP_BARTS) &&
1113             (rdev->family <= CHIP_CAYMAN) &&
1114             rdev->mc_fw) {
1115                 if (rdev->pm.default_vddc)
1116                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1117                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1118                 if (rdev->pm.default_vddci)
1119                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1120                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1121                 if (rdev->pm.default_sclk)
1122                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1123                 if (rdev->pm.default_mclk)
1124                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1125         }
1126 }
1127
1128 void radeon_pm_resume(struct radeon_device *rdev)
1129 {
1130         if (rdev->pm.pm_method == PM_METHOD_DPM)
1131                 radeon_pm_resume_dpm(rdev);
1132         else
1133                 radeon_pm_resume_old(rdev);
1134 }
1135
1136 static int radeon_pm_init_old(struct radeon_device *rdev)
1137 {
1138         int ret;
1139
1140         rdev->pm.profile = PM_PROFILE_DEFAULT;
1141         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1142         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1143         rdev->pm.dynpm_can_upclock = true;
1144         rdev->pm.dynpm_can_downclock = true;
1145         rdev->pm.default_sclk = rdev->clock.default_sclk;
1146         rdev->pm.default_mclk = rdev->clock.default_mclk;
1147         rdev->pm.current_sclk = rdev->clock.default_sclk;
1148         rdev->pm.current_mclk = rdev->clock.default_mclk;
1149         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1150
1151         if (rdev->bios) {
1152                 if (rdev->is_atom_bios)
1153                         radeon_atombios_get_power_modes(rdev);
1154                 else
1155                         radeon_combios_get_power_modes(rdev);
1156                 radeon_pm_print_states(rdev);
1157                 radeon_pm_init_profile(rdev);
1158                 /* set up the default clocks if the MC ucode is loaded */
1159                 if ((rdev->family >= CHIP_BARTS) &&
1160                     (rdev->family <= CHIP_CAYMAN) &&
1161                     rdev->mc_fw) {
1162                         if (rdev->pm.default_vddc)
1163                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1164                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1165                         if (rdev->pm.default_vddci)
1166                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1167                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1168                         if (rdev->pm.default_sclk)
1169                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1170                         if (rdev->pm.default_mclk)
1171                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1172                 }
1173         }
1174
1175         /* set up the internal thermal sensor if applicable */
1176         ret = radeon_hwmon_init(rdev);
1177         if (ret)
1178                 return ret;
1179
1180         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1181
1182         if (rdev->pm.num_power_states > 1) {
1183                 /* where's the best place to put these? */
1184                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1185                 if (ret)
1186                         DRM_ERROR("failed to create device file for power profile\n");
1187                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1188                 if (ret)
1189                         DRM_ERROR("failed to create device file for power method\n");
1190
1191                 if (radeon_debugfs_pm_init(rdev)) {
1192                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1193                 }
1194
1195                 DRM_INFO("radeon: power management initialized\n");
1196         }
1197
1198         return 0;
1199 }
1200
1201 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1202 {
1203         int i;
1204
1205         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1206                 printk("== power state %d ==\n", i);
1207                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1208         }
1209 }
1210
1211 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1212 {
1213         int ret;
1214
1215         /* default to balanced state */
1216         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1217         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1218         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1219         rdev->pm.default_sclk = rdev->clock.default_sclk;
1220         rdev->pm.default_mclk = rdev->clock.default_mclk;
1221         rdev->pm.current_sclk = rdev->clock.default_sclk;
1222         rdev->pm.current_mclk = rdev->clock.default_mclk;
1223         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1224
1225         if (rdev->bios && rdev->is_atom_bios)
1226                 radeon_atombios_get_power_modes(rdev);
1227         else
1228                 return -EINVAL;
1229
1230         /* set up the internal thermal sensor if applicable */
1231         ret = radeon_hwmon_init(rdev);
1232         if (ret)
1233                 return ret;
1234
1235         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1236         mutex_lock(&rdev->pm.mutex);
1237         radeon_dpm_init(rdev);
1238         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1239         if (radeon_dpm == 1)
1240                 radeon_dpm_print_power_states(rdev);
1241         radeon_dpm_setup_asic(rdev);
1242         ret = radeon_dpm_enable(rdev);
1243         mutex_unlock(&rdev->pm.mutex);
1244         if (ret)
1245                 goto dpm_failed;
1246         rdev->pm.dpm_enabled = true;
1247
1248         ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1249         if (ret)
1250                 DRM_ERROR("failed to create device file for dpm state\n");
1251         ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1252         if (ret)
1253                 DRM_ERROR("failed to create device file for dpm state\n");
1254         /* XXX: these are noops for dpm but are here for backwards compat */
1255         ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1256         if (ret)
1257                 DRM_ERROR("failed to create device file for power profile\n");
1258         ret = device_create_file(rdev->dev, &dev_attr_power_method);
1259         if (ret)
1260                 DRM_ERROR("failed to create device file for power method\n");
1261
1262         if (radeon_debugfs_pm_init(rdev)) {
1263                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1264         }
1265
1266         DRM_INFO("radeon: dpm initialized\n");
1267
1268         return 0;
1269
1270 dpm_failed:
1271         rdev->pm.dpm_enabled = false;
1272         if ((rdev->family >= CHIP_BARTS) &&
1273             (rdev->family <= CHIP_CAYMAN) &&
1274             rdev->mc_fw) {
1275                 if (rdev->pm.default_vddc)
1276                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1277                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1278                 if (rdev->pm.default_vddci)
1279                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1280                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1281                 if (rdev->pm.default_sclk)
1282                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1283                 if (rdev->pm.default_mclk)
1284                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1285         }
1286         DRM_ERROR("radeon: dpm initialization failed\n");
1287         return ret;
1288 }
1289
1290 int radeon_pm_init(struct radeon_device *rdev)
1291 {
1292         /* enable dpm on rv6xx+ */
1293         switch (rdev->family) {
1294         case CHIP_RV610:
1295         case CHIP_RV630:
1296         case CHIP_RV620:
1297         case CHIP_RV635:
1298         case CHIP_RV670:
1299         case CHIP_RS780:
1300         case CHIP_RS880:
1301         case CHIP_RV770:
1302         case CHIP_BARTS:
1303         case CHIP_TURKS:
1304         case CHIP_CAICOS:
1305         case CHIP_CAYMAN:
1306                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1307                 if (!rdev->rlc_fw)
1308                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1309                 else if ((rdev->family >= CHIP_RV770) &&
1310                          (!(rdev->flags & RADEON_IS_IGP)) &&
1311                          (!rdev->smc_fw))
1312                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1313                 else if (radeon_dpm == 1)
1314                         rdev->pm.pm_method = PM_METHOD_DPM;
1315                 else
1316                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1317                 break;
1318         case CHIP_RV730:
1319         case CHIP_RV710:
1320         case CHIP_RV740:
1321         case CHIP_CEDAR:
1322         case CHIP_REDWOOD:
1323         case CHIP_JUNIPER:
1324         case CHIP_CYPRESS:
1325         case CHIP_HEMLOCK:
1326         case CHIP_PALM:
1327         case CHIP_SUMO:
1328         case CHIP_SUMO2:
1329         case CHIP_ARUBA:
1330         case CHIP_TAHITI:
1331         case CHIP_PITCAIRN:
1332         case CHIP_VERDE:
1333         case CHIP_OLAND:
1334         case CHIP_HAINAN:
1335         case CHIP_BONAIRE:
1336         case CHIP_KABINI:
1337         case CHIP_KAVERI:
1338         case CHIP_HAWAII:
1339         case CHIP_MULLINS:
1340                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1341                 if (!rdev->rlc_fw)
1342                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1343                 else if ((rdev->family >= CHIP_RV770) &&
1344                          (!(rdev->flags & RADEON_IS_IGP)) &&
1345                          (!rdev->smc_fw))
1346                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1347                 else if (radeon_dpm == 0)
1348                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1349                 else
1350                         rdev->pm.pm_method = PM_METHOD_DPM;
1351                 break;
1352         default:
1353                 /* default to profile method */
1354                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1355                 break;
1356         }
1357
1358         if (rdev->pm.pm_method == PM_METHOD_DPM)
1359                 return radeon_pm_init_dpm(rdev);
1360         else
1361                 return radeon_pm_init_old(rdev);
1362 }
1363
1364 int radeon_pm_late_init(struct radeon_device *rdev)
1365 {
1366         int ret = 0;
1367
1368         if (rdev->pm.pm_method == PM_METHOD_DPM) {
1369                 mutex_lock(&rdev->pm.mutex);
1370                 ret = radeon_dpm_late_enable(rdev);
1371                 mutex_unlock(&rdev->pm.mutex);
1372         }
1373         return ret;
1374 }
1375
1376 static void radeon_pm_fini_old(struct radeon_device *rdev)
1377 {
1378         if (rdev->pm.num_power_states > 1) {
1379                 mutex_lock(&rdev->pm.mutex);
1380                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1381                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1382                         radeon_pm_update_profile(rdev);
1383                         radeon_pm_set_clocks(rdev);
1384                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1385                         /* reset default clocks */
1386                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1387                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1388                         radeon_pm_set_clocks(rdev);
1389                 }
1390                 mutex_unlock(&rdev->pm.mutex);
1391
1392                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1393
1394                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1395                 device_remove_file(rdev->dev, &dev_attr_power_method);
1396         }
1397
1398         radeon_hwmon_fini(rdev);
1399
1400         if (rdev->pm.power_state)
1401                 kfree(rdev->pm.power_state);
1402 }
1403
1404 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1405 {
1406         if (rdev->pm.num_power_states > 1) {
1407                 mutex_lock(&rdev->pm.mutex);
1408                 radeon_dpm_disable(rdev);
1409                 mutex_unlock(&rdev->pm.mutex);
1410
1411                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1412                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1413                 /* XXX backwards compat */
1414                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1415                 device_remove_file(rdev->dev, &dev_attr_power_method);
1416         }
1417         radeon_dpm_fini(rdev);
1418
1419         radeon_hwmon_fini(rdev);
1420
1421         if (rdev->pm.power_state)
1422                 kfree(rdev->pm.power_state);
1423 }
1424
1425 void radeon_pm_fini(struct radeon_device *rdev)
1426 {
1427         if (rdev->pm.pm_method == PM_METHOD_DPM)
1428                 radeon_pm_fini_dpm(rdev);
1429         else
1430                 radeon_pm_fini_old(rdev);
1431 }
1432
1433 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1434 {
1435         struct drm_device *ddev = rdev->ddev;
1436         struct drm_crtc *crtc;
1437         struct radeon_crtc *radeon_crtc;
1438
1439         if (rdev->pm.num_power_states < 2)
1440                 return;
1441
1442         mutex_lock(&rdev->pm.mutex);
1443
1444         rdev->pm.active_crtcs = 0;
1445         rdev->pm.active_crtc_count = 0;
1446         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1447                 list_for_each_entry(crtc,
1448                                     &ddev->mode_config.crtc_list, head) {
1449                         radeon_crtc = to_radeon_crtc(crtc);
1450                         if (radeon_crtc->enabled) {
1451                                 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1452                                 rdev->pm.active_crtc_count++;
1453                         }
1454                 }
1455         }
1456
1457         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1458                 radeon_pm_update_profile(rdev);
1459                 radeon_pm_set_clocks(rdev);
1460         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1461                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1462                         if (rdev->pm.active_crtc_count > 1) {
1463                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1464                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1465
1466                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1467                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1468                                         radeon_pm_get_dynpm_state(rdev);
1469                                         radeon_pm_set_clocks(rdev);
1470
1471                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1472                                 }
1473                         } else if (rdev->pm.active_crtc_count == 1) {
1474                                 /* TODO: Increase clocks if needed for current mode */
1475
1476                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1477                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1478                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1479                                         radeon_pm_get_dynpm_state(rdev);
1480                                         radeon_pm_set_clocks(rdev);
1481
1482                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1483                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1484                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1485                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1486                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1487                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1488                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1489                                 }
1490                         } else { /* count == 0 */
1491                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1492                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1493
1494                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1495                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1496                                         radeon_pm_get_dynpm_state(rdev);
1497                                         radeon_pm_set_clocks(rdev);
1498                                 }
1499                         }
1500                 }
1501         }
1502
1503         mutex_unlock(&rdev->pm.mutex);
1504 }
1505
1506 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1507 {
1508         struct drm_device *ddev = rdev->ddev;
1509         struct drm_crtc *crtc;
1510         struct radeon_crtc *radeon_crtc;
1511
1512         if (!rdev->pm.dpm_enabled)
1513                 return;
1514
1515         mutex_lock(&rdev->pm.mutex);
1516
1517         /* update active crtc counts */
1518         rdev->pm.dpm.new_active_crtcs = 0;
1519         rdev->pm.dpm.new_active_crtc_count = 0;
1520         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1521                 list_for_each_entry(crtc,
1522                                     &ddev->mode_config.crtc_list, head) {
1523                         radeon_crtc = to_radeon_crtc(crtc);
1524                         if (crtc->enabled) {
1525                                 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1526                                 rdev->pm.dpm.new_active_crtc_count++;
1527                         }
1528                 }
1529         }
1530
1531         /* update battery/ac status */
1532         if (power_supply_is_system_supplied() > 0)
1533                 rdev->pm.dpm.ac_power = true;
1534         else
1535                 rdev->pm.dpm.ac_power = false;
1536
1537         radeon_dpm_change_power_state_locked(rdev);
1538
1539         mutex_unlock(&rdev->pm.mutex);
1540
1541 }
1542
1543 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1544 {
1545         if (rdev->pm.pm_method == PM_METHOD_DPM)
1546                 radeon_pm_compute_clocks_dpm(rdev);
1547         else
1548                 radeon_pm_compute_clocks_old(rdev);
1549 }
1550
1551 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1552 {
1553         int  crtc, vpos, hpos, vbl_status;
1554         bool in_vbl = true;
1555
1556         /* Iterate over all active crtc's. All crtc's must be in vblank,
1557          * otherwise return in_vbl == false.
1558          */
1559         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1560                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1561                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1562                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1563                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1564                                 in_vbl = false;
1565                 }
1566         }
1567
1568         return in_vbl;
1569 }
1570
1571 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1572 {
1573         u32 stat_crtc = 0;
1574         bool in_vbl = radeon_pm_in_vbl(rdev);
1575
1576         if (in_vbl == false)
1577                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1578                          finish ? "exit" : "entry");
1579         return in_vbl;
1580 }
1581
1582 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1583 {
1584         struct radeon_device *rdev;
1585         int resched;
1586         rdev = container_of(work, struct radeon_device,
1587                                 pm.dynpm_idle_work.work);
1588
1589         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1590         mutex_lock(&rdev->pm.mutex);
1591         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1592                 int not_processed = 0;
1593                 int i;
1594
1595                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1596                         struct radeon_ring *ring = &rdev->ring[i];
1597
1598                         if (ring->ready) {
1599                                 not_processed += radeon_fence_count_emitted(rdev, i);
1600                                 if (not_processed >= 3)
1601                                         break;
1602                         }
1603                 }
1604
1605                 if (not_processed >= 3) { /* should upclock */
1606                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1607                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1608                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1609                                    rdev->pm.dynpm_can_upclock) {
1610                                 rdev->pm.dynpm_planned_action =
1611                                         DYNPM_ACTION_UPCLOCK;
1612                                 rdev->pm.dynpm_action_timeout = jiffies +
1613                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1614                         }
1615                 } else if (not_processed == 0) { /* should downclock */
1616                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1617                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1618                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1619                                    rdev->pm.dynpm_can_downclock) {
1620                                 rdev->pm.dynpm_planned_action =
1621                                         DYNPM_ACTION_DOWNCLOCK;
1622                                 rdev->pm.dynpm_action_timeout = jiffies +
1623                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1624                         }
1625                 }
1626
1627                 /* Note, radeon_pm_set_clocks is called with static_switch set
1628                  * to false since we want to wait for vbl to avoid flicker.
1629                  */
1630                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1631                     jiffies > rdev->pm.dynpm_action_timeout) {
1632                         radeon_pm_get_dynpm_state(rdev);
1633                         radeon_pm_set_clocks(rdev);
1634                 }
1635
1636                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1637                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1638         }
1639         mutex_unlock(&rdev->pm.mutex);
1640         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1641 }
1642
1643 /*
1644  * Debugfs info
1645  */
1646 #if defined(CONFIG_DEBUG_FS)
1647
1648 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1649 {
1650         struct drm_info_node *node = (struct drm_info_node *) m->private;
1651         struct drm_device *dev = node->minor->dev;
1652         struct radeon_device *rdev = dev->dev_private;
1653         struct drm_device *ddev = rdev->ddev;
1654
1655         if  ((rdev->flags & RADEON_IS_PX) &&
1656              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1657                 seq_printf(m, "PX asic powered off\n");
1658         } else if (rdev->pm.dpm_enabled) {
1659                 mutex_lock(&rdev->pm.mutex);
1660                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1661                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1662                 else
1663                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1664                 mutex_unlock(&rdev->pm.mutex);
1665         } else {
1666                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1667                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1668                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1669                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1670                 else
1671                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1672                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1673                 if (rdev->asic->pm.get_memory_clock)
1674                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1675                 if (rdev->pm.current_vddc)
1676                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1677                 if (rdev->asic->pm.get_pcie_lanes)
1678                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1679         }
1680
1681         return 0;
1682 }
1683
1684 static struct drm_info_list radeon_pm_info_list[] = {
1685         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1686 };
1687 #endif
1688
1689 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1690 {
1691 #if defined(CONFIG_DEBUG_FS)
1692         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1693 #else
1694         return 0;
1695 #endif
1696 }