drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 #define DI_PT_RECTLIST        0x11
  37 #define DI_INDEX_SIZE_16_BIT  0x0
  38 #define DI_SRC_SEL_AUTO_INDEX 0x2
  39
  40 #define FMT_8                 0x1
  41 #define FMT_5_6_5             0x8
  42 #define FMT_8_8_8_8           0x1a
  43 #define COLOR_8               0x1
  44 #define COLOR_5_6_5           0x8
  45 #define COLOR_8_8_8_8         0x1a
  46
  47 /* emits 17 */
  48 static void
  49 set_render_target(struct radeon_device *rdev, int format,
  50                   int w, int h, u64 gpu_addr)
  51 {
  52         u32 cb_color_info;
  53         int pitch, slice;
  54
  55         h = ALIGN(h, 8);
  56         if (h < 8)
  57                 h = 8;
  58
  59         cb_color_info = CB_FORMAT(format) |
  60                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  61                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  62         pitch = (w / 8) - 1;
  63         slice = ((w * h) / 64) - 1;
  64
  65         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  66         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  67         radeon_ring_write(rdev, gpu_addr >> 8);
  68         radeon_ring_write(rdev, pitch);
  69         radeon_ring_write(rdev, slice);
  70         radeon_ring_write(rdev, 0);
  71         radeon_ring_write(rdev, cb_color_info);
  72         radeon_ring_write(rdev, 0);
  73         radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
  74         radeon_ring_write(rdev, 0);
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, 0);
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, 0);
  79         radeon_ring_write(rdev, 0);
  80         radeon_ring_write(rdev, 0);
  81         radeon_ring_write(rdev, 0);
  82 }
  83
  84 /* emits 5dw */
  85 static void
  86 cp_set_surface_sync(struct radeon_device *rdev,
  87                     u32 sync_type, u32 size,
  88                     u64 mc_addr)
  89 {
  90         u32 cp_coher_size;
  91
  92         if (size == 0xffffffff)
  93                 cp_coher_size = 0xffffffff;
  94         else
  95                 cp_coher_size = ((size + 255) >> 8);
  96
  97         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
  98         radeon_ring_write(rdev, sync_type);
  99         radeon_ring_write(rdev, cp_coher_size);
 100         radeon_ring_write(rdev, mc_addr >> 8);
 101         radeon_ring_write(rdev, 10); /* poll interval */
 102 }
 103
 104 /* emits 11dw + 1 surface sync = 16dw */
 105 static void
 106 set_shaders(struct radeon_device *rdev)
 107 {
 108         u64 gpu_addr;
 109
 110         /* VS */
 111         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 112         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 113         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 114         radeon_ring_write(rdev, gpu_addr >> 8);
 115         radeon_ring_write(rdev, 2);
 116         radeon_ring_write(rdev, 0);
 117
 118         /* PS */
 119         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 120         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 121         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 122         radeon_ring_write(rdev, gpu_addr >> 8);
 123         radeon_ring_write(rdev, 1);
 124         radeon_ring_write(rdev, 0);
 125         radeon_ring_write(rdev, 2);
 126
 127         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 128         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 129 }
 130
 131 /* emits 10 + 1 sync (5) = 15 */
 132 static void
 133 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 134 {
 135         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 136
 137         /* high addr, stride */
 138         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 139                 SQ_VTXC_STRIDE(16);
 140 #ifdef __BIG_ENDIAN
 141         sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 142 #endif
 143         /* xyzw swizzles */
 144         sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
 145                 SQ_VTCX_SEL_Y(SQ_SEL_Y) |
 146                 SQ_VTCX_SEL_Z(SQ_SEL_Z) |
 147                 SQ_VTCX_SEL_W(SQ_SEL_W);
 148
 149         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 150         radeon_ring_write(rdev, 0x580);
 151         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 152         radeon_ring_write(rdev, 48 - 1); /* size */
 153         radeon_ring_write(rdev, sq_vtx_constant_word2);
 154         radeon_ring_write(rdev, sq_vtx_constant_word3);
 155         radeon_ring_write(rdev, 0);
 156         radeon_ring_write(rdev, 0);
 157         radeon_ring_write(rdev, 0);
 158         radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 159
 160         if ((rdev->family == CHIP_CEDAR) ||
 161             (rdev->family == CHIP_PALM) ||
 162             (rdev->family == CHIP_SUMO) ||
 163             (rdev->family == CHIP_SUMO2) ||
 164             (rdev->family == CHIP_CAICOS))
 165                 cp_set_surface_sync(rdev,
 166                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 167         else
 168                 cp_set_surface_sync(rdev,
 169                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 170
 171 }
 172
 173 /* emits 10 */
 174 static void
 175 set_tex_resource(struct radeon_device *rdev,
 176                  int format, int w, int h, int pitch,
 177                  u64 gpu_addr)
 178 {
 179         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 180         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 181
 182         if (h < 1)
 183                 h = 1;
 184
 185         sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
 186         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 187                                   ((w - 1) << 18));
 188         sq_tex_resource_word1 = ((h - 1) << 0) |
 189                                 TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 190         /* xyzw swizzles */
 191         sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
 192                                 TEX_DST_SEL_Y(SQ_SEL_Y) |
 193                                 TEX_DST_SEL_Z(SQ_SEL_Z) |
 194                                 TEX_DST_SEL_W(SQ_SEL_W);
 195
 196         sq_tex_resource_word7 = format |
 197                 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 198
 199         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 200         radeon_ring_write(rdev, 0);
 201         radeon_ring_write(rdev, sq_tex_resource_word0);
 202         radeon_ring_write(rdev, sq_tex_resource_word1);
 203         radeon_ring_write(rdev, gpu_addr >> 8);
 204         radeon_ring_write(rdev, gpu_addr >> 8);
 205         radeon_ring_write(rdev, sq_tex_resource_word4);
 206         radeon_ring_write(rdev, 0);
 207         radeon_ring_write(rdev, 0);
 208         radeon_ring_write(rdev, sq_tex_resource_word7);
 209 }
 210
 211 /* emits 12 */
 212 static void
 213 set_scissors(struct radeon_device *rdev, int x1, int y1,
 214              int x2, int y2)
 215 {
 216         /* workaround some hw bugs */
 217         if (x2 == 0)
 218                 x1 = 1;
 219         if (y2 == 0)
 220                 y1 = 1;
 221         if (rdev->family == CHIP_CAYMAN) {
 222                 if ((x2 == 1) && (y2 == 1))
 223                         x2 = 2;
 224         }
 225
 226         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 227         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 228         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 229         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 230
 231         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 232         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 233         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 234         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 235
 236         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 237         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 238         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 239         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 240 }
 241
 242 /* emits 10 */
 243 static void
 244 draw_auto(struct radeon_device *rdev)
 245 {
 246         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 247         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 248         radeon_ring_write(rdev, DI_PT_RECTLIST);
 249
 250         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 251         radeon_ring_write(rdev,
 252 #ifdef __BIG_ENDIAN
 253                           (2 << 2) |
 254 #endif
 255                           DI_INDEX_SIZE_16_BIT);
 256
 257         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 258         radeon_ring_write(rdev, 1);
 259
 260         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 261         radeon_ring_write(rdev, 3);
 262         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 263
 264 }
 265
 266 /* emits 39 */
 267 static void
 268 set_default_state(struct radeon_device *rdev)
 269 {
 270         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 271         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 272         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 273         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 274         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 275         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 276         int num_hs_threads, num_ls_threads;
 277         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 278         int num_hs_stack_entries, num_ls_stack_entries;
 279         u64 gpu_addr;
 280         int dwords;
 281
 282         /* set clear context state */
 283         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
 284         radeon_ring_write(rdev, 0);
 285
 286         if (rdev->family < CHIP_CAYMAN) {
 287                 switch (rdev->family) {
 288                 case CHIP_CEDAR:
 289                 default:
 290                         num_ps_gprs = 93;
 291                         num_vs_gprs = 46;
 292                         num_temp_gprs = 4;
 293                         num_gs_gprs = 31;
 294                         num_es_gprs = 31;
 295                         num_hs_gprs = 23;
 296                         num_ls_gprs = 23;
 297                         num_ps_threads = 96;
 298                         num_vs_threads = 16;
 299                         num_gs_threads = 16;
 300                         num_es_threads = 16;
 301                         num_hs_threads = 16;
 302                         num_ls_threads = 16;
 303                         num_ps_stack_entries = 42;
 304                         num_vs_stack_entries = 42;
 305                         num_gs_stack_entries = 42;
 306                         num_es_stack_entries = 42;
 307                         num_hs_stack_entries = 42;
 308                         num_ls_stack_entries = 42;
 309                         break;
 310                 case CHIP_REDWOOD:
 311                         num_ps_gprs = 93;
 312                         num_vs_gprs = 46;
 313                         num_temp_gprs = 4;
 314                         num_gs_gprs = 31;
 315                         num_es_gprs = 31;
 316                         num_hs_gprs = 23;
 317                         num_ls_gprs = 23;
 318                         num_ps_threads = 128;
 319                         num_vs_threads = 20;
 320                         num_gs_threads = 20;
 321                         num_es_threads = 20;
 322                         num_hs_threads = 20;
 323                         num_ls_threads = 20;
 324                         num_ps_stack_entries = 42;
 325                         num_vs_stack_entries = 42;
 326                         num_gs_stack_entries = 42;
 327                         num_es_stack_entries = 42;
 328                         num_hs_stack_entries = 42;
 329                         num_ls_stack_entries = 42;
 330                         break;
 331                 case CHIP_JUNIPER:
 332                         num_ps_gprs = 93;
 333                         num_vs_gprs = 46;
 334                         num_temp_gprs = 4;
 335                         num_gs_gprs = 31;
 336                         num_es_gprs = 31;
 337                         num_hs_gprs = 23;
 338                         num_ls_gprs = 23;
 339                         num_ps_threads = 128;
 340                         num_vs_threads = 20;
 341                         num_gs_threads = 20;
 342                         num_es_threads = 20;
 343                         num_hs_threads = 20;
 344                         num_ls_threads = 20;
 345                         num_ps_stack_entries = 85;
 346                         num_vs_stack_entries = 85;
 347                         num_gs_stack_entries = 85;
 348                         num_es_stack_entries = 85;
 349                         num_hs_stack_entries = 85;
 350                         num_ls_stack_entries = 85;
 351                         break;
 352                 case CHIP_CYPRESS:
 353                 case CHIP_HEMLOCK:
 354                         num_ps_gprs = 93;
 355                         num_vs_gprs = 46;
 356                         num_temp_gprs = 4;
 357                         num_gs_gprs = 31;
 358                         num_es_gprs = 31;
 359                         num_hs_gprs = 23;
 360                         num_ls_gprs = 23;
 361                         num_ps_threads = 128;
 362                         num_vs_threads = 20;
 363                         num_gs_threads = 20;
 364                         num_es_threads = 20;
 365                         num_hs_threads = 20;
 366                         num_ls_threads = 20;
 367                         num_ps_stack_entries = 85;
 368                         num_vs_stack_entries = 85;
 369                         num_gs_stack_entries = 85;
 370                         num_es_stack_entries = 85;
 371                         num_hs_stack_entries = 85;
 372                         num_ls_stack_entries = 85;
 373                         break;
 374                 case CHIP_PALM:
 375                         num_ps_gprs = 93;
 376                         num_vs_gprs = 46;
 377                         num_temp_gprs = 4;
 378                         num_gs_gprs = 31;
 379                         num_es_gprs = 31;
 380                         num_hs_gprs = 23;
 381                         num_ls_gprs = 23;
 382                         num_ps_threads = 96;
 383                         num_vs_threads = 16;
 384                         num_gs_threads = 16;
 385                         num_es_threads = 16;
 386                         num_hs_threads = 16;
 387                         num_ls_threads = 16;
 388                         num_ps_stack_entries = 42;
 389                         num_vs_stack_entries = 42;
 390                         num_gs_stack_entries = 42;
 391                         num_es_stack_entries = 42;
 392                         num_hs_stack_entries = 42;
 393                         num_ls_stack_entries = 42;
 394                         break;
 395                 case CHIP_SUMO:
 396                         num_ps_gprs = 93;
 397                         num_vs_gprs = 46;
 398                         num_temp_gprs = 4;
 399                         num_gs_gprs = 31;
 400                         num_es_gprs = 31;
 401                         num_hs_gprs = 23;
 402                         num_ls_gprs = 23;
 403                         num_ps_threads = 96;
 404                         num_vs_threads = 25;
 405                         num_gs_threads = 25;
 406                         num_es_threads = 25;
 407                         num_hs_threads = 25;
 408                         num_ls_threads = 25;
 409                         num_ps_stack_entries = 42;
 410                         num_vs_stack_entries = 42;
 411                         num_gs_stack_entries = 42;
 412                         num_es_stack_entries = 42;
 413                         num_hs_stack_entries = 42;
 414                         num_ls_stack_entries = 42;
 415                         break;
 416                 case CHIP_SUMO2:
 417                         num_ps_gprs = 93;
 418                         num_vs_gprs = 46;
 419                         num_temp_gprs = 4;
 420                         num_gs_gprs = 31;
 421                         num_es_gprs = 31;
 422                         num_hs_gprs = 23;
 423                         num_ls_gprs = 23;
 424                         num_ps_threads = 96;
 425                         num_vs_threads = 25;
 426                         num_gs_threads = 25;
 427                         num_es_threads = 25;
 428                         num_hs_threads = 25;
 429                         num_ls_threads = 25;
 430                         num_ps_stack_entries = 85;
 431                         num_vs_stack_entries = 85;
 432                         num_gs_stack_entries = 85;
 433                         num_es_stack_entries = 85;
 434                         num_hs_stack_entries = 85;
 435                         num_ls_stack_entries = 85;
 436                         break;
 437                 case CHIP_BARTS:
 438                         num_ps_gprs = 93;
 439                         num_vs_gprs = 46;
 440                         num_temp_gprs = 4;
 441                         num_gs_gprs = 31;
 442                         num_es_gprs = 31;
 443                         num_hs_gprs = 23;
 444                         num_ls_gprs = 23;
 445                         num_ps_threads = 128;
 446                         num_vs_threads = 20;
 447                         num_gs_threads = 20;
 448                         num_es_threads = 20;
 449                         num_hs_threads = 20;
 450                         num_ls_threads = 20;
 451                         num_ps_stack_entries = 85;
 452                         num_vs_stack_entries = 85;
 453                         num_gs_stack_entries = 85;
 454                         num_es_stack_entries = 85;
 455                         num_hs_stack_entries = 85;
 456                         num_ls_stack_entries = 85;
 457                         break;
 458                 case CHIP_TURKS:
 459                         num_ps_gprs = 93;
 460                         num_vs_gprs = 46;
 461                         num_temp_gprs = 4;
 462                         num_gs_gprs = 31;
 463                         num_es_gprs = 31;
 464                         num_hs_gprs = 23;
 465                         num_ls_gprs = 23;
 466                         num_ps_threads = 128;
 467                         num_vs_threads = 20;
 468                         num_gs_threads = 20;
 469                         num_es_threads = 20;
 470                         num_hs_threads = 20;
 471                         num_ls_threads = 20;
 472                         num_ps_stack_entries = 42;
 473                         num_vs_stack_entries = 42;
 474                         num_gs_stack_entries = 42;
 475                         num_es_stack_entries = 42;
 476                         num_hs_stack_entries = 42;
 477                         num_ls_stack_entries = 42;
 478                         break;
 479                 case CHIP_CAICOS:
 480                         num_ps_gprs = 93;
 481                         num_vs_gprs = 46;
 482                         num_temp_gprs = 4;
 483                         num_gs_gprs = 31;
 484                         num_es_gprs = 31;
 485                         num_hs_gprs = 23;
 486                         num_ls_gprs = 23;
 487                         num_ps_threads = 128;
 488                         num_vs_threads = 10;
 489                         num_gs_threads = 10;
 490                         num_es_threads = 10;
 491                         num_hs_threads = 10;
 492                         num_ls_threads = 10;
 493                         num_ps_stack_entries = 42;
 494                         num_vs_stack_entries = 42;
 495                         num_gs_stack_entries = 42;
 496                         num_es_stack_entries = 42;
 497                         num_hs_stack_entries = 42;
 498                         num_ls_stack_entries = 42;
 499                         break;
 500                 }
 501
 502                 if ((rdev->family == CHIP_CEDAR) ||
 503                     (rdev->family == CHIP_PALM) ||
 504                     (rdev->family == CHIP_SUMO) ||
 505                     (rdev->family == CHIP_SUMO2) ||
 506                     (rdev->family == CHIP_CAICOS))
 507                         sq_config = 0;
 508                 else
 509                         sq_config = VC_ENABLE;
 510
 511                 sq_config |= (EXPORT_SRC_C |
 512                               CS_PRIO(0) |
 513                               LS_PRIO(0) |
 514                               HS_PRIO(0) |
 515                               PS_PRIO(0) |
 516                               VS_PRIO(1) |
 517                               GS_PRIO(2) |
 518                               ES_PRIO(3));
 519
 520                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 521                                           NUM_VS_GPRS(num_vs_gprs) |
 522                                           NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 523                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 524                                           NUM_ES_GPRS(num_es_gprs));
 525                 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 526                                           NUM_LS_GPRS(num_ls_gprs));
 527                 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 528                                            NUM_VS_THREADS(num_vs_threads) |
 529                                            NUM_GS_THREADS(num_gs_threads) |
 530                                            NUM_ES_THREADS(num_es_threads));
 531                 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 532                                              NUM_LS_THREADS(num_ls_threads));
 533                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 534                                             NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 535                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 536                                             NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 537                 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 538                                             NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 539
 540                 /* disable dyn gprs */
 541                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 542                 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 543                 radeon_ring_write(rdev, 0);
 544
 545                 /* setup LDS */
 546                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 547                 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
 548                 radeon_ring_write(rdev, 0x10001000);
 549
 550                 /* SQ config */
 551                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 552                 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 553                 radeon_ring_write(rdev, sq_config);
 554                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 555                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 556                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
 557                 radeon_ring_write(rdev, 0);
 558                 radeon_ring_write(rdev, 0);
 559                 radeon_ring_write(rdev, sq_thread_resource_mgmt);
 560                 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
 561                 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 562                 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 563                 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
 564         }
 565
 566         /* CONTEXT_CONTROL */
 567         radeon_ring_write(rdev, 0xc0012800);
 568         radeon_ring_write(rdev, 0x80000000);
 569         radeon_ring_write(rdev, 0x80000000);
 570
 571         /* SQ_VTX_BASE_VTX_LOC */
 572         radeon_ring_write(rdev, 0xc0026f00);
 573         radeon_ring_write(rdev, 0x00000000);
 574         radeon_ring_write(rdev, 0x00000000);
 575         radeon_ring_write(rdev, 0x00000000);
 576
 577         /* SET_SAMPLER */
 578         radeon_ring_write(rdev, 0xc0036e00);
 579         radeon_ring_write(rdev, 0x00000000);
 580         radeon_ring_write(rdev, 0x00000012);
 581         radeon_ring_write(rdev, 0x00000000);
 582         radeon_ring_write(rdev, 0x00000000);
 583
 584         /* set to DX10/11 mode */
 585         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
 586         radeon_ring_write(rdev, 1);
 587
 588         /* emit an IB pointing at default state */
 589         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 590         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 591         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 592         radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
 593         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 594         radeon_ring_write(rdev, dwords);
 595
 596 }
 597
 598 int evergreen_blit_init(struct radeon_device *rdev)
 599 {
 600         u32 obj_size;
 601         int i, r, dwords;
 602         void *ptr;
 603         u32 packet2s[16];
 604         int num_packet2s = 0;
 605
 606         rdev->r600_blit.primitives.set_render_target = set_render_target;
 607         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 608         rdev->r600_blit.primitives.set_shaders = set_shaders;
 609         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 610         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 611         rdev->r600_blit.primitives.set_scissors = set_scissors;
 612         rdev->r600_blit.primitives.draw_auto = draw_auto;
 613         rdev->r600_blit.primitives.set_default_state = set_default_state;
 614
 615         rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
 616         rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
 617         rdev->r600_blit.ring_size_common += 5; /* done copy */
 618         rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
 619
 620         rdev->r600_blit.ring_size_per_loop = 74;
 621
 622         rdev->r600_blit.max_dim = 16384;
 623
 624         /* pin copy shader into vram if already initialized */
 625         if (rdev->r600_blit.shader_obj)
 626                 goto done;
 627
 628         mutex_init(&rdev->r600_blit.mutex);
 629         rdev->r600_blit.state_offset = 0;
 630
 631         if (rdev->family < CHIP_CAYMAN)
 632                 rdev->r600_blit.state_len = evergreen_default_size;
 633         else
 634                 rdev->r600_blit.state_len = cayman_default_size;
 635
 636         dwords = rdev->r600_blit.state_len;
 637         while (dwords & 0xf) {
 638                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 639                 dwords++;
 640         }
 641
 642         obj_size = dwords * 4;
 643         obj_size = ALIGN(obj_size, 256);
 644
 645         rdev->r600_blit.vs_offset = obj_size;
 646         if (rdev->family < CHIP_CAYMAN)
 647                 obj_size += evergreen_vs_size * 4;
 648         else
 649                 obj_size += cayman_vs_size * 4;
 650         obj_size = ALIGN(obj_size, 256);
 651
 652         rdev->r600_blit.ps_offset = obj_size;
 653         if (rdev->family < CHIP_CAYMAN)
 654                 obj_size += evergreen_ps_size * 4;
 655         else
 656                 obj_size += cayman_ps_size * 4;
 657         obj_size = ALIGN(obj_size, 256);
 658
 659         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 660                                 &rdev->r600_blit.shader_obj);
 661         if (r) {
 662                 DRM_ERROR("evergreen failed to allocate shader\n");
 663                 return r;
 664         }
 665
 666         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 667                   obj_size,
 668                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 669
 670         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 671         if (unlikely(r != 0))
 672                 return r;
 673         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 674         if (r) {
 675                 DRM_ERROR("failed to map blit object %d\n", r);
 676                 return r;
 677         }
 678
 679         if (rdev->family < CHIP_CAYMAN) {
 680                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 681                             evergreen_default_state, rdev->r600_blit.state_len * 4);
 682
 683                 if (num_packet2s)
 684                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 685                                     packet2s, num_packet2s * 4);
 686                 for (i = 0; i < evergreen_vs_size; i++)
 687                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
 688                 for (i = 0; i < evergreen_ps_size; i++)
 689                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
 690         } else {
 691                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 692                             cayman_default_state, rdev->r600_blit.state_len * 4);
 693
 694                 if (num_packet2s)
 695                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 696                                     packet2s, num_packet2s * 4);
 697                 for (i = 0; i < cayman_vs_size; i++)
 698                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
 699                 for (i = 0; i < cayman_ps_size; i++)
 700                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
 701         }
 702         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 703         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 704
 705 done:
 706         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 707         if (unlikely(r != 0))
 708                 return r;
 709         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 710                           &rdev->r600_blit.shader_gpu_addr);
 711         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 712         if (r) {
 713                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 714                 return r;
 715         }
 716         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 717         return 0;
 718 }