drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 #define DI_PT_RECTLIST        0x11
  37 #define DI_INDEX_SIZE_16_BIT  0x0
  38 #define DI_SRC_SEL_AUTO_INDEX 0x2
  39
  40 #define FMT_8                 0x1
  41 #define FMT_5_6_5             0x8
  42 #define FMT_8_8_8_8           0x1a
  43 #define COLOR_8               0x1
  44 #define COLOR_5_6_5           0x8
  45 #define COLOR_8_8_8_8         0x1a
  46
  47 /* emits 17 */
  48 static void
  49 set_render_target(struct radeon_device *rdev, int format,
  50                   int w, int h, u64 gpu_addr)
  51 {
  52         u32 cb_color_info;
  53         int pitch, slice;
  54
  55         h = ALIGN(h, 8);
  56         if (h < 8)
  57                 h = 8;
  58
  59         cb_color_info = CB_FORMAT(format) |
  60                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  61                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  62         pitch = (w / 8) - 1;
  63         slice = ((w * h) / 64) - 1;
  64
  65         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  66         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  67         radeon_ring_write(rdev, gpu_addr >> 8);
  68         radeon_ring_write(rdev, pitch);
  69         radeon_ring_write(rdev, slice);
  70         radeon_ring_write(rdev, 0);
  71         radeon_ring_write(rdev, cb_color_info);
  72         radeon_ring_write(rdev, 0);
  73         radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
  74         radeon_ring_write(rdev, 0);
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, 0);
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, 0);
  79         radeon_ring_write(rdev, 0);
  80         radeon_ring_write(rdev, 0);
  81         radeon_ring_write(rdev, 0);
  82 }
  83
  84 /* emits 5dw */
  85 static void
  86 cp_set_surface_sync(struct radeon_device *rdev,
  87                     u32 sync_type, u32 size,
  88                     u64 mc_addr)
  89 {
  90         u32 cp_coher_size;
  91
  92         if (size == 0xffffffff)
  93                 cp_coher_size = 0xffffffff;
  94         else
  95                 cp_coher_size = ((size + 255) >> 8);
  96
  97         if (rdev->family >= CHIP_CAYMAN) {
  98                 /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
  99                  * to the RB directly. For IBs, the CP programs this as part of the
 100                  * surface_sync packet.
 101                  */
 102                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 103                 radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
 104                 radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */
 105         }
 106         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
 107         radeon_ring_write(rdev, sync_type);
 108         radeon_ring_write(rdev, cp_coher_size);
 109         radeon_ring_write(rdev, mc_addr >> 8);
 110         radeon_ring_write(rdev, 10); /* poll interval */
 111 }
 112
 113 /* emits 11dw + 1 surface sync = 16dw */
 114 static void
 115 set_shaders(struct radeon_device *rdev)
 116 {
 117         u64 gpu_addr;
 118
 119         /* VS */
 120         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 121         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 122         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 123         radeon_ring_write(rdev, gpu_addr >> 8);
 124         radeon_ring_write(rdev, 2);
 125         radeon_ring_write(rdev, 0);
 126
 127         /* PS */
 128         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 129         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 130         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 131         radeon_ring_write(rdev, gpu_addr >> 8);
 132         radeon_ring_write(rdev, 1);
 133         radeon_ring_write(rdev, 0);
 134         radeon_ring_write(rdev, 2);
 135
 136         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 137         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 138 }
 139
 140 /* emits 10 + 1 sync (5) = 15 */
 141 static void
 142 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 143 {
 144         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 145
 146         /* high addr, stride */
 147         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 148                 SQ_VTXC_STRIDE(16);
 149 #ifdef __BIG_ENDIAN
 150         sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 151 #endif
 152         /* xyzw swizzles */
 153         sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
 154                 SQ_VTCX_SEL_Y(SQ_SEL_Y) |
 155                 SQ_VTCX_SEL_Z(SQ_SEL_Z) |
 156                 SQ_VTCX_SEL_W(SQ_SEL_W);
 157
 158         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 159         radeon_ring_write(rdev, 0x580);
 160         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 161         radeon_ring_write(rdev, 48 - 1); /* size */
 162         radeon_ring_write(rdev, sq_vtx_constant_word2);
 163         radeon_ring_write(rdev, sq_vtx_constant_word3);
 164         radeon_ring_write(rdev, 0);
 165         radeon_ring_write(rdev, 0);
 166         radeon_ring_write(rdev, 0);
 167         radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 168
 169         if ((rdev->family == CHIP_CEDAR) ||
 170             (rdev->family == CHIP_PALM) ||
 171             (rdev->family == CHIP_SUMO) ||
 172             (rdev->family == CHIP_SUMO2) ||
 173             (rdev->family == CHIP_CAICOS))
 174                 cp_set_surface_sync(rdev,
 175                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 176         else
 177                 cp_set_surface_sync(rdev,
 178                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 179
 180 }
 181
 182 /* emits 10 */
 183 static void
 184 set_tex_resource(struct radeon_device *rdev,
 185                  int format, int w, int h, int pitch,
 186                  u64 gpu_addr, u32 size)
 187 {
 188         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 189         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 190
 191         if (h < 1)
 192                 h = 1;
 193
 194         sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
 195         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 196                                   ((w - 1) << 18));
 197         sq_tex_resource_word1 = ((h - 1) << 0) |
 198                                 TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 199         /* xyzw swizzles */
 200         sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
 201                                 TEX_DST_SEL_Y(SQ_SEL_Y) |
 202                                 TEX_DST_SEL_Z(SQ_SEL_Z) |
 203                                 TEX_DST_SEL_W(SQ_SEL_W);
 204
 205         sq_tex_resource_word7 = format |
 206                 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 207
 208         cp_set_surface_sync(rdev,
 209                             PACKET3_TC_ACTION_ENA, size, gpu_addr);
 210
 211         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 212         radeon_ring_write(rdev, 0);
 213         radeon_ring_write(rdev, sq_tex_resource_word0);
 214         radeon_ring_write(rdev, sq_tex_resource_word1);
 215         radeon_ring_write(rdev, gpu_addr >> 8);
 216         radeon_ring_write(rdev, gpu_addr >> 8);
 217         radeon_ring_write(rdev, sq_tex_resource_word4);
 218         radeon_ring_write(rdev, 0);
 219         radeon_ring_write(rdev, 0);
 220         radeon_ring_write(rdev, sq_tex_resource_word7);
 221 }
 222
 223 /* emits 12 */
 224 static void
 225 set_scissors(struct radeon_device *rdev, int x1, int y1,
 226              int x2, int y2)
 227 {
 228         /* workaround some hw bugs */
 229         if (x2 == 0)
 230                 x1 = 1;
 231         if (y2 == 0)
 232                 y1 = 1;
 233         if (rdev->family == CHIP_CAYMAN) {
 234                 if ((x2 == 1) && (y2 == 1))
 235                         x2 = 2;
 236         }
 237
 238         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 239         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 240         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 241         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 242
 243         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 244         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 245         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 246         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 247
 248         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 249         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 250         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 251         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 252 }
 253
 254 /* emits 10 */
 255 static void
 256 draw_auto(struct radeon_device *rdev)
 257 {
 258         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 259         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 260         radeon_ring_write(rdev, DI_PT_RECTLIST);
 261
 262         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 263         radeon_ring_write(rdev,
 264 #ifdef __BIG_ENDIAN
 265                           (2 << 2) |
 266 #endif
 267                           DI_INDEX_SIZE_16_BIT);
 268
 269         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 270         radeon_ring_write(rdev, 1);
 271
 272         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 273         radeon_ring_write(rdev, 3);
 274         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 275
 276 }
 277
 278 /* emits 39 */
 279 static void
 280 set_default_state(struct radeon_device *rdev)
 281 {
 282         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 283         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 284         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 285         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 286         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 287         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 288         int num_hs_threads, num_ls_threads;
 289         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 290         int num_hs_stack_entries, num_ls_stack_entries;
 291         u64 gpu_addr;
 292         int dwords;
 293
 294         /* set clear context state */
 295         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
 296         radeon_ring_write(rdev, 0);
 297
 298         if (rdev->family < CHIP_CAYMAN) {
 299                 switch (rdev->family) {
 300                 case CHIP_CEDAR:
 301                 default:
 302                         num_ps_gprs = 93;
 303                         num_vs_gprs = 46;
 304                         num_temp_gprs = 4;
 305                         num_gs_gprs = 31;
 306                         num_es_gprs = 31;
 307                         num_hs_gprs = 23;
 308                         num_ls_gprs = 23;
 309                         num_ps_threads = 96;
 310                         num_vs_threads = 16;
 311                         num_gs_threads = 16;
 312                         num_es_threads = 16;
 313                         num_hs_threads = 16;
 314                         num_ls_threads = 16;
 315                         num_ps_stack_entries = 42;
 316                         num_vs_stack_entries = 42;
 317                         num_gs_stack_entries = 42;
 318                         num_es_stack_entries = 42;
 319                         num_hs_stack_entries = 42;
 320                         num_ls_stack_entries = 42;
 321                         break;
 322                 case CHIP_REDWOOD:
 323                         num_ps_gprs = 93;
 324                         num_vs_gprs = 46;
 325                         num_temp_gprs = 4;
 326                         num_gs_gprs = 31;
 327                         num_es_gprs = 31;
 328                         num_hs_gprs = 23;
 329                         num_ls_gprs = 23;
 330                         num_ps_threads = 128;
 331                         num_vs_threads = 20;
 332                         num_gs_threads = 20;
 333                         num_es_threads = 20;
 334                         num_hs_threads = 20;
 335                         num_ls_threads = 20;
 336                         num_ps_stack_entries = 42;
 337                         num_vs_stack_entries = 42;
 338                         num_gs_stack_entries = 42;
 339                         num_es_stack_entries = 42;
 340                         num_hs_stack_entries = 42;
 341                         num_ls_stack_entries = 42;
 342                         break;
 343                 case CHIP_JUNIPER:
 344                         num_ps_gprs = 93;
 345                         num_vs_gprs = 46;
 346                         num_temp_gprs = 4;
 347                         num_gs_gprs = 31;
 348                         num_es_gprs = 31;
 349                         num_hs_gprs = 23;
 350                         num_ls_gprs = 23;
 351                         num_ps_threads = 128;
 352                         num_vs_threads = 20;
 353                         num_gs_threads = 20;
 354                         num_es_threads = 20;
 355                         num_hs_threads = 20;
 356                         num_ls_threads = 20;
 357                         num_ps_stack_entries = 85;
 358                         num_vs_stack_entries = 85;
 359                         num_gs_stack_entries = 85;
 360                         num_es_stack_entries = 85;
 361                         num_hs_stack_entries = 85;
 362                         num_ls_stack_entries = 85;
 363                         break;
 364                 case CHIP_CYPRESS:
 365                 case CHIP_HEMLOCK:
 366                         num_ps_gprs = 93;
 367                         num_vs_gprs = 46;
 368                         num_temp_gprs = 4;
 369                         num_gs_gprs = 31;
 370                         num_es_gprs = 31;
 371                         num_hs_gprs = 23;
 372                         num_ls_gprs = 23;
 373                         num_ps_threads = 128;
 374                         num_vs_threads = 20;
 375                         num_gs_threads = 20;
 376                         num_es_threads = 20;
 377                         num_hs_threads = 20;
 378                         num_ls_threads = 20;
 379                         num_ps_stack_entries = 85;
 380                         num_vs_stack_entries = 85;
 381                         num_gs_stack_entries = 85;
 382                         num_es_stack_entries = 85;
 383                         num_hs_stack_entries = 85;
 384                         num_ls_stack_entries = 85;
 385                         break;
 386                 case CHIP_PALM:
 387                         num_ps_gprs = 93;
 388                         num_vs_gprs = 46;
 389                         num_temp_gprs = 4;
 390                         num_gs_gprs = 31;
 391                         num_es_gprs = 31;
 392                         num_hs_gprs = 23;
 393                         num_ls_gprs = 23;
 394                         num_ps_threads = 96;
 395                         num_vs_threads = 16;
 396                         num_gs_threads = 16;
 397                         num_es_threads = 16;
 398                         num_hs_threads = 16;
 399                         num_ls_threads = 16;
 400                         num_ps_stack_entries = 42;
 401                         num_vs_stack_entries = 42;
 402                         num_gs_stack_entries = 42;
 403                         num_es_stack_entries = 42;
 404                         num_hs_stack_entries = 42;
 405                         num_ls_stack_entries = 42;
 406                         break;
 407                 case CHIP_SUMO:
 408                         num_ps_gprs = 93;
 409                         num_vs_gprs = 46;
 410                         num_temp_gprs = 4;
 411                         num_gs_gprs = 31;
 412                         num_es_gprs = 31;
 413                         num_hs_gprs = 23;
 414                         num_ls_gprs = 23;
 415                         num_ps_threads = 96;
 416                         num_vs_threads = 25;
 417                         num_gs_threads = 25;
 418                         num_es_threads = 25;
 419                         num_hs_threads = 25;
 420                         num_ls_threads = 25;
 421                         num_ps_stack_entries = 42;
 422                         num_vs_stack_entries = 42;
 423                         num_gs_stack_entries = 42;
 424                         num_es_stack_entries = 42;
 425                         num_hs_stack_entries = 42;
 426                         num_ls_stack_entries = 42;
 427                         break;
 428                 case CHIP_SUMO2:
 429                         num_ps_gprs = 93;
 430                         num_vs_gprs = 46;
 431                         num_temp_gprs = 4;
 432                         num_gs_gprs = 31;
 433                         num_es_gprs = 31;
 434                         num_hs_gprs = 23;
 435                         num_ls_gprs = 23;
 436                         num_ps_threads = 96;
 437                         num_vs_threads = 25;
 438                         num_gs_threads = 25;
 439                         num_es_threads = 25;
 440                         num_hs_threads = 25;
 441                         num_ls_threads = 25;
 442                         num_ps_stack_entries = 85;
 443                         num_vs_stack_entries = 85;
 444                         num_gs_stack_entries = 85;
 445                         num_es_stack_entries = 85;
 446                         num_hs_stack_entries = 85;
 447                         num_ls_stack_entries = 85;
 448                         break;
 449                 case CHIP_BARTS:
 450                         num_ps_gprs = 93;
 451                         num_vs_gprs = 46;
 452                         num_temp_gprs = 4;
 453                         num_gs_gprs = 31;
 454                         num_es_gprs = 31;
 455                         num_hs_gprs = 23;
 456                         num_ls_gprs = 23;
 457                         num_ps_threads = 128;
 458                         num_vs_threads = 20;
 459                         num_gs_threads = 20;
 460                         num_es_threads = 20;
 461                         num_hs_threads = 20;
 462                         num_ls_threads = 20;
 463                         num_ps_stack_entries = 85;
 464                         num_vs_stack_entries = 85;
 465                         num_gs_stack_entries = 85;
 466                         num_es_stack_entries = 85;
 467                         num_hs_stack_entries = 85;
 468                         num_ls_stack_entries = 85;
 469                         break;
 470                 case CHIP_TURKS:
 471                         num_ps_gprs = 93;
 472                         num_vs_gprs = 46;
 473                         num_temp_gprs = 4;
 474                         num_gs_gprs = 31;
 475                         num_es_gprs = 31;
 476                         num_hs_gprs = 23;
 477                         num_ls_gprs = 23;
 478                         num_ps_threads = 128;
 479                         num_vs_threads = 20;
 480                         num_gs_threads = 20;
 481                         num_es_threads = 20;
 482                         num_hs_threads = 20;
 483                         num_ls_threads = 20;
 484                         num_ps_stack_entries = 42;
 485                         num_vs_stack_entries = 42;
 486                         num_gs_stack_entries = 42;
 487                         num_es_stack_entries = 42;
 488                         num_hs_stack_entries = 42;
 489                         num_ls_stack_entries = 42;
 490                         break;
 491                 case CHIP_CAICOS:
 492                         num_ps_gprs = 93;
 493                         num_vs_gprs = 46;
 494                         num_temp_gprs = 4;
 495                         num_gs_gprs = 31;
 496                         num_es_gprs = 31;
 497                         num_hs_gprs = 23;
 498                         num_ls_gprs = 23;
 499                         num_ps_threads = 128;
 500                         num_vs_threads = 10;
 501                         num_gs_threads = 10;
 502                         num_es_threads = 10;
 503                         num_hs_threads = 10;
 504                         num_ls_threads = 10;
 505                         num_ps_stack_entries = 42;
 506                         num_vs_stack_entries = 42;
 507                         num_gs_stack_entries = 42;
 508                         num_es_stack_entries = 42;
 509                         num_hs_stack_entries = 42;
 510                         num_ls_stack_entries = 42;
 511                         break;
 512                 }
 513
 514                 if ((rdev->family == CHIP_CEDAR) ||
 515                     (rdev->family == CHIP_PALM) ||
 516                     (rdev->family == CHIP_SUMO) ||
 517                     (rdev->family == CHIP_SUMO2) ||
 518                     (rdev->family == CHIP_CAICOS))
 519                         sq_config = 0;
 520                 else
 521                         sq_config = VC_ENABLE;
 522
 523                 sq_config |= (EXPORT_SRC_C |
 524                               CS_PRIO(0) |
 525                               LS_PRIO(0) |
 526                               HS_PRIO(0) |
 527                               PS_PRIO(0) |
 528                               VS_PRIO(1) |
 529                               GS_PRIO(2) |
 530                               ES_PRIO(3));
 531
 532                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 533                                           NUM_VS_GPRS(num_vs_gprs) |
 534                                           NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 535                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 536                                           NUM_ES_GPRS(num_es_gprs));
 537                 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 538                                           NUM_LS_GPRS(num_ls_gprs));
 539                 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 540                                            NUM_VS_THREADS(num_vs_threads) |
 541                                            NUM_GS_THREADS(num_gs_threads) |
 542                                            NUM_ES_THREADS(num_es_threads));
 543                 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 544                                              NUM_LS_THREADS(num_ls_threads));
 545                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 546                                             NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 547                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 548                                             NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 549                 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 550                                             NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 551
 552                 /* disable dyn gprs */
 553                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 554                 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 555                 radeon_ring_write(rdev, 0);
 556
 557                 /* setup LDS */
 558                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 559                 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
 560                 radeon_ring_write(rdev, 0x10001000);
 561
 562                 /* SQ config */
 563                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 564                 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 565                 radeon_ring_write(rdev, sq_config);
 566                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 567                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 568                 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
 569                 radeon_ring_write(rdev, 0);
 570                 radeon_ring_write(rdev, 0);
 571                 radeon_ring_write(rdev, sq_thread_resource_mgmt);
 572                 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
 573                 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 574                 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 575                 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
 576         }
 577
 578         /* CONTEXT_CONTROL */
 579         radeon_ring_write(rdev, 0xc0012800);
 580         radeon_ring_write(rdev, 0x80000000);
 581         radeon_ring_write(rdev, 0x80000000);
 582
 583         /* SQ_VTX_BASE_VTX_LOC */
 584         radeon_ring_write(rdev, 0xc0026f00);
 585         radeon_ring_write(rdev, 0x00000000);
 586         radeon_ring_write(rdev, 0x00000000);
 587         radeon_ring_write(rdev, 0x00000000);
 588
 589         /* SET_SAMPLER */
 590         radeon_ring_write(rdev, 0xc0036e00);
 591         radeon_ring_write(rdev, 0x00000000);
 592         radeon_ring_write(rdev, 0x00000012);
 593         radeon_ring_write(rdev, 0x00000000);
 594         radeon_ring_write(rdev, 0x00000000);
 595
 596         /* set to DX10/11 mode */
 597         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
 598         radeon_ring_write(rdev, 1);
 599
 600         /* emit an IB pointing at default state */
 601         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 602         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 603         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 604         radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
 605         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 606         radeon_ring_write(rdev, dwords);
 607
 608 }
 609
 610 int evergreen_blit_init(struct radeon_device *rdev)
 611 {
 612         u32 obj_size;
 613         int i, r, dwords;
 614         void *ptr;
 615         u32 packet2s[16];
 616         int num_packet2s = 0;
 617
 618         rdev->r600_blit.primitives.set_render_target = set_render_target;
 619         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 620         rdev->r600_blit.primitives.set_shaders = set_shaders;
 621         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 622         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 623         rdev->r600_blit.primitives.set_scissors = set_scissors;
 624         rdev->r600_blit.primitives.draw_auto = draw_auto;
 625         rdev->r600_blit.primitives.set_default_state = set_default_state;
 626
 627         rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
 628         rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
 629         rdev->r600_blit.ring_size_common += 5; /* done copy */
 630         rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
 631
 632         rdev->r600_blit.ring_size_per_loop = 74;
 633         if (rdev->family >= CHIP_CAYMAN)
 634                 rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
 635
 636         rdev->r600_blit.max_dim = 16384;
 637
 638         /* pin copy shader into vram if already initialized */
 639         if (rdev->r600_blit.shader_obj)
 640                 goto done;
 641
 642         mutex_init(&rdev->r600_blit.mutex);
 643         rdev->r600_blit.state_offset = 0;
 644
 645         if (rdev->family < CHIP_CAYMAN)
 646                 rdev->r600_blit.state_len = evergreen_default_size;
 647         else
 648                 rdev->r600_blit.state_len = cayman_default_size;
 649
 650         dwords = rdev->r600_blit.state_len;
 651         while (dwords & 0xf) {
 652                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 653                 dwords++;
 654         }
 655
 656         obj_size = dwords * 4;
 657         obj_size = ALIGN(obj_size, 256);
 658
 659         rdev->r600_blit.vs_offset = obj_size;
 660         if (rdev->family < CHIP_CAYMAN)
 661                 obj_size += evergreen_vs_size * 4;
 662         else
 663                 obj_size += cayman_vs_size * 4;
 664         obj_size = ALIGN(obj_size, 256);
 665
 666         rdev->r600_blit.ps_offset = obj_size;
 667         if (rdev->family < CHIP_CAYMAN)
 668                 obj_size += evergreen_ps_size * 4;
 669         else
 670                 obj_size += cayman_ps_size * 4;
 671         obj_size = ALIGN(obj_size, 256);
 672
 673         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 674                                 &rdev->r600_blit.shader_obj);
 675         if (r) {
 676                 DRM_ERROR("evergreen failed to allocate shader\n");
 677                 return r;
 678         }
 679
 680         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 681                   obj_size,
 682                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 683
 684         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 685         if (unlikely(r != 0))
 686                 return r;
 687         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 688         if (r) {
 689                 DRM_ERROR("failed to map blit object %d\n", r);
 690                 return r;
 691         }
 692
 693         if (rdev->family < CHIP_CAYMAN) {
 694                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 695                             evergreen_default_state, rdev->r600_blit.state_len * 4);
 696
 697                 if (num_packet2s)
 698                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 699                                     packet2s, num_packet2s * 4);
 700                 for (i = 0; i < evergreen_vs_size; i++)
 701                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
 702                 for (i = 0; i < evergreen_ps_size; i++)
 703                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
 704         } else {
 705                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 706                             cayman_default_state, rdev->r600_blit.state_len * 4);
 707
 708                 if (num_packet2s)
 709                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 710                                     packet2s, num_packet2s * 4);
 711                 for (i = 0; i < cayman_vs_size; i++)
 712                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
 713                 for (i = 0; i < cayman_ps_size; i++)
 714                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
 715         }
 716         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 717         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 718
 719 done:
 720         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 721         if (unlikely(r != 0))
 722                 return r;
 723         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 724                           &rdev->r600_blit.shader_gpu_addr);
 725         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 726         if (r) {
 727                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 728                 return r;
 729         }
 730         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 731         return 0;
 732 }