drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34
  35 #define DI_PT_RECTLIST        0x11
  36 #define DI_INDEX_SIZE_16_BIT  0x0
  37 #define DI_SRC_SEL_AUTO_INDEX 0x2
  38
  39 #define FMT_8                 0x1
  40 #define FMT_5_6_5             0x8
  41 #define FMT_8_8_8_8           0x1a
  42 #define COLOR_8               0x1
  43 #define COLOR_5_6_5           0x8
  44 #define COLOR_8_8_8_8         0x1a
  45
  46 /* emits 17 */
  47 static void
  48 set_render_target(struct radeon_device *rdev, int format,
  49                   int w, int h, u64 gpu_addr)
  50 {
  51         u32 cb_color_info;
  52         int pitch, slice;
  53
  54         h = ALIGN(h, 8);
  55         if (h < 8)
  56                 h = 8;
  57
  58         cb_color_info = ((format << 2) | (1 << 24));
  59         pitch = (w / 8) - 1;
  60         slice = ((w * h) / 64) - 1;
  61
  62         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  63         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  64         radeon_ring_write(rdev, gpu_addr >> 8);
  65         radeon_ring_write(rdev, pitch);
  66         radeon_ring_write(rdev, slice);
  67         radeon_ring_write(rdev, 0);
  68         radeon_ring_write(rdev, cb_color_info);
  69         radeon_ring_write(rdev, (1 << 4));
  70         radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
  71         radeon_ring_write(rdev, 0);
  72         radeon_ring_write(rdev, 0);
  73         radeon_ring_write(rdev, 0);
  74         radeon_ring_write(rdev, 0);
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, 0);
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, 0);
  79 }
  80
  81 /* emits 5dw */
  82 static void
  83 cp_set_surface_sync(struct radeon_device *rdev,
  84                     u32 sync_type, u32 size,
  85                     u64 mc_addr)
  86 {
  87         u32 cp_coher_size;
  88
  89         if (size == 0xffffffff)
  90                 cp_coher_size = 0xffffffff;
  91         else
  92                 cp_coher_size = ((size + 255) >> 8);
  93
  94         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
  95         radeon_ring_write(rdev, sync_type);
  96         radeon_ring_write(rdev, cp_coher_size);
  97         radeon_ring_write(rdev, mc_addr >> 8);
  98         radeon_ring_write(rdev, 10); /* poll interval */
  99 }
 100
 101 /* emits 11dw + 1 surface sync = 16dw */
 102 static void
 103 set_shaders(struct radeon_device *rdev)
 104 {
 105         u64 gpu_addr;
 106
 107         /* VS */
 108         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 109         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 110         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 111         radeon_ring_write(rdev, gpu_addr >> 8);
 112         radeon_ring_write(rdev, 2);
 113         radeon_ring_write(rdev, 0);
 114
 115         /* PS */
 116         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 117         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 118         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 119         radeon_ring_write(rdev, gpu_addr >> 8);
 120         radeon_ring_write(rdev, 1);
 121         radeon_ring_write(rdev, 0);
 122         radeon_ring_write(rdev, 2);
 123
 124         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 125         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 126 }
 127
 128 /* emits 10 + 1 sync (5) = 15 */
 129 static void
 130 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 131 {
 132         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 133
 134         /* high addr, stride */
 135         sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
 136         /* xyzw swizzles */
 137         sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
 138
 139         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 140         radeon_ring_write(rdev, 0x580);
 141         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 142         radeon_ring_write(rdev, 48 - 1); /* size */
 143         radeon_ring_write(rdev, sq_vtx_constant_word2);
 144         radeon_ring_write(rdev, sq_vtx_constant_word3);
 145         radeon_ring_write(rdev, 0);
 146         radeon_ring_write(rdev, 0);
 147         radeon_ring_write(rdev, 0);
 148         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 149
 150         if (rdev->family == CHIP_CEDAR)
 151                 cp_set_surface_sync(rdev,
 152                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 153         else
 154                 cp_set_surface_sync(rdev,
 155                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 156
 157 }
 158
 159 /* emits 10 */
 160 static void
 161 set_tex_resource(struct radeon_device *rdev,
 162                  int format, int w, int h, int pitch,
 163                  u64 gpu_addr)
 164 {
 165         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 166         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 167
 168         if (h < 1)
 169                 h = 1;
 170
 171         sq_tex_resource_word0 = (1 << 0); /* 2D */
 172         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 173                                   ((w - 1) << 18));
 174         sq_tex_resource_word1 = ((h - 1) << 0);
 175         /* xyzw swizzles */
 176         sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
 177
 178         sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
 179
 180         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 181         radeon_ring_write(rdev, 0);
 182         radeon_ring_write(rdev, sq_tex_resource_word0);
 183         radeon_ring_write(rdev, sq_tex_resource_word1);
 184         radeon_ring_write(rdev, gpu_addr >> 8);
 185         radeon_ring_write(rdev, gpu_addr >> 8);
 186         radeon_ring_write(rdev, sq_tex_resource_word4);
 187         radeon_ring_write(rdev, 0);
 188         radeon_ring_write(rdev, 0);
 189         radeon_ring_write(rdev, sq_tex_resource_word7);
 190 }
 191
 192 /* emits 12 */
 193 static void
 194 set_scissors(struct radeon_device *rdev, int x1, int y1,
 195              int x2, int y2)
 196 {
 197         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 198         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 199         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 200         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 201
 202         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 203         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 204         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 205         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 206
 207         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 208         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 209         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 210         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 211 }
 212
 213 /* emits 10 */
 214 static void
 215 draw_auto(struct radeon_device *rdev)
 216 {
 217         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 218         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 219         radeon_ring_write(rdev, DI_PT_RECTLIST);
 220
 221         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 222         radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
 223
 224         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 225         radeon_ring_write(rdev, 1);
 226
 227         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 228         radeon_ring_write(rdev, 3);
 229         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 230
 231 }
 232
 233 /* emits 30 */
 234 static void
 235 set_default_state(struct radeon_device *rdev)
 236 {
 237         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 238         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 239         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 240         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 241         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 242         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 243         int num_hs_threads, num_ls_threads;
 244         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 245         int num_hs_stack_entries, num_ls_stack_entries;
 246
 247         switch (rdev->family) {
 248         case CHIP_CEDAR:
 249         default:
 250                 num_ps_gprs = 93;
 251                 num_vs_gprs = 46;
 252                 num_temp_gprs = 4;
 253                 num_gs_gprs = 31;
 254                 num_es_gprs = 31;
 255                 num_hs_gprs = 23;
 256                 num_ls_gprs = 23;
 257                 num_ps_threads = 96;
 258                 num_vs_threads = 16;
 259                 num_gs_threads = 16;
 260                 num_es_threads = 16;
 261                 num_hs_threads = 16;
 262                 num_ls_threads = 16;
 263                 num_ps_stack_entries = 42;
 264                 num_vs_stack_entries = 42;
 265                 num_gs_stack_entries = 42;
 266                 num_es_stack_entries = 42;
 267                 num_hs_stack_entries = 42;
 268                 num_ls_stack_entries = 42;
 269                 break;
 270         case CHIP_REDWOOD:
 271                 num_ps_gprs = 93;
 272                 num_vs_gprs = 46;
 273                 num_temp_gprs = 4;
 274                 num_gs_gprs = 31;
 275                 num_es_gprs = 31;
 276                 num_hs_gprs = 23;
 277                 num_ls_gprs = 23;
 278                 num_ps_threads = 128;
 279                 num_vs_threads = 20;
 280                 num_gs_threads = 20;
 281                 num_es_threads = 20;
 282                 num_hs_threads = 20;
 283                 num_ls_threads = 20;
 284                 num_ps_stack_entries = 42;
 285                 num_vs_stack_entries = 42;
 286                 num_gs_stack_entries = 42;
 287                 num_es_stack_entries = 42;
 288                 num_hs_stack_entries = 42;
 289                 num_ls_stack_entries = 42;
 290                 break;
 291         case CHIP_JUNIPER:
 292                 num_ps_gprs = 93;
 293                 num_vs_gprs = 46;
 294                 num_temp_gprs = 4;
 295                 num_gs_gprs = 31;
 296                 num_es_gprs = 31;
 297                 num_hs_gprs = 23;
 298                 num_ls_gprs = 23;
 299                 num_ps_threads = 128;
 300                 num_vs_threads = 20;
 301                 num_gs_threads = 20;
 302                 num_es_threads = 20;
 303                 num_hs_threads = 20;
 304                 num_ls_threads = 20;
 305                 num_ps_stack_entries = 85;
 306                 num_vs_stack_entries = 85;
 307                 num_gs_stack_entries = 85;
 308                 num_es_stack_entries = 85;
 309                 num_hs_stack_entries = 85;
 310                 num_ls_stack_entries = 85;
 311                 break;
 312         case CHIP_CYPRESS:
 313         case CHIP_HEMLOCK:
 314                 num_ps_gprs = 93;
 315                 num_vs_gprs = 46;
 316                 num_temp_gprs = 4;
 317                 num_gs_gprs = 31;
 318                 num_es_gprs = 31;
 319                 num_hs_gprs = 23;
 320                 num_ls_gprs = 23;
 321                 num_ps_threads = 128;
 322                 num_vs_threads = 20;
 323                 num_gs_threads = 20;
 324                 num_es_threads = 20;
 325                 num_hs_threads = 20;
 326                 num_ls_threads = 20;
 327                 num_ps_stack_entries = 85;
 328                 num_vs_stack_entries = 85;
 329                 num_gs_stack_entries = 85;
 330                 num_es_stack_entries = 85;
 331                 num_hs_stack_entries = 85;
 332                 num_ls_stack_entries = 85;
 333                 break;
 334         }
 335
 336         if (rdev->family == CHIP_CEDAR)
 337                 sq_config = 0;
 338         else
 339                 sq_config = VC_ENABLE;
 340
 341         sq_config |= (EXPORT_SRC_C |
 342                       CS_PRIO(0) |
 343                       LS_PRIO(0) |
 344                       HS_PRIO(0) |
 345                       PS_PRIO(0) |
 346                       VS_PRIO(1) |
 347                       GS_PRIO(2) |
 348                       ES_PRIO(3));
 349
 350         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 351                                   NUM_VS_GPRS(num_vs_gprs) |
 352                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 353         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 354                                   NUM_ES_GPRS(num_es_gprs));
 355         sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 356                                   NUM_LS_GPRS(num_ls_gprs));
 357         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 358                                    NUM_VS_THREADS(num_vs_threads) |
 359                                    NUM_GS_THREADS(num_gs_threads) |
 360                                    NUM_ES_THREADS(num_es_threads));
 361         sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 362                                      NUM_LS_THREADS(num_ls_threads));
 363         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 364                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 365         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 366                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 367         sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 368                                     NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 369
 370         /* set clear context state */
 371         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
 372         radeon_ring_write(rdev, 0);
 373
 374         /* disable dyn gprs */
 375         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 376         radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 377         radeon_ring_write(rdev, 0);
 378
 379         /* SQ config */
 380         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 381         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 382         radeon_ring_write(rdev, sq_config);
 383         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 384         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 385         radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
 386         radeon_ring_write(rdev, 0);
 387         radeon_ring_write(rdev, 0);
 388         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 389         radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
 390         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 391         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 392         radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
 393
 394         /* CONTEXT_CONTROL */
 395         radeon_ring_write(rdev, 0xc0012800);
 396         radeon_ring_write(rdev, 0x80000000);
 397         radeon_ring_write(rdev, 0x80000000);
 398
 399         /* SQ_VTX_BASE_VTX_LOC */
 400         radeon_ring_write(rdev, 0xc0026f00);
 401         radeon_ring_write(rdev, 0x00000000);
 402         radeon_ring_write(rdev, 0x00000000);
 403         radeon_ring_write(rdev, 0x00000000);
 404
 405         /* SET_SAMPLER */
 406         radeon_ring_write(rdev, 0xc0036e00);
 407         radeon_ring_write(rdev, 0x00000000);
 408         radeon_ring_write(rdev, 0x00000012);
 409         radeon_ring_write(rdev, 0x00000000);
 410         radeon_ring_write(rdev, 0x00000000);
 411
 412 }
 413
 414 static inline uint32_t i2f(uint32_t input)
 415 {
 416         u32 result, i, exponent, fraction;
 417
 418         if ((input & 0x3fff) == 0)
 419                 result = 0; /* 0 is a special case */
 420         else {
 421                 exponent = 140; /* exponent biased by 127; */
 422                 fraction = (input & 0x3fff) << 10; /* cheat and only
 423                                                       handle numbers below 2^^15 */
 424                 for (i = 0; i < 14; i++) {
 425                         if (fraction & 0x800000)
 426                                 break;
 427                         else {
 428                                 fraction = fraction << 1; /* keep
 429                                                              shifting left until top bit = 1 */
 430                                 exponent = exponent - 1;
 431                         }
 432                 }
 433                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 434                                                                     off top bit; assumed 1 */
 435         }
 436         return result;
 437 }
 438
 439 int evergreen_blit_init(struct radeon_device *rdev)
 440 {
 441         u32 obj_size;
 442         int r;
 443         void *ptr;
 444
 445         /* pin copy shader into vram if already initialized */
 446         if (rdev->r600_blit.shader_obj)
 447                 goto done;
 448
 449         mutex_init(&rdev->r600_blit.mutex);
 450         rdev->r600_blit.state_offset = 0;
 451         rdev->r600_blit.state_len = 0;
 452         obj_size = 0;
 453
 454         rdev->r600_blit.vs_offset = obj_size;
 455         obj_size += evergreen_vs_size * 4;
 456         obj_size = ALIGN(obj_size, 256);
 457
 458         rdev->r600_blit.ps_offset = obj_size;
 459         obj_size += evergreen_ps_size * 4;
 460         obj_size = ALIGN(obj_size, 256);
 461
 462         r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM,
 463                                 &rdev->r600_blit.shader_obj);
 464         if (r) {
 465                 DRM_ERROR("evergreen failed to allocate shader\n");
 466                 return r;
 467         }
 468
 469         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 470                   obj_size,
 471                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 472
 473         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 474         if (unlikely(r != 0))
 475                 return r;
 476         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 477         if (r) {
 478                 DRM_ERROR("failed to map blit object %d\n", r);
 479                 return r;
 480         }
 481
 482         memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
 483         memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
 484         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 485         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 486
 487 done:
 488         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 489         if (unlikely(r != 0))
 490                 return r;
 491         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 492                           &rdev->r600_blit.shader_gpu_addr);
 493         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 494         if (r) {
 495                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 496                 return r;
 497         }
 498         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
 499         return 0;
 500 }
 501
 502 void evergreen_blit_fini(struct radeon_device *rdev)
 503 {
 504         int r;
 505
 506         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 507         if (rdev->r600_blit.shader_obj == NULL)
 508                 return;
 509         /* If we can't reserve the bo, unref should be enough to destroy
 510          * it when it becomes idle.
 511          */
 512         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 513         if (!r) {
 514                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 515                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 516         }
 517         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 518 }
 519
 520 static int evergreen_vb_ib_get(struct radeon_device *rdev)
 521 {
 522         int r;
 523         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 524         if (r) {
 525                 DRM_ERROR("failed to get IB for vertex buffer\n");
 526                 return r;
 527         }
 528
 529         rdev->r600_blit.vb_total = 64*1024;
 530         rdev->r600_blit.vb_used = 0;
 531         return 0;
 532 }
 533
 534 static void evergreen_vb_ib_put(struct radeon_device *rdev)
 535 {
 536         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 537         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 538 }
 539
 540 int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 541 {
 542         int r;
 543         int ring_size, line_size;
 544         int max_size;
 545         /* loops of emits + fence emit possible */
 546         int dwords_per_loop = 74, num_loops;
 547
 548         r = evergreen_vb_ib_get(rdev);
 549         if (r)
 550                 return r;
 551
 552         /* 8 bpp vs 32 bpp for xfer unit */
 553         if (size_bytes & 3)
 554                 line_size = 8192;
 555         else
 556                 line_size = 8192 * 4;
 557
 558         max_size = 8192 * line_size;
 559
 560         /* major loops cover the max size transfer */
 561         num_loops = ((size_bytes + max_size) / max_size);
 562         /* minor loops cover the extra non aligned bits */
 563         num_loops += ((size_bytes % line_size) ? 1 : 0);
 564         /* calculate number of loops correctly */
 565         ring_size = num_loops * dwords_per_loop;
 566         /* set default  + shaders */
 567         ring_size += 46; /* shaders + def state */
 568         ring_size += 10; /* fence emit for VB IB */
 569         ring_size += 5; /* done copy */
 570         ring_size += 10; /* fence emit for done copy */
 571         r = radeon_ring_lock(rdev, ring_size);
 572         if (r)
 573                 return r;
 574
 575         set_default_state(rdev); /* 30 */
 576         set_shaders(rdev); /* 16 */
 577         return 0;
 578 }
 579
 580 void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 581 {
 582         int r;
 583
 584         if (rdev->r600_blit.vb_ib)
 585                 evergreen_vb_ib_put(rdev);
 586
 587         if (fence)
 588                 r = radeon_fence_emit(rdev, fence);
 589
 590         radeon_ring_unlock_commit(rdev);
 591 }
 592
 593 void evergreen_kms_blit_copy(struct radeon_device *rdev,
 594                              u64 src_gpu_addr, u64 dst_gpu_addr,
 595                              int size_bytes)
 596 {
 597         int max_bytes;
 598         u64 vb_gpu_addr;
 599         u32 *vb;
 600
 601         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 602                   size_bytes, rdev->r600_blit.vb_used);
 603         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 604         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 605                 max_bytes = 8192;
 606
 607                 while (size_bytes) {
 608                         int cur_size = size_bytes;
 609                         int src_x = src_gpu_addr & 255;
 610                         int dst_x = dst_gpu_addr & 255;
 611                         int h = 1;
 612                         src_gpu_addr = src_gpu_addr & ~255ULL;
 613                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 614
 615                         if (!src_x && !dst_x) {
 616                                 h = (cur_size / max_bytes);
 617                                 if (h > 8192)
 618                                         h = 8192;
 619                                 if (h == 0)
 620                                         h = 1;
 621                                 else
 622                                         cur_size = max_bytes;
 623                         } else {
 624                                 if (cur_size > max_bytes)
 625                                         cur_size = max_bytes;
 626                                 if (cur_size > (max_bytes - dst_x))
 627                                         cur_size = (max_bytes - dst_x);
 628                                 if (cur_size > (max_bytes - src_x))
 629                                         cur_size = (max_bytes - src_x);
 630                         }
 631
 632                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 633                                 WARN_ON(1);
 634                         }
 635
 636                         vb[0] = i2f(dst_x);
 637                         vb[1] = 0;
 638                         vb[2] = i2f(src_x);
 639                         vb[3] = 0;
 640
 641                         vb[4] = i2f(dst_x);
 642                         vb[5] = i2f(h);
 643                         vb[6] = i2f(src_x);
 644                         vb[7] = i2f(h);
 645
 646                         vb[8] = i2f(dst_x + cur_size);
 647                         vb[9] = i2f(h);
 648                         vb[10] = i2f(src_x + cur_size);
 649                         vb[11] = i2f(h);
 650
 651                         /* src 10 */
 652                         set_tex_resource(rdev, FMT_8,
 653                                          src_x + cur_size, h, src_x + cur_size,
 654                                          src_gpu_addr);
 655
 656                         /* 5 */
 657                         cp_set_surface_sync(rdev,
 658                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 659
 660
 661                         /* dst 17 */
 662                         set_render_target(rdev, COLOR_8,
 663                                           dst_x + cur_size, h,
 664                                           dst_gpu_addr);
 665
 666                         /* scissors 12 */
 667                         set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 668
 669                         /* 15 */
 670                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 671                         set_vtx_resource(rdev, vb_gpu_addr);
 672
 673                         /* draw 10 */
 674                         draw_auto(rdev);
 675
 676                         /* 5 */
 677                         cp_set_surface_sync(rdev,
 678                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 679                                             cur_size * h, dst_gpu_addr);
 680
 681                         vb += 12;
 682                         rdev->r600_blit.vb_used += 12 * 4;
 683
 684                         src_gpu_addr += cur_size * h;
 685                         dst_gpu_addr += cur_size * h;
 686                         size_bytes -= cur_size * h;
 687                 }
 688         } else {
 689                 max_bytes = 8192 * 4;
 690
 691                 while (size_bytes) {
 692                         int cur_size = size_bytes;
 693                         int src_x = (src_gpu_addr & 255);
 694                         int dst_x = (dst_gpu_addr & 255);
 695                         int h = 1;
 696                         src_gpu_addr = src_gpu_addr & ~255ULL;
 697                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 698
 699                         if (!src_x && !dst_x) {
 700                                 h = (cur_size / max_bytes);
 701                                 if (h > 8192)
 702                                         h = 8192;
 703                                 if (h == 0)
 704                                         h = 1;
 705                                 else
 706                                         cur_size = max_bytes;
 707                         } else {
 708                                 if (cur_size > max_bytes)
 709                                         cur_size = max_bytes;
 710                                 if (cur_size > (max_bytes - dst_x))
 711                                         cur_size = (max_bytes - dst_x);
 712                                 if (cur_size > (max_bytes - src_x))
 713                                         cur_size = (max_bytes - src_x);
 714                         }
 715
 716                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 717                                 WARN_ON(1);
 718                         }
 719
 720                         vb[0] = i2f(dst_x / 4);
 721                         vb[1] = 0;
 722                         vb[2] = i2f(src_x / 4);
 723                         vb[3] = 0;
 724
 725                         vb[4] = i2f(dst_x / 4);
 726                         vb[5] = i2f(h);
 727                         vb[6] = i2f(src_x / 4);
 728                         vb[7] = i2f(h);
 729
 730                         vb[8] = i2f((dst_x + cur_size) / 4);
 731                         vb[9] = i2f(h);
 732                         vb[10] = i2f((src_x + cur_size) / 4);
 733                         vb[11] = i2f(h);
 734
 735                         /* src 10 */
 736                         set_tex_resource(rdev, FMT_8_8_8_8,
 737                                          (src_x + cur_size) / 4,
 738                                          h, (src_x + cur_size) / 4,
 739                                          src_gpu_addr);
 740                         /* 5 */
 741                         cp_set_surface_sync(rdev,
 742                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 743
 744                         /* dst 17 */
 745                         set_render_target(rdev, COLOR_8_8_8_8,
 746                                           (dst_x + cur_size) / 4, h,
 747                                           dst_gpu_addr);
 748
 749                         /* scissors 12  */
 750                         set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 751
 752                         /* Vertex buffer setup 15 */
 753                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 754                         set_vtx_resource(rdev, vb_gpu_addr);
 755
 756                         /* draw 10 */
 757                         draw_auto(rdev);
 758
 759                         /* 5 */
 760                         cp_set_surface_sync(rdev,
 761                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 762                                             cur_size * h, dst_gpu_addr);
 763
 764                         /* 74 ring dwords per loop */
 765                         vb += 12;
 766                         rdev->r600_blit.vb_used += 12 * 4;
 767
 768                         src_gpu_addr += cur_size * h;
 769                         dst_gpu_addr += cur_size * h;
 770                         size_bytes -= cur_size * h;
 771                 }
 772         }
 773 }
 774