drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 #define DI_PT_RECTLIST        0x11
  37 #define DI_INDEX_SIZE_16_BIT  0x0
  38 #define DI_SRC_SEL_AUTO_INDEX 0x2
  39
  40 #define FMT_8                 0x1
  41 #define FMT_5_6_5             0x8
  42 #define FMT_8_8_8_8           0x1a
  43 #define COLOR_8               0x1
  44 #define COLOR_5_6_5           0x8
  45 #define COLOR_8_8_8_8         0x1a
  46
  47 /* emits 17 */
  48 static void
  49 set_render_target(struct radeon_device *rdev, int format,
  50                   int w, int h, u64 gpu_addr)
  51 {
  52         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  53         u32 cb_color_info;
  54         int pitch, slice;
  55
  56         h = ALIGN(h, 8);
  57         if (h < 8)
  58                 h = 8;
  59
  60         cb_color_info = CB_FORMAT(format) |
  61                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  62                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  63         pitch = (w / 8) - 1;
  64         slice = ((w * h) / 64) - 1;
  65
  66         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  67         radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  68         radeon_ring_write(ring, gpu_addr >> 8);
  69         radeon_ring_write(ring, pitch);
  70         radeon_ring_write(ring, slice);
  71         radeon_ring_write(ring, 0);
  72         radeon_ring_write(ring, cb_color_info);
  73         radeon_ring_write(ring, 0);
  74         radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
  75         radeon_ring_write(ring, 0);
  76         radeon_ring_write(ring, 0);
  77         radeon_ring_write(ring, 0);
  78         radeon_ring_write(ring, 0);
  79         radeon_ring_write(ring, 0);
  80         radeon_ring_write(ring, 0);
  81         radeon_ring_write(ring, 0);
  82         radeon_ring_write(ring, 0);
  83 }
  84
  85 /* emits 5dw */
  86 static void
  87 cp_set_surface_sync(struct radeon_device *rdev,
  88                     u32 sync_type, u32 size,
  89                     u64 mc_addr)
  90 {
  91         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  92         u32 cp_coher_size;
  93
  94         if (size == 0xffffffff)
  95                 cp_coher_size = 0xffffffff;
  96         else
  97                 cp_coher_size = ((size + 255) >> 8);
  98
  99         if (rdev->family >= CHIP_CAYMAN) {
 100                 /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
 101                  * to the RB directly. For IBs, the CP programs this as part of the
 102                  * surface_sync packet.
 103                  */
 104                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 105                 radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
 106                 radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
 107         }
 108         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 109         radeon_ring_write(ring, sync_type);
 110         radeon_ring_write(ring, cp_coher_size);
 111         radeon_ring_write(ring, mc_addr >> 8);
 112         radeon_ring_write(ring, 10); /* poll interval */
 113 }
 114
 115 /* emits 11dw + 1 surface sync = 16dw */
 116 static void
 117 set_shaders(struct radeon_device *rdev)
 118 {
 119         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 120         u64 gpu_addr;
 121
 122         /* VS */
 123         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 124         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 125         radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 126         radeon_ring_write(ring, gpu_addr >> 8);
 127         radeon_ring_write(ring, 2);
 128         radeon_ring_write(ring, 0);
 129
 130         /* PS */
 131         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 132         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 133         radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 134         radeon_ring_write(ring, gpu_addr >> 8);
 135         radeon_ring_write(ring, 1);
 136         radeon_ring_write(ring, 0);
 137         radeon_ring_write(ring, 2);
 138
 139         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 140         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 141 }
 142
 143 /* emits 10 + 1 sync (5) = 15 */
 144 static void
 145 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 146 {
 147         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 148         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 149
 150         /* high addr, stride */
 151         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 152                 SQ_VTXC_STRIDE(16);
 153 #ifdef __BIG_ENDIAN
 154         sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 155 #endif
 156         /* xyzw swizzles */
 157         sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
 158                 SQ_VTCX_SEL_Y(SQ_SEL_Y) |
 159                 SQ_VTCX_SEL_Z(SQ_SEL_Z) |
 160                 SQ_VTCX_SEL_W(SQ_SEL_W);
 161
 162         radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
 163         radeon_ring_write(ring, 0x580);
 164         radeon_ring_write(ring, gpu_addr & 0xffffffff);
 165         radeon_ring_write(ring, 48 - 1); /* size */
 166         radeon_ring_write(ring, sq_vtx_constant_word2);
 167         radeon_ring_write(ring, sq_vtx_constant_word3);
 168         radeon_ring_write(ring, 0);
 169         radeon_ring_write(ring, 0);
 170         radeon_ring_write(ring, 0);
 171         radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 172
 173         if ((rdev->family == CHIP_CEDAR) ||
 174             (rdev->family == CHIP_PALM) ||
 175             (rdev->family == CHIP_SUMO) ||
 176             (rdev->family == CHIP_SUMO2) ||
 177             (rdev->family == CHIP_CAICOS))
 178                 cp_set_surface_sync(rdev,
 179                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 180         else
 181                 cp_set_surface_sync(rdev,
 182                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 183
 184 }
 185
 186 /* emits 10 */
 187 static void
 188 set_tex_resource(struct radeon_device *rdev,
 189                  int format, int w, int h, int pitch,
 190                  u64 gpu_addr, u32 size)
 191 {
 192         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 193         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 194         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 195
 196         if (h < 1)
 197                 h = 1;
 198
 199         sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
 200         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 201                                   ((w - 1) << 18));
 202         sq_tex_resource_word1 = ((h - 1) << 0) |
 203                                 TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
 204         /* xyzw swizzles */
 205         sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
 206                                 TEX_DST_SEL_Y(SQ_SEL_Y) |
 207                                 TEX_DST_SEL_Z(SQ_SEL_Z) |
 208                                 TEX_DST_SEL_W(SQ_SEL_W);
 209
 210         sq_tex_resource_word7 = format |
 211                 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 212
 213         cp_set_surface_sync(rdev,
 214                             PACKET3_TC_ACTION_ENA, size, gpu_addr);
 215
 216         radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
 217         radeon_ring_write(ring, 0);
 218         radeon_ring_write(ring, sq_tex_resource_word0);
 219         radeon_ring_write(ring, sq_tex_resource_word1);
 220         radeon_ring_write(ring, gpu_addr >> 8);
 221         radeon_ring_write(ring, gpu_addr >> 8);
 222         radeon_ring_write(ring, sq_tex_resource_word4);
 223         radeon_ring_write(ring, 0);
 224         radeon_ring_write(ring, 0);
 225         radeon_ring_write(ring, sq_tex_resource_word7);
 226 }
 227
 228 /* emits 12 */
 229 static void
 230 set_scissors(struct radeon_device *rdev, int x1, int y1,
 231              int x2, int y2)
 232 {
 233         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 234         /* workaround some hw bugs */
 235         if (x2 == 0)
 236                 x1 = 1;
 237         if (y2 == 0)
 238                 y1 = 1;
 239         if (rdev->family == CHIP_CAYMAN) {
 240                 if ((x2 == 1) && (y2 == 1))
 241                         x2 = 2;
 242         }
 243
 244         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 245         radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 246         radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
 247         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 248
 249         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 250         radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 251         radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
 252         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 253
 254         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 255         radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 256         radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
 257         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 258 }
 259
 260 /* emits 10 */
 261 static void
 262 draw_auto(struct radeon_device *rdev)
 263 {
 264         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 265         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 266         radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 267         radeon_ring_write(ring, DI_PT_RECTLIST);
 268
 269         radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
 270         radeon_ring_write(ring,
 271 #ifdef __BIG_ENDIAN
 272                           (2 << 2) |
 273 #endif
 274                           DI_INDEX_SIZE_16_BIT);
 275
 276         radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
 277         radeon_ring_write(ring, 1);
 278
 279         radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 280         radeon_ring_write(ring, 3);
 281         radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
 282
 283 }
 284
 285 /* emits 39 */
 286 static void
 287 set_default_state(struct radeon_device *rdev)
 288 {
 289         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 290         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 291         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 292         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 293         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 294         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 295         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 296         int num_hs_threads, num_ls_threads;
 297         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 298         int num_hs_stack_entries, num_ls_stack_entries;
 299         u64 gpu_addr;
 300         int dwords;
 301
 302         /* set clear context state */
 303         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
 304         radeon_ring_write(ring, 0);
 305
 306         if (rdev->family < CHIP_CAYMAN) {
 307                 switch (rdev->family) {
 308                 case CHIP_CEDAR:
 309                 default:
 310                         num_ps_gprs = 93;
 311                         num_vs_gprs = 46;
 312                         num_temp_gprs = 4;
 313                         num_gs_gprs = 31;
 314                         num_es_gprs = 31;
 315                         num_hs_gprs = 23;
 316                         num_ls_gprs = 23;
 317                         num_ps_threads = 96;
 318                         num_vs_threads = 16;
 319                         num_gs_threads = 16;
 320                         num_es_threads = 16;
 321                         num_hs_threads = 16;
 322                         num_ls_threads = 16;
 323                         num_ps_stack_entries = 42;
 324                         num_vs_stack_entries = 42;
 325                         num_gs_stack_entries = 42;
 326                         num_es_stack_entries = 42;
 327                         num_hs_stack_entries = 42;
 328                         num_ls_stack_entries = 42;
 329                         break;
 330                 case CHIP_REDWOOD:
 331                         num_ps_gprs = 93;
 332                         num_vs_gprs = 46;
 333                         num_temp_gprs = 4;
 334                         num_gs_gprs = 31;
 335                         num_es_gprs = 31;
 336                         num_hs_gprs = 23;
 337                         num_ls_gprs = 23;
 338                         num_ps_threads = 128;
 339                         num_vs_threads = 20;
 340                         num_gs_threads = 20;
 341                         num_es_threads = 20;
 342                         num_hs_threads = 20;
 343                         num_ls_threads = 20;
 344                         num_ps_stack_entries = 42;
 345                         num_vs_stack_entries = 42;
 346                         num_gs_stack_entries = 42;
 347                         num_es_stack_entries = 42;
 348                         num_hs_stack_entries = 42;
 349                         num_ls_stack_entries = 42;
 350                         break;
 351                 case CHIP_JUNIPER:
 352                         num_ps_gprs = 93;
 353                         num_vs_gprs = 46;
 354                         num_temp_gprs = 4;
 355                         num_gs_gprs = 31;
 356                         num_es_gprs = 31;
 357                         num_hs_gprs = 23;
 358                         num_ls_gprs = 23;
 359                         num_ps_threads = 128;
 360                         num_vs_threads = 20;
 361                         num_gs_threads = 20;
 362                         num_es_threads = 20;
 363                         num_hs_threads = 20;
 364                         num_ls_threads = 20;
 365                         num_ps_stack_entries = 85;
 366                         num_vs_stack_entries = 85;
 367                         num_gs_stack_entries = 85;
 368                         num_es_stack_entries = 85;
 369                         num_hs_stack_entries = 85;
 370                         num_ls_stack_entries = 85;
 371                         break;
 372                 case CHIP_CYPRESS:
 373                 case CHIP_HEMLOCK:
 374                         num_ps_gprs = 93;
 375                         num_vs_gprs = 46;
 376                         num_temp_gprs = 4;
 377                         num_gs_gprs = 31;
 378                         num_es_gprs = 31;
 379                         num_hs_gprs = 23;
 380                         num_ls_gprs = 23;
 381                         num_ps_threads = 128;
 382                         num_vs_threads = 20;
 383                         num_gs_threads = 20;
 384                         num_es_threads = 20;
 385                         num_hs_threads = 20;
 386                         num_ls_threads = 20;
 387                         num_ps_stack_entries = 85;
 388                         num_vs_stack_entries = 85;
 389                         num_gs_stack_entries = 85;
 390                         num_es_stack_entries = 85;
 391                         num_hs_stack_entries = 85;
 392                         num_ls_stack_entries = 85;
 393                         break;
 394                 case CHIP_PALM:
 395                         num_ps_gprs = 93;
 396                         num_vs_gprs = 46;
 397                         num_temp_gprs = 4;
 398                         num_gs_gprs = 31;
 399                         num_es_gprs = 31;
 400                         num_hs_gprs = 23;
 401                         num_ls_gprs = 23;
 402                         num_ps_threads = 96;
 403                         num_vs_threads = 16;
 404                         num_gs_threads = 16;
 405                         num_es_threads = 16;
 406                         num_hs_threads = 16;
 407                         num_ls_threads = 16;
 408                         num_ps_stack_entries = 42;
 409                         num_vs_stack_entries = 42;
 410                         num_gs_stack_entries = 42;
 411                         num_es_stack_entries = 42;
 412                         num_hs_stack_entries = 42;
 413                         num_ls_stack_entries = 42;
 414                         break;
 415                 case CHIP_SUMO:
 416                         num_ps_gprs = 93;
 417                         num_vs_gprs = 46;
 418                         num_temp_gprs = 4;
 419                         num_gs_gprs = 31;
 420                         num_es_gprs = 31;
 421                         num_hs_gprs = 23;
 422                         num_ls_gprs = 23;
 423                         num_ps_threads = 96;
 424                         num_vs_threads = 25;
 425                         num_gs_threads = 25;
 426                         num_es_threads = 25;
 427                         num_hs_threads = 25;
 428                         num_ls_threads = 25;
 429                         num_ps_stack_entries = 42;
 430                         num_vs_stack_entries = 42;
 431                         num_gs_stack_entries = 42;
 432                         num_es_stack_entries = 42;
 433                         num_hs_stack_entries = 42;
 434                         num_ls_stack_entries = 42;
 435                         break;
 436                 case CHIP_SUMO2:
 437                         num_ps_gprs = 93;
 438                         num_vs_gprs = 46;
 439                         num_temp_gprs = 4;
 440                         num_gs_gprs = 31;
 441                         num_es_gprs = 31;
 442                         num_hs_gprs = 23;
 443                         num_ls_gprs = 23;
 444                         num_ps_threads = 96;
 445                         num_vs_threads = 25;
 446                         num_gs_threads = 25;
 447                         num_es_threads = 25;
 448                         num_hs_threads = 25;
 449                         num_ls_threads = 25;
 450                         num_ps_stack_entries = 85;
 451                         num_vs_stack_entries = 85;
 452                         num_gs_stack_entries = 85;
 453                         num_es_stack_entries = 85;
 454                         num_hs_stack_entries = 85;
 455                         num_ls_stack_entries = 85;
 456                         break;
 457                 case CHIP_BARTS:
 458                         num_ps_gprs = 93;
 459                         num_vs_gprs = 46;
 460                         num_temp_gprs = 4;
 461                         num_gs_gprs = 31;
 462                         num_es_gprs = 31;
 463                         num_hs_gprs = 23;
 464                         num_ls_gprs = 23;
 465                         num_ps_threads = 128;
 466                         num_vs_threads = 20;
 467                         num_gs_threads = 20;
 468                         num_es_threads = 20;
 469                         num_hs_threads = 20;
 470                         num_ls_threads = 20;
 471                         num_ps_stack_entries = 85;
 472                         num_vs_stack_entries = 85;
 473                         num_gs_stack_entries = 85;
 474                         num_es_stack_entries = 85;
 475                         num_hs_stack_entries = 85;
 476                         num_ls_stack_entries = 85;
 477                         break;
 478                 case CHIP_TURKS:
 479                         num_ps_gprs = 93;
 480                         num_vs_gprs = 46;
 481                         num_temp_gprs = 4;
 482                         num_gs_gprs = 31;
 483                         num_es_gprs = 31;
 484                         num_hs_gprs = 23;
 485                         num_ls_gprs = 23;
 486                         num_ps_threads = 128;
 487                         num_vs_threads = 20;
 488                         num_gs_threads = 20;
 489                         num_es_threads = 20;
 490                         num_hs_threads = 20;
 491                         num_ls_threads = 20;
 492                         num_ps_stack_entries = 42;
 493                         num_vs_stack_entries = 42;
 494                         num_gs_stack_entries = 42;
 495                         num_es_stack_entries = 42;
 496                         num_hs_stack_entries = 42;
 497                         num_ls_stack_entries = 42;
 498                         break;
 499                 case CHIP_CAICOS:
 500                         num_ps_gprs = 93;
 501                         num_vs_gprs = 46;
 502                         num_temp_gprs = 4;
 503                         num_gs_gprs = 31;
 504                         num_es_gprs = 31;
 505                         num_hs_gprs = 23;
 506                         num_ls_gprs = 23;
 507                         num_ps_threads = 128;
 508                         num_vs_threads = 10;
 509                         num_gs_threads = 10;
 510                         num_es_threads = 10;
 511                         num_hs_threads = 10;
 512                         num_ls_threads = 10;
 513                         num_ps_stack_entries = 42;
 514                         num_vs_stack_entries = 42;
 515                         num_gs_stack_entries = 42;
 516                         num_es_stack_entries = 42;
 517                         num_hs_stack_entries = 42;
 518                         num_ls_stack_entries = 42;
 519                         break;
 520                 }
 521
 522                 if ((rdev->family == CHIP_CEDAR) ||
 523                     (rdev->family == CHIP_PALM) ||
 524                     (rdev->family == CHIP_SUMO) ||
 525                     (rdev->family == CHIP_SUMO2) ||
 526                     (rdev->family == CHIP_CAICOS))
 527                         sq_config = 0;
 528                 else
 529                         sq_config = VC_ENABLE;
 530
 531                 sq_config |= (EXPORT_SRC_C |
 532                               CS_PRIO(0) |
 533                               LS_PRIO(0) |
 534                               HS_PRIO(0) |
 535                               PS_PRIO(0) |
 536                               VS_PRIO(1) |
 537                               GS_PRIO(2) |
 538                               ES_PRIO(3));
 539
 540                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 541                                           NUM_VS_GPRS(num_vs_gprs) |
 542                                           NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 543                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 544                                           NUM_ES_GPRS(num_es_gprs));
 545                 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 546                                           NUM_LS_GPRS(num_ls_gprs));
 547                 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 548                                            NUM_VS_THREADS(num_vs_threads) |
 549                                            NUM_GS_THREADS(num_gs_threads) |
 550                                            NUM_ES_THREADS(num_es_threads));
 551                 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 552                                              NUM_LS_THREADS(num_ls_threads));
 553                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 554                                             NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 555                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 556                                             NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 557                 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 558                                             NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 559
 560                 /* disable dyn gprs */
 561                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 562                 radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 563                 radeon_ring_write(ring, 0);
 564
 565                 /* setup LDS */
 566                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 567                 radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
 568                 radeon_ring_write(ring, 0x10001000);
 569
 570                 /* SQ config */
 571                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 572                 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 573                 radeon_ring_write(ring, sq_config);
 574                 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
 575                 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
 576                 radeon_ring_write(ring, sq_gpr_resource_mgmt_3);
 577                 radeon_ring_write(ring, 0);
 578                 radeon_ring_write(ring, 0);
 579                 radeon_ring_write(ring, sq_thread_resource_mgmt);
 580                 radeon_ring_write(ring, sq_thread_resource_mgmt_2);
 581                 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
 582                 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
 583                 radeon_ring_write(ring, sq_stack_resource_mgmt_3);
 584         }
 585
 586         /* CONTEXT_CONTROL */
 587         radeon_ring_write(ring, 0xc0012800);
 588         radeon_ring_write(ring, 0x80000000);
 589         radeon_ring_write(ring, 0x80000000);
 590
 591         /* SQ_VTX_BASE_VTX_LOC */
 592         radeon_ring_write(ring, 0xc0026f00);
 593         radeon_ring_write(ring, 0x00000000);
 594         radeon_ring_write(ring, 0x00000000);
 595         radeon_ring_write(ring, 0x00000000);
 596
 597         /* SET_SAMPLER */
 598         radeon_ring_write(ring, 0xc0036e00);
 599         radeon_ring_write(ring, 0x00000000);
 600         radeon_ring_write(ring, 0x00000012);
 601         radeon_ring_write(ring, 0x00000000);
 602         radeon_ring_write(ring, 0x00000000);
 603
 604         /* set to DX10/11 mode */
 605         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
 606         radeon_ring_write(ring, 1);
 607
 608         /* emit an IB pointing at default state */
 609         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 610         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 611         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 612         radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
 613         radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
 614         radeon_ring_write(ring, dwords);
 615
 616 }
 617
 618 int evergreen_blit_init(struct radeon_device *rdev)
 619 {
 620         u32 obj_size;
 621         int i, r, dwords;
 622         void *ptr;
 623         u32 packet2s[16];
 624         int num_packet2s = 0;
 625
 626         rdev->r600_blit.primitives.set_render_target = set_render_target;
 627         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 628         rdev->r600_blit.primitives.set_shaders = set_shaders;
 629         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 630         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 631         rdev->r600_blit.primitives.set_scissors = set_scissors;
 632         rdev->r600_blit.primitives.draw_auto = draw_auto;
 633         rdev->r600_blit.primitives.set_default_state = set_default_state;
 634
 635         rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
 636         rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
 637         rdev->r600_blit.ring_size_common += 5; /* done copy */
 638         rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
 639
 640         rdev->r600_blit.ring_size_per_loop = 74;
 641         if (rdev->family >= CHIP_CAYMAN)
 642                 rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
 643
 644         rdev->r600_blit.max_dim = 16384;
 645
 646         /* pin copy shader into vram if already initialized */
 647         if (rdev->r600_blit.shader_obj)
 648                 goto done;
 649
 650         mutex_init(&rdev->r600_blit.mutex);
 651         rdev->r600_blit.state_offset = 0;
 652
 653         if (rdev->family < CHIP_CAYMAN)
 654                 rdev->r600_blit.state_len = evergreen_default_size;
 655         else
 656                 rdev->r600_blit.state_len = cayman_default_size;
 657
 658         dwords = rdev->r600_blit.state_len;
 659         while (dwords & 0xf) {
 660                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 661                 dwords++;
 662         }
 663
 664         obj_size = dwords * 4;
 665         obj_size = ALIGN(obj_size, 256);
 666
 667         rdev->r600_blit.vs_offset = obj_size;
 668         if (rdev->family < CHIP_CAYMAN)
 669                 obj_size += evergreen_vs_size * 4;
 670         else
 671                 obj_size += cayman_vs_size * 4;
 672         obj_size = ALIGN(obj_size, 256);
 673
 674         rdev->r600_blit.ps_offset = obj_size;
 675         if (rdev->family < CHIP_CAYMAN)
 676                 obj_size += evergreen_ps_size * 4;
 677         else
 678                 obj_size += cayman_ps_size * 4;
 679         obj_size = ALIGN(obj_size, 256);
 680
 681         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 682                                 &rdev->r600_blit.shader_obj);
 683         if (r) {
 684                 DRM_ERROR("evergreen failed to allocate shader\n");
 685                 return r;
 686         }
 687
 688         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 689                   obj_size,
 690                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 691
 692         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 693         if (unlikely(r != 0))
 694                 return r;
 695         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 696         if (r) {
 697                 DRM_ERROR("failed to map blit object %d\n", r);
 698                 return r;
 699         }
 700
 701         if (rdev->family < CHIP_CAYMAN) {
 702                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 703                             evergreen_default_state, rdev->r600_blit.state_len * 4);
 704
 705                 if (num_packet2s)
 706                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 707                                     packet2s, num_packet2s * 4);
 708                 for (i = 0; i < evergreen_vs_size; i++)
 709                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
 710                 for (i = 0; i < evergreen_ps_size; i++)
 711                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
 712         } else {
 713                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 714                             cayman_default_state, rdev->r600_blit.state_len * 4);
 715
 716                 if (num_packet2s)
 717                         memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 718                                     packet2s, num_packet2s * 4);
 719                 for (i = 0; i < cayman_vs_size; i++)
 720                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
 721                 for (i = 0; i < cayman_ps_size; i++)
 722                         *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
 723         }
 724         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 725         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 726
 727 done:
 728         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 729         if (unlikely(r != 0))
 730                 return r;
 731         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 732                           &rdev->r600_blit.shader_gpu_addr);
 733         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 734         if (r) {
 735                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 736                 return r;
 737         }
 738         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 739         return 0;
 740 }