drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/i7300_idle.h>
  37 #include "dma.h"
  38 #include "registers.h"
  39 #include "hw.h"
  40
  41 int ioat_pending_level = 4;
  42 module_param(ioat_pending_level, int, 0644);
  43 MODULE_PARM_DESC(ioat_pending_level,
  44                  "high-water mark for pushing ioat descriptors (default: 4)");
  45
  46 /* internal functions */
  47 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  48 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  49
  50 /**
  51  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  52  * @irq: interrupt id
  53  * @data: interrupt data
  54  */
  55 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  56 {
  57         struct ioatdma_device *instance = data;
  58         struct ioat_chan_common *chan;
  59         unsigned long attnstatus;
  60         int bit;
  61         u8 intrctrl;
  62
  63         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  64
  65         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  66                 return IRQ_NONE;
  67
  68         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  69                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  70                 return IRQ_NONE;
  71         }
  72
  73         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  74         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
  75                 chan = ioat_chan_by_index(instance, bit);
  76                 tasklet_schedule(&chan->cleanup_task);
  77         }
  78
  79         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  80         return IRQ_HANDLED;
  81 }
  82
  83 /**
  84  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  85  * @irq: interrupt id
  86  * @data: interrupt data
  87  */
  88 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  89 {
  90         struct ioat_chan_common *chan = data;
  91
  92         tasklet_schedule(&chan->cleanup_task);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 static void ioat1_cleanup_tasklet(unsigned long data);
  98
  99 /* common channel initialization */
 100 void ioat_init_channel(struct ioatdma_device *device,
 101                        struct ioat_chan_common *chan, int idx,
 102                        void (*timer_fn)(unsigned long),
 103                        void (*tasklet)(unsigned long),
 104                        unsigned long ioat)
 105 {
 106         struct dma_device *dma = &device->common;
 107
 108         chan->device = device;
 109         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 110         spin_lock_init(&chan->cleanup_lock);
 111         chan->common.device = dma;
 112         list_add_tail(&chan->common.device_node, &dma->channels);
 113         device->idx[idx] = chan;
 114         init_timer(&chan->timer);
 115         chan->timer.function = timer_fn;
 116         chan->timer.data = ioat;
 117         tasklet_init(&chan->cleanup_task, tasklet, ioat);
 118         tasklet_disable(&chan->cleanup_task);
 119 }
 120
 121 static void ioat1_timer_event(unsigned long data);
 122
 123 /**
 124  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 125  * @device: the device to be enumerated
 126  */
 127 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 128 {
 129         u8 xfercap_scale;
 130         u32 xfercap;
 131         int i;
 132         struct ioat_dma_chan *ioat;
 133         struct device *dev = &device->pdev->dev;
 134         struct dma_device *dma = &device->common;
 135
 136         INIT_LIST_HEAD(&dma->channels);
 137         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 138         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 139         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 140                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 141                          dma->chancnt, ARRAY_SIZE(device->idx));
 142                 dma->chancnt = ARRAY_SIZE(device->idx);
 143         }
 144         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 145         xfercap_scale &= 0x1f; /* bits [4:0] valid */
 146         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 147         dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
 148
 149 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 150         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 151                 dma->chancnt--;
 152 #endif
 153         for (i = 0; i < dma->chancnt; i++) {
 154                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 155                 if (!ioat)
 156                         break;
 157
 158                 ioat_init_channel(device, &ioat->base, i,
 159                                   ioat1_timer_event,
 160                                   ioat1_cleanup_tasklet,
 161                                   (unsigned long) ioat);
 162                 ioat->xfercap = xfercap;
 163                 spin_lock_init(&ioat->desc_lock);
 164                 INIT_LIST_HEAD(&ioat->free_desc);
 165                 INIT_LIST_HEAD(&ioat->used_desc);
 166         }
 167         dma->chancnt = i;
 168         return i;
 169 }
 170
 171 /**
 172  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 173  *                                 descriptors to hw
 174  * @chan: DMA channel handle
 175  */
 176 static inline void
 177 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 178 {
 179         void __iomem *reg_base = ioat->base.reg_base;
 180
 181         dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
 182                 __func__, ioat->pending);
 183         ioat->pending = 0;
 184         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 185 }
 186
 187 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 188 {
 189         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 190
 191         if (ioat->pending > 0) {
 192                 spin_lock_bh(&ioat->desc_lock);
 193                 __ioat1_dma_memcpy_issue_pending(ioat);
 194                 spin_unlock_bh(&ioat->desc_lock);
 195         }
 196 }
 197
 198 /**
 199  * ioat1_reset_channel - restart a channel
 200  * @ioat: IOAT DMA channel handle
 201  */
 202 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 203 {
 204         struct ioat_chan_common *chan = &ioat->base;
 205         void __iomem *reg_base = chan->reg_base;
 206         u32 chansts, chanerr;
 207
 208         dev_warn(to_dev(chan), "reset\n");
 209         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 210         chansts = *chan->completion & IOAT_CHANSTS_STATUS;
 211         if (chanerr) {
 212                 dev_err(to_dev(chan),
 213                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 214                         chan_num(chan), chansts, chanerr);
 215                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 216         }
 217
 218         /*
 219          * whack it upside the head with a reset
 220          * and wait for things to settle out.
 221          * force the pending count to a really big negative
 222          * to make sure no one forces an issue_pending
 223          * while we're waiting.
 224          */
 225
 226         ioat->pending = INT_MIN;
 227         writeb(IOAT_CHANCMD_RESET,
 228                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 229         set_bit(IOAT_RESET_PENDING, &chan->state);
 230         mod_timer(&chan->timer, jiffies + RESET_DELAY);
 231 }
 232
 233 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 234 {
 235         struct dma_chan *c = tx->chan;
 236         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 237         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 238         struct ioat_chan_common *chan = &ioat->base;
 239         struct ioat_desc_sw *first;
 240         struct ioat_desc_sw *chain_tail;
 241         dma_cookie_t cookie;
 242
 243         spin_lock_bh(&ioat->desc_lock);
 244         /* cookie incr and addition to used_list must be atomic */
 245         cookie = c->cookie;
 246         cookie++;
 247         if (cookie < 0)
 248                 cookie = 1;
 249         c->cookie = cookie;
 250         tx->cookie = cookie;
 251         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 252
 253         /* write address into NextDescriptor field of last desc in chain */
 254         first = to_ioat_desc(desc->tx_list.next);
 255         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 256         /* make descriptor updates globally visible before chaining */
 257         wmb();
 258         chain_tail->hw->next = first->txd.phys;
 259         list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
 260         dump_desc_dbg(ioat, chain_tail);
 261         dump_desc_dbg(ioat, first);
 262
 263         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 264                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 265
 266         ioat->pending += desc->hw->tx_cnt;
 267         if (ioat->pending >= ioat_pending_level)
 268                 __ioat1_dma_memcpy_issue_pending(ioat);
 269         spin_unlock_bh(&ioat->desc_lock);
 270
 271         return cookie;
 272 }
 273
 274 /**
 275  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 276  * @ioat: the channel supplying the memory pool for the descriptors
 277  * @flags: allocation flags
 278  */
 279 static struct ioat_desc_sw *
 280 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 281 {
 282         struct ioat_dma_descriptor *desc;
 283         struct ioat_desc_sw *desc_sw;
 284         struct ioatdma_device *ioatdma_device;
 285         dma_addr_t phys;
 286
 287         ioatdma_device = ioat->base.device;
 288         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 289         if (unlikely(!desc))
 290                 return NULL;
 291
 292         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 293         if (unlikely(!desc_sw)) {
 294                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 295                 return NULL;
 296         }
 297
 298         memset(desc, 0, sizeof(*desc));
 299
 300         INIT_LIST_HEAD(&desc_sw->tx_list);
 301         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 302         desc_sw->txd.tx_submit = ioat1_tx_submit;
 303         desc_sw->hw = desc;
 304         desc_sw->txd.phys = phys;
 305         set_desc_id(desc_sw, -1);
 306
 307         return desc_sw;
 308 }
 309
 310 static int ioat_initial_desc_count = 256;
 311 module_param(ioat_initial_desc_count, int, 0644);
 312 MODULE_PARM_DESC(ioat_initial_desc_count,
 313                  "ioat1: initial descriptors per channel (default: 256)");
 314 /**
 315  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 316  * @chan: the channel to be filled out
 317  */
 318 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 319 {
 320         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 321         struct ioat_chan_common *chan = &ioat->base;
 322         struct ioat_desc_sw *desc;
 323         u32 chanerr;
 324         int i;
 325         LIST_HEAD(tmp_list);
 326
 327         /* have we already been set up? */
 328         if (!list_empty(&ioat->free_desc))
 329                 return ioat->desccount;
 330
 331         /* Setup register to interrupt and write completion status on error */
 332         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 333
 334         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 335         if (chanerr) {
 336                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 337                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 338         }
 339
 340         /* Allocate descriptors */
 341         for (i = 0; i < ioat_initial_desc_count; i++) {
 342                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 343                 if (!desc) {
 344                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 345                         break;
 346                 }
 347                 set_desc_id(desc, i);
 348                 list_add_tail(&desc->node, &tmp_list);
 349         }
 350         spin_lock_bh(&ioat->desc_lock);
 351         ioat->desccount = i;
 352         list_splice(&tmp_list, &ioat->free_desc);
 353         spin_unlock_bh(&ioat->desc_lock);
 354
 355         /* allocate a completion writeback area */
 356         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 357         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 358                                           GFP_KERNEL, &chan->completion_dma);
 359         memset(chan->completion, 0, sizeof(*chan->completion));
 360         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 361                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 362         writel(((u64) chan->completion_dma) >> 32,
 363                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 364
 365         tasklet_enable(&chan->cleanup_task);
 366         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 367         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 368                 __func__, ioat->desccount);
 369         return ioat->desccount;
 370 }
 371
 372 /**
 373  * ioat1_dma_free_chan_resources - release all the descriptors
 374  * @chan: the channel to be cleaned
 375  */
 376 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 377 {
 378         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 379         struct ioat_chan_common *chan = &ioat->base;
 380         struct ioatdma_device *ioatdma_device = chan->device;
 381         struct ioat_desc_sw *desc, *_desc;
 382         int in_use_descs = 0;
 383
 384         /* Before freeing channel resources first check
 385          * if they have been previously allocated for this channel.
 386          */
 387         if (ioat->desccount == 0)
 388                 return;
 389
 390         tasklet_disable(&chan->cleanup_task);
 391         del_timer_sync(&chan->timer);
 392         ioat1_cleanup(ioat);
 393
 394         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 395          * before removing DMA descriptor resources.
 396          */
 397         writeb(IOAT_CHANCMD_RESET,
 398                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 399         mdelay(100);
 400
 401         spin_lock_bh(&ioat->desc_lock);
 402         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 403                 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
 404                         __func__, desc_id(desc));
 405                 dump_desc_dbg(ioat, desc);
 406                 in_use_descs++;
 407                 list_del(&desc->node);
 408                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 409                               desc->txd.phys);
 410                 kfree(desc);
 411         }
 412         list_for_each_entry_safe(desc, _desc,
 413                                  &ioat->free_desc, node) {
 414                 list_del(&desc->node);
 415                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 416                               desc->txd.phys);
 417                 kfree(desc);
 418         }
 419         spin_unlock_bh(&ioat->desc_lock);
 420
 421         pci_pool_free(ioatdma_device->completion_pool,
 422                       chan->completion,
 423                       chan->completion_dma);
 424
 425         /* one is ok since we left it on there on purpose */
 426         if (in_use_descs > 1)
 427                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 428                         in_use_descs - 1);
 429
 430         chan->last_completion = 0;
 431         chan->completion_dma = 0;
 432         ioat->pending = 0;
 433         ioat->desccount = 0;
 434 }
 435
 436 /**
 437  * ioat1_dma_get_next_descriptor - return the next available descriptor
 438  * @ioat: IOAT DMA channel handle
 439  *
 440  * Gets the next descriptor from the chain, and must be called with the
 441  * channel's desc_lock held.  Allocates more descriptors if the channel
 442  * has run out.
 443  */
 444 static struct ioat_desc_sw *
 445 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 446 {
 447         struct ioat_desc_sw *new;
 448
 449         if (!list_empty(&ioat->free_desc)) {
 450                 new = to_ioat_desc(ioat->free_desc.next);
 451                 list_del(&new->node);
 452         } else {
 453                 /* try to get another desc */
 454                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 455                 if (!new) {
 456                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 457                         return NULL;
 458                 }
 459         }
 460         dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
 461                 __func__, desc_id(new));
 462         prefetch(new->hw);
 463         return new;
 464 }
 465
 466 static struct dma_async_tx_descriptor *
 467 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 468                       dma_addr_t dma_src, size_t len, unsigned long flags)
 469 {
 470         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 471         struct ioat_desc_sw *desc;
 472         size_t copy;
 473         LIST_HEAD(chain);
 474         dma_addr_t src = dma_src;
 475         dma_addr_t dest = dma_dest;
 476         size_t total_len = len;
 477         struct ioat_dma_descriptor *hw = NULL;
 478         int tx_cnt = 0;
 479
 480         spin_lock_bh(&ioat->desc_lock);
 481         desc = ioat1_dma_get_next_descriptor(ioat);
 482         do {
 483                 if (!desc)
 484                         break;
 485
 486                 tx_cnt++;
 487                 copy = min_t(size_t, len, ioat->xfercap);
 488
 489                 hw = desc->hw;
 490                 hw->size = copy;
 491                 hw->ctl = 0;
 492                 hw->src_addr = src;
 493                 hw->dst_addr = dest;
 494
 495                 list_add_tail(&desc->node, &chain);
 496
 497                 len -= copy;
 498                 dest += copy;
 499                 src += copy;
 500                 if (len) {
 501                         struct ioat_desc_sw *next;
 502
 503                         async_tx_ack(&desc->txd);
 504                         next = ioat1_dma_get_next_descriptor(ioat);
 505                         hw->next = next ? next->txd.phys : 0;
 506                         dump_desc_dbg(ioat, desc);
 507                         desc = next;
 508                 } else
 509                         hw->next = 0;
 510         } while (len);
 511
 512         if (!desc) {
 513                 struct ioat_chan_common *chan = &ioat->base;
 514
 515                 dev_err(to_dev(chan),
 516                         "chan%d - get_next_desc failed\n", chan_num(chan));
 517                 list_splice(&chain, &ioat->free_desc);
 518                 spin_unlock_bh(&ioat->desc_lock);
 519                 return NULL;
 520         }
 521         spin_unlock_bh(&ioat->desc_lock);
 522
 523         desc->txd.flags = flags;
 524         desc->len = total_len;
 525         list_splice(&chain, &desc->tx_list);
 526         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 527         hw->ctl_f.compl_write = 1;
 528         hw->tx_cnt = tx_cnt;
 529         dump_desc_dbg(ioat, desc);
 530
 531         return &desc->txd;
 532 }
 533
 534 static void ioat1_cleanup_tasklet(unsigned long data)
 535 {
 536         struct ioat_dma_chan *chan = (void *)data;
 537
 538         ioat1_cleanup(chan);
 539         writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
 540 }
 541
 542 static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
 543                        int direction, enum dma_ctrl_flags flags, bool dst)
 544 {
 545         if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
 546             (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
 547                 pci_unmap_single(pdev, addr, len, direction);
 548         else
 549                 pci_unmap_page(pdev, addr, len, direction);
 550 }
 551
 552
 553 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 554                     size_t len, struct ioat_dma_descriptor *hw)
 555 {
 556         struct pci_dev *pdev = chan->device->pdev;
 557         size_t offset = len - hw->size;
 558
 559         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 560                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 561                            PCI_DMA_FROMDEVICE, flags, 1);
 562
 563         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 564                 ioat_unmap(pdev, hw->src_addr - offset, len,
 565                            PCI_DMA_TODEVICE, flags, 0);
 566 }
 567
 568 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
 569 {
 570         unsigned long phys_complete;
 571         u64 completion;
 572
 573         completion = *chan->completion;
 574         phys_complete = ioat_chansts_to_addr(completion);
 575
 576         dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
 577                 (unsigned long long) phys_complete);
 578
 579         if (is_ioat_halted(completion)) {
 580                 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 581                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 582                         chanerr);
 583
 584                 /* TODO do something to salvage the situation */
 585         }
 586
 587         return phys_complete;
 588 }
 589
 590 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 591                            unsigned long *phys_complete)
 592 {
 593         *phys_complete = ioat_get_current_completion(chan);
 594         if (*phys_complete == chan->last_completion)
 595                 return false;
 596         clear_bit(IOAT_COMPLETION_ACK, &chan->state);
 597         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 598
 599         return true;
 600 }
 601
 602 static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 603 {
 604         struct ioat_chan_common *chan = &ioat->base;
 605         struct list_head *_desc, *n;
 606         struct dma_async_tx_descriptor *tx;
 607
 608         dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
 609                  __func__, phys_complete);
 610         list_for_each_safe(_desc, n, &ioat->used_desc) {
 611                 struct ioat_desc_sw *desc;
 612
 613                 prefetch(n);
 614                 desc = list_entry(_desc, typeof(*desc), node);
 615                 tx = &desc->txd;
 616                 /*
 617                  * Incoming DMA requests may use multiple descriptors,
 618                  * due to exceeding xfercap, perhaps. If so, only the
 619                  * last one will have a cookie, and require unmapping.
 620                  */
 621                 dump_desc_dbg(ioat, desc);
 622                 if (tx->cookie) {
 623                         chan->completed_cookie = tx->cookie;
 624                         tx->cookie = 0;
 625                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 626                         if (tx->callback) {
 627                                 tx->callback(tx->callback_param);
 628                                 tx->callback = NULL;
 629                         }
 630                 }
 631
 632                 if (tx->phys != phys_complete) {
 633                         /*
 634                          * a completed entry, but not the last, so clean
 635                          * up if the client is done with the descriptor
 636                          */
 637                         if (async_tx_test_ack(tx))
 638                                 list_move_tail(&desc->node, &ioat->free_desc);
 639                 } else {
 640                         /*
 641                          * last used desc. Do not remove, so we can
 642                          * append from it.
 643                          */
 644
 645                         /* if nothing else is pending, cancel the
 646                          * completion timeout
 647                          */
 648                         if (n == &ioat->used_desc) {
 649                                 dev_dbg(to_dev(chan),
 650                                         "%s cancel completion timeout\n",
 651                                         __func__);
 652                                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 653                         }
 654
 655                         /* TODO check status bits? */
 656                         break;
 657                 }
 658         }
 659
 660         chan->last_completion = phys_complete;
 661 }
 662
 663 /**
 664  * ioat1_cleanup - cleanup up finished descriptors
 665  * @chan: ioat channel to be cleaned up
 666  *
 667  * To prevent lock contention we defer cleanup when the locks are
 668  * contended with a terminal timeout that forces cleanup and catches
 669  * completion notification errors.
 670  */
 671 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 672 {
 673         struct ioat_chan_common *chan = &ioat->base;
 674         unsigned long phys_complete;
 675
 676         prefetch(chan->completion);
 677
 678         if (!spin_trylock_bh(&chan->cleanup_lock))
 679                 return;
 680
 681         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 682                 spin_unlock_bh(&chan->cleanup_lock);
 683                 return;
 684         }
 685
 686         if (!spin_trylock_bh(&ioat->desc_lock)) {
 687                 spin_unlock_bh(&chan->cleanup_lock);
 688                 return;
 689         }
 690
 691         __cleanup(ioat, phys_complete);
 692
 693         spin_unlock_bh(&ioat->desc_lock);
 694         spin_unlock_bh(&chan->cleanup_lock);
 695 }
 696
 697 static void ioat1_timer_event(unsigned long data)
 698 {
 699         struct ioat_dma_chan *ioat = (void *) data;
 700         struct ioat_chan_common *chan = &ioat->base;
 701
 702         dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
 703
 704         spin_lock_bh(&chan->cleanup_lock);
 705         if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
 706                 struct ioat_desc_sw *desc;
 707
 708                 spin_lock_bh(&ioat->desc_lock);
 709
 710                 /* restart active descriptors */
 711                 desc = to_ioat_desc(ioat->used_desc.prev);
 712                 ioat_set_chainaddr(ioat, desc->txd.phys);
 713                 ioat_start(chan);
 714
 715                 ioat->pending = 0;
 716                 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 717                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 718                 spin_unlock_bh(&ioat->desc_lock);
 719         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 720                 unsigned long phys_complete;
 721
 722                 spin_lock_bh(&ioat->desc_lock);
 723                 /* if we haven't made progress and we have already
 724                  * acknowledged a pending completion once, then be more
 725                  * forceful with a restart
 726                  */
 727                 if (ioat_cleanup_preamble(chan, &phys_complete))
 728                         __cleanup(ioat, phys_complete);
 729                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 730                         ioat1_reset_channel(ioat);
 731                 else {
 732                         u64 status = ioat_chansts(chan);
 733
 734                         /* manually update the last completion address */
 735                         if (ioat_chansts_to_addr(status) != 0)
 736                                 *chan->completion = status;
 737
 738                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 739                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 740                 }
 741                 spin_unlock_bh(&ioat->desc_lock);
 742         }
 743         spin_unlock_bh(&chan->cleanup_lock);
 744 }
 745
 746 static enum dma_status
 747 ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie,
 748                       dma_cookie_t *done, dma_cookie_t *used)
 749 {
 750         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 751
 752         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
 753                 return DMA_SUCCESS;
 754
 755         ioat1_cleanup(ioat);
 756
 757         return ioat_is_complete(c, cookie, done, used);
 758 }
 759
 760 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 761 {
 762         struct ioat_chan_common *chan = &ioat->base;
 763         struct ioat_desc_sw *desc;
 764         struct ioat_dma_descriptor *hw;
 765
 766         spin_lock_bh(&ioat->desc_lock);
 767
 768         desc = ioat1_dma_get_next_descriptor(ioat);
 769
 770         if (!desc) {
 771                 dev_err(to_dev(chan),
 772                         "Unable to start null desc - get next desc failed\n");
 773                 spin_unlock_bh(&ioat->desc_lock);
 774                 return;
 775         }
 776
 777         hw = desc->hw;
 778         hw->ctl = 0;
 779         hw->ctl_f.null = 1;
 780         hw->ctl_f.int_en = 1;
 781         hw->ctl_f.compl_write = 1;
 782         /* set size to non-zero value (channel returns error when size is 0) */
 783         hw->size = NULL_DESC_BUFFER_SIZE;
 784         hw->src_addr = 0;
 785         hw->dst_addr = 0;
 786         async_tx_ack(&desc->txd);
 787         hw->next = 0;
 788         list_add_tail(&desc->node, &ioat->used_desc);
 789         dump_desc_dbg(ioat, desc);
 790
 791         ioat_set_chainaddr(ioat, desc->txd.phys);
 792         ioat_start(chan);
 793         spin_unlock_bh(&ioat->desc_lock);
 794 }
 795
 796 /*
 797  * Perform a IOAT transaction to verify the HW works.
 798  */
 799 #define IOAT_TEST_SIZE 2000
 800
 801 static void __devinit ioat_dma_test_callback(void *dma_async_param)
 802 {
 803         struct completion *cmp = dma_async_param;
 804
 805         complete(cmp);
 806 }
 807
 808 /**
 809  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 810  * @device: device to be tested
 811  */
 812 static int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 813 {
 814         int i;
 815         u8 *src;
 816         u8 *dest;
 817         struct dma_device *dma = &device->common;
 818         struct device *dev = &device->pdev->dev;
 819         struct dma_chan *dma_chan;
 820         struct dma_async_tx_descriptor *tx;
 821         dma_addr_t dma_dest, dma_src;
 822         dma_cookie_t cookie;
 823         int err = 0;
 824         struct completion cmp;
 825         unsigned long tmo;
 826         unsigned long flags;
 827
 828         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 829         if (!src)
 830                 return -ENOMEM;
 831         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 832         if (!dest) {
 833                 kfree(src);
 834                 return -ENOMEM;
 835         }
 836
 837         /* Fill in src buffer */
 838         for (i = 0; i < IOAT_TEST_SIZE; i++)
 839                 src[i] = (u8)i;
 840
 841         /* Start copy, using first DMA channel */
 842         dma_chan = container_of(dma->channels.next, struct dma_chan,
 843                                 device_node);
 844         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 845                 dev_err(dev, "selftest cannot allocate chan resource\n");
 846                 err = -ENODEV;
 847                 goto out;
 848         }
 849
 850         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 851         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 852         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 853                 DMA_PREP_INTERRUPT;
 854         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 855                                                    IOAT_TEST_SIZE, flags);
 856         if (!tx) {
 857                 dev_err(dev, "Self-test prep failed, disabling\n");
 858                 err = -ENODEV;
 859                 goto free_resources;
 860         }
 861
 862         async_tx_ack(tx);
 863         init_completion(&cmp);
 864         tx->callback = ioat_dma_test_callback;
 865         tx->callback_param = &cmp;
 866         cookie = tx->tx_submit(tx);
 867         if (cookie < 0) {
 868                 dev_err(dev, "Self-test setup failed, disabling\n");
 869                 err = -ENODEV;
 870                 goto free_resources;
 871         }
 872         dma->device_issue_pending(dma_chan);
 873
 874         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 875
 876         if (tmo == 0 ||
 877             dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
 878                                         != DMA_SUCCESS) {
 879                 dev_err(dev, "Self-test copy timed out, disabling\n");
 880                 err = -ENODEV;
 881                 goto free_resources;
 882         }
 883         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 884                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 885                 err = -ENODEV;
 886                 goto free_resources;
 887         }
 888
 889 free_resources:
 890         dma->device_free_chan_resources(dma_chan);
 891 out:
 892         kfree(src);
 893         kfree(dest);
 894         return err;
 895 }
 896
 897 static char ioat_interrupt_style[32] = "msix";
 898 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 899                     sizeof(ioat_interrupt_style), 0644);
 900 MODULE_PARM_DESC(ioat_interrupt_style,
 901                  "set ioat interrupt style: msix (default), "
 902                  "msix-single-vector, msi, intx)");
 903
 904 /**
 905  * ioat_dma_setup_interrupts - setup interrupt handler
 906  * @device: ioat device
 907  */
 908 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 909 {
 910         struct ioat_chan_common *chan;
 911         struct pci_dev *pdev = device->pdev;
 912         struct device *dev = &pdev->dev;
 913         struct msix_entry *msix;
 914         int i, j, msixcnt;
 915         int err = -EINVAL;
 916         u8 intrctrl = 0;
 917
 918         if (!strcmp(ioat_interrupt_style, "msix"))
 919                 goto msix;
 920         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 921                 goto msix_single_vector;
 922         if (!strcmp(ioat_interrupt_style, "msi"))
 923                 goto msi;
 924         if (!strcmp(ioat_interrupt_style, "intx"))
 925                 goto intx;
 926         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 927         goto err_no_irq;
 928
 929 msix:
 930         /* The number of MSI-X vectors should equal the number of channels */
 931         msixcnt = device->common.chancnt;
 932         for (i = 0; i < msixcnt; i++)
 933                 device->msix_entries[i].entry = i;
 934
 935         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
 936         if (err < 0)
 937                 goto msi;
 938         if (err > 0)
 939                 goto msix_single_vector;
 940
 941         for (i = 0; i < msixcnt; i++) {
 942                 msix = &device->msix_entries[i];
 943                 chan = ioat_chan_by_index(device, i);
 944                 err = devm_request_irq(dev, msix->vector,
 945                                        ioat_dma_do_interrupt_msix, 0,
 946                                        "ioat-msix", chan);
 947                 if (err) {
 948                         for (j = 0; j < i; j++) {
 949                                 msix = &device->msix_entries[j];
 950                                 chan = ioat_chan_by_index(device, j);
 951                                 devm_free_irq(dev, msix->vector, chan);
 952                         }
 953                         goto msix_single_vector;
 954                 }
 955         }
 956         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
 957         goto done;
 958
 959 msix_single_vector:
 960         msix = &device->msix_entries[0];
 961         msix->entry = 0;
 962         err = pci_enable_msix(pdev, device->msix_entries, 1);
 963         if (err)
 964                 goto msi;
 965
 966         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
 967                                "ioat-msix", device);
 968         if (err) {
 969                 pci_disable_msix(pdev);
 970                 goto msi;
 971         }
 972         goto done;
 973
 974 msi:
 975         err = pci_enable_msi(pdev);
 976         if (err)
 977                 goto intx;
 978
 979         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
 980                                "ioat-msi", device);
 981         if (err) {
 982                 pci_disable_msi(pdev);
 983                 goto intx;
 984         }
 985         goto done;
 986
 987 intx:
 988         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
 989                                IRQF_SHARED, "ioat-intx", device);
 990         if (err)
 991                 goto err_no_irq;
 992
 993 done:
 994         if (device->intr_quirk)
 995                 device->intr_quirk(device);
 996         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
 997         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
 998         return 0;
 999
1000 err_no_irq:
1001         /* Disable all interrupt generation */
1002         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1003         dev_err(dev, "no usable interrupts\n");
1004         return err;
1005 }
1006
1007 static void ioat_disable_interrupts(struct ioatdma_device *device)
1008 {
1009         /* Disable all interrupt generation */
1010         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1011 }
1012
1013 int __devinit ioat_probe(struct ioatdma_device *device)
1014 {
1015         int err = -ENODEV;
1016         struct dma_device *dma = &device->common;
1017         struct pci_dev *pdev = device->pdev;
1018         struct device *dev = &pdev->dev;
1019
1020         /* DMA coherent memory pool for DMA descriptor allocations */
1021         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1022                                            sizeof(struct ioat_dma_descriptor),
1023                                            64, 0);
1024         if (!device->dma_pool) {
1025                 err = -ENOMEM;
1026                 goto err_dma_pool;
1027         }
1028
1029         device->completion_pool = pci_pool_create("completion_pool", pdev,
1030                                                   sizeof(u64), SMP_CACHE_BYTES,
1031                                                   SMP_CACHE_BYTES);
1032
1033         if (!device->completion_pool) {
1034                 err = -ENOMEM;
1035                 goto err_completion_pool;
1036         }
1037
1038         device->enumerate_channels(device);
1039
1040         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1041         dma->dev = &pdev->dev;
1042
1043         dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
1044                 " %d channels, device version 0x%02x, driver version %s\n",
1045                 dma->chancnt, device->version, IOAT_DMA_VERSION);
1046
1047         if (!dma->chancnt) {
1048                 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
1049                         "zero channels detected\n");
1050                 goto err_setup_interrupts;
1051         }
1052
1053         err = ioat_dma_setup_interrupts(device);
1054         if (err)
1055                 goto err_setup_interrupts;
1056
1057         err = ioat_dma_self_test(device);
1058         if (err)
1059                 goto err_self_test;
1060
1061         return 0;
1062
1063 err_self_test:
1064         ioat_disable_interrupts(device);
1065 err_setup_interrupts:
1066         pci_pool_destroy(device->completion_pool);
1067 err_completion_pool:
1068         pci_pool_destroy(device->dma_pool);
1069 err_dma_pool:
1070         return err;
1071 }
1072
1073 int __devinit ioat_register(struct ioatdma_device *device)
1074 {
1075         int err = dma_async_device_register(&device->common);
1076
1077         if (err) {
1078                 ioat_disable_interrupts(device);
1079                 pci_pool_destroy(device->completion_pool);
1080                 pci_pool_destroy(device->dma_pool);
1081         }
1082
1083         return err;
1084 }
1085
1086 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1087 static void ioat1_intr_quirk(struct ioatdma_device *device)
1088 {
1089         struct pci_dev *pdev = device->pdev;
1090         u32 dmactrl;
1091
1092         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1093         if (pdev->msi_enabled)
1094                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1095         else
1096                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1097         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1098 }
1099
1100 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1101 {
1102         struct pci_dev *pdev = device->pdev;
1103         struct dma_device *dma;
1104         int err;
1105
1106         device->intr_quirk = ioat1_intr_quirk;
1107         device->enumerate_channels = ioat1_enumerate_channels;
1108         dma = &device->common;
1109         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1110         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1111         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1112         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1113         dma->device_is_tx_complete = ioat1_dma_is_complete;
1114
1115         err = ioat_probe(device);
1116         if (err)
1117                 return err;
1118         ioat_set_tcp_copy_break(4096);
1119         err = ioat_register(device);
1120         if (err)
1121                 return err;
1122         if (dca)
1123                 device->dca = ioat_dca_init(pdev, device->reg_base);
1124
1125         return err;
1126 }
1127
1128 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1129 {
1130         struct dma_device *dma = &device->common;
1131
1132         ioat_disable_interrupts(device);
1133
1134         dma_async_device_unregister(dma);
1135
1136         pci_pool_destroy(device->dma_pool);
1137         pci_pool_destroy(device->completion_pool);
1138
1139         INIT_LIST_HEAD(&dma->channels);
1140 }