drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/prefetch.h>
  38 #include <linux/i7300_idle.h>
  39 #include "dma.h"
  40 #include "registers.h"
  41 #include "hw.h"
  42
  43 int ioat_pending_level = 4;
  44 module_param(ioat_pending_level, int, 0644);
  45 MODULE_PARM_DESC(ioat_pending_level,
  46                  "high-water mark for pushing ioat descriptors (default: 4)");
  47
  48 /* internal functions */
  49 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  50 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  51
  52 /**
  53  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  54  * @irq: interrupt id
  55  * @data: interrupt data
  56  */
  57 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  58 {
  59         struct ioatdma_device *instance = data;
  60         struct ioat_chan_common *chan;
  61         unsigned long attnstatus;
  62         int bit;
  63         u8 intrctrl;
  64
  65         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  66
  67         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  68                 return IRQ_NONE;
  69
  70         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  71                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  72                 return IRQ_NONE;
  73         }
  74
  75         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  76         for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
  77                 chan = ioat_chan_by_index(instance, bit);
  78                 if (test_bit(IOAT_RUN, &chan->state))
  79                         tasklet_schedule(&chan->cleanup_task);
  80         }
  81
  82         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  83         return IRQ_HANDLED;
  84 }
  85
  86 /**
  87  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  88  * @irq: interrupt id
  89  * @data: interrupt data
  90  */
  91 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  92 {
  93         struct ioat_chan_common *chan = data;
  94
  95         if (test_bit(IOAT_RUN, &chan->state))
  96                 tasklet_schedule(&chan->cleanup_task);
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 /* common channel initialization */
 102 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
 103 {
 104         struct dma_device *dma = &device->common;
 105         struct dma_chan *c = &chan->common;
 106         unsigned long data = (unsigned long) c;
 107
 108         chan->device = device;
 109         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 110         spin_lock_init(&chan->cleanup_lock);
 111         chan->common.device = dma;
 112         list_add_tail(&chan->common.device_node, &dma->channels);
 113         device->idx[idx] = chan;
 114         init_timer(&chan->timer);
 115         chan->timer.function = device->timer_fn;
 116         chan->timer.data = data;
 117         tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
 118 }
 119
 120 /**
 121  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 122  * @device: the device to be enumerated
 123  */
 124 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 125 {
 126         u8 xfercap_scale;
 127         u32 xfercap;
 128         int i;
 129         struct ioat_dma_chan *ioat;
 130         struct device *dev = &device->pdev->dev;
 131         struct dma_device *dma = &device->common;
 132
 133         INIT_LIST_HEAD(&dma->channels);
 134         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 135         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 136         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 137                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 138                          dma->chancnt, ARRAY_SIZE(device->idx));
 139                 dma->chancnt = ARRAY_SIZE(device->idx);
 140         }
 141         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 142         xfercap_scale &= 0x1f; /* bits [4:0] valid */
 143         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 144         dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
 145
 146 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 147         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 148                 dma->chancnt--;
 149 #endif
 150         for (i = 0; i < dma->chancnt; i++) {
 151                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 152                 if (!ioat)
 153                         break;
 154
 155                 ioat_init_channel(device, &ioat->base, i);
 156                 ioat->xfercap = xfercap;
 157                 spin_lock_init(&ioat->desc_lock);
 158                 INIT_LIST_HEAD(&ioat->free_desc);
 159                 INIT_LIST_HEAD(&ioat->used_desc);
 160         }
 161         dma->chancnt = i;
 162         return i;
 163 }
 164
 165 /**
 166  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 167  *                                 descriptors to hw
 168  * @chan: DMA channel handle
 169  */
 170 static inline void
 171 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 172 {
 173         void __iomem *reg_base = ioat->base.reg_base;
 174
 175         dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
 176                 __func__, ioat->pending);
 177         ioat->pending = 0;
 178         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 179 }
 180
 181 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 182 {
 183         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 184
 185         if (ioat->pending > 0) {
 186                 spin_lock_bh(&ioat->desc_lock);
 187                 __ioat1_dma_memcpy_issue_pending(ioat);
 188                 spin_unlock_bh(&ioat->desc_lock);
 189         }
 190 }
 191
 192 /**
 193  * ioat1_reset_channel - restart a channel
 194  * @ioat: IOAT DMA channel handle
 195  */
 196 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 197 {
 198         struct ioat_chan_common *chan = &ioat->base;
 199         void __iomem *reg_base = chan->reg_base;
 200         u32 chansts, chanerr;
 201
 202         dev_warn(to_dev(chan), "reset\n");
 203         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 204         chansts = *chan->completion & IOAT_CHANSTS_STATUS;
 205         if (chanerr) {
 206                 dev_err(to_dev(chan),
 207                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 208                         chan_num(chan), chansts, chanerr);
 209                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 210         }
 211
 212         /*
 213          * whack it upside the head with a reset
 214          * and wait for things to settle out.
 215          * force the pending count to a really big negative
 216          * to make sure no one forces an issue_pending
 217          * while we're waiting.
 218          */
 219
 220         ioat->pending = INT_MIN;
 221         writeb(IOAT_CHANCMD_RESET,
 222                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 223         set_bit(IOAT_RESET_PENDING, &chan->state);
 224         mod_timer(&chan->timer, jiffies + RESET_DELAY);
 225 }
 226
 227 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 228 {
 229         struct dma_chan *c = tx->chan;
 230         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 231         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 232         struct ioat_chan_common *chan = &ioat->base;
 233         struct ioat_desc_sw *first;
 234         struct ioat_desc_sw *chain_tail;
 235         dma_cookie_t cookie;
 236
 237         spin_lock_bh(&ioat->desc_lock);
 238         /* cookie incr and addition to used_list must be atomic */
 239         cookie = c->cookie;
 240         cookie++;
 241         if (cookie < 0)
 242                 cookie = 1;
 243         c->cookie = cookie;
 244         tx->cookie = cookie;
 245         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 246
 247         /* write address into NextDescriptor field of last desc in chain */
 248         first = to_ioat_desc(desc->tx_list.next);
 249         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 250         /* make descriptor updates globally visible before chaining */
 251         wmb();
 252         chain_tail->hw->next = first->txd.phys;
 253         list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
 254         dump_desc_dbg(ioat, chain_tail);
 255         dump_desc_dbg(ioat, first);
 256
 257         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 258                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 259
 260         ioat->active += desc->hw->tx_cnt;
 261         ioat->pending += desc->hw->tx_cnt;
 262         if (ioat->pending >= ioat_pending_level)
 263                 __ioat1_dma_memcpy_issue_pending(ioat);
 264         spin_unlock_bh(&ioat->desc_lock);
 265
 266         return cookie;
 267 }
 268
 269 /**
 270  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 271  * @ioat: the channel supplying the memory pool for the descriptors
 272  * @flags: allocation flags
 273  */
 274 static struct ioat_desc_sw *
 275 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 276 {
 277         struct ioat_dma_descriptor *desc;
 278         struct ioat_desc_sw *desc_sw;
 279         struct ioatdma_device *ioatdma_device;
 280         dma_addr_t phys;
 281
 282         ioatdma_device = ioat->base.device;
 283         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 284         if (unlikely(!desc))
 285                 return NULL;
 286
 287         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 288         if (unlikely(!desc_sw)) {
 289                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 290                 return NULL;
 291         }
 292
 293         memset(desc, 0, sizeof(*desc));
 294
 295         INIT_LIST_HEAD(&desc_sw->tx_list);
 296         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 297         desc_sw->txd.tx_submit = ioat1_tx_submit;
 298         desc_sw->hw = desc;
 299         desc_sw->txd.phys = phys;
 300         set_desc_id(desc_sw, -1);
 301
 302         return desc_sw;
 303 }
 304
 305 static int ioat_initial_desc_count = 256;
 306 module_param(ioat_initial_desc_count, int, 0644);
 307 MODULE_PARM_DESC(ioat_initial_desc_count,
 308                  "ioat1: initial descriptors per channel (default: 256)");
 309 /**
 310  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 311  * @chan: the channel to be filled out
 312  */
 313 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 314 {
 315         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 316         struct ioat_chan_common *chan = &ioat->base;
 317         struct ioat_desc_sw *desc;
 318         u32 chanerr;
 319         int i;
 320         LIST_HEAD(tmp_list);
 321
 322         /* have we already been set up? */
 323         if (!list_empty(&ioat->free_desc))
 324                 return ioat->desccount;
 325
 326         /* Setup register to interrupt and write completion status on error */
 327         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 328
 329         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 330         if (chanerr) {
 331                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 332                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 333         }
 334
 335         /* Allocate descriptors */
 336         for (i = 0; i < ioat_initial_desc_count; i++) {
 337                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 338                 if (!desc) {
 339                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 340                         break;
 341                 }
 342                 set_desc_id(desc, i);
 343                 list_add_tail(&desc->node, &tmp_list);
 344         }
 345         spin_lock_bh(&ioat->desc_lock);
 346         ioat->desccount = i;
 347         list_splice(&tmp_list, &ioat->free_desc);
 348         spin_unlock_bh(&ioat->desc_lock);
 349
 350         /* allocate a completion writeback area */
 351         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 352         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 353                                           GFP_KERNEL, &chan->completion_dma);
 354         memset(chan->completion, 0, sizeof(*chan->completion));
 355         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 356                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 357         writel(((u64) chan->completion_dma) >> 32,
 358                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 359
 360         set_bit(IOAT_RUN, &chan->state);
 361         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 362         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 363                 __func__, ioat->desccount);
 364         return ioat->desccount;
 365 }
 366
 367 void ioat_stop(struct ioat_chan_common *chan)
 368 {
 369         struct ioatdma_device *device = chan->device;
 370         struct pci_dev *pdev = device->pdev;
 371         int chan_id = chan_num(chan);
 372
 373         /* 1/ stop irq from firing tasklets
 374          * 2/ stop the tasklet from re-arming irqs
 375          */
 376         clear_bit(IOAT_RUN, &chan->state);
 377
 378         /* flush inflight interrupts */
 379 #ifdef CONFIG_PCI_MSI
 380         if (pdev->msix_enabled) {
 381                 struct msix_entry *msix = &device->msix_entries[chan_id];
 382                 synchronize_irq(msix->vector);
 383         } else
 384 #endif
 385                 synchronize_irq(pdev->irq);
 386
 387         /* flush inflight timers */
 388         del_timer_sync(&chan->timer);
 389
 390         /* flush inflight tasklet runs */
 391         tasklet_kill(&chan->cleanup_task);
 392
 393         /* final cleanup now that everything is quiesced and can't re-arm */
 394         device->cleanup_fn((unsigned long) &chan->common);
 395 }
 396
 397 /**
 398  * ioat1_dma_free_chan_resources - release all the descriptors
 399  * @chan: the channel to be cleaned
 400  */
 401 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 402 {
 403         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 404         struct ioat_chan_common *chan = &ioat->base;
 405         struct ioatdma_device *ioatdma_device = chan->device;
 406         struct ioat_desc_sw *desc, *_desc;
 407         int in_use_descs = 0;
 408
 409         /* Before freeing channel resources first check
 410          * if they have been previously allocated for this channel.
 411          */
 412         if (ioat->desccount == 0)
 413                 return;
 414
 415         ioat_stop(chan);
 416
 417         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 418          * before removing DMA descriptor resources.
 419          */
 420         writeb(IOAT_CHANCMD_RESET,
 421                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 422         mdelay(100);
 423
 424         spin_lock_bh(&ioat->desc_lock);
 425         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 426                 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
 427                         __func__, desc_id(desc));
 428                 dump_desc_dbg(ioat, desc);
 429                 in_use_descs++;
 430                 list_del(&desc->node);
 431                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 432                               desc->txd.phys);
 433                 kfree(desc);
 434         }
 435         list_for_each_entry_safe(desc, _desc,
 436                                  &ioat->free_desc, node) {
 437                 list_del(&desc->node);
 438                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 439                               desc->txd.phys);
 440                 kfree(desc);
 441         }
 442         spin_unlock_bh(&ioat->desc_lock);
 443
 444         pci_pool_free(ioatdma_device->completion_pool,
 445                       chan->completion,
 446                       chan->completion_dma);
 447
 448         /* one is ok since we left it on there on purpose */
 449         if (in_use_descs > 1)
 450                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 451                         in_use_descs - 1);
 452
 453         chan->last_completion = 0;
 454         chan->completion_dma = 0;
 455         ioat->pending = 0;
 456         ioat->desccount = 0;
 457 }
 458
 459 /**
 460  * ioat1_dma_get_next_descriptor - return the next available descriptor
 461  * @ioat: IOAT DMA channel handle
 462  *
 463  * Gets the next descriptor from the chain, and must be called with the
 464  * channel's desc_lock held.  Allocates more descriptors if the channel
 465  * has run out.
 466  */
 467 static struct ioat_desc_sw *
 468 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 469 {
 470         struct ioat_desc_sw *new;
 471
 472         if (!list_empty(&ioat->free_desc)) {
 473                 new = to_ioat_desc(ioat->free_desc.next);
 474                 list_del(&new->node);
 475         } else {
 476                 /* try to get another desc */
 477                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 478                 if (!new) {
 479                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 480                         return NULL;
 481                 }
 482         }
 483         dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
 484                 __func__, desc_id(new));
 485         prefetch(new->hw);
 486         return new;
 487 }
 488
 489 static struct dma_async_tx_descriptor *
 490 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 491                       dma_addr_t dma_src, size_t len, unsigned long flags)
 492 {
 493         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 494         struct ioat_desc_sw *desc;
 495         size_t copy;
 496         LIST_HEAD(chain);
 497         dma_addr_t src = dma_src;
 498         dma_addr_t dest = dma_dest;
 499         size_t total_len = len;
 500         struct ioat_dma_descriptor *hw = NULL;
 501         int tx_cnt = 0;
 502
 503         spin_lock_bh(&ioat->desc_lock);
 504         desc = ioat1_dma_get_next_descriptor(ioat);
 505         do {
 506                 if (!desc)
 507                         break;
 508
 509                 tx_cnt++;
 510                 copy = min_t(size_t, len, ioat->xfercap);
 511
 512                 hw = desc->hw;
 513                 hw->size = copy;
 514                 hw->ctl = 0;
 515                 hw->src_addr = src;
 516                 hw->dst_addr = dest;
 517
 518                 list_add_tail(&desc->node, &chain);
 519
 520                 len -= copy;
 521                 dest += copy;
 522                 src += copy;
 523                 if (len) {
 524                         struct ioat_desc_sw *next;
 525
 526                         async_tx_ack(&desc->txd);
 527                         next = ioat1_dma_get_next_descriptor(ioat);
 528                         hw->next = next ? next->txd.phys : 0;
 529                         dump_desc_dbg(ioat, desc);
 530                         desc = next;
 531                 } else
 532                         hw->next = 0;
 533         } while (len);
 534
 535         if (!desc) {
 536                 struct ioat_chan_common *chan = &ioat->base;
 537
 538                 dev_err(to_dev(chan),
 539                         "chan%d - get_next_desc failed\n", chan_num(chan));
 540                 list_splice(&chain, &ioat->free_desc);
 541                 spin_unlock_bh(&ioat->desc_lock);
 542                 return NULL;
 543         }
 544         spin_unlock_bh(&ioat->desc_lock);
 545
 546         desc->txd.flags = flags;
 547         desc->len = total_len;
 548         list_splice(&chain, &desc->tx_list);
 549         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 550         hw->ctl_f.compl_write = 1;
 551         hw->tx_cnt = tx_cnt;
 552         dump_desc_dbg(ioat, desc);
 553
 554         return &desc->txd;
 555 }
 556
 557 static void ioat1_cleanup_event(unsigned long data)
 558 {
 559         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 560         struct ioat_chan_common *chan = &ioat->base;
 561
 562         ioat1_cleanup(ioat);
 563         if (!test_bit(IOAT_RUN, &chan->state))
 564                 return;
 565         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 566 }
 567
 568 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 569                     size_t len, struct ioat_dma_descriptor *hw)
 570 {
 571         struct pci_dev *pdev = chan->device->pdev;
 572         size_t offset = len - hw->size;
 573
 574         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 575                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 576                            PCI_DMA_FROMDEVICE, flags, 1);
 577
 578         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 579                 ioat_unmap(pdev, hw->src_addr - offset, len,
 580                            PCI_DMA_TODEVICE, flags, 0);
 581 }
 582
 583 dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
 584 {
 585         dma_addr_t phys_complete;
 586         u64 completion;
 587
 588         completion = *chan->completion;
 589         phys_complete = ioat_chansts_to_addr(completion);
 590
 591         dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
 592                 (unsigned long long) phys_complete);
 593
 594         if (is_ioat_halted(completion)) {
 595                 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 596                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 597                         chanerr);
 598
 599                 /* TODO do something to salvage the situation */
 600         }
 601
 602         return phys_complete;
 603 }
 604
 605 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 606                            dma_addr_t *phys_complete)
 607 {
 608         *phys_complete = ioat_get_current_completion(chan);
 609         if (*phys_complete == chan->last_completion)
 610                 return false;
 611         clear_bit(IOAT_COMPLETION_ACK, &chan->state);
 612         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 613
 614         return true;
 615 }
 616
 617 static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
 618 {
 619         struct ioat_chan_common *chan = &ioat->base;
 620         struct list_head *_desc, *n;
 621         struct dma_async_tx_descriptor *tx;
 622
 623         dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n",
 624                  __func__, (unsigned long long) phys_complete);
 625         list_for_each_safe(_desc, n, &ioat->used_desc) {
 626                 struct ioat_desc_sw *desc;
 627
 628                 prefetch(n);
 629                 desc = list_entry(_desc, typeof(*desc), node);
 630                 tx = &desc->txd;
 631                 /*
 632                  * Incoming DMA requests may use multiple descriptors,
 633                  * due to exceeding xfercap, perhaps. If so, only the
 634                  * last one will have a cookie, and require unmapping.
 635                  */
 636                 dump_desc_dbg(ioat, desc);
 637                 if (tx->cookie) {
 638                         chan->completed_cookie = tx->cookie;
 639                         tx->cookie = 0;
 640                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 641                         ioat->active -= desc->hw->tx_cnt;
 642                         if (tx->callback) {
 643                                 tx->callback(tx->callback_param);
 644                                 tx->callback = NULL;
 645                         }
 646                 }
 647
 648                 if (tx->phys != phys_complete) {
 649                         /*
 650                          * a completed entry, but not the last, so clean
 651                          * up if the client is done with the descriptor
 652                          */
 653                         if (async_tx_test_ack(tx))
 654                                 list_move_tail(&desc->node, &ioat->free_desc);
 655                 } else {
 656                         /*
 657                          * last used desc. Do not remove, so we can
 658                          * append from it.
 659                          */
 660
 661                         /* if nothing else is pending, cancel the
 662                          * completion timeout
 663                          */
 664                         if (n == &ioat->used_desc) {
 665                                 dev_dbg(to_dev(chan),
 666                                         "%s cancel completion timeout\n",
 667                                         __func__);
 668                                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 669                         }
 670
 671                         /* TODO check status bits? */
 672                         break;
 673                 }
 674         }
 675
 676         chan->last_completion = phys_complete;
 677 }
 678
 679 /**
 680  * ioat1_cleanup - cleanup up finished descriptors
 681  * @chan: ioat channel to be cleaned up
 682  *
 683  * To prevent lock contention we defer cleanup when the locks are
 684  * contended with a terminal timeout that forces cleanup and catches
 685  * completion notification errors.
 686  */
 687 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 688 {
 689         struct ioat_chan_common *chan = &ioat->base;
 690         dma_addr_t phys_complete;
 691
 692         prefetch(chan->completion);
 693
 694         if (!spin_trylock_bh(&chan->cleanup_lock))
 695                 return;
 696
 697         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 698                 spin_unlock_bh(&chan->cleanup_lock);
 699                 return;
 700         }
 701
 702         if (!spin_trylock_bh(&ioat->desc_lock)) {
 703                 spin_unlock_bh(&chan->cleanup_lock);
 704                 return;
 705         }
 706
 707         __cleanup(ioat, phys_complete);
 708
 709         spin_unlock_bh(&ioat->desc_lock);
 710         spin_unlock_bh(&chan->cleanup_lock);
 711 }
 712
 713 static void ioat1_timer_event(unsigned long data)
 714 {
 715         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 716         struct ioat_chan_common *chan = &ioat->base;
 717
 718         dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
 719
 720         spin_lock_bh(&chan->cleanup_lock);
 721         if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
 722                 struct ioat_desc_sw *desc;
 723
 724                 spin_lock_bh(&ioat->desc_lock);
 725
 726                 /* restart active descriptors */
 727                 desc = to_ioat_desc(ioat->used_desc.prev);
 728                 ioat_set_chainaddr(ioat, desc->txd.phys);
 729                 ioat_start(chan);
 730
 731                 ioat->pending = 0;
 732                 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 733                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 734                 spin_unlock_bh(&ioat->desc_lock);
 735         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 736                 dma_addr_t phys_complete;
 737
 738                 spin_lock_bh(&ioat->desc_lock);
 739                 /* if we haven't made progress and we have already
 740                  * acknowledged a pending completion once, then be more
 741                  * forceful with a restart
 742                  */
 743                 if (ioat_cleanup_preamble(chan, &phys_complete))
 744                         __cleanup(ioat, phys_complete);
 745                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 746                         ioat1_reset_channel(ioat);
 747                 else {
 748                         u64 status = ioat_chansts(chan);
 749
 750                         /* manually update the last completion address */
 751                         if (ioat_chansts_to_addr(status) != 0)
 752                                 *chan->completion = status;
 753
 754                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 755                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 756                 }
 757                 spin_unlock_bh(&ioat->desc_lock);
 758         }
 759         spin_unlock_bh(&chan->cleanup_lock);
 760 }
 761
 762 enum dma_status
 763 ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 764                    struct dma_tx_state *txstate)
 765 {
 766         struct ioat_chan_common *chan = to_chan_common(c);
 767         struct ioatdma_device *device = chan->device;
 768
 769         if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
 770                 return DMA_SUCCESS;
 771
 772         device->cleanup_fn((unsigned long) c);
 773
 774         return ioat_tx_status(c, cookie, txstate);
 775 }
 776
 777 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 778 {
 779         struct ioat_chan_common *chan = &ioat->base;
 780         struct ioat_desc_sw *desc;
 781         struct ioat_dma_descriptor *hw;
 782
 783         spin_lock_bh(&ioat->desc_lock);
 784
 785         desc = ioat1_dma_get_next_descriptor(ioat);
 786
 787         if (!desc) {
 788                 dev_err(to_dev(chan),
 789                         "Unable to start null desc - get next desc failed\n");
 790                 spin_unlock_bh(&ioat->desc_lock);
 791                 return;
 792         }
 793
 794         hw = desc->hw;
 795         hw->ctl = 0;
 796         hw->ctl_f.null = 1;
 797         hw->ctl_f.int_en = 1;
 798         hw->ctl_f.compl_write = 1;
 799         /* set size to non-zero value (channel returns error when size is 0) */
 800         hw->size = NULL_DESC_BUFFER_SIZE;
 801         hw->src_addr = 0;
 802         hw->dst_addr = 0;
 803         async_tx_ack(&desc->txd);
 804         hw->next = 0;
 805         list_add_tail(&desc->node, &ioat->used_desc);
 806         dump_desc_dbg(ioat, desc);
 807
 808         ioat_set_chainaddr(ioat, desc->txd.phys);
 809         ioat_start(chan);
 810         spin_unlock_bh(&ioat->desc_lock);
 811 }
 812
 813 /*
 814  * Perform a IOAT transaction to verify the HW works.
 815  */
 816 #define IOAT_TEST_SIZE 2000
 817
 818 static void __devinit ioat_dma_test_callback(void *dma_async_param)
 819 {
 820         struct completion *cmp = dma_async_param;
 821
 822         complete(cmp);
 823 }
 824
 825 /**
 826  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 827  * @device: device to be tested
 828  */
 829 int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 830 {
 831         int i;
 832         u8 *src;
 833         u8 *dest;
 834         struct dma_device *dma = &device->common;
 835         struct device *dev = &device->pdev->dev;
 836         struct dma_chan *dma_chan;
 837         struct dma_async_tx_descriptor *tx;
 838         dma_addr_t dma_dest, dma_src;
 839         dma_cookie_t cookie;
 840         int err = 0;
 841         struct completion cmp;
 842         unsigned long tmo;
 843         unsigned long flags;
 844
 845         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 846         if (!src)
 847                 return -ENOMEM;
 848         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 849         if (!dest) {
 850                 kfree(src);
 851                 return -ENOMEM;
 852         }
 853
 854         /* Fill in src buffer */
 855         for (i = 0; i < IOAT_TEST_SIZE; i++)
 856                 src[i] = (u8)i;
 857
 858         /* Start copy, using first DMA channel */
 859         dma_chan = container_of(dma->channels.next, struct dma_chan,
 860                                 device_node);
 861         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 862                 dev_err(dev, "selftest cannot allocate chan resource\n");
 863                 err = -ENODEV;
 864                 goto out;
 865         }
 866
 867         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 868         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 869         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 870                 DMA_PREP_INTERRUPT;
 871         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 872                                                    IOAT_TEST_SIZE, flags);
 873         if (!tx) {
 874                 dev_err(dev, "Self-test prep failed, disabling\n");
 875                 err = -ENODEV;
 876                 goto free_resources;
 877         }
 878
 879         async_tx_ack(tx);
 880         init_completion(&cmp);
 881         tx->callback = ioat_dma_test_callback;
 882         tx->callback_param = &cmp;
 883         cookie = tx->tx_submit(tx);
 884         if (cookie < 0) {
 885                 dev_err(dev, "Self-test setup failed, disabling\n");
 886                 err = -ENODEV;
 887                 goto free_resources;
 888         }
 889         dma->device_issue_pending(dma_chan);
 890
 891         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 892
 893         if (tmo == 0 ||
 894             dma->device_tx_status(dma_chan, cookie, NULL)
 895                                         != DMA_SUCCESS) {
 896                 dev_err(dev, "Self-test copy timed out, disabling\n");
 897                 err = -ENODEV;
 898                 goto free_resources;
 899         }
 900         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 901                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 902                 err = -ENODEV;
 903                 goto free_resources;
 904         }
 905
 906 free_resources:
 907         dma->device_free_chan_resources(dma_chan);
 908 out:
 909         kfree(src);
 910         kfree(dest);
 911         return err;
 912 }
 913
 914 static char ioat_interrupt_style[32] = "msix";
 915 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 916                     sizeof(ioat_interrupt_style), 0644);
 917 MODULE_PARM_DESC(ioat_interrupt_style,
 918                  "set ioat interrupt style: msix (default), "
 919                  "msix-single-vector, msi, intx)");
 920
 921 /**
 922  * ioat_dma_setup_interrupts - setup interrupt handler
 923  * @device: ioat device
 924  */
 925 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 926 {
 927         struct ioat_chan_common *chan;
 928         struct pci_dev *pdev = device->pdev;
 929         struct device *dev = &pdev->dev;
 930         struct msix_entry *msix;
 931         int i, j, msixcnt;
 932         int err = -EINVAL;
 933         u8 intrctrl = 0;
 934
 935         if (!strcmp(ioat_interrupt_style, "msix"))
 936                 goto msix;
 937         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 938                 goto msix_single_vector;
 939         if (!strcmp(ioat_interrupt_style, "msi"))
 940                 goto msi;
 941         if (!strcmp(ioat_interrupt_style, "intx"))
 942                 goto intx;
 943         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 944         goto err_no_irq;
 945
 946 msix:
 947         /* The number of MSI-X vectors should equal the number of channels */
 948         msixcnt = device->common.chancnt;
 949         for (i = 0; i < msixcnt; i++)
 950                 device->msix_entries[i].entry = i;
 951
 952         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
 953         if (err < 0)
 954                 goto msi;
 955         if (err > 0)
 956                 goto msix_single_vector;
 957
 958         for (i = 0; i < msixcnt; i++) {
 959                 msix = &device->msix_entries[i];
 960                 chan = ioat_chan_by_index(device, i);
 961                 err = devm_request_irq(dev, msix->vector,
 962                                        ioat_dma_do_interrupt_msix, 0,
 963                                        "ioat-msix", chan);
 964                 if (err) {
 965                         for (j = 0; j < i; j++) {
 966                                 msix = &device->msix_entries[j];
 967                                 chan = ioat_chan_by_index(device, j);
 968                                 devm_free_irq(dev, msix->vector, chan);
 969                         }
 970                         goto msix_single_vector;
 971                 }
 972         }
 973         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
 974         goto done;
 975
 976 msix_single_vector:
 977         msix = &device->msix_entries[0];
 978         msix->entry = 0;
 979         err = pci_enable_msix(pdev, device->msix_entries, 1);
 980         if (err)
 981                 goto msi;
 982
 983         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
 984                                "ioat-msix", device);
 985         if (err) {
 986                 pci_disable_msix(pdev);
 987                 goto msi;
 988         }
 989         goto done;
 990
 991 msi:
 992         err = pci_enable_msi(pdev);
 993         if (err)
 994                 goto intx;
 995
 996         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
 997                                "ioat-msi", device);
 998         if (err) {
 999                 pci_disable_msi(pdev);
1000                 goto intx;
1001         }
1002         goto done;
1003
1004 intx:
1005         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
1006                                IRQF_SHARED, "ioat-intx", device);
1007         if (err)
1008                 goto err_no_irq;
1009
1010 done:
1011         if (device->intr_quirk)
1012                 device->intr_quirk(device);
1013         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1014         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1015         return 0;
1016
1017 err_no_irq:
1018         /* Disable all interrupt generation */
1019         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1020         dev_err(dev, "no usable interrupts\n");
1021         return err;
1022 }
1023
1024 static void ioat_disable_interrupts(struct ioatdma_device *device)
1025 {
1026         /* Disable all interrupt generation */
1027         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1028 }
1029
1030 int __devinit ioat_probe(struct ioatdma_device *device)
1031 {
1032         int err = -ENODEV;
1033         struct dma_device *dma = &device->common;
1034         struct pci_dev *pdev = device->pdev;
1035         struct device *dev = &pdev->dev;
1036
1037         /* DMA coherent memory pool for DMA descriptor allocations */
1038         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1039                                            sizeof(struct ioat_dma_descriptor),
1040                                            64, 0);
1041         if (!device->dma_pool) {
1042                 err = -ENOMEM;
1043                 goto err_dma_pool;
1044         }
1045
1046         device->completion_pool = pci_pool_create("completion_pool", pdev,
1047                                                   sizeof(u64), SMP_CACHE_BYTES,
1048                                                   SMP_CACHE_BYTES);
1049
1050         if (!device->completion_pool) {
1051                 err = -ENOMEM;
1052                 goto err_completion_pool;
1053         }
1054
1055         device->enumerate_channels(device);
1056
1057         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1058         dma->dev = &pdev->dev;
1059
1060         if (!dma->chancnt) {
1061                 dev_err(dev, "channel enumeration error\n");
1062                 goto err_setup_interrupts;
1063         }
1064
1065         err = ioat_dma_setup_interrupts(device);
1066         if (err)
1067                 goto err_setup_interrupts;
1068
1069         err = device->self_test(device);
1070         if (err)
1071                 goto err_self_test;
1072
1073         return 0;
1074
1075 err_self_test:
1076         ioat_disable_interrupts(device);
1077 err_setup_interrupts:
1078         pci_pool_destroy(device->completion_pool);
1079 err_completion_pool:
1080         pci_pool_destroy(device->dma_pool);
1081 err_dma_pool:
1082         return err;
1083 }
1084
1085 int __devinit ioat_register(struct ioatdma_device *device)
1086 {
1087         int err = dma_async_device_register(&device->common);
1088
1089         if (err) {
1090                 ioat_disable_interrupts(device);
1091                 pci_pool_destroy(device->completion_pool);
1092                 pci_pool_destroy(device->dma_pool);
1093         }
1094
1095         return err;
1096 }
1097
1098 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1099 static void ioat1_intr_quirk(struct ioatdma_device *device)
1100 {
1101         struct pci_dev *pdev = device->pdev;
1102         u32 dmactrl;
1103
1104         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1105         if (pdev->msi_enabled)
1106                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1107         else
1108                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1109         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1110 }
1111
1112 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1113 {
1114         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1115
1116         return sprintf(page, "%d\n", ioat->desccount);
1117 }
1118 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1119
1120 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1121 {
1122         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1123
1124         return sprintf(page, "%d\n", ioat->active);
1125 }
1126 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1127
1128 static ssize_t cap_show(struct dma_chan *c, char *page)
1129 {
1130         struct dma_device *dma = c->device;
1131
1132         return sprintf(page, "copy%s%s%s%s%s%s\n",
1133                        dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1134                        dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1135                        dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1136                        dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1137                        dma_has_cap(DMA_MEMSET, dma->cap_mask)  ? " fill" : "",
1138                        dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1139
1140 }
1141 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1142
1143 static ssize_t version_show(struct dma_chan *c, char *page)
1144 {
1145         struct dma_device *dma = c->device;
1146         struct ioatdma_device *device = to_ioatdma_device(dma);
1147
1148         return sprintf(page, "%d.%d\n",
1149                        device->version >> 4, device->version & 0xf);
1150 }
1151 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1152
1153 static struct attribute *ioat1_attrs[] = {
1154         &ring_size_attr.attr,
1155         &ring_active_attr.attr,
1156         &ioat_cap_attr.attr,
1157         &ioat_version_attr.attr,
1158         NULL,
1159 };
1160
1161 static ssize_t
1162 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1163 {
1164         struct ioat_sysfs_entry *entry;
1165         struct ioat_chan_common *chan;
1166
1167         entry = container_of(attr, struct ioat_sysfs_entry, attr);
1168         chan = container_of(kobj, struct ioat_chan_common, kobj);
1169
1170         if (!entry->show)
1171                 return -EIO;
1172         return entry->show(&chan->common, page);
1173 }
1174
1175 const struct sysfs_ops ioat_sysfs_ops = {
1176         .show   = ioat_attr_show,
1177 };
1178
1179 static struct kobj_type ioat1_ktype = {
1180         .sysfs_ops = &ioat_sysfs_ops,
1181         .default_attrs = ioat1_attrs,
1182 };
1183
1184 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1185 {
1186         struct dma_device *dma = &device->common;
1187         struct dma_chan *c;
1188
1189         list_for_each_entry(c, &dma->channels, device_node) {
1190                 struct ioat_chan_common *chan = to_chan_common(c);
1191                 struct kobject *parent = &c->dev->device.kobj;
1192                 int err;
1193
1194                 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1195                 if (err) {
1196                         dev_warn(to_dev(chan),
1197                                  "sysfs init error (%d), continuing...\n", err);
1198                         kobject_put(&chan->kobj);
1199                         set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1200                 }
1201         }
1202 }
1203
1204 void ioat_kobject_del(struct ioatdma_device *device)
1205 {
1206         struct dma_device *dma = &device->common;
1207         struct dma_chan *c;
1208
1209         list_for_each_entry(c, &dma->channels, device_node) {
1210                 struct ioat_chan_common *chan = to_chan_common(c);
1211
1212                 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1213                         kobject_del(&chan->kobj);
1214                         kobject_put(&chan->kobj);
1215                 }
1216         }
1217 }
1218
1219 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1220 {
1221         struct pci_dev *pdev = device->pdev;
1222         struct dma_device *dma;
1223         int err;
1224
1225         device->intr_quirk = ioat1_intr_quirk;
1226         device->enumerate_channels = ioat1_enumerate_channels;
1227         device->self_test = ioat_dma_self_test;
1228         device->timer_fn = ioat1_timer_event;
1229         device->cleanup_fn = ioat1_cleanup_event;
1230         dma = &device->common;
1231         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1232         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1233         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1234         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1235         dma->device_tx_status = ioat_dma_tx_status;
1236
1237         err = ioat_probe(device);
1238         if (err)
1239                 return err;
1240         ioat_set_tcp_copy_break(4096);
1241         err = ioat_register(device);
1242         if (err)
1243                 return err;
1244         ioat_kobject_add(device, &ioat1_ktype);
1245
1246         if (dca)
1247                 device->dca = ioat_dca_init(pdev, device->reg_base);
1248
1249         return err;
1250 }
1251
1252 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1253 {
1254         struct dma_device *dma = &device->common;
1255
1256         ioat_disable_interrupts(device);
1257
1258         ioat_kobject_del(device);
1259
1260         dma_async_device_unregister(dma);
1261
1262         pci_pool_destroy(device->dma_pool);
1263         pci_pool_destroy(device->completion_pool);
1264
1265         INIT_LIST_HEAD(&dma->channels);
1266 }