2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
202 access &= ACC_WRITE_MASK | ACC_USER_MASK;
204 trace_mark_mmio_spte(sptep, gfn, access);
205 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
208 static bool is_mmio_spte(u64 spte)
210 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
213 static gfn_t get_mmio_spte_gfn(u64 spte)
215 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
218 static unsigned get_mmio_spte_access(u64 spte)
220 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
225 if (unlikely(is_noslot_pfn(pfn))) {
226 mark_mmio_spte(sptep, gfn, access);
233 static inline u64 rsvd_bits(int s, int e)
235 return ((1ULL << (e - s + 1)) - 1) << s;
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239 u64 dirty_mask, u64 nx_mask, u64 x_mask)
241 shadow_user_mask = user_mask;
242 shadow_accessed_mask = accessed_mask;
243 shadow_dirty_mask = dirty_mask;
244 shadow_nx_mask = nx_mask;
245 shadow_x_mask = x_mask;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu *vcpu)
256 return vcpu->arch.efer & EFER_NX;
259 static int is_shadow_present_pte(u64 pte)
261 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
264 static int is_large_pte(u64 pte)
266 return pte & PT_PAGE_SIZE_MASK;
269 static int is_dirty_gpte(unsigned long pte)
271 return pte & PT_DIRTY_MASK;
274 static int is_rmap_spte(u64 pte)
276 return is_shadow_present_pte(pte);
279 static int is_last_spte(u64 pte, int level)
281 if (level == PT_PAGE_TABLE_LEVEL)
283 if (is_large_pte(pte))
288 static pfn_t spte_to_pfn(u64 pte)
290 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
293 static gfn_t pse36_gfn_delta(u32 gpte)
295 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
297 return (gpte & PT32_DIR_PSE36_MASK) << shift;
301 static void __set_spte(u64 *sptep, u64 spte)
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
313 return xchg(sptep, spte);
316 static u64 __get_spte_lockless(u64 *sptep)
318 return ACCESS_ONCE(*sptep);
321 static bool __check_direct_spte_mmio_pf(u64 spte)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64 *sptep, u64 spte)
337 struct kvm_mmu_page *sp = page_header(__pa(sptep));
339 if (is_shadow_present_pte(spte))
342 /* Ensure the spte is completely set before we increase the count */
344 sp->clear_spte_count++;
347 static void __set_spte(u64 *sptep, u64 spte)
349 union split_spte *ssptep, sspte;
351 ssptep = (union split_spte *)sptep;
352 sspte = (union split_spte)spte;
354 ssptep->spte_high = sspte.spte_high;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep->spte_low = sspte.spte_low;
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
368 union split_spte *ssptep, sspte;
370 ssptep = (union split_spte *)sptep;
371 sspte = (union split_spte)spte;
373 ssptep->spte_low = sspte.spte_low;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep->spte_high = sspte.spte_high;
382 count_spte_clear(sptep, spte);
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
387 union split_spte *ssptep, sspte, orig;
389 ssptep = (union split_spte *)sptep;
390 sspte = (union split_spte)spte;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394 orig.spte_high = ssptep->spte_high;
395 ssptep->spte_high = sspte.spte_high;
396 count_spte_clear(sptep, spte);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64 __get_spte_lockless(u64 *sptep)
410 struct kvm_mmu_page *sp = page_header(__pa(sptep));
411 union split_spte spte, *orig = (union split_spte *)sptep;
415 count = sp->clear_spte_count;
418 spte.spte_low = orig->spte_low;
421 spte.spte_high = orig->spte_high;
424 if (unlikely(spte.spte_low != orig->spte_low ||
425 count != sp->clear_spte_count))
431 static bool __check_direct_spte_mmio_pf(u64 spte)
433 union split_spte sspte = (union split_spte)spte;
434 u32 high_mmio_mask = shadow_mmio_mask >> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte.spte_low == 0ull &&
442 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
449 static bool spte_is_locklessly_modifiable(u64 spte)
451 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
452 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
455 static bool spte_has_volatile_bits(u64 spte)
458 * Always atomicly update spte if it can be updated
459 * out of mmu-lock, it can ensure dirty bit is not lost,
460 * also, it can help us to get a stable is_writable_pte()
461 * to ensure tlb flush is not missed.
463 if (spte_is_locklessly_modifiable(spte))
466 if (!shadow_accessed_mask)
469 if (!is_shadow_present_pte(spte))
472 if ((spte & shadow_accessed_mask) &&
473 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
479 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
481 return (old_spte & bit_mask) && !(new_spte & bit_mask);
484 /* Rules for using mmu_spte_set:
485 * Set the sptep from nonpresent to present.
486 * Note: the sptep being assigned *must* be either not present
487 * or in a state where the hardware will not attempt to update
490 static void mmu_spte_set(u64 *sptep, u64 new_spte)
492 WARN_ON(is_shadow_present_pte(*sptep));
493 __set_spte(sptep, new_spte);
496 /* Rules for using mmu_spte_update:
497 * Update the state bits, it means the mapped pfn is not changged.
499 * Whenever we overwrite a writable spte with a read-only one we
500 * should flush remote TLBs. Otherwise rmap_write_protect
501 * will find a read-only spte, even though the writable spte
502 * might be cached on a CPU's TLB, the return value indicates this
505 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
507 u64 old_spte = *sptep;
510 WARN_ON(!is_rmap_spte(new_spte));
512 if (!is_shadow_present_pte(old_spte)) {
513 mmu_spte_set(sptep, new_spte);
517 if (!spte_has_volatile_bits(old_spte))
518 __update_clear_spte_fast(sptep, new_spte);
520 old_spte = __update_clear_spte_slow(sptep, new_spte);
523 * For the spte updated out of mmu-lock is safe, since
524 * we always atomicly update it, see the comments in
525 * spte_has_volatile_bits().
527 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
530 if (!shadow_accessed_mask)
533 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
534 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
535 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
536 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
542 * Rules for using mmu_spte_clear_track_bits:
543 * It sets the sptep from present to nonpresent, and track the
544 * state bits, it is used to clear the last level sptep.
546 static int mmu_spte_clear_track_bits(u64 *sptep)
549 u64 old_spte = *sptep;
551 if (!spte_has_volatile_bits(old_spte))
552 __update_clear_spte_fast(sptep, 0ull);
554 old_spte = __update_clear_spte_slow(sptep, 0ull);
556 if (!is_rmap_spte(old_spte))
559 pfn = spte_to_pfn(old_spte);
562 * KVM does not hold the refcount of the page used by
563 * kvm mmu, before reclaiming the page, we should
564 * unmap it from mmu first.
566 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
568 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
569 kvm_set_pfn_accessed(pfn);
570 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
571 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
593 * Prevent page table teardown by making any free-er wait during
594 * kvm_flush_remote_tlbs() IPI to all active vcpus.
597 vcpu->mode = READING_SHADOW_PAGE_TABLES;
599 * Make sure a following spte read is not reordered ahead of the write
605 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
608 * Make sure the write to vcpu->mode is not reordered in front of
609 * reads to sptes. If it does, kvm_commit_zap_page() can see us
610 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
613 vcpu->mode = OUTSIDE_GUEST_MODE;
617 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
618 struct kmem_cache *base_cache, int min)
622 if (cache->nobjs >= min)
624 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
625 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
628 cache->objects[cache->nobjs++] = obj;
633 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
638 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
639 struct kmem_cache *cache)
642 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
645 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
650 if (cache->nobjs >= min)
652 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
653 page = (void *)__get_free_page(GFP_KERNEL);
656 cache->objects[cache->nobjs++] = page;
661 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
664 free_page((unsigned long)mc->objects[--mc->nobjs]);
667 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
671 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
672 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
675 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
678 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
679 mmu_page_header_cache, 4);
684 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
686 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
687 pte_list_desc_cache);
688 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
689 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
690 mmu_page_header_cache);
693 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
698 p = mc->objects[--mc->nobjs];
702 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
704 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
707 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
709 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
712 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
714 if (!sp->role.direct)
715 return sp->gfns[index];
717 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
720 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
723 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
725 sp->gfns[index] = gfn;
729 * Return the pointer to the large page information for a given gfn,
730 * handling slots that are not large page aligned.
732 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
733 struct kvm_memory_slot *slot,
738 idx = gfn_to_index(gfn, slot->base_gfn, level);
739 return &slot->arch.lpage_info[level - 2][idx];
742 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
744 struct kvm_memory_slot *slot;
745 struct kvm_lpage_info *linfo;
748 slot = gfn_to_memslot(kvm, gfn);
749 for (i = PT_DIRECTORY_LEVEL;
750 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
751 linfo = lpage_info_slot(gfn, slot, i);
752 linfo->write_count += 1;
754 kvm->arch.indirect_shadow_pages++;
757 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
759 struct kvm_memory_slot *slot;
760 struct kvm_lpage_info *linfo;
763 slot = gfn_to_memslot(kvm, gfn);
764 for (i = PT_DIRECTORY_LEVEL;
765 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
766 linfo = lpage_info_slot(gfn, slot, i);
767 linfo->write_count -= 1;
768 WARN_ON(linfo->write_count < 0);
770 kvm->arch.indirect_shadow_pages--;
773 static int has_wrprotected_page(struct kvm *kvm,
777 struct kvm_memory_slot *slot;
778 struct kvm_lpage_info *linfo;
780 slot = gfn_to_memslot(kvm, gfn);
782 linfo = lpage_info_slot(gfn, slot, level);
783 return linfo->write_count;
789 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
791 unsigned long page_size;
794 page_size = kvm_host_page_size(kvm, gfn);
796 for (i = PT_PAGE_TABLE_LEVEL;
797 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
798 if (page_size >= KVM_HPAGE_SIZE(i))
807 static struct kvm_memory_slot *
808 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
811 struct kvm_memory_slot *slot;
813 slot = gfn_to_memslot(vcpu->kvm, gfn);
814 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
815 (no_dirty_log && slot->dirty_bitmap))
821 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
823 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
826 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
828 int host_level, level, max_level;
830 host_level = host_mapping_level(vcpu->kvm, large_gfn);
832 if (host_level == PT_PAGE_TABLE_LEVEL)
835 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
837 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
845 * Pte mapping structures:
847 * If pte_list bit zero is zero, then pte_list point to the spte.
849 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850 * pte_list_desc containing more mappings.
852 * Returns the number of pte entries before the spte was added or zero if
853 * the spte was not added.
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857 unsigned long *pte_list)
859 struct pte_list_desc *desc;
863 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864 *pte_list = (unsigned long)spte;
865 } else if (!(*pte_list & 1)) {
866 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867 desc = mmu_alloc_pte_list_desc(vcpu);
868 desc->sptes[0] = (u64 *)*pte_list;
869 desc->sptes[1] = spte;
870 *pte_list = (unsigned long)desc | 1;
873 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
877 count += PTE_LIST_EXT;
879 if (desc->sptes[PTE_LIST_EXT-1]) {
880 desc->more = mmu_alloc_pte_list_desc(vcpu);
883 for (i = 0; desc->sptes[i]; ++i)
885 desc->sptes[i] = spte;
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892 int i, struct pte_list_desc *prev_desc)
896 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
898 desc->sptes[i] = desc->sptes[j];
899 desc->sptes[j] = NULL;
902 if (!prev_desc && !desc->more)
903 *pte_list = (unsigned long)desc->sptes[0];
906 prev_desc->more = desc->more;
908 *pte_list = (unsigned long)desc->more | 1;
909 mmu_free_pte_list_desc(desc);
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
914 struct pte_list_desc *desc;
915 struct pte_list_desc *prev_desc;
919 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
921 } else if (!(*pte_list & 1)) {
922 rmap_printk("pte_list_remove: %p 1->0\n", spte);
923 if ((u64 *)*pte_list != spte) {
924 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
929 rmap_printk("pte_list_remove: %p many->many\n", spte);
930 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
933 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934 if (desc->sptes[i] == spte) {
935 pte_list_desc_remove_entry(pte_list,
943 pr_err("pte_list_remove: %p many->many\n", spte);
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
951 struct pte_list_desc *desc;
957 if (!(*pte_list & 1))
958 return fn((u64 *)*pte_list);
960 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
962 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969 struct kvm_memory_slot *slot)
973 idx = gfn_to_index(gfn, slot->base_gfn, level);
974 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
978 * Take gfn and return the reverse mapping to it.
980 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
982 struct kvm_memory_slot *slot;
984 slot = gfn_to_memslot(kvm, gfn);
985 return __gfn_to_rmap(gfn, level, slot);
988 static bool rmap_can_add(struct kvm_vcpu *vcpu)
990 struct kvm_mmu_memory_cache *cache;
992 cache = &vcpu->arch.mmu_pte_list_desc_cache;
993 return mmu_memory_cache_free_objects(cache);
996 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
998 struct kvm_mmu_page *sp;
999 unsigned long *rmapp;
1001 sp = page_header(__pa(spte));
1002 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1003 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1004 return pte_list_add(vcpu, spte, rmapp);
1007 static void rmap_remove(struct kvm *kvm, u64 *spte)
1009 struct kvm_mmu_page *sp;
1011 unsigned long *rmapp;
1013 sp = page_header(__pa(spte));
1014 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1015 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1016 pte_list_remove(spte, rmapp);
1020 * Used by the following functions to iterate through the sptes linked by a
1021 * rmap. All fields are private and not assumed to be used outside.
1023 struct rmap_iterator {
1024 /* private fields */
1025 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1026 int pos; /* index of the sptep */
1030 * Iteration must be started by this function. This should also be used after
1031 * removing/dropping sptes from the rmap link because in such cases the
1032 * information in the itererator may not be valid.
1034 * Returns sptep if found, NULL otherwise.
1036 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1046 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1048 return iter->desc->sptes[iter->pos];
1052 * Must be used with a valid iterator: e.g. after rmap_get_first().
1054 * Returns sptep if found, NULL otherwise.
1056 static u64 *rmap_get_next(struct rmap_iterator *iter)
1059 if (iter->pos < PTE_LIST_EXT - 1) {
1063 sptep = iter->desc->sptes[iter->pos];
1068 iter->desc = iter->desc->more;
1072 /* desc->sptes[0] cannot be NULL */
1073 return iter->desc->sptes[iter->pos];
1080 static void drop_spte(struct kvm *kvm, u64 *sptep)
1082 if (mmu_spte_clear_track_bits(sptep))
1083 rmap_remove(kvm, sptep);
1087 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1089 if (is_large_pte(*sptep)) {
1090 WARN_ON(page_header(__pa(sptep))->role.level ==
1091 PT_PAGE_TABLE_LEVEL);
1092 drop_spte(kvm, sptep);
1100 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1102 if (__drop_large_spte(vcpu->kvm, sptep))
1103 kvm_flush_remote_tlbs(vcpu->kvm);
1107 * Write-protect on the specified @sptep, @pt_protect indicates whether
1108 * spte write-protection is caused by protecting shadow page table.
1110 * Note: write protection is difference between drity logging and spte
1112 * - for dirty logging, the spte can be set to writable at anytime if
1113 * its dirty bitmap is properly set.
1114 * - for spte protection, the spte can be writable only after unsync-ing
1117 * Return true if tlb need be flushed.
1119 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1123 if (!is_writable_pte(spte) &&
1124 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1127 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1130 spte &= ~SPTE_MMU_WRITEABLE;
1131 spte = spte & ~PT_WRITABLE_MASK;
1133 return mmu_spte_update(sptep, spte);
1136 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1140 struct rmap_iterator iter;
1143 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1144 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1146 flush |= spte_write_protect(kvm, sptep, pt_protect);
1147 sptep = rmap_get_next(&iter);
1154 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1155 * @kvm: kvm instance
1156 * @slot: slot to protect
1157 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1158 * @mask: indicates which pages we should protect
1160 * Used when we do not need to care about huge page mappings: e.g. during dirty
1161 * logging we do not have any such mappings.
1163 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1164 struct kvm_memory_slot *slot,
1165 gfn_t gfn_offset, unsigned long mask)
1167 unsigned long *rmapp;
1170 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1171 PT_PAGE_TABLE_LEVEL, slot);
1172 __rmap_write_protect(kvm, rmapp, false);
1174 /* clear the first set bit */
1179 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1181 struct kvm_memory_slot *slot;
1182 unsigned long *rmapp;
1184 bool write_protected = false;
1186 slot = gfn_to_memslot(kvm, gfn);
1188 for (i = PT_PAGE_TABLE_LEVEL;
1189 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1190 rmapp = __gfn_to_rmap(gfn, i, slot);
1191 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1194 return write_protected;
1197 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1198 struct kvm_memory_slot *slot, unsigned long data)
1201 struct rmap_iterator iter;
1202 int need_tlb_flush = 0;
1204 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1205 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1206 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1208 drop_spte(kvm, sptep);
1212 return need_tlb_flush;
1215 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1216 struct kvm_memory_slot *slot, unsigned long data)
1219 struct rmap_iterator iter;
1222 pte_t *ptep = (pte_t *)data;
1225 WARN_ON(pte_huge(*ptep));
1226 new_pfn = pte_pfn(*ptep);
1228 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1229 BUG_ON(!is_shadow_present_pte(*sptep));
1230 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1234 if (pte_write(*ptep)) {
1235 drop_spte(kvm, sptep);
1236 sptep = rmap_get_first(*rmapp, &iter);
1238 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1239 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1241 new_spte &= ~PT_WRITABLE_MASK;
1242 new_spte &= ~SPTE_HOST_WRITEABLE;
1243 new_spte &= ~shadow_accessed_mask;
1245 mmu_spte_clear_track_bits(sptep);
1246 mmu_spte_set(sptep, new_spte);
1247 sptep = rmap_get_next(&iter);
1252 kvm_flush_remote_tlbs(kvm);
1257 static int kvm_handle_hva_range(struct kvm *kvm,
1258 unsigned long start,
1261 int (*handler)(struct kvm *kvm,
1262 unsigned long *rmapp,
1263 struct kvm_memory_slot *slot,
1264 unsigned long data))
1268 struct kvm_memslots *slots;
1269 struct kvm_memory_slot *memslot;
1271 slots = kvm_memslots(kvm);
1273 kvm_for_each_memslot(memslot, slots) {
1274 unsigned long hva_start, hva_end;
1275 gfn_t gfn_start, gfn_end;
1277 hva_start = max(start, memslot->userspace_addr);
1278 hva_end = min(end, memslot->userspace_addr +
1279 (memslot->npages << PAGE_SHIFT));
1280 if (hva_start >= hva_end)
1283 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1284 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1286 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1287 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1289 for (j = PT_PAGE_TABLE_LEVEL;
1290 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1291 unsigned long idx, idx_end;
1292 unsigned long *rmapp;
1295 * {idx(page_j) | page_j intersects with
1296 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1298 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1299 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1301 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1303 for (; idx <= idx_end; ++idx)
1304 ret |= handler(kvm, rmapp++, memslot, data);
1311 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1313 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1314 struct kvm_memory_slot *slot,
1315 unsigned long data))
1317 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1320 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1322 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1325 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1327 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1330 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1332 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1335 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1336 struct kvm_memory_slot *slot, unsigned long data)
1339 struct rmap_iterator uninitialized_var(iter);
1343 * In case of absence of EPT Access and Dirty Bits supports,
1344 * emulate the accessed bit for EPT, by checking if this page has
1345 * an EPT mapping, and clearing it if it does. On the next access,
1346 * a new EPT mapping will be established.
1347 * This has some overhead, but not as much as the cost of swapping
1348 * out actively used pages or breaking up actively used hugepages.
1350 if (!shadow_accessed_mask) {
1351 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1355 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1356 sptep = rmap_get_next(&iter)) {
1357 BUG_ON(!is_shadow_present_pte(*sptep));
1359 if (*sptep & shadow_accessed_mask) {
1361 clear_bit((ffs(shadow_accessed_mask) - 1),
1362 (unsigned long *)sptep);
1366 /* @data has hva passed to kvm_age_hva(). */
1367 trace_kvm_age_page(data, slot, young);
1371 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1372 struct kvm_memory_slot *slot, unsigned long data)
1375 struct rmap_iterator iter;
1379 * If there's no access bit in the secondary pte set by the
1380 * hardware it's up to gup-fast/gup to set the access bit in
1381 * the primary pte or in the page structure.
1383 if (!shadow_accessed_mask)
1386 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1387 sptep = rmap_get_next(&iter)) {
1388 BUG_ON(!is_shadow_present_pte(*sptep));
1390 if (*sptep & shadow_accessed_mask) {
1399 #define RMAP_RECYCLE_THRESHOLD 1000
1401 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1403 unsigned long *rmapp;
1404 struct kvm_mmu_page *sp;
1406 sp = page_header(__pa(spte));
1408 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1410 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1411 kvm_flush_remote_tlbs(vcpu->kvm);
1414 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1416 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1419 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1421 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1425 static int is_empty_shadow_page(u64 *spt)
1430 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1431 if (is_shadow_present_pte(*pos)) {
1432 printk(KERN_ERR "%s: %p %llx\n", __func__,
1441 * This value is the sum of all of the kvm instances's
1442 * kvm->arch.n_used_mmu_pages values. We need a global,
1443 * aggregate version in order to make the slab shrinker
1446 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1448 kvm->arch.n_used_mmu_pages += nr;
1449 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1452 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1454 ASSERT(is_empty_shadow_page(sp->spt));
1455 hlist_del(&sp->hash_link);
1456 list_del(&sp->link);
1457 free_page((unsigned long)sp->spt);
1458 if (!sp->role.direct)
1459 free_page((unsigned long)sp->gfns);
1460 kmem_cache_free(mmu_page_header_cache, sp);
1463 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1465 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1468 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1469 struct kvm_mmu_page *sp, u64 *parent_pte)
1474 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1477 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1480 pte_list_remove(parent_pte, &sp->parent_ptes);
1483 static void drop_parent_pte(struct kvm_mmu_page *sp,
1486 mmu_page_remove_parent_pte(sp, parent_pte);
1487 mmu_spte_clear_no_track(parent_pte);
1490 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1491 u64 *parent_pte, int direct)
1493 struct kvm_mmu_page *sp;
1494 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1495 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1497 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1498 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1499 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1500 sp->parent_ptes = 0;
1501 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1502 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1506 static void mark_unsync(u64 *spte);
1507 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1509 pte_list_walk(&sp->parent_ptes, mark_unsync);
1512 static void mark_unsync(u64 *spte)
1514 struct kvm_mmu_page *sp;
1517 sp = page_header(__pa(spte));
1518 index = spte - sp->spt;
1519 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1521 if (sp->unsync_children++)
1523 kvm_mmu_mark_parents_unsync(sp);
1526 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1527 struct kvm_mmu_page *sp)
1532 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1536 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1537 struct kvm_mmu_page *sp, u64 *spte,
1543 #define KVM_PAGE_ARRAY_NR 16
1545 struct kvm_mmu_pages {
1546 struct mmu_page_and_offset {
1547 struct kvm_mmu_page *sp;
1549 } page[KVM_PAGE_ARRAY_NR];
1553 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1559 for (i=0; i < pvec->nr; i++)
1560 if (pvec->page[i].sp == sp)
1563 pvec->page[pvec->nr].sp = sp;
1564 pvec->page[pvec->nr].idx = idx;
1566 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1569 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1570 struct kvm_mmu_pages *pvec)
1572 int i, ret, nr_unsync_leaf = 0;
1574 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1575 struct kvm_mmu_page *child;
1576 u64 ent = sp->spt[i];
1578 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1579 goto clear_child_bitmap;
1581 child = page_header(ent & PT64_BASE_ADDR_MASK);
1583 if (child->unsync_children) {
1584 if (mmu_pages_add(pvec, child, i))
1587 ret = __mmu_unsync_walk(child, pvec);
1589 goto clear_child_bitmap;
1591 nr_unsync_leaf += ret;
1594 } else if (child->unsync) {
1596 if (mmu_pages_add(pvec, child, i))
1599 goto clear_child_bitmap;
1604 __clear_bit(i, sp->unsync_child_bitmap);
1605 sp->unsync_children--;
1606 WARN_ON((int)sp->unsync_children < 0);
1610 return nr_unsync_leaf;
1613 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1614 struct kvm_mmu_pages *pvec)
1616 if (!sp->unsync_children)
1619 mmu_pages_add(pvec, sp, 0);
1620 return __mmu_unsync_walk(sp, pvec);
1623 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1625 WARN_ON(!sp->unsync);
1626 trace_kvm_mmu_sync_page(sp);
1628 --kvm->stat.mmu_unsync;
1631 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1632 struct list_head *invalid_list);
1633 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1634 struct list_head *invalid_list);
1636 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1637 hlist_for_each_entry(sp, pos, \
1638 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1639 if ((sp)->gfn != (gfn)) {} else
1641 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1642 hlist_for_each_entry(sp, pos, \
1643 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1644 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1645 (sp)->role.invalid) {} else
1647 /* @sp->gfn should be write-protected at the call site */
1648 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1649 struct list_head *invalid_list, bool clear_unsync)
1651 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1652 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1657 kvm_unlink_unsync_page(vcpu->kvm, sp);
1659 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1660 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1664 kvm_mmu_flush_tlb(vcpu);
1668 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1669 struct kvm_mmu_page *sp)
1671 LIST_HEAD(invalid_list);
1674 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1676 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1681 #ifdef CONFIG_KVM_MMU_AUDIT
1682 #include "mmu_audit.c"
1684 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1685 static void mmu_audit_disable(void) { }
1688 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1689 struct list_head *invalid_list)
1691 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1694 /* @gfn should be write-protected at the call site */
1695 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1697 struct kvm_mmu_page *s;
1698 struct hlist_node *node;
1699 LIST_HEAD(invalid_list);
1702 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1706 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1707 kvm_unlink_unsync_page(vcpu->kvm, s);
1708 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1709 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1710 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1716 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1718 kvm_mmu_flush_tlb(vcpu);
1721 struct mmu_page_path {
1722 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1723 unsigned int idx[PT64_ROOT_LEVEL-1];
1726 #define for_each_sp(pvec, sp, parents, i) \
1727 for (i = mmu_pages_next(&pvec, &parents, -1), \
1728 sp = pvec.page[i].sp; \
1729 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1730 i = mmu_pages_next(&pvec, &parents, i))
1732 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1733 struct mmu_page_path *parents,
1738 for (n = i+1; n < pvec->nr; n++) {
1739 struct kvm_mmu_page *sp = pvec->page[n].sp;
1741 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1742 parents->idx[0] = pvec->page[n].idx;
1746 parents->parent[sp->role.level-2] = sp;
1747 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1753 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1755 struct kvm_mmu_page *sp;
1756 unsigned int level = 0;
1759 unsigned int idx = parents->idx[level];
1761 sp = parents->parent[level];
1765 --sp->unsync_children;
1766 WARN_ON((int)sp->unsync_children < 0);
1767 __clear_bit(idx, sp->unsync_child_bitmap);
1769 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1772 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1773 struct mmu_page_path *parents,
1774 struct kvm_mmu_pages *pvec)
1776 parents->parent[parent->role.level-1] = NULL;
1780 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1781 struct kvm_mmu_page *parent)
1784 struct kvm_mmu_page *sp;
1785 struct mmu_page_path parents;
1786 struct kvm_mmu_pages pages;
1787 LIST_HEAD(invalid_list);
1789 kvm_mmu_pages_init(parent, &parents, &pages);
1790 while (mmu_unsync_walk(parent, &pages)) {
1791 bool protected = false;
1793 for_each_sp(pages, sp, parents, i)
1794 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1797 kvm_flush_remote_tlbs(vcpu->kvm);
1799 for_each_sp(pages, sp, parents, i) {
1800 kvm_sync_page(vcpu, sp, &invalid_list);
1801 mmu_pages_clear_parents(&parents);
1803 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1804 cond_resched_lock(&vcpu->kvm->mmu_lock);
1805 kvm_mmu_pages_init(parent, &parents, &pages);
1809 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1813 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1817 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1819 sp->write_flooding_count = 0;
1822 static void clear_sp_write_flooding_count(u64 *spte)
1824 struct kvm_mmu_page *sp = page_header(__pa(spte));
1826 __clear_sp_write_flooding_count(sp);
1829 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1837 union kvm_mmu_page_role role;
1839 struct kvm_mmu_page *sp;
1840 struct hlist_node *node;
1841 bool need_sync = false;
1843 role = vcpu->arch.mmu.base_role;
1845 role.direct = direct;
1848 role.access = access;
1849 if (!vcpu->arch.mmu.direct_map
1850 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1851 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1852 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1853 role.quadrant = quadrant;
1855 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1856 if (!need_sync && sp->unsync)
1859 if (sp->role.word != role.word)
1862 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1865 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1866 if (sp->unsync_children) {
1867 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1868 kvm_mmu_mark_parents_unsync(sp);
1869 } else if (sp->unsync)
1870 kvm_mmu_mark_parents_unsync(sp);
1872 __clear_sp_write_flooding_count(sp);
1873 trace_kvm_mmu_get_page(sp, false);
1876 ++vcpu->kvm->stat.mmu_cache_miss;
1877 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1882 hlist_add_head(&sp->hash_link,
1883 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1885 if (rmap_write_protect(vcpu->kvm, gfn))
1886 kvm_flush_remote_tlbs(vcpu->kvm);
1887 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1888 kvm_sync_pages(vcpu, gfn);
1890 account_shadowed(vcpu->kvm, gfn);
1892 init_shadow_page_table(sp);
1893 trace_kvm_mmu_get_page(sp, true);
1897 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1898 struct kvm_vcpu *vcpu, u64 addr)
1900 iterator->addr = addr;
1901 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1902 iterator->level = vcpu->arch.mmu.shadow_root_level;
1904 if (iterator->level == PT64_ROOT_LEVEL &&
1905 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1906 !vcpu->arch.mmu.direct_map)
1909 if (iterator->level == PT32E_ROOT_LEVEL) {
1910 iterator->shadow_addr
1911 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1912 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1914 if (!iterator->shadow_addr)
1915 iterator->level = 0;
1919 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1921 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1924 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1925 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1929 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1932 if (is_last_spte(spte, iterator->level)) {
1933 iterator->level = 0;
1937 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1941 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1943 return __shadow_walk_next(iterator, *iterator->sptep);
1946 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1950 spte = __pa(sp->spt)
1951 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1952 | PT_WRITABLE_MASK | PT_USER_MASK;
1953 mmu_spte_set(sptep, spte);
1956 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1957 unsigned direct_access)
1959 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1960 struct kvm_mmu_page *child;
1963 * For the direct sp, if the guest pte's dirty bit
1964 * changed form clean to dirty, it will corrupt the
1965 * sp's access: allow writable in the read-only sp,
1966 * so we should update the spte at this point to get
1967 * a new sp with the correct access.
1969 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1970 if (child->role.access == direct_access)
1973 drop_parent_pte(child, sptep);
1974 kvm_flush_remote_tlbs(vcpu->kvm);
1978 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1982 struct kvm_mmu_page *child;
1985 if (is_shadow_present_pte(pte)) {
1986 if (is_last_spte(pte, sp->role.level)) {
1987 drop_spte(kvm, spte);
1988 if (is_large_pte(pte))
1991 child = page_header(pte & PT64_BASE_ADDR_MASK);
1992 drop_parent_pte(child, spte);
1997 if (is_mmio_spte(pte))
1998 mmu_spte_clear_no_track(spte);
2003 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2004 struct kvm_mmu_page *sp)
2008 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2009 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2012 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2014 mmu_page_remove_parent_pte(sp, parent_pte);
2017 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2020 struct rmap_iterator iter;
2022 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2023 drop_parent_pte(sp, sptep);
2026 static int mmu_zap_unsync_children(struct kvm *kvm,
2027 struct kvm_mmu_page *parent,
2028 struct list_head *invalid_list)
2031 struct mmu_page_path parents;
2032 struct kvm_mmu_pages pages;
2034 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2037 kvm_mmu_pages_init(parent, &parents, &pages);
2038 while (mmu_unsync_walk(parent, &pages)) {
2039 struct kvm_mmu_page *sp;
2041 for_each_sp(pages, sp, parents, i) {
2042 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2043 mmu_pages_clear_parents(&parents);
2046 kvm_mmu_pages_init(parent, &parents, &pages);
2052 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2053 struct list_head *invalid_list)
2057 trace_kvm_mmu_prepare_zap_page(sp);
2058 ++kvm->stat.mmu_shadow_zapped;
2059 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2060 kvm_mmu_page_unlink_children(kvm, sp);
2061 kvm_mmu_unlink_parents(kvm, sp);
2062 if (!sp->role.invalid && !sp->role.direct)
2063 unaccount_shadowed(kvm, sp->gfn);
2065 kvm_unlink_unsync_page(kvm, sp);
2066 if (!sp->root_count) {
2069 list_move(&sp->link, invalid_list);
2070 kvm_mod_used_mmu_pages(kvm, -1);
2072 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2073 kvm_reload_remote_mmus(kvm);
2076 sp->role.invalid = 1;
2080 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2081 struct list_head *invalid_list)
2083 struct kvm_mmu_page *sp;
2085 if (list_empty(invalid_list))
2089 * wmb: make sure everyone sees our modifications to the page tables
2090 * rmb: make sure we see changes to vcpu->mode
2095 * Wait for all vcpus to exit guest mode and/or lockless shadow
2098 kvm_flush_remote_tlbs(kvm);
2101 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2102 WARN_ON(!sp->role.invalid || sp->root_count);
2103 kvm_mmu_free_page(sp);
2104 } while (!list_empty(invalid_list));
2108 * Changing the number of mmu pages allocated to the vm
2109 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2111 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2113 LIST_HEAD(invalid_list);
2115 * If we set the number of mmu pages to be smaller be than the
2116 * number of actived pages , we must to free some mmu pages before we
2120 spin_lock(&kvm->mmu_lock);
2122 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2123 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2124 !list_empty(&kvm->arch.active_mmu_pages)) {
2125 struct kvm_mmu_page *page;
2127 page = container_of(kvm->arch.active_mmu_pages.prev,
2128 struct kvm_mmu_page, link);
2129 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2131 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2132 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2135 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2137 spin_unlock(&kvm->mmu_lock);
2140 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2142 struct kvm_mmu_page *sp;
2143 struct hlist_node *node;
2144 LIST_HEAD(invalid_list);
2147 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2149 spin_lock(&kvm->mmu_lock);
2150 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2151 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2154 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2156 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2157 spin_unlock(&kvm->mmu_lock);
2161 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2164 * The function is based on mtrr_type_lookup() in
2165 * arch/x86/kernel/cpu/mtrr/generic.c
2167 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2172 u8 prev_match, curr_match;
2173 int num_var_ranges = KVM_NR_VAR_MTRR;
2175 if (!mtrr_state->enabled)
2178 /* Make end inclusive end, instead of exclusive */
2181 /* Look in fixed ranges. Just return the type as per start */
2182 if (mtrr_state->have_fixed && (start < 0x100000)) {
2185 if (start < 0x80000) {
2187 idx += (start >> 16);
2188 return mtrr_state->fixed_ranges[idx];
2189 } else if (start < 0xC0000) {
2191 idx += ((start - 0x80000) >> 14);
2192 return mtrr_state->fixed_ranges[idx];
2193 } else if (start < 0x1000000) {
2195 idx += ((start - 0xC0000) >> 12);
2196 return mtrr_state->fixed_ranges[idx];
2201 * Look in variable ranges
2202 * Look of multiple ranges matching this address and pick type
2203 * as per MTRR precedence
2205 if (!(mtrr_state->enabled & 2))
2206 return mtrr_state->def_type;
2209 for (i = 0; i < num_var_ranges; ++i) {
2210 unsigned short start_state, end_state;
2212 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2215 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2216 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2217 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2218 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2220 start_state = ((start & mask) == (base & mask));
2221 end_state = ((end & mask) == (base & mask));
2222 if (start_state != end_state)
2225 if ((start & mask) != (base & mask))
2228 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2229 if (prev_match == 0xFF) {
2230 prev_match = curr_match;
2234 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2235 curr_match == MTRR_TYPE_UNCACHABLE)
2236 return MTRR_TYPE_UNCACHABLE;
2238 if ((prev_match == MTRR_TYPE_WRBACK &&
2239 curr_match == MTRR_TYPE_WRTHROUGH) ||
2240 (prev_match == MTRR_TYPE_WRTHROUGH &&
2241 curr_match == MTRR_TYPE_WRBACK)) {
2242 prev_match = MTRR_TYPE_WRTHROUGH;
2243 curr_match = MTRR_TYPE_WRTHROUGH;
2246 if (prev_match != curr_match)
2247 return MTRR_TYPE_UNCACHABLE;
2250 if (prev_match != 0xFF)
2253 return mtrr_state->def_type;
2256 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2260 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2261 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2262 if (mtrr == 0xfe || mtrr == 0xff)
2263 mtrr = MTRR_TYPE_WRBACK;
2266 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2268 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2270 trace_kvm_mmu_unsync_page(sp);
2271 ++vcpu->kvm->stat.mmu_unsync;
2274 kvm_mmu_mark_parents_unsync(sp);
2277 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2279 struct kvm_mmu_page *s;
2280 struct hlist_node *node;
2282 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2285 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2286 __kvm_unsync_page(vcpu, s);
2290 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2293 struct kvm_mmu_page *s;
2294 struct hlist_node *node;
2295 bool need_unsync = false;
2297 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2301 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2308 kvm_unsync_pages(vcpu, gfn);
2312 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2313 unsigned pte_access, int level,
2314 gfn_t gfn, pfn_t pfn, bool speculative,
2315 bool can_unsync, bool host_writable)
2320 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2323 spte = PT_PRESENT_MASK;
2325 spte |= shadow_accessed_mask;
2327 if (pte_access & ACC_EXEC_MASK)
2328 spte |= shadow_x_mask;
2330 spte |= shadow_nx_mask;
2332 if (pte_access & ACC_USER_MASK)
2333 spte |= shadow_user_mask;
2335 if (level > PT_PAGE_TABLE_LEVEL)
2336 spte |= PT_PAGE_SIZE_MASK;
2338 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2339 kvm_is_mmio_pfn(pfn));
2342 spte |= SPTE_HOST_WRITEABLE;
2344 pte_access &= ~ACC_WRITE_MASK;
2346 spte |= (u64)pfn << PAGE_SHIFT;
2348 if (pte_access & ACC_WRITE_MASK) {
2351 * Other vcpu creates new sp in the window between
2352 * mapping_level() and acquiring mmu-lock. We can
2353 * allow guest to retry the access, the mapping can
2354 * be fixed if guest refault.
2356 if (level > PT_PAGE_TABLE_LEVEL &&
2357 has_wrprotected_page(vcpu->kvm, gfn, level))
2360 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2363 * Optimization: for pte sync, if spte was writable the hash
2364 * lookup is unnecessary (and expensive). Write protection
2365 * is responsibility of mmu_get_page / kvm_sync_page.
2366 * Same reasoning can be applied to dirty page accounting.
2368 if (!can_unsync && is_writable_pte(*sptep))
2371 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2372 pgprintk("%s: found shadow page for %llx, marking ro\n",
2375 pte_access &= ~ACC_WRITE_MASK;
2376 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2380 if (pte_access & ACC_WRITE_MASK)
2381 mark_page_dirty(vcpu->kvm, gfn);
2384 if (mmu_spte_update(sptep, spte))
2385 kvm_flush_remote_tlbs(vcpu->kvm);
2390 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2391 unsigned pte_access, int write_fault, int *emulate,
2392 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2395 int was_rmapped = 0;
2398 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2399 *sptep, write_fault, gfn);
2401 if (is_rmap_spte(*sptep)) {
2403 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2404 * the parent of the now unreachable PTE.
2406 if (level > PT_PAGE_TABLE_LEVEL &&
2407 !is_large_pte(*sptep)) {
2408 struct kvm_mmu_page *child;
2411 child = page_header(pte & PT64_BASE_ADDR_MASK);
2412 drop_parent_pte(child, sptep);
2413 kvm_flush_remote_tlbs(vcpu->kvm);
2414 } else if (pfn != spte_to_pfn(*sptep)) {
2415 pgprintk("hfn old %llx new %llx\n",
2416 spte_to_pfn(*sptep), pfn);
2417 drop_spte(vcpu->kvm, sptep);
2418 kvm_flush_remote_tlbs(vcpu->kvm);
2423 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2424 true, host_writable)) {
2427 kvm_mmu_flush_tlb(vcpu);
2430 if (unlikely(is_mmio_spte(*sptep) && emulate))
2433 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2434 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2435 is_large_pte(*sptep)? "2MB" : "4kB",
2436 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2438 if (!was_rmapped && is_large_pte(*sptep))
2439 ++vcpu->kvm->stat.lpages;
2441 if (is_shadow_present_pte(*sptep)) {
2443 rmap_count = rmap_add(vcpu, sptep, gfn);
2444 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2445 rmap_recycle(vcpu, sptep, gfn);
2449 kvm_release_pfn_clean(pfn);
2452 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2454 mmu_free_roots(vcpu);
2457 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2461 bit7 = (gpte >> 7) & 1;
2462 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2465 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2468 struct kvm_memory_slot *slot;
2470 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2472 return KVM_PFN_ERR_FAULT;
2474 return gfn_to_pfn_memslot_atomic(slot, gfn);
2477 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2478 struct kvm_mmu_page *sp, u64 *spte,
2481 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2484 if (!is_present_gpte(gpte))
2487 if (!(gpte & PT_ACCESSED_MASK))
2493 drop_spte(vcpu->kvm, spte);
2497 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2498 struct kvm_mmu_page *sp,
2499 u64 *start, u64 *end)
2501 struct page *pages[PTE_PREFETCH_NUM];
2502 unsigned access = sp->role.access;
2506 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2507 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2510 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2514 for (i = 0; i < ret; i++, gfn++, start++)
2515 mmu_set_spte(vcpu, start, access, 0, NULL,
2516 sp->role.level, gfn, page_to_pfn(pages[i]),
2522 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2523 struct kvm_mmu_page *sp, u64 *sptep)
2525 u64 *spte, *start = NULL;
2528 WARN_ON(!sp->role.direct);
2530 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2533 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2534 if (is_shadow_present_pte(*spte) || spte == sptep) {
2537 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2545 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2547 struct kvm_mmu_page *sp;
2550 * Since it's no accessed bit on EPT, it's no way to
2551 * distinguish between actually accessed translations
2552 * and prefetched, so disable pte prefetch if EPT is
2555 if (!shadow_accessed_mask)
2558 sp = page_header(__pa(sptep));
2559 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2562 __direct_pte_prefetch(vcpu, sp, sptep);
2565 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2566 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2569 struct kvm_shadow_walk_iterator iterator;
2570 struct kvm_mmu_page *sp;
2574 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2575 if (iterator.level == level) {
2576 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2577 write, &emulate, level, gfn, pfn,
2578 prefault, map_writable);
2579 direct_pte_prefetch(vcpu, iterator.sptep);
2580 ++vcpu->stat.pf_fixed;
2584 drop_large_spte(vcpu, iterator.sptep);
2586 if (!is_shadow_present_pte(*iterator.sptep)) {
2587 u64 base_addr = iterator.addr;
2589 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2590 pseudo_gfn = base_addr >> PAGE_SHIFT;
2591 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2593 1, ACC_ALL, iterator.sptep);
2595 mmu_spte_set(iterator.sptep,
2597 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2598 | shadow_user_mask | shadow_x_mask
2599 | shadow_accessed_mask);
2605 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2609 info.si_signo = SIGBUS;
2611 info.si_code = BUS_MCEERR_AR;
2612 info.si_addr = (void __user *)address;
2613 info.si_addr_lsb = PAGE_SHIFT;
2615 send_sig_info(SIGBUS, &info, tsk);
2618 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2621 * Do not cache the mmio info caused by writing the readonly gfn
2622 * into the spte otherwise read access on readonly gfn also can
2623 * caused mmio page fault and treat it as mmio access.
2624 * Return 1 to tell kvm to emulate it.
2626 if (pfn == KVM_PFN_ERR_RO_FAULT)
2629 if (pfn == KVM_PFN_ERR_HWPOISON) {
2630 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2637 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2638 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2642 int level = *levelp;
2645 * Check if it's a transparent hugepage. If this would be an
2646 * hugetlbfs page, level wouldn't be set to
2647 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2650 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2651 level == PT_PAGE_TABLE_LEVEL &&
2652 PageTransCompound(pfn_to_page(pfn)) &&
2653 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2656 * mmu_notifier_retry was successful and we hold the
2657 * mmu_lock here, so the pmd can't become splitting
2658 * from under us, and in turn
2659 * __split_huge_page_refcount() can't run from under
2660 * us and we can safely transfer the refcount from
2661 * PG_tail to PG_head as we switch the pfn to tail to
2664 *levelp = level = PT_DIRECTORY_LEVEL;
2665 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2666 VM_BUG_ON((gfn & mask) != (pfn & mask));
2670 kvm_release_pfn_clean(pfn);
2678 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2679 pfn_t pfn, unsigned access, int *ret_val)
2683 /* The pfn is invalid, report the error! */
2684 if (unlikely(is_error_pfn(pfn))) {
2685 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2689 if (unlikely(is_noslot_pfn(pfn)))
2690 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2697 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2700 * #PF can be fast only if the shadow page table is present and it
2701 * is caused by write-protect, that means we just need change the
2702 * W bit of the spte which can be done out of mmu-lock.
2704 if (!(error_code & PFERR_PRESENT_MASK) ||
2705 !(error_code & PFERR_WRITE_MASK))
2712 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2714 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2717 WARN_ON(!sp->role.direct);
2720 * The gfn of direct spte is stable since it is calculated
2723 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2725 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2726 mark_page_dirty(vcpu->kvm, gfn);
2733 * - true: let the vcpu to access on the same address again.
2734 * - false: let the real page fault path to fix it.
2736 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2739 struct kvm_shadow_walk_iterator iterator;
2743 if (!page_fault_can_be_fast(vcpu, error_code))
2746 walk_shadow_page_lockless_begin(vcpu);
2747 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2748 if (!is_shadow_present_pte(spte) || iterator.level < level)
2752 * If the mapping has been changed, let the vcpu fault on the
2753 * same address again.
2755 if (!is_rmap_spte(spte)) {
2760 if (!is_last_spte(spte, level))
2764 * Check if it is a spurious fault caused by TLB lazily flushed.
2766 * Need not check the access of upper level table entries since
2767 * they are always ACC_ALL.
2769 if (is_writable_pte(spte)) {
2775 * Currently, to simplify the code, only the spte write-protected
2776 * by dirty-log can be fast fixed.
2778 if (!spte_is_locklessly_modifiable(spte))
2782 * Currently, fast page fault only works for direct mapping since
2783 * the gfn is not stable for indirect shadow page.
2784 * See Documentation/virtual/kvm/locking.txt to get more detail.
2786 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2788 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2790 walk_shadow_page_lockless_end(vcpu);
2795 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2796 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2798 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2799 gfn_t gfn, bool prefault)
2805 unsigned long mmu_seq;
2806 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2808 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2809 if (likely(!force_pt_level)) {
2810 level = mapping_level(vcpu, gfn);
2812 * This path builds a PAE pagetable - so we can map
2813 * 2mb pages at maximum. Therefore check if the level
2814 * is larger than that.
2816 if (level > PT_DIRECTORY_LEVEL)
2817 level = PT_DIRECTORY_LEVEL;
2819 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2821 level = PT_PAGE_TABLE_LEVEL;
2823 if (fast_page_fault(vcpu, v, level, error_code))
2826 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2829 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2832 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2835 spin_lock(&vcpu->kvm->mmu_lock);
2836 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2838 kvm_mmu_free_some_pages(vcpu);
2839 if (likely(!force_pt_level))
2840 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2841 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2843 spin_unlock(&vcpu->kvm->mmu_lock);
2849 spin_unlock(&vcpu->kvm->mmu_lock);
2850 kvm_release_pfn_clean(pfn);
2855 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2858 struct kvm_mmu_page *sp;
2859 LIST_HEAD(invalid_list);
2861 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2863 spin_lock(&vcpu->kvm->mmu_lock);
2864 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2865 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2866 vcpu->arch.mmu.direct_map)) {
2867 hpa_t root = vcpu->arch.mmu.root_hpa;
2869 sp = page_header(root);
2871 if (!sp->root_count && sp->role.invalid) {
2872 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2873 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2875 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2876 spin_unlock(&vcpu->kvm->mmu_lock);
2879 for (i = 0; i < 4; ++i) {
2880 hpa_t root = vcpu->arch.mmu.pae_root[i];
2883 root &= PT64_BASE_ADDR_MASK;
2884 sp = page_header(root);
2886 if (!sp->root_count && sp->role.invalid)
2887 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2890 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2892 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2893 spin_unlock(&vcpu->kvm->mmu_lock);
2894 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2897 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2901 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2902 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2909 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2911 struct kvm_mmu_page *sp;
2914 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2915 spin_lock(&vcpu->kvm->mmu_lock);
2916 kvm_mmu_free_some_pages(vcpu);
2917 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2920 spin_unlock(&vcpu->kvm->mmu_lock);
2921 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2922 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2923 for (i = 0; i < 4; ++i) {
2924 hpa_t root = vcpu->arch.mmu.pae_root[i];
2926 ASSERT(!VALID_PAGE(root));
2927 spin_lock(&vcpu->kvm->mmu_lock);
2928 kvm_mmu_free_some_pages(vcpu);
2929 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2931 PT32_ROOT_LEVEL, 1, ACC_ALL,
2933 root = __pa(sp->spt);
2935 spin_unlock(&vcpu->kvm->mmu_lock);
2936 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2938 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2945 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2947 struct kvm_mmu_page *sp;
2952 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2954 if (mmu_check_root(vcpu, root_gfn))
2958 * Do we shadow a long mode page table? If so we need to
2959 * write-protect the guests page table root.
2961 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2962 hpa_t root = vcpu->arch.mmu.root_hpa;
2964 ASSERT(!VALID_PAGE(root));
2966 spin_lock(&vcpu->kvm->mmu_lock);
2967 kvm_mmu_free_some_pages(vcpu);
2968 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2970 root = __pa(sp->spt);
2972 spin_unlock(&vcpu->kvm->mmu_lock);
2973 vcpu->arch.mmu.root_hpa = root;
2978 * We shadow a 32 bit page table. This may be a legacy 2-level
2979 * or a PAE 3-level page table. In either case we need to be aware that
2980 * the shadow page table may be a PAE or a long mode page table.
2982 pm_mask = PT_PRESENT_MASK;
2983 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2984 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2986 for (i = 0; i < 4; ++i) {
2987 hpa_t root = vcpu->arch.mmu.pae_root[i];
2989 ASSERT(!VALID_PAGE(root));
2990 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2991 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2992 if (!is_present_gpte(pdptr)) {
2993 vcpu->arch.mmu.pae_root[i] = 0;
2996 root_gfn = pdptr >> PAGE_SHIFT;
2997 if (mmu_check_root(vcpu, root_gfn))
3000 spin_lock(&vcpu->kvm->mmu_lock);
3001 kvm_mmu_free_some_pages(vcpu);
3002 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3005 root = __pa(sp->spt);
3007 spin_unlock(&vcpu->kvm->mmu_lock);
3009 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3011 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3014 * If we shadow a 32 bit page table with a long mode page
3015 * table we enter this path.
3017 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3018 if (vcpu->arch.mmu.lm_root == NULL) {
3020 * The additional page necessary for this is only
3021 * allocated on demand.
3026 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3027 if (lm_root == NULL)
3030 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3032 vcpu->arch.mmu.lm_root = lm_root;
3035 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3041 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3043 if (vcpu->arch.mmu.direct_map)
3044 return mmu_alloc_direct_roots(vcpu);
3046 return mmu_alloc_shadow_roots(vcpu);
3049 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3052 struct kvm_mmu_page *sp;
3054 if (vcpu->arch.mmu.direct_map)
3057 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3060 vcpu_clear_mmio_info(vcpu, ~0ul);
3061 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3062 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3063 hpa_t root = vcpu->arch.mmu.root_hpa;
3064 sp = page_header(root);
3065 mmu_sync_children(vcpu, sp);
3066 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3069 for (i = 0; i < 4; ++i) {
3070 hpa_t root = vcpu->arch.mmu.pae_root[i];
3072 if (root && VALID_PAGE(root)) {
3073 root &= PT64_BASE_ADDR_MASK;
3074 sp = page_header(root);
3075 mmu_sync_children(vcpu, sp);
3078 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3081 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3083 spin_lock(&vcpu->kvm->mmu_lock);
3084 mmu_sync_roots(vcpu);
3085 spin_unlock(&vcpu->kvm->mmu_lock);
3088 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3089 u32 access, struct x86_exception *exception)
3092 exception->error_code = 0;
3096 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3098 struct x86_exception *exception)
3101 exception->error_code = 0;
3102 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3105 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3108 return vcpu_match_mmio_gpa(vcpu, addr);
3110 return vcpu_match_mmio_gva(vcpu, addr);
3115 * On direct hosts, the last spte is only allows two states
3116 * for mmio page fault:
3117 * - It is the mmio spte
3118 * - It is zapped or it is being zapped.
3120 * This function completely checks the spte when the last spte
3121 * is not the mmio spte.
3123 static bool check_direct_spte_mmio_pf(u64 spte)
3125 return __check_direct_spte_mmio_pf(spte);
3128 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3130 struct kvm_shadow_walk_iterator iterator;
3133 walk_shadow_page_lockless_begin(vcpu);
3134 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3135 if (!is_shadow_present_pte(spte))
3137 walk_shadow_page_lockless_end(vcpu);
3143 * If it is a real mmio page fault, return 1 and emulat the instruction
3144 * directly, return 0 to let CPU fault again on the address, -1 is
3145 * returned if bug is detected.
3147 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3151 if (quickly_check_mmio_pf(vcpu, addr, direct))
3154 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3156 if (is_mmio_spte(spte)) {
3157 gfn_t gfn = get_mmio_spte_gfn(spte);
3158 unsigned access = get_mmio_spte_access(spte);
3163 trace_handle_mmio_page_fault(addr, gfn, access);
3164 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3169 * It's ok if the gva is remapped by other cpus on shadow guest,
3170 * it's a BUG if the gfn is not a mmio page.
3172 if (direct && !check_direct_spte_mmio_pf(spte))
3176 * If the page table is zapped by other cpus, let CPU fault again on
3181 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3183 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3184 u32 error_code, bool direct)
3188 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3193 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3194 u32 error_code, bool prefault)
3199 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3201 if (unlikely(error_code & PFERR_RSVD_MASK))
3202 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3204 r = mmu_topup_memory_caches(vcpu);
3209 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3211 gfn = gva >> PAGE_SHIFT;
3213 return nonpaging_map(vcpu, gva & PAGE_MASK,
3214 error_code, gfn, prefault);
3217 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3219 struct kvm_arch_async_pf arch;
3221 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3223 arch.direct_map = vcpu->arch.mmu.direct_map;
3224 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3226 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3229 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3231 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3232 kvm_event_needs_reinjection(vcpu)))
3235 return kvm_x86_ops->interrupt_allowed(vcpu);
3238 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3239 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3243 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3246 return false; /* *pfn has correct page already */
3248 if (!prefault && can_do_async_pf(vcpu)) {
3249 trace_kvm_try_async_get_page(gva, gfn);
3250 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3251 trace_kvm_async_pf_doublefault(gva, gfn);
3252 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3254 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3258 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3263 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3270 gfn_t gfn = gpa >> PAGE_SHIFT;
3271 unsigned long mmu_seq;
3272 int write = error_code & PFERR_WRITE_MASK;
3276 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3278 if (unlikely(error_code & PFERR_RSVD_MASK))
3279 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3281 r = mmu_topup_memory_caches(vcpu);
3285 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3286 if (likely(!force_pt_level)) {
3287 level = mapping_level(vcpu, gfn);
3288 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3290 level = PT_PAGE_TABLE_LEVEL;
3292 if (fast_page_fault(vcpu, gpa, level, error_code))
3295 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3298 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3301 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3304 spin_lock(&vcpu->kvm->mmu_lock);
3305 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3307 kvm_mmu_free_some_pages(vcpu);
3308 if (likely(!force_pt_level))
3309 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3310 r = __direct_map(vcpu, gpa, write, map_writable,
3311 level, gfn, pfn, prefault);
3312 spin_unlock(&vcpu->kvm->mmu_lock);
3317 spin_unlock(&vcpu->kvm->mmu_lock);
3318 kvm_release_pfn_clean(pfn);
3322 static void nonpaging_free(struct kvm_vcpu *vcpu)
3324 mmu_free_roots(vcpu);
3327 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3328 struct kvm_mmu *context)
3330 context->new_cr3 = nonpaging_new_cr3;
3331 context->page_fault = nonpaging_page_fault;
3332 context->gva_to_gpa = nonpaging_gva_to_gpa;
3333 context->free = nonpaging_free;
3334 context->sync_page = nonpaging_sync_page;
3335 context->invlpg = nonpaging_invlpg;
3336 context->update_pte = nonpaging_update_pte;
3337 context->root_level = 0;
3338 context->shadow_root_level = PT32E_ROOT_LEVEL;
3339 context->root_hpa = INVALID_PAGE;
3340 context->direct_map = true;
3341 context->nx = false;
3345 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3347 ++vcpu->stat.tlb_flush;
3348 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3351 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3353 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3354 mmu_free_roots(vcpu);
3357 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3359 return kvm_read_cr3(vcpu);
3362 static void inject_page_fault(struct kvm_vcpu *vcpu,
3363 struct x86_exception *fault)
3365 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3368 static void paging_free(struct kvm_vcpu *vcpu)
3370 nonpaging_free(vcpu);
3373 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3377 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3379 mask = (unsigned)~ACC_WRITE_MASK;
3380 /* Allow write access to dirty gptes */
3381 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3385 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3388 if (unlikely(is_mmio_spte(*sptep))) {
3389 if (gfn != get_mmio_spte_gfn(*sptep)) {
3390 mmu_spte_clear_no_track(sptep);
3395 mark_mmio_spte(sptep, gfn, access);
3402 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3406 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3407 access &= ~(gpte >> PT64_NX_SHIFT);
3412 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3417 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3418 return mmu->last_pte_bitmap & (1 << index);
3422 #include "paging_tmpl.h"
3426 #include "paging_tmpl.h"
3429 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3430 struct kvm_mmu *context)
3432 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3433 u64 exb_bit_rsvd = 0;
3436 exb_bit_rsvd = rsvd_bits(63, 63);
3437 switch (context->root_level) {
3438 case PT32_ROOT_LEVEL:
3439 /* no rsvd bits for 2 level 4K page table entries */
3440 context->rsvd_bits_mask[0][1] = 0;
3441 context->rsvd_bits_mask[0][0] = 0;
3442 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3444 if (!is_pse(vcpu)) {
3445 context->rsvd_bits_mask[1][1] = 0;
3449 if (is_cpuid_PSE36())
3450 /* 36bits PSE 4MB page */
3451 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3453 /* 32 bits PSE 4MB page */
3454 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3456 case PT32E_ROOT_LEVEL:
3457 context->rsvd_bits_mask[0][2] =
3458 rsvd_bits(maxphyaddr, 63) |
3459 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3460 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3461 rsvd_bits(maxphyaddr, 62); /* PDE */
3462 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3463 rsvd_bits(maxphyaddr, 62); /* PTE */
3464 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3465 rsvd_bits(maxphyaddr, 62) |
3466 rsvd_bits(13, 20); /* large page */
3467 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3469 case PT64_ROOT_LEVEL:
3470 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3471 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3472 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3473 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3474 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3475 rsvd_bits(maxphyaddr, 51);
3476 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3477 rsvd_bits(maxphyaddr, 51);
3478 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3479 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3480 rsvd_bits(maxphyaddr, 51) |
3482 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3483 rsvd_bits(maxphyaddr, 51) |
3484 rsvd_bits(13, 20); /* large page */
3485 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3490 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3492 unsigned bit, byte, pfec;
3494 bool fault, x, w, u, wf, uf, ff, smep;
3496 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3497 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3500 wf = pfec & PFERR_WRITE_MASK;
3501 uf = pfec & PFERR_USER_MASK;
3502 ff = pfec & PFERR_FETCH_MASK;
3503 for (bit = 0; bit < 8; ++bit) {
3504 x = bit & ACC_EXEC_MASK;
3505 w = bit & ACC_WRITE_MASK;
3506 u = bit & ACC_USER_MASK;
3508 /* Not really needed: !nx will cause pte.nx to fault */
3510 /* Allow supervisor writes if !cr0.wp */
3511 w |= !is_write_protection(vcpu) && !uf;
3512 /* Disallow supervisor fetches of user code if cr4.smep */
3513 x &= !(smep && u && !uf);
3515 fault = (ff && !x) || (uf && !u) || (wf && !w);
3516 map |= fault << bit;
3518 mmu->permissions[byte] = map;
3522 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3525 unsigned level, root_level = mmu->root_level;
3526 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3528 if (root_level == PT32E_ROOT_LEVEL)
3530 /* PT_PAGE_TABLE_LEVEL always terminates */
3531 map = 1 | (1 << ps_set_index);
3532 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3533 if (level <= PT_PDPE_LEVEL
3534 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3535 map |= 1 << (ps_set_index | (level - 1));
3537 mmu->last_pte_bitmap = map;
3540 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3541 struct kvm_mmu *context,
3544 context->nx = is_nx(vcpu);
3545 context->root_level = level;
3547 reset_rsvds_bits_mask(vcpu, context);
3548 update_permission_bitmask(vcpu, context);
3549 update_last_pte_bitmap(vcpu, context);
3551 ASSERT(is_pae(vcpu));
3552 context->new_cr3 = paging_new_cr3;
3553 context->page_fault = paging64_page_fault;
3554 context->gva_to_gpa = paging64_gva_to_gpa;
3555 context->sync_page = paging64_sync_page;
3556 context->invlpg = paging64_invlpg;
3557 context->update_pte = paging64_update_pte;
3558 context->free = paging_free;
3559 context->shadow_root_level = level;
3560 context->root_hpa = INVALID_PAGE;
3561 context->direct_map = false;
3565 static int paging64_init_context(struct kvm_vcpu *vcpu,
3566 struct kvm_mmu *context)
3568 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3571 static int paging32_init_context(struct kvm_vcpu *vcpu,
3572 struct kvm_mmu *context)
3574 context->nx = false;
3575 context->root_level = PT32_ROOT_LEVEL;
3577 reset_rsvds_bits_mask(vcpu, context);
3578 update_permission_bitmask(vcpu, context);
3579 update_last_pte_bitmap(vcpu, context);
3581 context->new_cr3 = paging_new_cr3;
3582 context->page_fault = paging32_page_fault;
3583 context->gva_to_gpa = paging32_gva_to_gpa;
3584 context->free = paging_free;
3585 context->sync_page = paging32_sync_page;
3586 context->invlpg = paging32_invlpg;
3587 context->update_pte = paging32_update_pte;
3588 context->shadow_root_level = PT32E_ROOT_LEVEL;
3589 context->root_hpa = INVALID_PAGE;
3590 context->direct_map = false;
3594 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3595 struct kvm_mmu *context)
3597 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3600 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3602 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3604 context->base_role.word = 0;
3605 context->new_cr3 = nonpaging_new_cr3;
3606 context->page_fault = tdp_page_fault;
3607 context->free = nonpaging_free;
3608 context->sync_page = nonpaging_sync_page;
3609 context->invlpg = nonpaging_invlpg;
3610 context->update_pte = nonpaging_update_pte;
3611 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3612 context->root_hpa = INVALID_PAGE;
3613 context->direct_map = true;
3614 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3615 context->get_cr3 = get_cr3;
3616 context->get_pdptr = kvm_pdptr_read;
3617 context->inject_page_fault = kvm_inject_page_fault;
3619 if (!is_paging(vcpu)) {
3620 context->nx = false;
3621 context->gva_to_gpa = nonpaging_gva_to_gpa;
3622 context->root_level = 0;
3623 } else if (is_long_mode(vcpu)) {
3624 context->nx = is_nx(vcpu);
3625 context->root_level = PT64_ROOT_LEVEL;
3626 reset_rsvds_bits_mask(vcpu, context);
3627 context->gva_to_gpa = paging64_gva_to_gpa;
3628 } else if (is_pae(vcpu)) {
3629 context->nx = is_nx(vcpu);
3630 context->root_level = PT32E_ROOT_LEVEL;
3631 reset_rsvds_bits_mask(vcpu, context);
3632 context->gva_to_gpa = paging64_gva_to_gpa;
3634 context->nx = false;
3635 context->root_level = PT32_ROOT_LEVEL;
3636 reset_rsvds_bits_mask(vcpu, context);
3637 context->gva_to_gpa = paging32_gva_to_gpa;
3640 update_permission_bitmask(vcpu, context);
3641 update_last_pte_bitmap(vcpu, context);
3646 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3649 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3651 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3653 if (!is_paging(vcpu))
3654 r = nonpaging_init_context(vcpu, context);
3655 else if (is_long_mode(vcpu))
3656 r = paging64_init_context(vcpu, context);
3657 else if (is_pae(vcpu))
3658 r = paging32E_init_context(vcpu, context);
3660 r = paging32_init_context(vcpu, context);
3662 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3663 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3664 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3665 vcpu->arch.mmu.base_role.smep_andnot_wp
3666 = smep && !is_write_protection(vcpu);
3670 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3672 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3674 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3676 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3677 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3678 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3679 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3684 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3686 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3688 g_context->get_cr3 = get_cr3;
3689 g_context->get_pdptr = kvm_pdptr_read;
3690 g_context->inject_page_fault = kvm_inject_page_fault;
3693 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3694 * translation of l2_gpa to l1_gpa addresses is done using the
3695 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3696 * functions between mmu and nested_mmu are swapped.
3698 if (!is_paging(vcpu)) {
3699 g_context->nx = false;
3700 g_context->root_level = 0;
3701 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3702 } else if (is_long_mode(vcpu)) {
3703 g_context->nx = is_nx(vcpu);
3704 g_context->root_level = PT64_ROOT_LEVEL;
3705 reset_rsvds_bits_mask(vcpu, g_context);
3706 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3707 } else if (is_pae(vcpu)) {
3708 g_context->nx = is_nx(vcpu);
3709 g_context->root_level = PT32E_ROOT_LEVEL;
3710 reset_rsvds_bits_mask(vcpu, g_context);
3711 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3713 g_context->nx = false;
3714 g_context->root_level = PT32_ROOT_LEVEL;
3715 reset_rsvds_bits_mask(vcpu, g_context);
3716 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3719 update_permission_bitmask(vcpu, g_context);
3720 update_last_pte_bitmap(vcpu, g_context);
3725 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3727 if (mmu_is_nested(vcpu))
3728 return init_kvm_nested_mmu(vcpu);
3729 else if (tdp_enabled)
3730 return init_kvm_tdp_mmu(vcpu);
3732 return init_kvm_softmmu(vcpu);
3735 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3738 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3739 /* mmu.free() should set root_hpa = INVALID_PAGE */
3740 vcpu->arch.mmu.free(vcpu);
3743 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3745 destroy_kvm_mmu(vcpu);
3746 return init_kvm_mmu(vcpu);
3748 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3750 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3754 r = mmu_topup_memory_caches(vcpu);
3757 r = mmu_alloc_roots(vcpu);
3758 spin_lock(&vcpu->kvm->mmu_lock);
3759 mmu_sync_roots(vcpu);
3760 spin_unlock(&vcpu->kvm->mmu_lock);
3763 /* set_cr3() should ensure TLB has been flushed */
3764 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3768 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3770 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3772 mmu_free_roots(vcpu);
3774 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3776 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3777 struct kvm_mmu_page *sp, u64 *spte,
3780 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3781 ++vcpu->kvm->stat.mmu_pde_zapped;
3785 ++vcpu->kvm->stat.mmu_pte_updated;
3786 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3789 static bool need_remote_flush(u64 old, u64 new)
3791 if (!is_shadow_present_pte(old))
3793 if (!is_shadow_present_pte(new))
3795 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3797 old ^= PT64_NX_MASK;
3798 new ^= PT64_NX_MASK;
3799 return (old & ~new & PT64_PERM_MASK) != 0;
3802 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3803 bool remote_flush, bool local_flush)
3809 kvm_flush_remote_tlbs(vcpu->kvm);
3810 else if (local_flush)
3811 kvm_mmu_flush_tlb(vcpu);
3814 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3815 const u8 *new, int *bytes)
3821 * Assume that the pte write on a page table of the same type
3822 * as the current vcpu paging mode since we update the sptes only
3823 * when they have the same mode.
3825 if (is_pae(vcpu) && *bytes == 4) {
3826 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3829 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3832 new = (const u8 *)&gentry;
3837 gentry = *(const u32 *)new;
3840 gentry = *(const u64 *)new;
3851 * If we're seeing too many writes to a page, it may no longer be a page table,
3852 * or we may be forking, in which case it is better to unmap the page.
3854 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3857 * Skip write-flooding detected for the sp whose level is 1, because
3858 * it can become unsync, then the guest page is not write-protected.
3860 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3863 return ++sp->write_flooding_count >= 3;
3867 * Misaligned accesses are too much trouble to fix up; also, they usually
3868 * indicate a page is not used as a page table.
3870 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3873 unsigned offset, pte_size, misaligned;
3875 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3876 gpa, bytes, sp->role.word);
3878 offset = offset_in_page(gpa);
3879 pte_size = sp->role.cr4_pae ? 8 : 4;
3882 * Sometimes, the OS only writes the last one bytes to update status
3883 * bits, for example, in linux, andb instruction is used in clear_bit().
3885 if (!(offset & (pte_size - 1)) && bytes == 1)
3888 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3889 misaligned |= bytes < 4;
3894 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3896 unsigned page_offset, quadrant;
3900 page_offset = offset_in_page(gpa);
3901 level = sp->role.level;
3903 if (!sp->role.cr4_pae) {
3904 page_offset <<= 1; /* 32->64 */
3906 * A 32-bit pde maps 4MB while the shadow pdes map
3907 * only 2MB. So we need to double the offset again
3908 * and zap two pdes instead of one.
3910 if (level == PT32_ROOT_LEVEL) {
3911 page_offset &= ~7; /* kill rounding error */
3915 quadrant = page_offset >> PAGE_SHIFT;
3916 page_offset &= ~PAGE_MASK;
3917 if (quadrant != sp->role.quadrant)
3921 spte = &sp->spt[page_offset / sizeof(*spte)];
3925 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3926 const u8 *new, int bytes)
3928 gfn_t gfn = gpa >> PAGE_SHIFT;
3929 union kvm_mmu_page_role mask = { .word = 0 };
3930 struct kvm_mmu_page *sp;
3931 struct hlist_node *node;
3932 LIST_HEAD(invalid_list);
3933 u64 entry, gentry, *spte;
3935 bool remote_flush, local_flush, zap_page;
3938 * If we don't have indirect shadow pages, it means no page is
3939 * write-protected, so we can exit simply.
3941 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3944 zap_page = remote_flush = local_flush = false;
3946 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3948 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3951 * No need to care whether allocation memory is successful
3952 * or not since pte prefetch is skiped if it does not have
3953 * enough objects in the cache.
3955 mmu_topup_memory_caches(vcpu);
3957 spin_lock(&vcpu->kvm->mmu_lock);
3958 ++vcpu->kvm->stat.mmu_pte_write;
3959 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3961 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3962 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3963 if (detect_write_misaligned(sp, gpa, bytes) ||
3964 detect_write_flooding(sp)) {
3965 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3967 ++vcpu->kvm->stat.mmu_flooded;
3971 spte = get_written_sptes(sp, gpa, &npte);
3978 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3980 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3981 & mask.word) && rmap_can_add(vcpu))
3982 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3983 if (need_remote_flush(entry, *spte))
3984 remote_flush = true;
3988 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3989 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3990 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3991 spin_unlock(&vcpu->kvm->mmu_lock);
3994 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3999 if (vcpu->arch.mmu.direct_map)
4002 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4004 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4008 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4010 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
4012 LIST_HEAD(invalid_list);
4014 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
4015 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4016 struct kvm_mmu_page *sp;
4018 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4019 struct kvm_mmu_page, link);
4020 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4021 ++vcpu->kvm->stat.mmu_recycled;
4023 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4026 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4028 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4029 return vcpu_match_mmio_gpa(vcpu, addr);
4031 return vcpu_match_mmio_gva(vcpu, addr);
4034 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4035 void *insn, int insn_len)
4037 int r, emulation_type = EMULTYPE_RETRY;
4038 enum emulation_result er;
4040 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4049 if (is_mmio_page_fault(vcpu, cr2))
4052 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4057 case EMULATE_DO_MMIO:
4058 ++vcpu->stat.mmio_exits;
4068 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4070 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4072 vcpu->arch.mmu.invlpg(vcpu, gva);
4073 kvm_mmu_flush_tlb(vcpu);
4074 ++vcpu->stat.invlpg;
4076 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4078 void kvm_enable_tdp(void)
4082 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4084 void kvm_disable_tdp(void)
4086 tdp_enabled = false;
4088 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4090 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4092 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4093 if (vcpu->arch.mmu.lm_root != NULL)
4094 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4097 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4105 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4106 * Therefore we need to allocate shadow page tables in the first
4107 * 4GB of memory, which happens to fit the DMA32 zone.
4109 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4113 vcpu->arch.mmu.pae_root = page_address(page);
4114 for (i = 0; i < 4; ++i)
4115 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4120 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4124 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4125 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4126 vcpu->arch.mmu.translate_gpa = translate_gpa;
4127 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4129 return alloc_mmu_pages(vcpu);
4132 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4135 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4137 return init_kvm_mmu(vcpu);
4140 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4142 struct kvm_memory_slot *memslot;
4146 memslot = id_to_memslot(kvm->memslots, slot);
4147 last_gfn = memslot->base_gfn + memslot->npages - 1;
4149 spin_lock(&kvm->mmu_lock);
4151 for (i = PT_PAGE_TABLE_LEVEL;
4152 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4153 unsigned long *rmapp;
4154 unsigned long last_index, index;
4156 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4157 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4159 for (index = 0; index <= last_index; ++index, ++rmapp) {
4161 __rmap_write_protect(kvm, rmapp, false);
4163 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4164 kvm_flush_remote_tlbs(kvm);
4165 cond_resched_lock(&kvm->mmu_lock);
4170 kvm_flush_remote_tlbs(kvm);
4171 spin_unlock(&kvm->mmu_lock);
4174 void kvm_mmu_zap_all(struct kvm *kvm)
4176 struct kvm_mmu_page *sp, *node;
4177 LIST_HEAD(invalid_list);
4179 spin_lock(&kvm->mmu_lock);
4181 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4182 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4185 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4186 spin_unlock(&kvm->mmu_lock);
4189 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4190 struct list_head *invalid_list)
4192 struct kvm_mmu_page *page;
4194 if (list_empty(&kvm->arch.active_mmu_pages))
4197 page = container_of(kvm->arch.active_mmu_pages.prev,
4198 struct kvm_mmu_page, link);
4199 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4202 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4205 int nr_to_scan = sc->nr_to_scan;
4207 if (nr_to_scan == 0)
4210 raw_spin_lock(&kvm_lock);
4212 list_for_each_entry(kvm, &vm_list, vm_list) {
4214 LIST_HEAD(invalid_list);
4217 * Never scan more than sc->nr_to_scan VM instances.
4218 * Will not hit this condition practically since we do not try
4219 * to shrink more than one VM and it is very unlikely to see
4220 * !n_used_mmu_pages so many times.
4225 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4226 * here. We may skip a VM instance errorneosly, but we do not
4227 * want to shrink a VM that only started to populate its MMU
4230 if (!kvm->arch.n_used_mmu_pages)
4233 idx = srcu_read_lock(&kvm->srcu);
4234 spin_lock(&kvm->mmu_lock);
4236 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4237 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4239 spin_unlock(&kvm->mmu_lock);
4240 srcu_read_unlock(&kvm->srcu, idx);
4242 list_move_tail(&kvm->vm_list, &vm_list);
4246 raw_spin_unlock(&kvm_lock);
4249 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4252 static struct shrinker mmu_shrinker = {
4253 .shrink = mmu_shrink,
4254 .seeks = DEFAULT_SEEKS * 10,
4257 static void mmu_destroy_caches(void)
4259 if (pte_list_desc_cache)
4260 kmem_cache_destroy(pte_list_desc_cache);
4261 if (mmu_page_header_cache)
4262 kmem_cache_destroy(mmu_page_header_cache);
4265 int kvm_mmu_module_init(void)
4267 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4268 sizeof(struct pte_list_desc),
4270 if (!pte_list_desc_cache)
4273 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4274 sizeof(struct kvm_mmu_page),
4276 if (!mmu_page_header_cache)
4279 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4282 register_shrinker(&mmu_shrinker);
4287 mmu_destroy_caches();
4292 * Caculate mmu pages needed for kvm.
4294 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4296 unsigned int nr_mmu_pages;
4297 unsigned int nr_pages = 0;
4298 struct kvm_memslots *slots;
4299 struct kvm_memory_slot *memslot;
4301 slots = kvm_memslots(kvm);
4303 kvm_for_each_memslot(memslot, slots)
4304 nr_pages += memslot->npages;
4306 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4307 nr_mmu_pages = max(nr_mmu_pages,
4308 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4310 return nr_mmu_pages;
4313 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4315 struct kvm_shadow_walk_iterator iterator;
4319 walk_shadow_page_lockless_begin(vcpu);
4320 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4321 sptes[iterator.level-1] = spte;
4323 if (!is_shadow_present_pte(spte))
4326 walk_shadow_page_lockless_end(vcpu);
4330 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4332 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4336 destroy_kvm_mmu(vcpu);
4337 free_mmu_pages(vcpu);
4338 mmu_free_memory_caches(vcpu);
4341 void kvm_mmu_module_exit(void)
4343 mmu_destroy_caches();
4344 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4345 unregister_shrinker(&mmu_shrinker);
4346 mmu_audit_disable();