arch/x86/kvm/mmu.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Avi Kivity   <avi@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  */
  20
  21 #include "irq.h"
  22 #include "mmu.h"
  23 #include "x86.h"
  24 #include "kvm_cache_regs.h"
  25
  26 #include <linux/kvm_host.h>
  27 #include <linux/types.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/highmem.h>
  31 #include <linux/module.h>
  32 #include <linux/swap.h>
  33 #include <linux/hugetlb.h>
  34 #include <linux/compiler.h>
  35 #include <linux/srcu.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 #include <asm/page.h>
  40 #include <asm/cmpxchg.h>
  41 #include <asm/io.h>
  42 #include <asm/vmx.h>
  43
  44 /*
  45  * When setting this variable to true it enables Two-Dimensional-Paging
  46  * where the hardware walks 2 page tables:
  47  * 1. the guest-virtual to guest-physical
  48  * 2. while doing 1. it walks guest-physical to host-physical
  49  * If the hardware supports that we don't need to do shadow paging.
  50  */
  51 bool tdp_enabled = false;
  52
  53 enum {
  54         AUDIT_PRE_PAGE_FAULT,
  55         AUDIT_POST_PAGE_FAULT,
  56         AUDIT_PRE_PTE_WRITE,
  57         AUDIT_POST_PTE_WRITE,
  58         AUDIT_PRE_SYNC,
  59         AUDIT_POST_SYNC
  60 };
  61
  62 char *audit_point_name[] = {
  63         "pre page fault",
  64         "post page fault",
  65         "pre pte write",
  66         "post pte write",
  67         "pre sync",
  68         "post sync"
  69 };
  70
  71 #undef MMU_DEBUG
  72
  73 #ifdef MMU_DEBUG
  74
  75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
  76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
  77
  78 #else
  79
  80 #define pgprintk(x...) do { } while (0)
  81 #define rmap_printk(x...) do { } while (0)
  82
  83 #endif
  84
  85 #ifdef MMU_DEBUG
  86 static int dbg = 0;
  87 module_param(dbg, bool, 0644);
  88 #endif
  89
  90 static int oos_shadow = 1;
  91 module_param(oos_shadow, bool, 0644);
  92
  93 #ifndef MMU_DEBUG
  94 #define ASSERT(x) do { } while (0)
  95 #else
  96 #define ASSERT(x)                                                       \
  97         if (!(x)) {                                                     \
  98                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
  99                        __FILE__, __LINE__, #x);                         \
 100         }
 101 #endif
 102
 103 #define PTE_PREFETCH_NUM                8
 104
 105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
 106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 107
 108 #define PT64_LEVEL_BITS 9
 109
 110 #define PT64_LEVEL_SHIFT(level) \
 111                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
 112
 113 #define PT64_INDEX(address, level)\
 114         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
 115
 116
 117 #define PT32_LEVEL_BITS 10
 118
 119 #define PT32_LEVEL_SHIFT(level) \
 120                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
 121
 122 #define PT32_LVL_OFFSET_MASK(level) \
 123         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 124                                                 * PT32_LEVEL_BITS))) - 1))
 125
 126 #define PT32_INDEX(address, level)\
 127         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
 128
 129
 130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
 131 #define PT64_DIR_BASE_ADDR_MASK \
 132         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
 133 #define PT64_LVL_ADDR_MASK(level) \
 134         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 135                                                 * PT64_LEVEL_BITS))) - 1))
 136 #define PT64_LVL_OFFSET_MASK(level) \
 137         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 138                                                 * PT64_LEVEL_BITS))) - 1))
 139
 140 #define PT32_BASE_ADDR_MASK PAGE_MASK
 141 #define PT32_DIR_BASE_ADDR_MASK \
 142         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
 143 #define PT32_LVL_ADDR_MASK(level) \
 144         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 145                                             * PT32_LEVEL_BITS))) - 1))
 146
 147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
 148                         | PT64_NX_MASK)
 149
 150 #define PTE_LIST_EXT 4
 151
 152 #define ACC_EXEC_MASK    1
 153 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
 154 #define ACC_USER_MASK    PT_USER_MASK
 155 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
 156
 157 #include <trace/events/kvm.h>
 158
 159 #define CREATE_TRACE_POINTS
 160 #include "mmutrace.h"
 161
 162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
 163
 164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 165
 166 struct pte_list_desc {
 167         u64 *sptes[PTE_LIST_EXT];
 168         struct pte_list_desc *more;
 169 };
 170
 171 struct kvm_shadow_walk_iterator {
 172         u64 addr;
 173         hpa_t shadow_addr;
 174         u64 *sptep;
 175         int level;
 176         unsigned index;
 177 };
 178
 179 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
 180         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
 181              shadow_walk_okay(&(_walker));                      \
 182              shadow_walk_next(&(_walker)))
 183
 184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
 185         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
 186              shadow_walk_okay(&(_walker)) &&                            \
 187                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
 188              __shadow_walk_next(&(_walker), spte))
 189
 190 static struct kmem_cache *pte_list_desc_cache;
 191 static struct kmem_cache *mmu_page_header_cache;
 192 static struct percpu_counter kvm_total_used_mmu_pages;
 193
 194 static u64 __read_mostly shadow_nx_mask;
 195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
 196 static u64 __read_mostly shadow_user_mask;
 197 static u64 __read_mostly shadow_accessed_mask;
 198 static u64 __read_mostly shadow_dirty_mask;
 199 static u64 __read_mostly shadow_mmio_mask;
 200
 201 static void mmu_spte_set(u64 *sptep, u64 spte);
 202
 203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 204 {
 205         shadow_mmio_mask = mmio_mask;
 206 }
 207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 208
 209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
 210 {
 211         access &= ACC_WRITE_MASK | ACC_USER_MASK;
 212
 213         trace_mark_mmio_spte(sptep, gfn, access);
 214         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
 215 }
 216
 217 static bool is_mmio_spte(u64 spte)
 218 {
 219         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
 220 }
 221
 222 static gfn_t get_mmio_spte_gfn(u64 spte)
 223 {
 224         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
 225 }
 226
 227 static unsigned get_mmio_spte_access(u64 spte)
 228 {
 229         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
 230 }
 231
 232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
 233 {
 234         if (unlikely(is_noslot_pfn(pfn))) {
 235                 mark_mmio_spte(sptep, gfn, access);
 236                 return true;
 237         }
 238
 239         return false;
 240 }
 241
 242 static inline u64 rsvd_bits(int s, int e)
 243 {
 244         return ((1ULL << (e - s + 1)) - 1) << s;
 245 }
 246
 247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
 248                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
 249 {
 250         shadow_user_mask = user_mask;
 251         shadow_accessed_mask = accessed_mask;
 252         shadow_dirty_mask = dirty_mask;
 253         shadow_nx_mask = nx_mask;
 254         shadow_x_mask = x_mask;
 255 }
 256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
 257
 258 static int is_cpuid_PSE36(void)
 259 {
 260         return 1;
 261 }
 262
 263 static int is_nx(struct kvm_vcpu *vcpu)
 264 {
 265         return vcpu->arch.efer & EFER_NX;
 266 }
 267
 268 static int is_shadow_present_pte(u64 pte)
 269 {
 270         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
 271 }
 272
 273 static int is_large_pte(u64 pte)
 274 {
 275         return pte & PT_PAGE_SIZE_MASK;
 276 }
 277
 278 static int is_dirty_gpte(unsigned long pte)
 279 {
 280         return pte & PT_DIRTY_MASK;
 281 }
 282
 283 static int is_rmap_spte(u64 pte)
 284 {
 285         return is_shadow_present_pte(pte);
 286 }
 287
 288 static int is_last_spte(u64 pte, int level)
 289 {
 290         if (level == PT_PAGE_TABLE_LEVEL)
 291                 return 1;
 292         if (is_large_pte(pte))
 293                 return 1;
 294         return 0;
 295 }
 296
 297 static pfn_t spte_to_pfn(u64 pte)
 298 {
 299         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
 300 }
 301
 302 static gfn_t pse36_gfn_delta(u32 gpte)
 303 {
 304         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
 305
 306         return (gpte & PT32_DIR_PSE36_MASK) << shift;
 307 }
 308
 309 #ifdef CONFIG_X86_64
 310 static void __set_spte(u64 *sptep, u64 spte)
 311 {
 312         *sptep = spte;
 313 }
 314
 315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 316 {
 317         *sptep = spte;
 318 }
 319
 320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 321 {
 322         return xchg(sptep, spte);
 323 }
 324
 325 static u64 __get_spte_lockless(u64 *sptep)
 326 {
 327         return ACCESS_ONCE(*sptep);
 328 }
 329
 330 static bool __check_direct_spte_mmio_pf(u64 spte)
 331 {
 332         /* It is valid if the spte is zapped. */
 333         return spte == 0ull;
 334 }
 335 #else
 336 union split_spte {
 337         struct {
 338                 u32 spte_low;
 339                 u32 spte_high;
 340         };
 341         u64 spte;
 342 };
 343
 344 static void count_spte_clear(u64 *sptep, u64 spte)
 345 {
 346         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 347
 348         if (is_shadow_present_pte(spte))
 349                 return;
 350
 351         /* Ensure the spte is completely set before we increase the count */
 352         smp_wmb();
 353         sp->clear_spte_count++;
 354 }
 355
 356 static void __set_spte(u64 *sptep, u64 spte)
 357 {
 358         union split_spte *ssptep, sspte;
 359
 360         ssptep = (union split_spte *)sptep;
 361         sspte = (union split_spte)spte;
 362
 363         ssptep->spte_high = sspte.spte_high;
 364
 365         /*
 366          * If we map the spte from nonpresent to present, We should store
 367          * the high bits firstly, then set present bit, so cpu can not
 368          * fetch this spte while we are setting the spte.
 369          */
 370         smp_wmb();
 371
 372         ssptep->spte_low = sspte.spte_low;
 373 }
 374
 375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 376 {
 377         union split_spte *ssptep, sspte;
 378
 379         ssptep = (union split_spte *)sptep;
 380         sspte = (union split_spte)spte;
 381
 382         ssptep->spte_low = sspte.spte_low;
 383
 384         /*
 385          * If we map the spte from present to nonpresent, we should clear
 386          * present bit firstly to avoid vcpu fetch the old high bits.
 387          */
 388         smp_wmb();
 389
 390         ssptep->spte_high = sspte.spte_high;
 391         count_spte_clear(sptep, spte);
 392 }
 393
 394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 395 {
 396         union split_spte *ssptep, sspte, orig;
 397
 398         ssptep = (union split_spte *)sptep;
 399         sspte = (union split_spte)spte;
 400
 401         /* xchg acts as a barrier before the setting of the high bits */
 402         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
 403         orig.spte_high = ssptep->spte_high;
 404         ssptep->spte_high = sspte.spte_high;
 405         count_spte_clear(sptep, spte);
 406
 407         return orig.spte;
 408 }
 409
 410 /*
 411  * The idea using the light way get the spte on x86_32 guest is from
 412  * gup_get_pte(arch/x86/mm/gup.c).
 413  * The difference is we can not catch the spte tlb flush if we leave
 414  * guest mode, so we emulate it by increase clear_spte_count when spte
 415  * is cleared.
 416  */
 417 static u64 __get_spte_lockless(u64 *sptep)
 418 {
 419         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 420         union split_spte spte, *orig = (union split_spte *)sptep;
 421         int count;
 422
 423 retry:
 424         count = sp->clear_spte_count;
 425         smp_rmb();
 426
 427         spte.spte_low = orig->spte_low;
 428         smp_rmb();
 429
 430         spte.spte_high = orig->spte_high;
 431         smp_rmb();
 432
 433         if (unlikely(spte.spte_low != orig->spte_low ||
 434               count != sp->clear_spte_count))
 435                 goto retry;
 436
 437         return spte.spte;
 438 }
 439
 440 static bool __check_direct_spte_mmio_pf(u64 spte)
 441 {
 442         union split_spte sspte = (union split_spte)spte;
 443         u32 high_mmio_mask = shadow_mmio_mask >> 32;
 444
 445         /* It is valid if the spte is zapped. */
 446         if (spte == 0ull)
 447                 return true;
 448
 449         /* It is valid if the spte is being zapped. */
 450         if (sspte.spte_low == 0ull &&
 451             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
 452                 return true;
 453
 454         return false;
 455 }
 456 #endif
 457
 458 static bool spte_has_volatile_bits(u64 spte)
 459 {
 460         if (!shadow_accessed_mask)
 461                 return false;
 462
 463         if (!is_shadow_present_pte(spte))
 464                 return false;
 465
 466         if ((spte & shadow_accessed_mask) &&
 467               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
 468                 return false;
 469
 470         return true;
 471 }
 472
 473 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
 474 {
 475         return (old_spte & bit_mask) && !(new_spte & bit_mask);
 476 }
 477
 478 /* Rules for using mmu_spte_set:
 479  * Set the sptep from nonpresent to present.
 480  * Note: the sptep being assigned *must* be either not present
 481  * or in a state where the hardware will not attempt to update
 482  * the spte.
 483  */
 484 static void mmu_spte_set(u64 *sptep, u64 new_spte)
 485 {
 486         WARN_ON(is_shadow_present_pte(*sptep));
 487         __set_spte(sptep, new_spte);
 488 }
 489
 490 /* Rules for using mmu_spte_update:
 491  * Update the state bits, it means the mapped pfn is not changged.
 492  */
 493 static void mmu_spte_update(u64 *sptep, u64 new_spte)
 494 {
 495         u64 mask, old_spte = *sptep;
 496
 497         WARN_ON(!is_rmap_spte(new_spte));
 498
 499         if (!is_shadow_present_pte(old_spte))
 500                 return mmu_spte_set(sptep, new_spte);
 501
 502         new_spte |= old_spte & shadow_dirty_mask;
 503
 504         mask = shadow_accessed_mask;
 505         if (is_writable_pte(old_spte))
 506                 mask |= shadow_dirty_mask;
 507
 508         if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
 509                 __update_clear_spte_fast(sptep, new_spte);
 510         else
 511                 old_spte = __update_clear_spte_slow(sptep, new_spte);
 512
 513         if (!shadow_accessed_mask)
 514                 return;
 515
 516         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
 517                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
 518         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
 519                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
 520 }
 521
 522 /*
 523  * Rules for using mmu_spte_clear_track_bits:
 524  * It sets the sptep from present to nonpresent, and track the
 525  * state bits, it is used to clear the last level sptep.
 526  */
 527 static int mmu_spte_clear_track_bits(u64 *sptep)
 528 {
 529         pfn_t pfn;
 530         u64 old_spte = *sptep;
 531
 532         if (!spte_has_volatile_bits(old_spte))
 533                 __update_clear_spte_fast(sptep, 0ull);
 534         else
 535                 old_spte = __update_clear_spte_slow(sptep, 0ull);
 536
 537         if (!is_rmap_spte(old_spte))
 538                 return 0;
 539
 540         pfn = spte_to_pfn(old_spte);
 541         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
 542                 kvm_set_pfn_accessed(pfn);
 543         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
 544                 kvm_set_pfn_dirty(pfn);
 545         return 1;
 546 }
 547
 548 /*
 549  * Rules for using mmu_spte_clear_no_track:
 550  * Directly clear spte without caring the state bits of sptep,
 551  * it is used to set the upper level spte.
 552  */
 553 static void mmu_spte_clear_no_track(u64 *sptep)
 554 {
 555         __update_clear_spte_fast(sptep, 0ull);
 556 }
 557
 558 static u64 mmu_spte_get_lockless(u64 *sptep)
 559 {
 560         return __get_spte_lockless(sptep);
 561 }
 562
 563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
 564 {
 565         rcu_read_lock();
 566         atomic_inc(&vcpu->kvm->arch.reader_counter);
 567
 568         /* Increase the counter before walking shadow page table */
 569         smp_mb__after_atomic_inc();
 570 }
 571
 572 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
 573 {
 574         /* Decrease the counter after walking shadow page table finished */
 575         smp_mb__before_atomic_dec();
 576         atomic_dec(&vcpu->kvm->arch.reader_counter);
 577         rcu_read_unlock();
 578 }
 579
 580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
 581                                   struct kmem_cache *base_cache, int min)
 582 {
 583         void *obj;
 584
 585         if (cache->nobjs >= min)
 586                 return 0;
 587         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 588                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
 589                 if (!obj)
 590                         return -ENOMEM;
 591                 cache->objects[cache->nobjs++] = obj;
 592         }
 593         return 0;
 594 }
 595
 596 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
 597                                   struct kmem_cache *cache)
 598 {
 599         while (mc->nobjs)
 600                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
 601 }
 602
 603 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
 604                                        int min)
 605 {
 606         void *page;
 607
 608         if (cache->nobjs >= min)
 609                 return 0;
 610         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 611                 page = (void *)__get_free_page(GFP_KERNEL);
 612                 if (!page)
 613                         return -ENOMEM;
 614                 cache->objects[cache->nobjs++] = page;
 615         }
 616         return 0;
 617 }
 618
 619 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
 620 {
 621         while (mc->nobjs)
 622                 free_page((unsigned long)mc->objects[--mc->nobjs]);
 623 }
 624
 625 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
 626 {
 627         int r;
 628
 629         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 630                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
 631         if (r)
 632                 goto out;
 633         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
 634         if (r)
 635                 goto out;
 636         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
 637                                    mmu_page_header_cache, 4);
 638 out:
 639         return r;
 640 }
 641
 642 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
 643 {
 644         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 645                                 pte_list_desc_cache);
 646         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
 647         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
 648                                 mmu_page_header_cache);
 649 }
 650
 651 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
 652                                     size_t size)
 653 {
 654         void *p;
 655
 656         BUG_ON(!mc->nobjs);
 657         p = mc->objects[--mc->nobjs];
 658         return p;
 659 }
 660
 661 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
 662 {
 663         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
 664                                       sizeof(struct pte_list_desc));
 665 }
 666
 667 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
 668 {
 669         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
 670 }
 671
 672 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
 673 {
 674         if (!sp->role.direct)
 675                 return sp->gfns[index];
 676
 677         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
 678 }
 679
 680 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
 681 {
 682         if (sp->role.direct)
 683                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
 684         else
 685                 sp->gfns[index] = gfn;
 686 }
 687
 688 /*
 689  * Return the pointer to the large page information for a given gfn,
 690  * handling slots that are not large page aligned.
 691  */
 692 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
 693                                               struct kvm_memory_slot *slot,
 694                                               int level)
 695 {
 696         unsigned long idx;
 697
 698         idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
 699               (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
 700         return &slot->lpage_info[level - 2][idx];
 701 }
 702
 703 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
 704 {
 705         struct kvm_memory_slot *slot;
 706         struct kvm_lpage_info *linfo;
 707         int i;
 708
 709         slot = gfn_to_memslot(kvm, gfn);
 710         for (i = PT_DIRECTORY_LEVEL;
 711              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 712                 linfo = lpage_info_slot(gfn, slot, i);
 713                 linfo->write_count += 1;
 714         }
 715         kvm->arch.indirect_shadow_pages++;
 716 }
 717
 718 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
 719 {
 720         struct kvm_memory_slot *slot;
 721         struct kvm_lpage_info *linfo;
 722         int i;
 723
 724         slot = gfn_to_memslot(kvm, gfn);
 725         for (i = PT_DIRECTORY_LEVEL;
 726              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 727                 linfo = lpage_info_slot(gfn, slot, i);
 728                 linfo->write_count -= 1;
 729                 WARN_ON(linfo->write_count < 0);
 730         }
 731         kvm->arch.indirect_shadow_pages--;
 732 }
 733
 734 static int has_wrprotected_page(struct kvm *kvm,
 735                                 gfn_t gfn,
 736                                 int level)
 737 {
 738         struct kvm_memory_slot *slot;
 739         struct kvm_lpage_info *linfo;
 740
 741         slot = gfn_to_memslot(kvm, gfn);
 742         if (slot) {
 743                 linfo = lpage_info_slot(gfn, slot, level);
 744                 return linfo->write_count;
 745         }
 746
 747         return 1;
 748 }
 749
 750 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
 751 {
 752         unsigned long page_size;
 753         int i, ret = 0;
 754
 755         page_size = kvm_host_page_size(kvm, gfn);
 756
 757         for (i = PT_PAGE_TABLE_LEVEL;
 758              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
 759                 if (page_size >= KVM_HPAGE_SIZE(i))
 760                         ret = i;
 761                 else
 762                         break;
 763         }
 764
 765         return ret;
 766 }
 767
 768 static struct kvm_memory_slot *
 769 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
 770                             bool no_dirty_log)
 771 {
 772         struct kvm_memory_slot *slot;
 773
 774         slot = gfn_to_memslot(vcpu->kvm, gfn);
 775         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
 776               (no_dirty_log && slot->dirty_bitmap))
 777                 slot = NULL;
 778
 779         return slot;
 780 }
 781
 782 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 783 {
 784         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
 785 }
 786
 787 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 788 {
 789         int host_level, level, max_level;
 790
 791         host_level = host_mapping_level(vcpu->kvm, large_gfn);
 792
 793         if (host_level == PT_PAGE_TABLE_LEVEL)
 794                 return host_level;
 795
 796         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
 797                 kvm_x86_ops->get_lpage_level() : host_level;
 798
 799         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
 800                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
 801                         break;
 802
 803         return level - 1;
 804 }
 805
 806 /*
 807  * Pte mapping structures:
 808  *
 809  * If pte_list bit zero is zero, then pte_list point to the spte.
 810  *
 811  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
 812  * pte_list_desc containing more mappings.
 813  *
 814  * Returns the number of pte entries before the spte was added or zero if
 815  * the spte was not added.
 816  *
 817  */
 818 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
 819                         unsigned long *pte_list)
 820 {
 821         struct pte_list_desc *desc;
 822         int i, count = 0;
 823
 824         if (!*pte_list) {
 825                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
 826                 *pte_list = (unsigned long)spte;
 827         } else if (!(*pte_list & 1)) {
 828                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
 829                 desc = mmu_alloc_pte_list_desc(vcpu);
 830                 desc->sptes[0] = (u64 *)*pte_list;
 831                 desc->sptes[1] = spte;
 832                 *pte_list = (unsigned long)desc | 1;
 833                 ++count;
 834         } else {
 835                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
 836                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 837                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
 838                         desc = desc->more;
 839                         count += PTE_LIST_EXT;
 840                 }
 841                 if (desc->sptes[PTE_LIST_EXT-1]) {
 842                         desc->more = mmu_alloc_pte_list_desc(vcpu);
 843                         desc = desc->more;
 844                 }
 845                 for (i = 0; desc->sptes[i]; ++i)
 846                         ++count;
 847                 desc->sptes[i] = spte;
 848         }
 849         return count;
 850 }
 851
 852 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
 853 {
 854         struct pte_list_desc *desc;
 855         u64 *prev_spte;
 856         int i;
 857
 858         if (!*pte_list)
 859                 return NULL;
 860         else if (!(*pte_list & 1)) {
 861                 if (!spte)
 862                         return (u64 *)*pte_list;
 863                 return NULL;
 864         }
 865         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 866         prev_spte = NULL;
 867         while (desc) {
 868                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
 869                         if (prev_spte == spte)
 870                                 return desc->sptes[i];
 871                         prev_spte = desc->sptes[i];
 872                 }
 873                 desc = desc->more;
 874         }
 875         return NULL;
 876 }
 877
 878 static void
 879 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
 880                            int i, struct pte_list_desc *prev_desc)
 881 {
 882         int j;
 883
 884         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
 885                 ;
 886         desc->sptes[i] = desc->sptes[j];
 887         desc->sptes[j] = NULL;
 888         if (j != 0)
 889                 return;
 890         if (!prev_desc && !desc->more)
 891                 *pte_list = (unsigned long)desc->sptes[0];
 892         else
 893                 if (prev_desc)
 894                         prev_desc->more = desc->more;
 895                 else
 896                         *pte_list = (unsigned long)desc->more | 1;
 897         mmu_free_pte_list_desc(desc);
 898 }
 899
 900 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
 901 {
 902         struct pte_list_desc *desc;
 903         struct pte_list_desc *prev_desc;
 904         int i;
 905
 906         if (!*pte_list) {
 907                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
 908                 BUG();
 909         } else if (!(*pte_list & 1)) {
 910                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
 911                 if ((u64 *)*pte_list != spte) {
 912                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
 913                         BUG();
 914                 }
 915                 *pte_list = 0;
 916         } else {
 917                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
 918                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 919                 prev_desc = NULL;
 920                 while (desc) {
 921                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 922                                 if (desc->sptes[i] == spte) {
 923                                         pte_list_desc_remove_entry(pte_list,
 924                                                                desc, i,
 925                                                                prev_desc);
 926                                         return;
 927                                 }
 928                         prev_desc = desc;
 929                         desc = desc->more;
 930                 }
 931                 pr_err("pte_list_remove: %p many->many\n", spte);
 932                 BUG();
 933         }
 934 }
 935
 936 typedef void (*pte_list_walk_fn) (u64 *spte);
 937 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
 938 {
 939         struct pte_list_desc *desc;
 940         int i;
 941
 942         if (!*pte_list)
 943                 return;
 944
 945         if (!(*pte_list & 1))
 946                 return fn((u64 *)*pte_list);
 947
 948         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 949         while (desc) {
 950                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 951                         fn(desc->sptes[i]);
 952                 desc = desc->more;
 953         }
 954 }
 955
 956 /*
 957  * Take gfn and return the reverse mapping to it.
 958  */
 959 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
 960 {
 961         struct kvm_memory_slot *slot;
 962         struct kvm_lpage_info *linfo;
 963
 964         slot = gfn_to_memslot(kvm, gfn);
 965         if (likely(level == PT_PAGE_TABLE_LEVEL))
 966                 return &slot->rmap[gfn - slot->base_gfn];
 967
 968         linfo = lpage_info_slot(gfn, slot, level);
 969
 970         return &linfo->rmap_pde;
 971 }
 972
 973 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 974 {
 975         struct kvm_mmu_page *sp;
 976         unsigned long *rmapp;
 977
 978         sp = page_header(__pa(spte));
 979         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
 980         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
 981         return pte_list_add(vcpu, spte, rmapp);
 982 }
 983
 984 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
 985 {
 986         return pte_list_next(rmapp, spte);
 987 }
 988
 989 static void rmap_remove(struct kvm *kvm, u64 *spte)
 990 {
 991         struct kvm_mmu_page *sp;
 992         gfn_t gfn;
 993         unsigned long *rmapp;
 994
 995         sp = page_header(__pa(spte));
 996         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
 997         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
 998         pte_list_remove(spte, rmapp);
 999 }
1000
1001 static void drop_spte(struct kvm *kvm, u64 *sptep)
1002 {
1003         if (mmu_spte_clear_track_bits(sptep))
1004                 rmap_remove(kvm, sptep);
1005 }
1006
1007 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1008 {
1009         unsigned long *rmapp;
1010         u64 *spte;
1011         int i, write_protected = 0;
1012
1013         rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
1014
1015         spte = rmap_next(kvm, rmapp, NULL);
1016         while (spte) {
1017                 BUG_ON(!spte);
1018                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1019                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1020                 if (is_writable_pte(*spte)) {
1021                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1022                         write_protected = 1;
1023                 }
1024                 spte = rmap_next(kvm, rmapp, spte);
1025         }
1026
1027         /* check for huge page mappings */
1028         for (i = PT_DIRECTORY_LEVEL;
1029              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1030                 rmapp = gfn_to_rmap(kvm, gfn, i);
1031                 spte = rmap_next(kvm, rmapp, NULL);
1032                 while (spte) {
1033                         BUG_ON(!spte);
1034                         BUG_ON(!(*spte & PT_PRESENT_MASK));
1035                         BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
1036                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1037                         if (is_writable_pte(*spte)) {
1038                                 drop_spte(kvm, spte);
1039                                 --kvm->stat.lpages;
1040                                 spte = NULL;
1041                                 write_protected = 1;
1042                         }
1043                         spte = rmap_next(kvm, rmapp, spte);
1044                 }
1045         }
1046
1047         return write_protected;
1048 }
1049
1050 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1051                            unsigned long data)
1052 {
1053         u64 *spte;
1054         int need_tlb_flush = 0;
1055
1056         while ((spte = rmap_next(kvm, rmapp, NULL))) {
1057                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1058                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1059                 drop_spte(kvm, spte);
1060                 need_tlb_flush = 1;
1061         }
1062         return need_tlb_flush;
1063 }
1064
1065 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1066                              unsigned long data)
1067 {
1068         int need_flush = 0;
1069         u64 *spte, new_spte;
1070         pte_t *ptep = (pte_t *)data;
1071         pfn_t new_pfn;
1072
1073         WARN_ON(pte_huge(*ptep));
1074         new_pfn = pte_pfn(*ptep);
1075         spte = rmap_next(kvm, rmapp, NULL);
1076         while (spte) {
1077                 BUG_ON(!is_shadow_present_pte(*spte));
1078                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1079                 need_flush = 1;
1080                 if (pte_write(*ptep)) {
1081                         drop_spte(kvm, spte);
1082                         spte = rmap_next(kvm, rmapp, NULL);
1083                 } else {
1084                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1085                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1086
1087                         new_spte &= ~PT_WRITABLE_MASK;
1088                         new_spte &= ~SPTE_HOST_WRITEABLE;
1089                         new_spte &= ~shadow_accessed_mask;
1090                         mmu_spte_clear_track_bits(spte);
1091                         mmu_spte_set(spte, new_spte);
1092                         spte = rmap_next(kvm, rmapp, spte);
1093                 }
1094         }
1095         if (need_flush)
1096                 kvm_flush_remote_tlbs(kvm);
1097
1098         return 0;
1099 }
1100
1101 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1102                           unsigned long data,
1103                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1104                                          unsigned long data))
1105 {
1106         int i, j;
1107         int ret;
1108         int retval = 0;
1109         struct kvm_memslots *slots;
1110
1111         slots = kvm_memslots(kvm);
1112
1113         for (i = 0; i < slots->nmemslots; i++) {
1114                 struct kvm_memory_slot *memslot = &slots->memslots[i];
1115                 unsigned long start = memslot->userspace_addr;
1116                 unsigned long end;
1117
1118                 end = start + (memslot->npages << PAGE_SHIFT);
1119                 if (hva >= start && hva < end) {
1120                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1121                         gfn_t gfn = memslot->base_gfn + gfn_offset;
1122
1123                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1124
1125                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1126                                 struct kvm_lpage_info *linfo;
1127
1128                                 linfo = lpage_info_slot(gfn, memslot,
1129                                                         PT_DIRECTORY_LEVEL + j);
1130                                 ret |= handler(kvm, &linfo->rmap_pde, data);
1131                         }
1132                         trace_kvm_age_page(hva, memslot, ret);
1133                         retval |= ret;
1134                 }
1135         }
1136
1137         return retval;
1138 }
1139
1140 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1141 {
1142         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1143 }
1144
1145 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1146 {
1147         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1148 }
1149
1150 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1151                          unsigned long data)
1152 {
1153         u64 *spte;
1154         int young = 0;
1155
1156         /*
1157          * Emulate the accessed bit for EPT, by checking if this page has
1158          * an EPT mapping, and clearing it if it does. On the next access,
1159          * a new EPT mapping will be established.
1160          * This has some overhead, but not as much as the cost of swapping
1161          * out actively used pages or breaking up actively used hugepages.
1162          */
1163         if (!shadow_accessed_mask)
1164                 return kvm_unmap_rmapp(kvm, rmapp, data);
1165
1166         spte = rmap_next(kvm, rmapp, NULL);
1167         while (spte) {
1168                 int _young;
1169                 u64 _spte = *spte;
1170                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1171                 _young = _spte & PT_ACCESSED_MASK;
1172                 if (_young) {
1173                         young = 1;
1174                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1175                 }
1176                 spte = rmap_next(kvm, rmapp, spte);
1177         }
1178         return young;
1179 }
1180
1181 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1182                               unsigned long data)
1183 {
1184         u64 *spte;
1185         int young = 0;
1186
1187         /*
1188          * If there's no access bit in the secondary pte set by the
1189          * hardware it's up to gup-fast/gup to set the access bit in
1190          * the primary pte or in the page structure.
1191          */
1192         if (!shadow_accessed_mask)
1193                 goto out;
1194
1195         spte = rmap_next(kvm, rmapp, NULL);
1196         while (spte) {
1197                 u64 _spte = *spte;
1198                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1199                 young = _spte & PT_ACCESSED_MASK;
1200                 if (young) {
1201                         young = 1;
1202                         break;
1203                 }
1204                 spte = rmap_next(kvm, rmapp, spte);
1205         }
1206 out:
1207         return young;
1208 }
1209
1210 #define RMAP_RECYCLE_THRESHOLD 1000
1211
1212 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1213 {
1214         unsigned long *rmapp;
1215         struct kvm_mmu_page *sp;
1216
1217         sp = page_header(__pa(spte));
1218
1219         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1220
1221         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1222         kvm_flush_remote_tlbs(vcpu->kvm);
1223 }
1224
1225 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1226 {
1227         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1228 }
1229
1230 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1231 {
1232         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1233 }
1234
1235 #ifdef MMU_DEBUG
1236 static int is_empty_shadow_page(u64 *spt)
1237 {
1238         u64 *pos;
1239         u64 *end;
1240
1241         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1242                 if (is_shadow_present_pte(*pos)) {
1243                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1244                                pos, *pos);
1245                         return 0;
1246                 }
1247         return 1;
1248 }
1249 #endif
1250
1251 /*
1252  * This value is the sum of all of the kvm instances's
1253  * kvm->arch.n_used_mmu_pages values.  We need a global,
1254  * aggregate version in order to make the slab shrinker
1255  * faster
1256  */
1257 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1258 {
1259         kvm->arch.n_used_mmu_pages += nr;
1260         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1261 }
1262
1263 /*
1264  * Remove the sp from shadow page cache, after call it,
1265  * we can not find this sp from the cache, and the shadow
1266  * page table is still valid.
1267  * It should be under the protection of mmu lock.
1268  */
1269 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1270 {
1271         ASSERT(is_empty_shadow_page(sp->spt));
1272         hlist_del(&sp->hash_link);
1273         if (!sp->role.direct)
1274                 free_page((unsigned long)sp->gfns);
1275 }
1276
1277 /*
1278  * Free the shadow page table and the sp, we can do it
1279  * out of the protection of mmu lock.
1280  */
1281 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1282 {
1283         list_del(&sp->link);
1284         free_page((unsigned long)sp->spt);
1285         kmem_cache_free(mmu_page_header_cache, sp);
1286 }
1287
1288 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1289 {
1290         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1291 }
1292
1293 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1294                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1295 {
1296         if (!parent_pte)
1297                 return;
1298
1299         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1300 }
1301
1302 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1303                                        u64 *parent_pte)
1304 {
1305         pte_list_remove(parent_pte, &sp->parent_ptes);
1306 }
1307
1308 static void drop_parent_pte(struct kvm_mmu_page *sp,
1309                             u64 *parent_pte)
1310 {
1311         mmu_page_remove_parent_pte(sp, parent_pte);
1312         mmu_spte_clear_no_track(parent_pte);
1313 }
1314
1315 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1316                                                u64 *parent_pte, int direct)
1317 {
1318         struct kvm_mmu_page *sp;
1319         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1320                                         sizeof *sp);
1321         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1322         if (!direct)
1323                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1324                                                   PAGE_SIZE);
1325         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1326         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1327         bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1328         sp->parent_ptes = 0;
1329         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1330         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1331         return sp;
1332 }
1333
1334 static void mark_unsync(u64 *spte);
1335 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1336 {
1337         pte_list_walk(&sp->parent_ptes, mark_unsync);
1338 }
1339
1340 static void mark_unsync(u64 *spte)
1341 {
1342         struct kvm_mmu_page *sp;
1343         unsigned int index;
1344
1345         sp = page_header(__pa(spte));
1346         index = spte - sp->spt;
1347         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1348                 return;
1349         if (sp->unsync_children++)
1350                 return;
1351         kvm_mmu_mark_parents_unsync(sp);
1352 }
1353
1354 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1355                                struct kvm_mmu_page *sp)
1356 {
1357         return 1;
1358 }
1359
1360 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1361 {
1362 }
1363
1364 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1365                                  struct kvm_mmu_page *sp, u64 *spte,
1366                                  const void *pte)
1367 {
1368         WARN_ON(1);
1369 }
1370
1371 #define KVM_PAGE_ARRAY_NR 16
1372
1373 struct kvm_mmu_pages {
1374         struct mmu_page_and_offset {
1375                 struct kvm_mmu_page *sp;
1376                 unsigned int idx;
1377         } page[KVM_PAGE_ARRAY_NR];
1378         unsigned int nr;
1379 };
1380
1381 #define for_each_unsync_children(bitmap, idx)           \
1382         for (idx = find_first_bit(bitmap, 512);         \
1383              idx < 512;                                 \
1384              idx = find_next_bit(bitmap, 512, idx+1))
1385
1386 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1387                          int idx)
1388 {
1389         int i;
1390
1391         if (sp->unsync)
1392                 for (i=0; i < pvec->nr; i++)
1393                         if (pvec->page[i].sp == sp)
1394                                 return 0;
1395
1396         pvec->page[pvec->nr].sp = sp;
1397         pvec->page[pvec->nr].idx = idx;
1398         pvec->nr++;
1399         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1400 }
1401
1402 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1403                            struct kvm_mmu_pages *pvec)
1404 {
1405         int i, ret, nr_unsync_leaf = 0;
1406
1407         for_each_unsync_children(sp->unsync_child_bitmap, i) {
1408                 struct kvm_mmu_page *child;
1409                 u64 ent = sp->spt[i];
1410
1411                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1412                         goto clear_child_bitmap;
1413
1414                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1415
1416                 if (child->unsync_children) {
1417                         if (mmu_pages_add(pvec, child, i))
1418                                 return -ENOSPC;
1419
1420                         ret = __mmu_unsync_walk(child, pvec);
1421                         if (!ret)
1422                                 goto clear_child_bitmap;
1423                         else if (ret > 0)
1424                                 nr_unsync_leaf += ret;
1425                         else
1426                                 return ret;
1427                 } else if (child->unsync) {
1428                         nr_unsync_leaf++;
1429                         if (mmu_pages_add(pvec, child, i))
1430                                 return -ENOSPC;
1431                 } else
1432                          goto clear_child_bitmap;
1433
1434                 continue;
1435
1436 clear_child_bitmap:
1437                 __clear_bit(i, sp->unsync_child_bitmap);
1438                 sp->unsync_children--;
1439                 WARN_ON((int)sp->unsync_children < 0);
1440         }
1441
1442
1443         return nr_unsync_leaf;
1444 }
1445
1446 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1447                            struct kvm_mmu_pages *pvec)
1448 {
1449         if (!sp->unsync_children)
1450                 return 0;
1451
1452         mmu_pages_add(pvec, sp, 0);
1453         return __mmu_unsync_walk(sp, pvec);
1454 }
1455
1456 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1457 {
1458         WARN_ON(!sp->unsync);
1459         trace_kvm_mmu_sync_page(sp);
1460         sp->unsync = 0;
1461         --kvm->stat.mmu_unsync;
1462 }
1463
1464 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1465                                     struct list_head *invalid_list);
1466 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1467                                     struct list_head *invalid_list);
1468
1469 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1470   hlist_for_each_entry(sp, pos,                                         \
1471    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1472         if ((sp)->gfn != (gfn)) {} else
1473
1474 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1475   hlist_for_each_entry(sp, pos,                                         \
1476    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1477                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1478                         (sp)->role.invalid) {} else
1479
1480 /* @sp->gfn should be write-protected at the call site */
1481 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1482                            struct list_head *invalid_list, bool clear_unsync)
1483 {
1484         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1485                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1486                 return 1;
1487         }
1488
1489         if (clear_unsync)
1490                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1491
1492         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1493                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1494                 return 1;
1495         }
1496
1497         kvm_mmu_flush_tlb(vcpu);
1498         return 0;
1499 }
1500
1501 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1502                                    struct kvm_mmu_page *sp)
1503 {
1504         LIST_HEAD(invalid_list);
1505         int ret;
1506
1507         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1508         if (ret)
1509                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1510
1511         return ret;
1512 }
1513
1514 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1515                          struct list_head *invalid_list)
1516 {
1517         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1518 }
1519
1520 /* @gfn should be write-protected at the call site */
1521 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1522 {
1523         struct kvm_mmu_page *s;
1524         struct hlist_node *node;
1525         LIST_HEAD(invalid_list);
1526         bool flush = false;
1527
1528         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1529                 if (!s->unsync)
1530                         continue;
1531
1532                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1533                 kvm_unlink_unsync_page(vcpu->kvm, s);
1534                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1535                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1536                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1537                         continue;
1538                 }
1539                 flush = true;
1540         }
1541
1542         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1543         if (flush)
1544                 kvm_mmu_flush_tlb(vcpu);
1545 }
1546
1547 struct mmu_page_path {
1548         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1549         unsigned int idx[PT64_ROOT_LEVEL-1];
1550 };
1551
1552 #define for_each_sp(pvec, sp, parents, i)                       \
1553                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1554                         sp = pvec.page[i].sp;                   \
1555                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1556                         i = mmu_pages_next(&pvec, &parents, i))
1557
1558 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1559                           struct mmu_page_path *parents,
1560                           int i)
1561 {
1562         int n;
1563
1564         for (n = i+1; n < pvec->nr; n++) {
1565                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1566
1567                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1568                         parents->idx[0] = pvec->page[n].idx;
1569                         return n;
1570                 }
1571
1572                 parents->parent[sp->role.level-2] = sp;
1573                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1574         }
1575
1576         return n;
1577 }
1578
1579 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1580 {
1581         struct kvm_mmu_page *sp;
1582         unsigned int level = 0;
1583
1584         do {
1585                 unsigned int idx = parents->idx[level];
1586
1587                 sp = parents->parent[level];
1588                 if (!sp)
1589                         return;
1590
1591                 --sp->unsync_children;
1592                 WARN_ON((int)sp->unsync_children < 0);
1593                 __clear_bit(idx, sp->unsync_child_bitmap);
1594                 level++;
1595         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1596 }
1597
1598 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1599                                struct mmu_page_path *parents,
1600                                struct kvm_mmu_pages *pvec)
1601 {
1602         parents->parent[parent->role.level-1] = NULL;
1603         pvec->nr = 0;
1604 }
1605
1606 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1607                               struct kvm_mmu_page *parent)
1608 {
1609         int i;
1610         struct kvm_mmu_page *sp;
1611         struct mmu_page_path parents;
1612         struct kvm_mmu_pages pages;
1613         LIST_HEAD(invalid_list);
1614
1615         kvm_mmu_pages_init(parent, &parents, &pages);
1616         while (mmu_unsync_walk(parent, &pages)) {
1617                 int protected = 0;
1618
1619                 for_each_sp(pages, sp, parents, i)
1620                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1621
1622                 if (protected)
1623                         kvm_flush_remote_tlbs(vcpu->kvm);
1624
1625                 for_each_sp(pages, sp, parents, i) {
1626                         kvm_sync_page(vcpu, sp, &invalid_list);
1627                         mmu_pages_clear_parents(&parents);
1628                 }
1629                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1630                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1631                 kvm_mmu_pages_init(parent, &parents, &pages);
1632         }
1633 }
1634
1635 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1636 {
1637         int i;
1638
1639         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1640                 sp->spt[i] = 0ull;
1641 }
1642
1643 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1644                                              gfn_t gfn,
1645                                              gva_t gaddr,
1646                                              unsigned level,
1647                                              int direct,
1648                                              unsigned access,
1649                                              u64 *parent_pte)
1650 {
1651         union kvm_mmu_page_role role;
1652         unsigned quadrant;
1653         struct kvm_mmu_page *sp;
1654         struct hlist_node *node;
1655         bool need_sync = false;
1656
1657         role = vcpu->arch.mmu.base_role;
1658         role.level = level;
1659         role.direct = direct;
1660         if (role.direct)
1661                 role.cr4_pae = 0;
1662         role.access = access;
1663         if (!vcpu->arch.mmu.direct_map
1664             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1665                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1666                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1667                 role.quadrant = quadrant;
1668         }
1669         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1670                 if (!need_sync && sp->unsync)
1671                         need_sync = true;
1672
1673                 if (sp->role.word != role.word)
1674                         continue;
1675
1676                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1677                         break;
1678
1679                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1680                 if (sp->unsync_children) {
1681                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1682                         kvm_mmu_mark_parents_unsync(sp);
1683                 } else if (sp->unsync)
1684                         kvm_mmu_mark_parents_unsync(sp);
1685
1686                 trace_kvm_mmu_get_page(sp, false);
1687                 return sp;
1688         }
1689         ++vcpu->kvm->stat.mmu_cache_miss;
1690         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1691         if (!sp)
1692                 return sp;
1693         sp->gfn = gfn;
1694         sp->role = role;
1695         hlist_add_head(&sp->hash_link,
1696                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1697         if (!direct) {
1698                 if (rmap_write_protect(vcpu->kvm, gfn))
1699                         kvm_flush_remote_tlbs(vcpu->kvm);
1700                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1701                         kvm_sync_pages(vcpu, gfn);
1702
1703                 account_shadowed(vcpu->kvm, gfn);
1704         }
1705         init_shadow_page_table(sp);
1706         trace_kvm_mmu_get_page(sp, true);
1707         return sp;
1708 }
1709
1710 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1711                              struct kvm_vcpu *vcpu, u64 addr)
1712 {
1713         iterator->addr = addr;
1714         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1715         iterator->level = vcpu->arch.mmu.shadow_root_level;
1716
1717         if (iterator->level == PT64_ROOT_LEVEL &&
1718             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1719             !vcpu->arch.mmu.direct_map)
1720                 --iterator->level;
1721
1722         if (iterator->level == PT32E_ROOT_LEVEL) {
1723                 iterator->shadow_addr
1724                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1725                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1726                 --iterator->level;
1727                 if (!iterator->shadow_addr)
1728                         iterator->level = 0;
1729         }
1730 }
1731
1732 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1733 {
1734         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1735                 return false;
1736
1737         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1738         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1739         return true;
1740 }
1741
1742 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1743                                u64 spte)
1744 {
1745         if (is_last_spte(spte, iterator->level)) {
1746                 iterator->level = 0;
1747                 return;
1748         }
1749
1750         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1751         --iterator->level;
1752 }
1753
1754 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1755 {
1756         return __shadow_walk_next(iterator, *iterator->sptep);
1757 }
1758
1759 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1760 {
1761         u64 spte;
1762
1763         spte = __pa(sp->spt)
1764                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1765                 | PT_WRITABLE_MASK | PT_USER_MASK;
1766         mmu_spte_set(sptep, spte);
1767 }
1768
1769 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1770 {
1771         if (is_large_pte(*sptep)) {
1772                 drop_spte(vcpu->kvm, sptep);
1773                 kvm_flush_remote_tlbs(vcpu->kvm);
1774         }
1775 }
1776
1777 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1778                                    unsigned direct_access)
1779 {
1780         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1781                 struct kvm_mmu_page *child;
1782
1783                 /*
1784                  * For the direct sp, if the guest pte's dirty bit
1785                  * changed form clean to dirty, it will corrupt the
1786                  * sp's access: allow writable in the read-only sp,
1787                  * so we should update the spte at this point to get
1788                  * a new sp with the correct access.
1789                  */
1790                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1791                 if (child->role.access == direct_access)
1792                         return;
1793
1794                 drop_parent_pte(child, sptep);
1795                 kvm_flush_remote_tlbs(vcpu->kvm);
1796         }
1797 }
1798
1799 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1800                              u64 *spte)
1801 {
1802         u64 pte;
1803         struct kvm_mmu_page *child;
1804
1805         pte = *spte;
1806         if (is_shadow_present_pte(pte)) {
1807                 if (is_last_spte(pte, sp->role.level))
1808                         drop_spte(kvm, spte);
1809                 else {
1810                         child = page_header(pte & PT64_BASE_ADDR_MASK);
1811                         drop_parent_pte(child, spte);
1812                 }
1813         } else if (is_mmio_spte(pte))
1814                 mmu_spte_clear_no_track(spte);
1815
1816         if (is_large_pte(pte))
1817                 --kvm->stat.lpages;
1818 }
1819
1820 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1821                                          struct kvm_mmu_page *sp)
1822 {
1823         unsigned i;
1824
1825         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1826                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1827 }
1828
1829 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1830 {
1831         mmu_page_remove_parent_pte(sp, parent_pte);
1832 }
1833
1834 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1835 {
1836         int i;
1837         struct kvm_vcpu *vcpu;
1838
1839         kvm_for_each_vcpu(i, vcpu, kvm)
1840                 vcpu->arch.last_pte_updated = NULL;
1841 }
1842
1843 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1844 {
1845         u64 *parent_pte;
1846
1847         while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1848                 drop_parent_pte(sp, parent_pte);
1849 }
1850
1851 static int mmu_zap_unsync_children(struct kvm *kvm,
1852                                    struct kvm_mmu_page *parent,
1853                                    struct list_head *invalid_list)
1854 {
1855         int i, zapped = 0;
1856         struct mmu_page_path parents;
1857         struct kvm_mmu_pages pages;
1858
1859         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1860                 return 0;
1861
1862         kvm_mmu_pages_init(parent, &parents, &pages);
1863         while (mmu_unsync_walk(parent, &pages)) {
1864                 struct kvm_mmu_page *sp;
1865
1866                 for_each_sp(pages, sp, parents, i) {
1867                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1868                         mmu_pages_clear_parents(&parents);
1869                         zapped++;
1870                 }
1871                 kvm_mmu_pages_init(parent, &parents, &pages);
1872         }
1873
1874         return zapped;
1875 }
1876
1877 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1878                                     struct list_head *invalid_list)
1879 {
1880         int ret;
1881
1882         trace_kvm_mmu_prepare_zap_page(sp);
1883         ++kvm->stat.mmu_shadow_zapped;
1884         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1885         kvm_mmu_page_unlink_children(kvm, sp);
1886         kvm_mmu_unlink_parents(kvm, sp);
1887         if (!sp->role.invalid && !sp->role.direct)
1888                 unaccount_shadowed(kvm, sp->gfn);
1889         if (sp->unsync)
1890                 kvm_unlink_unsync_page(kvm, sp);
1891         if (!sp->root_count) {
1892                 /* Count self */
1893                 ret++;
1894                 list_move(&sp->link, invalid_list);
1895                 kvm_mod_used_mmu_pages(kvm, -1);
1896         } else {
1897                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1898                 kvm_reload_remote_mmus(kvm);
1899         }
1900
1901         sp->role.invalid = 1;
1902         kvm_mmu_reset_last_pte_updated(kvm);
1903         return ret;
1904 }
1905
1906 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1907 {
1908         struct kvm_mmu_page *sp;
1909
1910         list_for_each_entry(sp, invalid_list, link)
1911                 kvm_mmu_isolate_page(sp);
1912 }
1913
1914 static void free_pages_rcu(struct rcu_head *head)
1915 {
1916         struct kvm_mmu_page *next, *sp;
1917
1918         sp = container_of(head, struct kvm_mmu_page, rcu);
1919         while (sp) {
1920                 if (!list_empty(&sp->link))
1921                         next = list_first_entry(&sp->link,
1922                                       struct kvm_mmu_page, link);
1923                 else
1924                         next = NULL;
1925                 kvm_mmu_free_page(sp);
1926                 sp = next;
1927         }
1928 }
1929
1930 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1931                                     struct list_head *invalid_list)
1932 {
1933         struct kvm_mmu_page *sp;
1934
1935         if (list_empty(invalid_list))
1936                 return;
1937
1938         kvm_flush_remote_tlbs(kvm);
1939
1940         if (atomic_read(&kvm->arch.reader_counter)) {
1941                 kvm_mmu_isolate_pages(invalid_list);
1942                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1943                 list_del_init(invalid_list);
1944
1945                 trace_kvm_mmu_delay_free_pages(sp);
1946                 call_rcu(&sp->rcu, free_pages_rcu);
1947                 return;
1948         }
1949
1950         do {
1951                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1952                 WARN_ON(!sp->role.invalid || sp->root_count);
1953                 kvm_mmu_isolate_page(sp);
1954                 kvm_mmu_free_page(sp);
1955         } while (!list_empty(invalid_list));
1956
1957 }
1958
1959 /*
1960  * Changing the number of mmu pages allocated to the vm
1961  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1962  */
1963 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1964 {
1965         LIST_HEAD(invalid_list);
1966         /*
1967          * If we set the number of mmu pages to be smaller be than the
1968          * number of actived pages , we must to free some mmu pages before we
1969          * change the value
1970          */
1971
1972         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1973                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1974                         !list_empty(&kvm->arch.active_mmu_pages)) {
1975                         struct kvm_mmu_page *page;
1976
1977                         page = container_of(kvm->arch.active_mmu_pages.prev,
1978                                             struct kvm_mmu_page, link);
1979                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1980                 }
1981                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1982                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1983         }
1984
1985         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1986 }
1987
1988 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1989 {
1990         struct kvm_mmu_page *sp;
1991         struct hlist_node *node;
1992         LIST_HEAD(invalid_list);
1993         int r;
1994
1995         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1996         r = 0;
1997
1998         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1999                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2000                          sp->role.word);
2001                 r = 1;
2002                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2003         }
2004         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2005         return r;
2006 }
2007
2008 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
2009 {
2010         struct kvm_mmu_page *sp;
2011         struct hlist_node *node;
2012         LIST_HEAD(invalid_list);
2013
2014         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2015                 pgprintk("%s: zap %llx %x\n",
2016                          __func__, gfn, sp->role.word);
2017                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2018         }
2019         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2020 }
2021
2022 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2023 {
2024         int slot = memslot_id(kvm, gfn);
2025         struct kvm_mmu_page *sp = page_header(__pa(pte));
2026
2027         __set_bit(slot, sp->slot_bitmap);
2028 }
2029
2030 /*
2031  * The function is based on mtrr_type_lookup() in
2032  * arch/x86/kernel/cpu/mtrr/generic.c
2033  */
2034 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2035                          u64 start, u64 end)
2036 {
2037         int i;
2038         u64 base, mask;
2039         u8 prev_match, curr_match;
2040         int num_var_ranges = KVM_NR_VAR_MTRR;
2041
2042         if (!mtrr_state->enabled)
2043                 return 0xFF;
2044
2045         /* Make end inclusive end, instead of exclusive */
2046         end--;
2047
2048         /* Look in fixed ranges. Just return the type as per start */
2049         if (mtrr_state->have_fixed && (start < 0x100000)) {
2050                 int idx;
2051
2052                 if (start < 0x80000) {
2053                         idx = 0;
2054                         idx += (start >> 16);
2055                         return mtrr_state->fixed_ranges[idx];
2056                 } else if (start < 0xC0000) {
2057                         idx = 1 * 8;
2058                         idx += ((start - 0x80000) >> 14);
2059                         return mtrr_state->fixed_ranges[idx];
2060                 } else if (start < 0x1000000) {
2061                         idx = 3 * 8;
2062                         idx += ((start - 0xC0000) >> 12);
2063                         return mtrr_state->fixed_ranges[idx];
2064                 }
2065         }
2066
2067         /*
2068          * Look in variable ranges
2069          * Look of multiple ranges matching this address and pick type
2070          * as per MTRR precedence
2071          */
2072         if (!(mtrr_state->enabled & 2))
2073                 return mtrr_state->def_type;
2074
2075         prev_match = 0xFF;
2076         for (i = 0; i < num_var_ranges; ++i) {
2077                 unsigned short start_state, end_state;
2078
2079                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2080                         continue;
2081
2082                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2083                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2084                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2085                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2086
2087                 start_state = ((start & mask) == (base & mask));
2088                 end_state = ((end & mask) == (base & mask));
2089                 if (start_state != end_state)
2090                         return 0xFE;
2091
2092                 if ((start & mask) != (base & mask))
2093                         continue;
2094
2095                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2096                 if (prev_match == 0xFF) {
2097                         prev_match = curr_match;
2098                         continue;
2099                 }
2100
2101                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2102                     curr_match == MTRR_TYPE_UNCACHABLE)
2103                         return MTRR_TYPE_UNCACHABLE;
2104
2105                 if ((prev_match == MTRR_TYPE_WRBACK &&
2106                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2107                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2108                      curr_match == MTRR_TYPE_WRBACK)) {
2109                         prev_match = MTRR_TYPE_WRTHROUGH;
2110                         curr_match = MTRR_TYPE_WRTHROUGH;
2111                 }
2112
2113                 if (prev_match != curr_match)
2114                         return MTRR_TYPE_UNCACHABLE;
2115         }
2116
2117         if (prev_match != 0xFF)
2118                 return prev_match;
2119
2120         return mtrr_state->def_type;
2121 }
2122
2123 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2124 {
2125         u8 mtrr;
2126
2127         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2128                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2129         if (mtrr == 0xfe || mtrr == 0xff)
2130                 mtrr = MTRR_TYPE_WRBACK;
2131         return mtrr;
2132 }
2133 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2134
2135 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2136 {
2137         trace_kvm_mmu_unsync_page(sp);
2138         ++vcpu->kvm->stat.mmu_unsync;
2139         sp->unsync = 1;
2140
2141         kvm_mmu_mark_parents_unsync(sp);
2142 }
2143
2144 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2145 {
2146         struct kvm_mmu_page *s;
2147         struct hlist_node *node;
2148
2149         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2150                 if (s->unsync)
2151                         continue;
2152                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2153                 __kvm_unsync_page(vcpu, s);
2154         }
2155 }
2156
2157 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2158                                   bool can_unsync)
2159 {
2160         struct kvm_mmu_page *s;
2161         struct hlist_node *node;
2162         bool need_unsync = false;
2163
2164         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2165                 if (!can_unsync)
2166                         return 1;
2167
2168                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2169                         return 1;
2170
2171                 if (!need_unsync && !s->unsync) {
2172                         if (!oos_shadow)
2173                                 return 1;
2174                         need_unsync = true;
2175                 }
2176         }
2177         if (need_unsync)
2178                 kvm_unsync_pages(vcpu, gfn);
2179         return 0;
2180 }
2181
2182 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2183                     unsigned pte_access, int user_fault,
2184                     int write_fault, int level,
2185                     gfn_t gfn, pfn_t pfn, bool speculative,
2186                     bool can_unsync, bool host_writable)
2187 {
2188         u64 spte, entry = *sptep;
2189         int ret = 0;
2190
2191         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2192                 return 0;
2193
2194         /*
2195          * We don't set the accessed bit, since we sometimes want to see
2196          * whether the guest actually used the pte (in order to detect
2197          * demand paging).
2198          */
2199         spte = PT_PRESENT_MASK;
2200         if (!speculative)
2201                 spte |= shadow_accessed_mask;
2202
2203         if (pte_access & ACC_EXEC_MASK)
2204                 spte |= shadow_x_mask;
2205         else
2206                 spte |= shadow_nx_mask;
2207         if (pte_access & ACC_USER_MASK)
2208                 spte |= shadow_user_mask;
2209         if (level > PT_PAGE_TABLE_LEVEL)
2210                 spte |= PT_PAGE_SIZE_MASK;
2211         if (tdp_enabled)
2212                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2213                         kvm_is_mmio_pfn(pfn));
2214
2215         if (host_writable)
2216                 spte |= SPTE_HOST_WRITEABLE;
2217         else
2218                 pte_access &= ~ACC_WRITE_MASK;
2219
2220         spte |= (u64)pfn << PAGE_SHIFT;
2221
2222         if ((pte_access & ACC_WRITE_MASK)
2223             || (!vcpu->arch.mmu.direct_map && write_fault
2224                 && !is_write_protection(vcpu) && !user_fault)) {
2225
2226                 if (level > PT_PAGE_TABLE_LEVEL &&
2227                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2228                         ret = 1;
2229                         drop_spte(vcpu->kvm, sptep);
2230                         goto done;
2231                 }
2232
2233                 spte |= PT_WRITABLE_MASK;
2234
2235                 if (!vcpu->arch.mmu.direct_map
2236                     && !(pte_access & ACC_WRITE_MASK)) {
2237                         spte &= ~PT_USER_MASK;
2238                         /*
2239                          * If we converted a user page to a kernel page,
2240                          * so that the kernel can write to it when cr0.wp=0,
2241                          * then we should prevent the kernel from executing it
2242                          * if SMEP is enabled.
2243                          */
2244                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2245                                 spte |= PT64_NX_MASK;
2246                 }
2247
2248                 /*
2249                  * Optimization: for pte sync, if spte was writable the hash
2250                  * lookup is unnecessary (and expensive). Write protection
2251                  * is responsibility of mmu_get_page / kvm_sync_page.
2252                  * Same reasoning can be applied to dirty page accounting.
2253                  */
2254                 if (!can_unsync && is_writable_pte(*sptep))
2255                         goto set_pte;
2256
2257                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2258                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2259                                  __func__, gfn);
2260                         ret = 1;
2261                         pte_access &= ~ACC_WRITE_MASK;
2262                         if (is_writable_pte(spte))
2263                                 spte &= ~PT_WRITABLE_MASK;
2264                 }
2265         }
2266
2267         if (pte_access & ACC_WRITE_MASK)
2268                 mark_page_dirty(vcpu->kvm, gfn);
2269
2270 set_pte:
2271         mmu_spte_update(sptep, spte);
2272         /*
2273          * If we overwrite a writable spte with a read-only one we
2274          * should flush remote TLBs. Otherwise rmap_write_protect
2275          * will find a read-only spte, even though the writable spte
2276          * might be cached on a CPU's TLB.
2277          */
2278         if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2279                 kvm_flush_remote_tlbs(vcpu->kvm);
2280 done:
2281         return ret;
2282 }
2283
2284 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2285                          unsigned pt_access, unsigned pte_access,
2286                          int user_fault, int write_fault,
2287                          int *emulate, int level, gfn_t gfn,
2288                          pfn_t pfn, bool speculative,
2289                          bool host_writable)
2290 {
2291         int was_rmapped = 0;
2292         int rmap_count;
2293
2294         pgprintk("%s: spte %llx access %x write_fault %d"
2295                  " user_fault %d gfn %llx\n",
2296                  __func__, *sptep, pt_access,
2297                  write_fault, user_fault, gfn);
2298
2299         if (is_rmap_spte(*sptep)) {
2300                 /*
2301                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2302                  * the parent of the now unreachable PTE.
2303                  */
2304                 if (level > PT_PAGE_TABLE_LEVEL &&
2305                     !is_large_pte(*sptep)) {
2306                         struct kvm_mmu_page *child;
2307                         u64 pte = *sptep;
2308
2309                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2310                         drop_parent_pte(child, sptep);
2311                         kvm_flush_remote_tlbs(vcpu->kvm);
2312                 } else if (pfn != spte_to_pfn(*sptep)) {
2313                         pgprintk("hfn old %llx new %llx\n",
2314                                  spte_to_pfn(*sptep), pfn);
2315                         drop_spte(vcpu->kvm, sptep);
2316                         kvm_flush_remote_tlbs(vcpu->kvm);
2317                 } else
2318                         was_rmapped = 1;
2319         }
2320
2321         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2322                       level, gfn, pfn, speculative, true,
2323                       host_writable)) {
2324                 if (write_fault)
2325                         *emulate = 1;
2326                 kvm_mmu_flush_tlb(vcpu);
2327         }
2328
2329         if (unlikely(is_mmio_spte(*sptep) && emulate))
2330                 *emulate = 1;
2331
2332         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2333         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2334                  is_large_pte(*sptep)? "2MB" : "4kB",
2335                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2336                  *sptep, sptep);
2337         if (!was_rmapped && is_large_pte(*sptep))
2338                 ++vcpu->kvm->stat.lpages;
2339
2340         if (is_shadow_present_pte(*sptep)) {
2341                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2342                 if (!was_rmapped) {
2343                         rmap_count = rmap_add(vcpu, sptep, gfn);
2344                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2345                                 rmap_recycle(vcpu, sptep, gfn);
2346                 }
2347         }
2348         kvm_release_pfn_clean(pfn);
2349         if (speculative) {
2350                 vcpu->arch.last_pte_updated = sptep;
2351                 vcpu->arch.last_pte_gfn = gfn;
2352         }
2353 }
2354
2355 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2356 {
2357 }
2358
2359 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2360                                      bool no_dirty_log)
2361 {
2362         struct kvm_memory_slot *slot;
2363         unsigned long hva;
2364
2365         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2366         if (!slot) {
2367                 get_page(fault_page);
2368                 return page_to_pfn(fault_page);
2369         }
2370
2371         hva = gfn_to_hva_memslot(slot, gfn);
2372
2373         return hva_to_pfn_atomic(vcpu->kvm, hva);
2374 }
2375
2376 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2377                                     struct kvm_mmu_page *sp,
2378                                     u64 *start, u64 *end)
2379 {
2380         struct page *pages[PTE_PREFETCH_NUM];
2381         unsigned access = sp->role.access;
2382         int i, ret;
2383         gfn_t gfn;
2384
2385         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2386         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2387                 return -1;
2388
2389         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2390         if (ret <= 0)
2391                 return -1;
2392
2393         for (i = 0; i < ret; i++, gfn++, start++)
2394                 mmu_set_spte(vcpu, start, ACC_ALL,
2395                              access, 0, 0, NULL,
2396                              sp->role.level, gfn,
2397                              page_to_pfn(pages[i]), true, true);
2398
2399         return 0;
2400 }
2401
2402 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2403                                   struct kvm_mmu_page *sp, u64 *sptep)
2404 {
2405         u64 *spte, *start = NULL;
2406         int i;
2407
2408         WARN_ON(!sp->role.direct);
2409
2410         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2411         spte = sp->spt + i;
2412
2413         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2414                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2415                         if (!start)
2416                                 continue;
2417                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2418                                 break;
2419                         start = NULL;
2420                 } else if (!start)
2421                         start = spte;
2422         }
2423 }
2424
2425 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2426 {
2427         struct kvm_mmu_page *sp;
2428
2429         /*
2430          * Since it's no accessed bit on EPT, it's no way to
2431          * distinguish between actually accessed translations
2432          * and prefetched, so disable pte prefetch if EPT is
2433          * enabled.
2434          */
2435         if (!shadow_accessed_mask)
2436                 return;
2437
2438         sp = page_header(__pa(sptep));
2439         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2440                 return;
2441
2442         __direct_pte_prefetch(vcpu, sp, sptep);
2443 }
2444
2445 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2446                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2447                         bool prefault)
2448 {
2449         struct kvm_shadow_walk_iterator iterator;
2450         struct kvm_mmu_page *sp;
2451         int emulate = 0;
2452         gfn_t pseudo_gfn;
2453
2454         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2455                 return 0;
2456
2457         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2458                 if (iterator.level == level) {
2459                         unsigned pte_access = ACC_ALL;
2460
2461                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2462                                      0, write, &emulate,
2463                                      level, gfn, pfn, prefault, map_writable);
2464                         direct_pte_prefetch(vcpu, iterator.sptep);
2465                         ++vcpu->stat.pf_fixed;
2466                         break;
2467                 }
2468
2469                 if (!is_shadow_present_pte(*iterator.sptep)) {
2470                         u64 base_addr = iterator.addr;
2471
2472                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2473                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2474                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2475                                               iterator.level - 1,
2476                                               1, ACC_ALL, iterator.sptep);
2477                         if (!sp) {
2478                                 pgprintk("nonpaging_map: ENOMEM\n");
2479                                 kvm_release_pfn_clean(pfn);
2480                                 return -ENOMEM;
2481                         }
2482
2483                         mmu_spte_set(iterator.sptep,
2484                                      __pa(sp->spt)
2485                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2486                                      | shadow_user_mask | shadow_x_mask
2487                                      | shadow_accessed_mask);
2488                 }
2489         }
2490         return emulate;
2491 }
2492
2493 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2494 {
2495         siginfo_t info;
2496
2497         info.si_signo   = SIGBUS;
2498         info.si_errno   = 0;
2499         info.si_code    = BUS_MCEERR_AR;
2500         info.si_addr    = (void __user *)address;
2501         info.si_addr_lsb = PAGE_SHIFT;
2502
2503         send_sig_info(SIGBUS, &info, tsk);
2504 }
2505
2506 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2507 {
2508         kvm_release_pfn_clean(pfn);
2509         if (is_hwpoison_pfn(pfn)) {
2510                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2511                 return 0;
2512         }
2513
2514         return -EFAULT;
2515 }
2516
2517 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2518                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2519 {
2520         pfn_t pfn = *pfnp;
2521         gfn_t gfn = *gfnp;
2522         int level = *levelp;
2523
2524         /*
2525          * Check if it's a transparent hugepage. If this would be an
2526          * hugetlbfs page, level wouldn't be set to
2527          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2528          * here.
2529          */
2530         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2531             level == PT_PAGE_TABLE_LEVEL &&
2532             PageTransCompound(pfn_to_page(pfn)) &&
2533             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2534                 unsigned long mask;
2535                 /*
2536                  * mmu_notifier_retry was successful and we hold the
2537                  * mmu_lock here, so the pmd can't become splitting
2538                  * from under us, and in turn
2539                  * __split_huge_page_refcount() can't run from under
2540                  * us and we can safely transfer the refcount from
2541                  * PG_tail to PG_head as we switch the pfn to tail to
2542                  * head.
2543                  */
2544                 *levelp = level = PT_DIRECTORY_LEVEL;
2545                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2546                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2547                 if (pfn & mask) {
2548                         gfn &= ~mask;
2549                         *gfnp = gfn;
2550                         kvm_release_pfn_clean(pfn);
2551                         pfn &= ~mask;
2552                         if (!get_page_unless_zero(pfn_to_page(pfn)))
2553                                 BUG();
2554                         *pfnp = pfn;
2555                 }
2556         }
2557 }
2558
2559 static bool mmu_invalid_pfn(pfn_t pfn)
2560 {
2561         return unlikely(is_invalid_pfn(pfn));
2562 }
2563
2564 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2565                                 pfn_t pfn, unsigned access, int *ret_val)
2566 {
2567         bool ret = true;
2568
2569         /* The pfn is invalid, report the error! */
2570         if (unlikely(is_invalid_pfn(pfn))) {
2571                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2572                 goto exit;
2573         }
2574
2575         if (unlikely(is_noslot_pfn(pfn)))
2576                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2577
2578         ret = false;
2579 exit:
2580         return ret;
2581 }
2582
2583 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2584                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2585
2586 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2587                          bool prefault)
2588 {
2589         int r;
2590         int level;
2591         int force_pt_level;
2592         pfn_t pfn;
2593         unsigned long mmu_seq;
2594         bool map_writable;
2595
2596         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2597         if (likely(!force_pt_level)) {
2598                 level = mapping_level(vcpu, gfn);
2599                 /*
2600                  * This path builds a PAE pagetable - so we can map
2601                  * 2mb pages at maximum. Therefore check if the level
2602                  * is larger than that.
2603                  */
2604                 if (level > PT_DIRECTORY_LEVEL)
2605                         level = PT_DIRECTORY_LEVEL;
2606
2607                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2608         } else
2609                 level = PT_PAGE_TABLE_LEVEL;
2610
2611         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2612         smp_rmb();
2613
2614         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2615                 return 0;
2616
2617         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2618                 return r;
2619
2620         spin_lock(&vcpu->kvm->mmu_lock);
2621         if (mmu_notifier_retry(vcpu, mmu_seq))
2622                 goto out_unlock;
2623         kvm_mmu_free_some_pages(vcpu);
2624         if (likely(!force_pt_level))
2625                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2626         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2627                          prefault);
2628         spin_unlock(&vcpu->kvm->mmu_lock);
2629
2630
2631         return r;
2632
2633 out_unlock:
2634         spin_unlock(&vcpu->kvm->mmu_lock);
2635         kvm_release_pfn_clean(pfn);
2636         return 0;
2637 }
2638
2639
2640 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2641 {
2642         int i;
2643         struct kvm_mmu_page *sp;
2644         LIST_HEAD(invalid_list);
2645
2646         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2647                 return;
2648         spin_lock(&vcpu->kvm->mmu_lock);
2649         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2650             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2651              vcpu->arch.mmu.direct_map)) {
2652                 hpa_t root = vcpu->arch.mmu.root_hpa;
2653
2654                 sp = page_header(root);
2655                 --sp->root_count;
2656                 if (!sp->root_count && sp->role.invalid) {
2657                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2658                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2659                 }
2660                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2661                 spin_unlock(&vcpu->kvm->mmu_lock);
2662                 return;
2663         }
2664         for (i = 0; i < 4; ++i) {
2665                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2666
2667                 if (root) {
2668                         root &= PT64_BASE_ADDR_MASK;
2669                         sp = page_header(root);
2670                         --sp->root_count;
2671                         if (!sp->root_count && sp->role.invalid)
2672                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2673                                                          &invalid_list);
2674                 }
2675                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2676         }
2677         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2678         spin_unlock(&vcpu->kvm->mmu_lock);
2679         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2680 }
2681
2682 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2683 {
2684         int ret = 0;
2685
2686         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2687                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2688                 ret = 1;
2689         }
2690
2691         return ret;
2692 }
2693
2694 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2695 {
2696         struct kvm_mmu_page *sp;
2697         unsigned i;
2698
2699         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2700                 spin_lock(&vcpu->kvm->mmu_lock);
2701                 kvm_mmu_free_some_pages(vcpu);
2702                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2703                                       1, ACC_ALL, NULL);
2704                 ++sp->root_count;
2705                 spin_unlock(&vcpu->kvm->mmu_lock);
2706                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2707         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2708                 for (i = 0; i < 4; ++i) {
2709                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2710
2711                         ASSERT(!VALID_PAGE(root));
2712                         spin_lock(&vcpu->kvm->mmu_lock);
2713                         kvm_mmu_free_some_pages(vcpu);
2714                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2715                                               i << 30,
2716                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2717                                               NULL);
2718                         root = __pa(sp->spt);
2719                         ++sp->root_count;
2720                         spin_unlock(&vcpu->kvm->mmu_lock);
2721                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2722                 }
2723                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2724         } else
2725                 BUG();
2726
2727         return 0;
2728 }
2729
2730 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2731 {
2732         struct kvm_mmu_page *sp;
2733         u64 pdptr, pm_mask;
2734         gfn_t root_gfn;
2735         int i;
2736
2737         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2738
2739         if (mmu_check_root(vcpu, root_gfn))
2740                 return 1;
2741
2742         /*
2743          * Do we shadow a long mode page table? If so we need to
2744          * write-protect the guests page table root.
2745          */
2746         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2747                 hpa_t root = vcpu->arch.mmu.root_hpa;
2748
2749                 ASSERT(!VALID_PAGE(root));
2750
2751                 spin_lock(&vcpu->kvm->mmu_lock);
2752                 kvm_mmu_free_some_pages(vcpu);
2753                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2754                                       0, ACC_ALL, NULL);
2755                 root = __pa(sp->spt);
2756                 ++sp->root_count;
2757                 spin_unlock(&vcpu->kvm->mmu_lock);
2758                 vcpu->arch.mmu.root_hpa = root;
2759                 return 0;
2760         }
2761
2762         /*
2763          * We shadow a 32 bit page table. This may be a legacy 2-level
2764          * or a PAE 3-level page table. In either case we need to be aware that
2765          * the shadow page table may be a PAE or a long mode page table.
2766          */
2767         pm_mask = PT_PRESENT_MASK;
2768         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2769                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2770
2771         for (i = 0; i < 4; ++i) {
2772                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2773
2774                 ASSERT(!VALID_PAGE(root));
2775                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2776                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2777                         if (!is_present_gpte(pdptr)) {
2778                                 vcpu->arch.mmu.pae_root[i] = 0;
2779                                 continue;
2780                         }
2781                         root_gfn = pdptr >> PAGE_SHIFT;
2782                         if (mmu_check_root(vcpu, root_gfn))
2783                                 return 1;
2784                 }
2785                 spin_lock(&vcpu->kvm->mmu_lock);
2786                 kvm_mmu_free_some_pages(vcpu);
2787                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2788                                       PT32_ROOT_LEVEL, 0,
2789                                       ACC_ALL, NULL);
2790                 root = __pa(sp->spt);
2791                 ++sp->root_count;
2792                 spin_unlock(&vcpu->kvm->mmu_lock);
2793
2794                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2795         }
2796         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2797
2798         /*
2799          * If we shadow a 32 bit page table with a long mode page
2800          * table we enter this path.
2801          */
2802         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2803                 if (vcpu->arch.mmu.lm_root == NULL) {
2804                         /*
2805                          * The additional page necessary for this is only
2806                          * allocated on demand.
2807                          */
2808
2809                         u64 *lm_root;
2810
2811                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2812                         if (lm_root == NULL)
2813                                 return 1;
2814
2815                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2816
2817                         vcpu->arch.mmu.lm_root = lm_root;
2818                 }
2819
2820                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2821         }
2822
2823         return 0;
2824 }
2825
2826 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2827 {
2828         if (vcpu->arch.mmu.direct_map)
2829                 return mmu_alloc_direct_roots(vcpu);
2830         else
2831                 return mmu_alloc_shadow_roots(vcpu);
2832 }
2833
2834 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2835 {
2836         int i;
2837         struct kvm_mmu_page *sp;
2838
2839         if (vcpu->arch.mmu.direct_map)
2840                 return;
2841
2842         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2843                 return;
2844
2845         vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
2846         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2847         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2848                 hpa_t root = vcpu->arch.mmu.root_hpa;
2849                 sp = page_header(root);
2850                 mmu_sync_children(vcpu, sp);
2851                 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2852                 return;
2853         }
2854         for (i = 0; i < 4; ++i) {
2855                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2856
2857                 if (root && VALID_PAGE(root)) {
2858                         root &= PT64_BASE_ADDR_MASK;
2859                         sp = page_header(root);
2860                         mmu_sync_children(vcpu, sp);
2861                 }
2862         }
2863         trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2864 }
2865
2866 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2867 {
2868         spin_lock(&vcpu->kvm->mmu_lock);
2869         mmu_sync_roots(vcpu);
2870         spin_unlock(&vcpu->kvm->mmu_lock);
2871 }
2872
2873 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2874                                   u32 access, struct x86_exception *exception)
2875 {
2876         if (exception)
2877                 exception->error_code = 0;
2878         return vaddr;
2879 }
2880
2881 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2882                                          u32 access,
2883                                          struct x86_exception *exception)
2884 {
2885         if (exception)
2886                 exception->error_code = 0;
2887         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2888 }
2889
2890 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2891 {
2892         if (direct)
2893                 return vcpu_match_mmio_gpa(vcpu, addr);
2894
2895         return vcpu_match_mmio_gva(vcpu, addr);
2896 }
2897
2898
2899 /*
2900  * On direct hosts, the last spte is only allows two states
2901  * for mmio page fault:
2902  *   - It is the mmio spte
2903  *   - It is zapped or it is being zapped.
2904  *
2905  * This function completely checks the spte when the last spte
2906  * is not the mmio spte.
2907  */
2908 static bool check_direct_spte_mmio_pf(u64 spte)
2909 {
2910         return __check_direct_spte_mmio_pf(spte);
2911 }
2912
2913 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2914 {
2915         struct kvm_shadow_walk_iterator iterator;
2916         u64 spte = 0ull;
2917
2918         walk_shadow_page_lockless_begin(vcpu);
2919         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2920                 if (!is_shadow_present_pte(spte))
2921                         break;
2922         walk_shadow_page_lockless_end(vcpu);
2923
2924         return spte;
2925 }
2926
2927 /*
2928  * If it is a real mmio page fault, return 1 and emulat the instruction
2929  * directly, return 0 to let CPU fault again on the address, -1 is
2930  * returned if bug is detected.
2931  */
2932 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2933 {
2934         u64 spte;
2935
2936         if (quickly_check_mmio_pf(vcpu, addr, direct))
2937                 return 1;
2938
2939         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2940
2941         if (is_mmio_spte(spte)) {
2942                 gfn_t gfn = get_mmio_spte_gfn(spte);
2943                 unsigned access = get_mmio_spte_access(spte);
2944
2945                 if (direct)
2946                         addr = 0;
2947
2948                 trace_handle_mmio_page_fault(addr, gfn, access);
2949                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2950                 return 1;
2951         }
2952
2953         /*
2954          * It's ok if the gva is remapped by other cpus on shadow guest,
2955          * it's a BUG if the gfn is not a mmio page.
2956          */
2957         if (direct && !check_direct_spte_mmio_pf(spte))
2958                 return -1;
2959
2960         /*
2961          * If the page table is zapped by other cpus, let CPU fault again on
2962          * the address.
2963          */
2964         return 0;
2965 }
2966 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2967
2968 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2969                                   u32 error_code, bool direct)
2970 {
2971         int ret;
2972
2973         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2974         WARN_ON(ret < 0);
2975         return ret;
2976 }
2977
2978 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2979                                 u32 error_code, bool prefault)
2980 {
2981         gfn_t gfn;
2982         int r;
2983
2984         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2985
2986         if (unlikely(error_code & PFERR_RSVD_MASK))
2987                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2988
2989         r = mmu_topup_memory_caches(vcpu);
2990         if (r)
2991                 return r;
2992
2993         ASSERT(vcpu);
2994         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2995
2996         gfn = gva >> PAGE_SHIFT;
2997
2998         return nonpaging_map(vcpu, gva & PAGE_MASK,
2999                              error_code & PFERR_WRITE_MASK, gfn, prefault);
3000 }
3001
3002 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3003 {
3004         struct kvm_arch_async_pf arch;
3005
3006         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3007         arch.gfn = gfn;
3008         arch.direct_map = vcpu->arch.mmu.direct_map;
3009         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3010
3011         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3012 }
3013
3014 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3015 {
3016         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3017                      kvm_event_needs_reinjection(vcpu)))
3018                 return false;
3019
3020         if (is_guest_mode(vcpu))
3021                 return false;
3022
3023         return kvm_x86_ops->interrupt_allowed(vcpu);
3024 }
3025
3026 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3027                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3028 {
3029         bool async;
3030
3031         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3032
3033         if (!async)
3034                 return false; /* *pfn has correct page already */
3035
3036         put_page(pfn_to_page(*pfn));
3037
3038         if (!prefault && kvm_can_do_async_pf(vcpu)) {
3039                 trace_kvm_try_async_get_page(gva, gfn);
3040                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3041                         trace_kvm_async_pf_doublefault(gva, gfn);
3042                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3043                         return true;
3044                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3045                         return true;
3046         }
3047
3048         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3049
3050         return false;
3051 }
3052
3053 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3054                           bool prefault)
3055 {
3056         pfn_t pfn;
3057         int r;
3058         int level;
3059         int force_pt_level;
3060         gfn_t gfn = gpa >> PAGE_SHIFT;
3061         unsigned long mmu_seq;
3062         int write = error_code & PFERR_WRITE_MASK;
3063         bool map_writable;
3064
3065         ASSERT(vcpu);
3066         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3067
3068         if (unlikely(error_code & PFERR_RSVD_MASK))
3069                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3070
3071         r = mmu_topup_memory_caches(vcpu);
3072         if (r)
3073                 return r;
3074
3075         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3076         if (likely(!force_pt_level)) {
3077                 level = mapping_level(vcpu, gfn);
3078                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3079         } else
3080                 level = PT_PAGE_TABLE_LEVEL;
3081
3082         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3083         smp_rmb();
3084
3085         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3086                 return 0;
3087
3088         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3089                 return r;
3090
3091         spin_lock(&vcpu->kvm->mmu_lock);
3092         if (mmu_notifier_retry(vcpu, mmu_seq))
3093                 goto out_unlock;
3094         kvm_mmu_free_some_pages(vcpu);
3095         if (likely(!force_pt_level))
3096                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3097         r = __direct_map(vcpu, gpa, write, map_writable,
3098                          level, gfn, pfn, prefault);
3099         spin_unlock(&vcpu->kvm->mmu_lock);
3100
3101         return r;
3102
3103 out_unlock:
3104         spin_unlock(&vcpu->kvm->mmu_lock);
3105         kvm_release_pfn_clean(pfn);
3106         return 0;
3107 }
3108
3109 static void nonpaging_free(struct kvm_vcpu *vcpu)
3110 {
3111         mmu_free_roots(vcpu);
3112 }
3113
3114 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3115                                   struct kvm_mmu *context)
3116 {
3117         context->new_cr3 = nonpaging_new_cr3;
3118         context->page_fault = nonpaging_page_fault;
3119         context->gva_to_gpa = nonpaging_gva_to_gpa;
3120         context->free = nonpaging_free;
3121         context->sync_page = nonpaging_sync_page;
3122         context->invlpg = nonpaging_invlpg;
3123         context->update_pte = nonpaging_update_pte;
3124         context->root_level = 0;
3125         context->shadow_root_level = PT32E_ROOT_LEVEL;
3126         context->root_hpa = INVALID_PAGE;
3127         context->direct_map = true;
3128         context->nx = false;
3129         return 0;
3130 }
3131
3132 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3133 {
3134         ++vcpu->stat.tlb_flush;
3135         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3136 }
3137
3138 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3139 {
3140         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3141         mmu_free_roots(vcpu);
3142 }
3143
3144 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3145 {
3146         return kvm_read_cr3(vcpu);
3147 }
3148
3149 static void inject_page_fault(struct kvm_vcpu *vcpu,
3150                               struct x86_exception *fault)
3151 {
3152         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3153 }
3154
3155 static void paging_free(struct kvm_vcpu *vcpu)
3156 {
3157         nonpaging_free(vcpu);
3158 }
3159
3160 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3161 {
3162         int bit7;
3163
3164         bit7 = (gpte >> 7) & 1;
3165         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3166 }
3167
3168 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3169                            int *nr_present)
3170 {
3171         if (unlikely(is_mmio_spte(*sptep))) {
3172                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3173                         mmu_spte_clear_no_track(sptep);
3174                         return true;
3175                 }
3176
3177                 (*nr_present)++;
3178                 mark_mmio_spte(sptep, gfn, access);
3179                 return true;
3180         }
3181
3182         return false;
3183 }
3184
3185 #define PTTYPE 64
3186 #include "paging_tmpl.h"
3187 #undef PTTYPE
3188
3189 #define PTTYPE 32
3190 #include "paging_tmpl.h"
3191 #undef PTTYPE
3192
3193 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3194                                   struct kvm_mmu *context,
3195                                   int level)
3196 {
3197         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3198         u64 exb_bit_rsvd = 0;
3199
3200         if (!context->nx)
3201                 exb_bit_rsvd = rsvd_bits(63, 63);
3202         switch (level) {
3203         case PT32_ROOT_LEVEL:
3204                 /* no rsvd bits for 2 level 4K page table entries */
3205                 context->rsvd_bits_mask[0][1] = 0;
3206                 context->rsvd_bits_mask[0][0] = 0;
3207                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3208
3209                 if (!is_pse(vcpu)) {
3210                         context->rsvd_bits_mask[1][1] = 0;
3211                         break;
3212                 }
3213
3214                 if (is_cpuid_PSE36())
3215                         /* 36bits PSE 4MB page */
3216                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3217                 else
3218                         /* 32 bits PSE 4MB page */
3219                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3220                 break;
3221         case PT32E_ROOT_LEVEL:
3222                 context->rsvd_bits_mask[0][2] =
3223                         rsvd_bits(maxphyaddr, 63) |
3224                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3225                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3226                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3227                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3228                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3229                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3230                         rsvd_bits(maxphyaddr, 62) |
3231                         rsvd_bits(13, 20);              /* large page */
3232                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3233                 break;
3234         case PT64_ROOT_LEVEL:
3235                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3236                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3237                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3238                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3239                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3240                         rsvd_bits(maxphyaddr, 51);
3241                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3242                         rsvd_bits(maxphyaddr, 51);
3243                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3244                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3245                         rsvd_bits(maxphyaddr, 51) |
3246                         rsvd_bits(13, 29);
3247                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3248                         rsvd_bits(maxphyaddr, 51) |
3249                         rsvd_bits(13, 20);              /* large page */
3250                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3251                 break;
3252         }
3253 }
3254
3255 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3256                                         struct kvm_mmu *context,
3257                                         int level)
3258 {
3259         context->nx = is_nx(vcpu);
3260
3261         reset_rsvds_bits_mask(vcpu, context, level);
3262
3263         ASSERT(is_pae(vcpu));
3264         context->new_cr3 = paging_new_cr3;
3265         context->page_fault = paging64_page_fault;
3266         context->gva_to_gpa = paging64_gva_to_gpa;
3267         context->sync_page = paging64_sync_page;
3268         context->invlpg = paging64_invlpg;
3269         context->update_pte = paging64_update_pte;
3270         context->free = paging_free;
3271         context->root_level = level;
3272         context->shadow_root_level = level;
3273         context->root_hpa = INVALID_PAGE;
3274         context->direct_map = false;
3275         return 0;
3276 }
3277
3278 static int paging64_init_context(struct kvm_vcpu *vcpu,
3279                                  struct kvm_mmu *context)
3280 {
3281         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3282 }
3283
3284 static int paging32_init_context(struct kvm_vcpu *vcpu,
3285                                  struct kvm_mmu *context)
3286 {
3287         context->nx = false;
3288
3289         reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3290
3291         context->new_cr3 = paging_new_cr3;
3292         context->page_fault = paging32_page_fault;
3293         context->gva_to_gpa = paging32_gva_to_gpa;
3294         context->free = paging_free;
3295         context->sync_page = paging32_sync_page;
3296         context->invlpg = paging32_invlpg;
3297         context->update_pte = paging32_update_pte;
3298         context->root_level = PT32_ROOT_LEVEL;
3299         context->shadow_root_level = PT32E_ROOT_LEVEL;
3300         context->root_hpa = INVALID_PAGE;
3301         context->direct_map = false;
3302         return 0;
3303 }
3304
3305 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3306                                   struct kvm_mmu *context)
3307 {
3308         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3309 }
3310
3311 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3312 {
3313         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3314
3315         context->base_role.word = 0;
3316         context->new_cr3 = nonpaging_new_cr3;
3317         context->page_fault = tdp_page_fault;
3318         context->free = nonpaging_free;
3319         context->sync_page = nonpaging_sync_page;
3320         context->invlpg = nonpaging_invlpg;
3321         context->update_pte = nonpaging_update_pte;
3322         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3323         context->root_hpa = INVALID_PAGE;
3324         context->direct_map = true;
3325         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3326         context->get_cr3 = get_cr3;
3327         context->get_pdptr = kvm_pdptr_read;
3328         context->inject_page_fault = kvm_inject_page_fault;
3329         context->nx = is_nx(vcpu);
3330
3331         if (!is_paging(vcpu)) {
3332                 context->nx = false;
3333                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3334                 context->root_level = 0;
3335         } else if (is_long_mode(vcpu)) {
3336                 context->nx = is_nx(vcpu);
3337                 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3338                 context->gva_to_gpa = paging64_gva_to_gpa;
3339                 context->root_level = PT64_ROOT_LEVEL;
3340         } else if (is_pae(vcpu)) {
3341                 context->nx = is_nx(vcpu);
3342                 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3343                 context->gva_to_gpa = paging64_gva_to_gpa;
3344                 context->root_level = PT32E_ROOT_LEVEL;
3345         } else {
3346                 context->nx = false;
3347                 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3348                 context->gva_to_gpa = paging32_gva_to_gpa;
3349                 context->root_level = PT32_ROOT_LEVEL;
3350         }
3351
3352         return 0;
3353 }
3354
3355 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3356 {
3357         int r;
3358         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3359         ASSERT(vcpu);
3360         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3361
3362         if (!is_paging(vcpu))
3363                 r = nonpaging_init_context(vcpu, context);
3364         else if (is_long_mode(vcpu))
3365                 r = paging64_init_context(vcpu, context);
3366         else if (is_pae(vcpu))
3367                 r = paging32E_init_context(vcpu, context);
3368         else
3369                 r = paging32_init_context(vcpu, context);
3370
3371         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3372         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3373         vcpu->arch.mmu.base_role.smep_andnot_wp
3374                 = smep && !is_write_protection(vcpu);
3375
3376         return r;
3377 }
3378 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3379
3380 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3381 {
3382         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3383
3384         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3385         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3386         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3387         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3388
3389         return r;
3390 }
3391
3392 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3393 {
3394         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3395
3396         g_context->get_cr3           = get_cr3;
3397         g_context->get_pdptr         = kvm_pdptr_read;
3398         g_context->inject_page_fault = kvm_inject_page_fault;
3399
3400         /*
3401          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3402          * translation of l2_gpa to l1_gpa addresses is done using the
3403          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3404          * functions between mmu and nested_mmu are swapped.
3405          */
3406         if (!is_paging(vcpu)) {
3407                 g_context->nx = false;
3408                 g_context->root_level = 0;
3409                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3410         } else if (is_long_mode(vcpu)) {
3411                 g_context->nx = is_nx(vcpu);
3412                 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3413                 g_context->root_level = PT64_ROOT_LEVEL;
3414                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3415         } else if (is_pae(vcpu)) {
3416                 g_context->nx = is_nx(vcpu);
3417                 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3418                 g_context->root_level = PT32E_ROOT_LEVEL;
3419                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3420         } else {
3421                 g_context->nx = false;
3422                 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3423                 g_context->root_level = PT32_ROOT_LEVEL;
3424                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3425         }
3426
3427         return 0;
3428 }
3429
3430 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3431 {
3432         if (mmu_is_nested(vcpu))
3433                 return init_kvm_nested_mmu(vcpu);
3434         else if (tdp_enabled)
3435                 return init_kvm_tdp_mmu(vcpu);
3436         else
3437                 return init_kvm_softmmu(vcpu);
3438 }
3439
3440 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3441 {
3442         ASSERT(vcpu);
3443         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3444                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3445                 vcpu->arch.mmu.free(vcpu);
3446 }
3447
3448 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3449 {
3450         destroy_kvm_mmu(vcpu);
3451         return init_kvm_mmu(vcpu);
3452 }
3453 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3454
3455 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3456 {
3457         int r;
3458
3459         r = mmu_topup_memory_caches(vcpu);
3460         if (r)
3461                 goto out;
3462         r = mmu_alloc_roots(vcpu);
3463         spin_lock(&vcpu->kvm->mmu_lock);
3464         mmu_sync_roots(vcpu);
3465         spin_unlock(&vcpu->kvm->mmu_lock);
3466         if (r)
3467                 goto out;
3468         /* set_cr3() should ensure TLB has been flushed */
3469         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3470 out:
3471         return r;
3472 }
3473 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3474
3475 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3476 {
3477         mmu_free_roots(vcpu);
3478 }
3479 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3480
3481 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3482                                   struct kvm_mmu_page *sp, u64 *spte,
3483                                   const void *new)
3484 {
3485         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3486                 ++vcpu->kvm->stat.mmu_pde_zapped;
3487                 return;
3488         }
3489
3490         ++vcpu->kvm->stat.mmu_pte_updated;
3491         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3492 }
3493
3494 static bool need_remote_flush(u64 old, u64 new)
3495 {
3496         if (!is_shadow_present_pte(old))
3497                 return false;
3498         if (!is_shadow_present_pte(new))
3499                 return true;
3500         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3501                 return true;
3502         old ^= PT64_NX_MASK;
3503         new ^= PT64_NX_MASK;
3504         return (old & ~new & PT64_PERM_MASK) != 0;
3505 }
3506
3507 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3508                                     bool remote_flush, bool local_flush)
3509 {
3510         if (zap_page)
3511                 return;
3512
3513         if (remote_flush)
3514                 kvm_flush_remote_tlbs(vcpu->kvm);
3515         else if (local_flush)
3516                 kvm_mmu_flush_tlb(vcpu);
3517 }
3518
3519 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3520 {
3521         u64 *spte = vcpu->arch.last_pte_updated;
3522
3523         return !!(spte && (*spte & shadow_accessed_mask));
3524 }
3525
3526 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3527 {
3528         u64 *spte = vcpu->arch.last_pte_updated;
3529
3530         if (spte
3531             && vcpu->arch.last_pte_gfn == gfn
3532             && shadow_accessed_mask
3533             && !(*spte & shadow_accessed_mask)
3534             && is_shadow_present_pte(*spte))
3535                 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3536 }
3537
3538 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3539                        const u8 *new, int bytes,
3540                        bool guest_initiated)
3541 {
3542         gfn_t gfn = gpa >> PAGE_SHIFT;
3543         union kvm_mmu_page_role mask = { .word = 0 };
3544         struct kvm_mmu_page *sp;
3545         struct hlist_node *node;
3546         LIST_HEAD(invalid_list);
3547         u64 entry, gentry, *spte;
3548         unsigned pte_size, page_offset, misaligned, quadrant, offset;
3549         int level, npte, invlpg_counter, r, flooded = 0;
3550         bool remote_flush, local_flush, zap_page;
3551
3552         /*
3553          * If we don't have indirect shadow pages, it means no page is
3554          * write-protected, so we can exit simply.
3555          */
3556         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3557                 return;
3558
3559         zap_page = remote_flush = local_flush = false;
3560         offset = offset_in_page(gpa);
3561
3562         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3563
3564         invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3565
3566         /*
3567          * Assume that the pte write on a page table of the same type
3568          * as the current vcpu paging mode since we update the sptes only
3569          * when they have the same mode.
3570          */
3571         if ((is_pae(vcpu) && bytes == 4) || !new) {
3572                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3573                 if (is_pae(vcpu)) {
3574                         gpa &= ~(gpa_t)7;
3575                         bytes = 8;
3576                 }
3577                 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3578                 if (r)
3579                         gentry = 0;
3580                 new = (const u8 *)&gentry;
3581         }
3582
3583         switch (bytes) {
3584         case 4:
3585                 gentry = *(const u32 *)new;
3586                 break;
3587         case 8:
3588                 gentry = *(const u64 *)new;
3589                 break;
3590         default:
3591                 gentry = 0;
3592                 break;
3593         }
3594
3595         spin_lock(&vcpu->kvm->mmu_lock);
3596         if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3597                 gentry = 0;
3598         kvm_mmu_free_some_pages(vcpu);
3599         ++vcpu->kvm->stat.mmu_pte_write;
3600         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3601         if (guest_initiated) {
3602                 kvm_mmu_access_page(vcpu, gfn);
3603                 if (gfn == vcpu->arch.last_pt_write_gfn
3604                     && !last_updated_pte_accessed(vcpu)) {
3605                         ++vcpu->arch.last_pt_write_count;
3606                         if (vcpu->arch.last_pt_write_count >= 3)
3607                                 flooded = 1;
3608                 } else {
3609                         vcpu->arch.last_pt_write_gfn = gfn;
3610                         vcpu->arch.last_pt_write_count = 1;
3611                         vcpu->arch.last_pte_updated = NULL;
3612                 }
3613         }
3614
3615         mask.cr0_wp = mask.cr4_pae = mask.nxe = mask.smep_andnot_wp = 1;
3616         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3617                 pte_size = sp->role.cr4_pae ? 8 : 4;
3618                 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3619                 misaligned |= bytes < 4;
3620                 if (misaligned || flooded) {
3621                         /*
3622                          * Misaligned accesses are too much trouble to fix
3623                          * up; also, they usually indicate a page is not used
3624                          * as a page table.
3625                          *
3626                          * If we're seeing too many writes to a page,
3627                          * it may no longer be a page table, or we may be
3628                          * forking, in which case it is better to unmap the
3629                          * page.
3630                          */
3631                         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3632                                  gpa, bytes, sp->role.word);
3633                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3634                                                      &invalid_list);
3635                         ++vcpu->kvm->stat.mmu_flooded;
3636                         continue;
3637                 }
3638                 page_offset = offset;
3639                 level = sp->role.level;
3640                 npte = 1;
3641                 if (!sp->role.cr4_pae) {
3642                         page_offset <<= 1;      /* 32->64 */
3643                         /*
3644                          * A 32-bit pde maps 4MB while the shadow pdes map
3645                          * only 2MB.  So we need to double the offset again
3646                          * and zap two pdes instead of one.
3647                          */
3648                         if (level == PT32_ROOT_LEVEL) {
3649                                 page_offset &= ~7; /* kill rounding error */
3650                                 page_offset <<= 1;
3651                                 npte = 2;
3652                         }
3653                         quadrant = page_offset >> PAGE_SHIFT;
3654                         page_offset &= ~PAGE_MASK;
3655                         if (quadrant != sp->role.quadrant)
3656                                 continue;
3657                 }
3658                 local_flush = true;
3659                 spte = &sp->spt[page_offset / sizeof(*spte)];
3660                 while (npte--) {
3661                         entry = *spte;
3662                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3663                         if (gentry &&
3664                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3665                               & mask.word))
3666                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3667                         if (!remote_flush && need_remote_flush(entry, *spte))
3668                                 remote_flush = true;
3669                         ++spte;
3670                 }
3671         }
3672         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3673         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3674         trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3675         spin_unlock(&vcpu->kvm->mmu_lock);
3676 }
3677
3678 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3679 {
3680         gpa_t gpa;
3681         int r;
3682
3683         if (vcpu->arch.mmu.direct_map)
3684                 return 0;
3685
3686         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3687
3688         spin_lock(&vcpu->kvm->mmu_lock);
3689         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3690         spin_unlock(&vcpu->kvm->mmu_lock);
3691         return r;
3692 }
3693 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3694
3695 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3696 {
3697         LIST_HEAD(invalid_list);
3698
3699         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3700                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3701                 struct kvm_mmu_page *sp;
3702
3703                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3704                                   struct kvm_mmu_page, link);
3705                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3706                 ++vcpu->kvm->stat.mmu_recycled;
3707         }
3708         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3709 }
3710
3711 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3712                        void *insn, int insn_len)
3713 {
3714         int r;
3715         enum emulation_result er;
3716
3717         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3718         if (r < 0)
3719                 goto out;
3720
3721         if (!r) {
3722                 r = 1;
3723                 goto out;
3724         }
3725
3726         r = mmu_topup_memory_caches(vcpu);
3727         if (r)
3728                 goto out;
3729
3730         er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3731
3732         switch (er) {
3733         case EMULATE_DONE:
3734                 return 1;
3735         case EMULATE_DO_MMIO:
3736                 ++vcpu->stat.mmio_exits;
3737                 /* fall through */
3738         case EMULATE_FAIL:
3739                 return 0;
3740         default:
3741                 BUG();
3742         }
3743 out:
3744         return r;
3745 }
3746 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3747
3748 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3749 {
3750         vcpu->arch.mmu.invlpg(vcpu, gva);
3751         kvm_mmu_flush_tlb(vcpu);
3752         ++vcpu->stat.invlpg;
3753 }
3754 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3755
3756 void kvm_enable_tdp(void)
3757 {
3758         tdp_enabled = true;
3759 }
3760 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3761
3762 void kvm_disable_tdp(void)
3763 {
3764         tdp_enabled = false;
3765 }
3766 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3767
3768 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3769 {
3770         free_page((unsigned long)vcpu->arch.mmu.pae_root);
3771         if (vcpu->arch.mmu.lm_root != NULL)
3772                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3773 }
3774
3775 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3776 {
3777         struct page *page;
3778         int i;
3779
3780         ASSERT(vcpu);
3781
3782         /*
3783          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3784          * Therefore we need to allocate shadow page tables in the first
3785          * 4GB of memory, which happens to fit the DMA32 zone.
3786          */
3787         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3788         if (!page)
3789                 return -ENOMEM;
3790
3791         vcpu->arch.mmu.pae_root = page_address(page);
3792         for (i = 0; i < 4; ++i)
3793                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3794
3795         return 0;
3796 }
3797
3798 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3799 {
3800         ASSERT(vcpu);
3801         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3802
3803         return alloc_mmu_pages(vcpu);
3804 }
3805
3806 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3807 {
3808         ASSERT(vcpu);
3809         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3810
3811         return init_kvm_mmu(vcpu);
3812 }
3813
3814 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3815 {
3816         struct kvm_mmu_page *sp;
3817
3818         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3819                 int i;
3820                 u64 *pt;
3821
3822                 if (!test_bit(slot, sp->slot_bitmap))
3823                         continue;
3824
3825                 pt = sp->spt;
3826                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3827                         if (!is_shadow_present_pte(pt[i]) ||
3828                               !is_last_spte(pt[i], sp->role.level))
3829                                 continue;
3830
3831                         if (is_large_pte(pt[i])) {
3832                                 drop_spte(kvm, &pt[i]);
3833                                 --kvm->stat.lpages;
3834                                 continue;
3835                         }
3836
3837                         /* avoid RMW */
3838                         if (is_writable_pte(pt[i]))
3839                                 mmu_spte_update(&pt[i],
3840                                                 pt[i] & ~PT_WRITABLE_MASK);
3841                 }
3842         }
3843         kvm_flush_remote_tlbs(kvm);
3844 }
3845
3846 void kvm_mmu_zap_all(struct kvm *kvm)
3847 {
3848         struct kvm_mmu_page *sp, *node;
3849         LIST_HEAD(invalid_list);
3850
3851         spin_lock(&kvm->mmu_lock);
3852 restart:
3853         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3854                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3855                         goto restart;
3856
3857         kvm_mmu_commit_zap_page(kvm, &invalid_list);
3858         spin_unlock(&kvm->mmu_lock);
3859 }
3860
3861 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3862                                                struct list_head *invalid_list)
3863 {
3864         struct kvm_mmu_page *page;
3865
3866         page = container_of(kvm->arch.active_mmu_pages.prev,
3867                             struct kvm_mmu_page, link);
3868         return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3869 }
3870
3871 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3872 {
3873         struct kvm *kvm;
3874         struct kvm *kvm_freed = NULL;
3875         int nr_to_scan = sc->nr_to_scan;
3876
3877         if (nr_to_scan == 0)
3878                 goto out;
3879
3880         raw_spin_lock(&kvm_lock);
3881
3882         list_for_each_entry(kvm, &vm_list, vm_list) {
3883                 int idx, freed_pages;
3884                 LIST_HEAD(invalid_list);
3885
3886                 idx = srcu_read_lock(&kvm->srcu);
3887                 spin_lock(&kvm->mmu_lock);
3888                 if (!kvm_freed && nr_to_scan > 0 &&
3889                     kvm->arch.n_used_mmu_pages > 0) {
3890                         freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3891                                                           &invalid_list);
3892                         kvm_freed = kvm;
3893                 }
3894                 nr_to_scan--;
3895
3896                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3897                 spin_unlock(&kvm->mmu_lock);
3898                 srcu_read_unlock(&kvm->srcu, idx);
3899         }
3900         if (kvm_freed)
3901                 list_move_tail(&kvm_freed->vm_list, &vm_list);
3902
3903         raw_spin_unlock(&kvm_lock);
3904
3905 out:
3906         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3907 }
3908
3909 static struct shrinker mmu_shrinker = {
3910         .shrink = mmu_shrink,
3911         .seeks = DEFAULT_SEEKS * 10,
3912 };
3913
3914 static void mmu_destroy_caches(void)
3915 {
3916         if (pte_list_desc_cache)
3917                 kmem_cache_destroy(pte_list_desc_cache);
3918         if (mmu_page_header_cache)
3919                 kmem_cache_destroy(mmu_page_header_cache);
3920 }
3921
3922 int kvm_mmu_module_init(void)
3923 {
3924         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3925                                             sizeof(struct pte_list_desc),
3926                                             0, 0, NULL);
3927         if (!pte_list_desc_cache)
3928                 goto nomem;
3929
3930         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3931                                                   sizeof(struct kvm_mmu_page),
3932                                                   0, 0, NULL);
3933         if (!mmu_page_header_cache)
3934                 goto nomem;
3935
3936         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3937                 goto nomem;
3938
3939         register_shrinker(&mmu_shrinker);
3940
3941         return 0;
3942
3943 nomem:
3944         mmu_destroy_caches();
3945         return -ENOMEM;
3946 }
3947
3948 /*
3949  * Caculate mmu pages needed for kvm.
3950  */
3951 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3952 {
3953         int i;
3954         unsigned int nr_mmu_pages;
3955         unsigned int  nr_pages = 0;
3956         struct kvm_memslots *slots;
3957
3958         slots = kvm_memslots(kvm);
3959
3960         for (i = 0; i < slots->nmemslots; i++)
3961                 nr_pages += slots->memslots[i].npages;
3962
3963         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3964         nr_mmu_pages = max(nr_mmu_pages,
3965                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3966
3967         return nr_mmu_pages;
3968 }
3969
3970 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3971                                 unsigned len)
3972 {
3973         if (len > buffer->len)
3974                 return NULL;
3975         return buffer->ptr;
3976 }
3977
3978 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3979                                 unsigned len)
3980 {
3981         void *ret;
3982
3983         ret = pv_mmu_peek_buffer(buffer, len);
3984         if (!ret)
3985                 return ret;
3986         buffer->ptr += len;
3987         buffer->len -= len;
3988         buffer->processed += len;
3989         return ret;
3990 }
3991
3992 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3993                              gpa_t addr, gpa_t value)
3994 {
3995         int bytes = 8;
3996         int r;
3997
3998         if (!is_long_mode(vcpu) && !is_pae(vcpu))
3999                 bytes = 4;
4000
4001         r = mmu_topup_memory_caches(vcpu);
4002         if (r)
4003                 return r;
4004
4005         if (!emulator_write_phys(vcpu, addr, &value, bytes))
4006                 return -EFAULT;
4007
4008         return 1;
4009 }
4010
4011 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
4012 {
4013         (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
4014         return 1;
4015 }
4016
4017 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
4018 {
4019         spin_lock(&vcpu->kvm->mmu_lock);
4020         mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
4021         spin_unlock(&vcpu->kvm->mmu_lock);
4022         return 1;
4023 }
4024
4025 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
4026                              struct kvm_pv_mmu_op_buffer *buffer)
4027 {
4028         struct kvm_mmu_op_header *header;
4029
4030         header = pv_mmu_peek_buffer(buffer, sizeof *header);
4031         if (!header)
4032                 return 0;
4033         switch (header->op) {
4034         case KVM_MMU_OP_WRITE_PTE: {
4035                 struct kvm_mmu_op_write_pte *wpte;
4036
4037                 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
4038                 if (!wpte)
4039                         return 0;
4040                 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
4041                                         wpte->pte_val);
4042         }
4043         case KVM_MMU_OP_FLUSH_TLB: {
4044                 struct kvm_mmu_op_flush_tlb *ftlb;
4045
4046                 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
4047                 if (!ftlb)
4048                         return 0;
4049                 return kvm_pv_mmu_flush_tlb(vcpu);
4050         }
4051         case KVM_MMU_OP_RELEASE_PT: {
4052                 struct kvm_mmu_op_release_pt *rpt;
4053
4054                 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
4055                 if (!rpt)
4056                         return 0;
4057                 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
4058         }
4059         default: return 0;
4060         }
4061 }
4062
4063 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
4064                   gpa_t addr, unsigned long *ret)
4065 {
4066         int r;
4067         struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
4068
4069         buffer->ptr = buffer->buf;
4070         buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
4071         buffer->processed = 0;
4072
4073         r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
4074         if (r)
4075                 goto out;
4076
4077         while (buffer->len) {
4078                 r = kvm_pv_mmu_op_one(vcpu, buffer);
4079                 if (r < 0)
4080                         goto out;
4081                 if (r == 0)
4082                         break;
4083         }
4084
4085         r = 1;
4086 out:
4087         *ret = buffer->processed;
4088         return r;
4089 }
4090
4091 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4092 {
4093         struct kvm_shadow_walk_iterator iterator;
4094         u64 spte;
4095         int nr_sptes = 0;
4096
4097         walk_shadow_page_lockless_begin(vcpu);
4098         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4099                 sptes[iterator.level-1] = spte;
4100                 nr_sptes++;
4101                 if (!is_shadow_present_pte(spte))
4102                         break;
4103         }
4104         walk_shadow_page_lockless_end(vcpu);
4105
4106         return nr_sptes;
4107 }
4108 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4109
4110 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4111 {
4112         ASSERT(vcpu);
4113
4114         destroy_kvm_mmu(vcpu);
4115         free_mmu_pages(vcpu);
4116         mmu_free_memory_caches(vcpu);
4117 }
4118
4119 #ifdef CONFIG_KVM_MMU_AUDIT
4120 #include "mmu_audit.c"
4121 #else
4122 static void mmu_audit_disable(void) { }
4123 #endif
4124
4125 void kvm_mmu_module_exit(void)
4126 {
4127         mmu_destroy_caches();
4128         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4129         unregister_shrinker(&mmu_shrinker);
4130         mmu_audit_disable();
4131 }