arch/powerpc/sysdev/ipic.c

   1 /*
   2  * arch/powerpc/sysdev/ipic.c
   3  *
   4  * IPIC routines implementations.
   5  *
   6  * Copyright 2005 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/slab.h>
  18 #include <linux/stddef.h>
  19 #include <linux/sched.h>
  20 #include <linux/signal.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/device.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/spinlock.h>
  25 #include <asm/irq.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/ipic.h>
  29
  30 #include "ipic.h"
  31
  32 static struct ipic * primary_ipic;
  33 static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
  34 static DEFINE_SPINLOCK(ipic_lock);
  35
  36 static struct ipic_info ipic_info[] = {
  37         [1] = {
  38                 .mask   = IPIC_SIMSR_H,
  39                 .prio   = IPIC_SIPRR_C,
  40                 .force  = IPIC_SIFCR_H,
  41                 .bit    = 16,
  42                 .prio_mask = 0,
  43         },
  44         [2] = {
  45                 .mask   = IPIC_SIMSR_H,
  46                 .prio   = IPIC_SIPRR_C,
  47                 .force  = IPIC_SIFCR_H,
  48                 .bit    = 17,
  49                 .prio_mask = 1,
  50         },
  51         [3] = {
  52                 .mask   = IPIC_SIMSR_H,
  53                 .prio   = IPIC_SIPRR_C,
  54                 .force  = IPIC_SIFCR_H,
  55                 .bit    = 18,
  56                 .prio_mask = 2,
  57         },
  58         [4] = {
  59                 .mask   = IPIC_SIMSR_H,
  60                 .prio   = IPIC_SIPRR_C,
  61                 .force  = IPIC_SIFCR_H,
  62                 .bit    = 19,
  63                 .prio_mask = 3,
  64         },
  65         [5] = {
  66                 .mask   = IPIC_SIMSR_H,
  67                 .prio   = IPIC_SIPRR_C,
  68                 .force  = IPIC_SIFCR_H,
  69                 .bit    = 20,
  70                 .prio_mask = 4,
  71         },
  72         [6] = {
  73                 .mask   = IPIC_SIMSR_H,
  74                 .prio   = IPIC_SIPRR_C,
  75                 .force  = IPIC_SIFCR_H,
  76                 .bit    = 21,
  77                 .prio_mask = 5,
  78         },
  79         [7] = {
  80                 .mask   = IPIC_SIMSR_H,
  81                 .prio   = IPIC_SIPRR_C,
  82                 .force  = IPIC_SIFCR_H,
  83                 .bit    = 22,
  84                 .prio_mask = 6,
  85         },
  86         [8] = {
  87                 .mask   = IPIC_SIMSR_H,
  88                 .prio   = IPIC_SIPRR_C,
  89                 .force  = IPIC_SIFCR_H,
  90                 .bit    = 23,
  91                 .prio_mask = 7,
  92         },
  93         [9] = {
  94                 .mask   = IPIC_SIMSR_H,
  95                 .prio   = IPIC_SIPRR_D,
  96                 .force  = IPIC_SIFCR_H,
  97                 .bit    = 24,
  98                 .prio_mask = 0,
  99         },
 100         [10] = {
 101                 .mask   = IPIC_SIMSR_H,
 102                 .prio   = IPIC_SIPRR_D,
 103                 .force  = IPIC_SIFCR_H,
 104                 .bit    = 25,
 105                 .prio_mask = 1,
 106         },
 107         [11] = {
 108                 .mask   = IPIC_SIMSR_H,
 109                 .prio   = IPIC_SIPRR_D,
 110                 .force  = IPIC_SIFCR_H,
 111                 .bit    = 26,
 112                 .prio_mask = 2,
 113         },
 114         [12] = {
 115                 .mask   = IPIC_SIMSR_H,
 116                 .prio   = IPIC_SIPRR_D,
 117                 .force  = IPIC_SIFCR_H,
 118                 .bit    = 27,
 119                 .prio_mask = 3,
 120         },
 121         [13] = {
 122                 .mask   = IPIC_SIMSR_H,
 123                 .prio   = IPIC_SIPRR_D,
 124                 .force  = IPIC_SIFCR_H,
 125                 .bit    = 28,
 126                 .prio_mask = 4,
 127         },
 128         [14] = {
 129                 .mask   = IPIC_SIMSR_H,
 130                 .prio   = IPIC_SIPRR_D,
 131                 .force  = IPIC_SIFCR_H,
 132                 .bit    = 29,
 133                 .prio_mask = 5,
 134         },
 135         [15] = {
 136                 .mask   = IPIC_SIMSR_H,
 137                 .prio   = IPIC_SIPRR_D,
 138                 .force  = IPIC_SIFCR_H,
 139                 .bit    = 30,
 140                 .prio_mask = 6,
 141         },
 142         [16] = {
 143                 .mask   = IPIC_SIMSR_H,
 144                 .prio   = IPIC_SIPRR_D,
 145                 .force  = IPIC_SIFCR_H,
 146                 .bit    = 31,
 147                 .prio_mask = 7,
 148         },
 149         [17] = {
 150                 .ack    = IPIC_SEPNR,
 151                 .mask   = IPIC_SEMSR,
 152                 .prio   = IPIC_SMPRR_A,
 153                 .force  = IPIC_SEFCR,
 154                 .bit    = 1,
 155                 .prio_mask = 5,
 156         },
 157         [18] = {
 158                 .ack    = IPIC_SEPNR,
 159                 .mask   = IPIC_SEMSR,
 160                 .prio   = IPIC_SMPRR_A,
 161                 .force  = IPIC_SEFCR,
 162                 .bit    = 2,
 163                 .prio_mask = 6,
 164         },
 165         [19] = {
 166                 .ack    = IPIC_SEPNR,
 167                 .mask   = IPIC_SEMSR,
 168                 .prio   = IPIC_SMPRR_A,
 169                 .force  = IPIC_SEFCR,
 170                 .bit    = 3,
 171                 .prio_mask = 7,
 172         },
 173         [20] = {
 174                 .ack    = IPIC_SEPNR,
 175                 .mask   = IPIC_SEMSR,
 176                 .prio   = IPIC_SMPRR_B,
 177                 .force  = IPIC_SEFCR,
 178                 .bit    = 4,
 179                 .prio_mask = 4,
 180         },
 181         [21] = {
 182                 .ack    = IPIC_SEPNR,
 183                 .mask   = IPIC_SEMSR,
 184                 .prio   = IPIC_SMPRR_B,
 185                 .force  = IPIC_SEFCR,
 186                 .bit    = 5,
 187                 .prio_mask = 5,
 188         },
 189         [22] = {
 190                 .ack    = IPIC_SEPNR,
 191                 .mask   = IPIC_SEMSR,
 192                 .prio   = IPIC_SMPRR_B,
 193                 .force  = IPIC_SEFCR,
 194                 .bit    = 6,
 195                 .prio_mask = 6,
 196         },
 197         [23] = {
 198                 .ack    = IPIC_SEPNR,
 199                 .mask   = IPIC_SEMSR,
 200                 .prio   = IPIC_SMPRR_B,
 201                 .force  = IPIC_SEFCR,
 202                 .bit    = 7,
 203                 .prio_mask = 7,
 204         },
 205         [32] = {
 206                 .mask   = IPIC_SIMSR_H,
 207                 .prio   = IPIC_SIPRR_A,
 208                 .force  = IPIC_SIFCR_H,
 209                 .bit    = 0,
 210                 .prio_mask = 0,
 211         },
 212         [33] = {
 213                 .mask   = IPIC_SIMSR_H,
 214                 .prio   = IPIC_SIPRR_A,
 215                 .force  = IPIC_SIFCR_H,
 216                 .bit    = 1,
 217                 .prio_mask = 1,
 218         },
 219         [34] = {
 220                 .mask   = IPIC_SIMSR_H,
 221                 .prio   = IPIC_SIPRR_A,
 222                 .force  = IPIC_SIFCR_H,
 223                 .bit    = 2,
 224                 .prio_mask = 2,
 225         },
 226         [35] = {
 227                 .mask   = IPIC_SIMSR_H,
 228                 .prio   = IPIC_SIPRR_A,
 229                 .force  = IPIC_SIFCR_H,
 230                 .bit    = 3,
 231                 .prio_mask = 3,
 232         },
 233         [36] = {
 234                 .mask   = IPIC_SIMSR_H,
 235                 .prio   = IPIC_SIPRR_A,
 236                 .force  = IPIC_SIFCR_H,
 237                 .bit    = 4,
 238                 .prio_mask = 4,
 239         },
 240         [37] = {
 241                 .mask   = IPIC_SIMSR_H,
 242                 .prio   = IPIC_SIPRR_A,
 243                 .force  = IPIC_SIFCR_H,
 244                 .bit    = 5,
 245                 .prio_mask = 5,
 246         },
 247         [38] = {
 248                 .mask   = IPIC_SIMSR_H,
 249                 .prio   = IPIC_SIPRR_A,
 250                 .force  = IPIC_SIFCR_H,
 251                 .bit    = 6,
 252                 .prio_mask = 6,
 253         },
 254         [39] = {
 255                 .mask   = IPIC_SIMSR_H,
 256                 .prio   = IPIC_SIPRR_A,
 257                 .force  = IPIC_SIFCR_H,
 258                 .bit    = 7,
 259                 .prio_mask = 7,
 260         },
 261         [40] = {
 262                 .mask   = IPIC_SIMSR_H,
 263                 .prio   = IPIC_SIPRR_B,
 264                 .force  = IPIC_SIFCR_H,
 265                 .bit    = 8,
 266                 .prio_mask = 0,
 267         },
 268         [41] = {
 269                 .mask   = IPIC_SIMSR_H,
 270                 .prio   = IPIC_SIPRR_B,
 271                 .force  = IPIC_SIFCR_H,
 272                 .bit    = 9,
 273                 .prio_mask = 1,
 274         },
 275         [42] = {
 276                 .mask   = IPIC_SIMSR_H,
 277                 .prio   = IPIC_SIPRR_B,
 278                 .force  = IPIC_SIFCR_H,
 279                 .bit    = 10,
 280                 .prio_mask = 2,
 281         },
 282         [43] = {
 283                 .mask   = IPIC_SIMSR_H,
 284                 .prio   = IPIC_SIPRR_B,
 285                 .force  = IPIC_SIFCR_H,
 286                 .bit    = 11,
 287                 .prio_mask = 3,
 288         },
 289         [44] = {
 290                 .mask   = IPIC_SIMSR_H,
 291                 .prio   = IPIC_SIPRR_B,
 292                 .force  = IPIC_SIFCR_H,
 293                 .bit    = 12,
 294                 .prio_mask = 4,
 295         },
 296         [45] = {
 297                 .mask   = IPIC_SIMSR_H,
 298                 .prio   = IPIC_SIPRR_B,
 299                 .force  = IPIC_SIFCR_H,
 300                 .bit    = 13,
 301                 .prio_mask = 5,
 302         },
 303         [46] = {
 304                 .mask   = IPIC_SIMSR_H,
 305                 .prio   = IPIC_SIPRR_B,
 306                 .force  = IPIC_SIFCR_H,
 307                 .bit    = 14,
 308                 .prio_mask = 6,
 309         },
 310         [47] = {
 311                 .mask   = IPIC_SIMSR_H,
 312                 .prio   = IPIC_SIPRR_B,
 313                 .force  = IPIC_SIFCR_H,
 314                 .bit    = 15,
 315                 .prio_mask = 7,
 316         },
 317         [48] = {
 318                 .mask   = IPIC_SEMSR,
 319                 .prio   = IPIC_SMPRR_A,
 320                 .force  = IPIC_SEFCR,
 321                 .bit    = 0,
 322                 .prio_mask = 4,
 323         },
 324         [64] = {
 325                 .mask   = IPIC_SIMSR_L,
 326                 .prio   = IPIC_SMPRR_A,
 327                 .force  = IPIC_SIFCR_L,
 328                 .bit    = 0,
 329                 .prio_mask = 0,
 330         },
 331         [65] = {
 332                 .mask   = IPIC_SIMSR_L,
 333                 .prio   = IPIC_SMPRR_A,
 334                 .force  = IPIC_SIFCR_L,
 335                 .bit    = 1,
 336                 .prio_mask = 1,
 337         },
 338         [66] = {
 339                 .mask   = IPIC_SIMSR_L,
 340                 .prio   = IPIC_SMPRR_A,
 341                 .force  = IPIC_SIFCR_L,
 342                 .bit    = 2,
 343                 .prio_mask = 2,
 344         },
 345         [67] = {
 346                 .mask   = IPIC_SIMSR_L,
 347                 .prio   = IPIC_SMPRR_A,
 348                 .force  = IPIC_SIFCR_L,
 349                 .bit    = 3,
 350                 .prio_mask = 3,
 351         },
 352         [68] = {
 353                 .mask   = IPIC_SIMSR_L,
 354                 .prio   = IPIC_SMPRR_B,
 355                 .force  = IPIC_SIFCR_L,
 356                 .bit    = 4,
 357                 .prio_mask = 0,
 358         },
 359         [69] = {
 360                 .mask   = IPIC_SIMSR_L,
 361                 .prio   = IPIC_SMPRR_B,
 362                 .force  = IPIC_SIFCR_L,
 363                 .bit    = 5,
 364                 .prio_mask = 1,
 365         },
 366         [70] = {
 367                 .mask   = IPIC_SIMSR_L,
 368                 .prio   = IPIC_SMPRR_B,
 369                 .force  = IPIC_SIFCR_L,
 370                 .bit    = 6,
 371                 .prio_mask = 2,
 372         },
 373         [71] = {
 374                 .mask   = IPIC_SIMSR_L,
 375                 .prio   = IPIC_SMPRR_B,
 376                 .force  = IPIC_SIFCR_L,
 377                 .bit    = 7,
 378                 .prio_mask = 3,
 379         },
 380         [72] = {
 381                 .mask   = IPIC_SIMSR_L,
 382                 .prio   = 0,
 383                 .force  = IPIC_SIFCR_L,
 384                 .bit    = 8,
 385         },
 386         [73] = {
 387                 .mask   = IPIC_SIMSR_L,
 388                 .prio   = 0,
 389                 .force  = IPIC_SIFCR_L,
 390                 .bit    = 9,
 391         },
 392         [74] = {
 393                 .mask   = IPIC_SIMSR_L,
 394                 .prio   = 0,
 395                 .force  = IPIC_SIFCR_L,
 396                 .bit    = 10,
 397         },
 398         [75] = {
 399                 .mask   = IPIC_SIMSR_L,
 400                 .prio   = 0,
 401                 .force  = IPIC_SIFCR_L,
 402                 .bit    = 11,
 403         },
 404         [76] = {
 405                 .mask   = IPIC_SIMSR_L,
 406                 .prio   = 0,
 407                 .force  = IPIC_SIFCR_L,
 408                 .bit    = 12,
 409         },
 410         [77] = {
 411                 .mask   = IPIC_SIMSR_L,
 412                 .prio   = 0,
 413                 .force  = IPIC_SIFCR_L,
 414                 .bit    = 13,
 415         },
 416         [78] = {
 417                 .mask   = IPIC_SIMSR_L,
 418                 .prio   = 0,
 419                 .force  = IPIC_SIFCR_L,
 420                 .bit    = 14,
 421         },
 422         [79] = {
 423                 .mask   = IPIC_SIMSR_L,
 424                 .prio   = 0,
 425                 .force  = IPIC_SIFCR_L,
 426                 .bit    = 15,
 427         },
 428         [80] = {
 429                 .mask   = IPIC_SIMSR_L,
 430                 .prio   = 0,
 431                 .force  = IPIC_SIFCR_L,
 432                 .bit    = 16,
 433         },
 434         [81] = {
 435                 .mask   = IPIC_SIMSR_L,
 436                 .prio   = 0,
 437                 .force  = IPIC_SIFCR_L,
 438                 .bit    = 17,
 439         },
 440         [82] = {
 441                 .mask   = IPIC_SIMSR_L,
 442                 .prio   = 0,
 443                 .force  = IPIC_SIFCR_L,
 444                 .bit    = 18,
 445         },
 446         [83] = {
 447                 .mask   = IPIC_SIMSR_L,
 448                 .prio   = 0,
 449                 .force  = IPIC_SIFCR_L,
 450                 .bit    = 19,
 451         },
 452         [84] = {
 453                 .mask   = IPIC_SIMSR_L,
 454                 .prio   = 0,
 455                 .force  = IPIC_SIFCR_L,
 456                 .bit    = 20,
 457         },
 458         [85] = {
 459                 .mask   = IPIC_SIMSR_L,
 460                 .prio   = 0,
 461                 .force  = IPIC_SIFCR_L,
 462                 .bit    = 21,
 463         },
 464         [86] = {
 465                 .mask   = IPIC_SIMSR_L,
 466                 .prio   = 0,
 467                 .force  = IPIC_SIFCR_L,
 468                 .bit    = 22,
 469         },
 470         [87] = {
 471                 .mask   = IPIC_SIMSR_L,
 472                 .prio   = 0,
 473                 .force  = IPIC_SIFCR_L,
 474                 .bit    = 23,
 475         },
 476         [88] = {
 477                 .mask   = IPIC_SIMSR_L,
 478                 .prio   = 0,
 479                 .force  = IPIC_SIFCR_L,
 480                 .bit    = 24,
 481         },
 482         [89] = {
 483                 .mask   = IPIC_SIMSR_L,
 484                 .prio   = 0,
 485                 .force  = IPIC_SIFCR_L,
 486                 .bit    = 25,
 487         },
 488         [90] = {
 489                 .mask   = IPIC_SIMSR_L,
 490                 .prio   = 0,
 491                 .force  = IPIC_SIFCR_L,
 492                 .bit    = 26,
 493         },
 494         [91] = {
 495                 .mask   = IPIC_SIMSR_L,
 496                 .prio   = 0,
 497                 .force  = IPIC_SIFCR_L,
 498                 .bit    = 27,
 499         },
 500 };
 501
 502 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
 503 {
 504         return in_be32(base + (reg >> 2));
 505 }
 506
 507 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
 508 {
 509         out_be32(base + (reg >> 2), value);
 510 }
 511
 512 static inline struct ipic * ipic_from_irq(unsigned int virq)
 513 {
 514         return primary_ipic;
 515 }
 516
 517 #define ipic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 518
 519 static void ipic_unmask_irq(unsigned int virq)
 520 {
 521         struct ipic *ipic = ipic_from_irq(virq);
 522         unsigned int src = ipic_irq_to_hw(virq);
 523         unsigned long flags;
 524         u32 temp;
 525
 526         spin_lock_irqsave(&ipic_lock, flags);
 527
 528         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 529         temp |= (1 << (31 - ipic_info[src].bit));
 530         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 531
 532         spin_unlock_irqrestore(&ipic_lock, flags);
 533 }
 534
 535 static void ipic_mask_irq(unsigned int virq)
 536 {
 537         struct ipic *ipic = ipic_from_irq(virq);
 538         unsigned int src = ipic_irq_to_hw(virq);
 539         unsigned long flags;
 540         u32 temp;
 541
 542         spin_lock_irqsave(&ipic_lock, flags);
 543
 544         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 545         temp &= ~(1 << (31 - ipic_info[src].bit));
 546         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 547
 548         /* mb() can't guarantee that masking is finished.  But it does finish
 549          * for nearly all cases. */
 550         mb();
 551
 552         spin_unlock_irqrestore(&ipic_lock, flags);
 553 }
 554
 555 static void ipic_ack_irq(unsigned int virq)
 556 {
 557         struct ipic *ipic = ipic_from_irq(virq);
 558         unsigned int src = ipic_irq_to_hw(virq);
 559         unsigned long flags;
 560         u32 temp;
 561
 562         spin_lock_irqsave(&ipic_lock, flags);
 563
 564         temp = ipic_read(ipic->regs, ipic_info[src].ack);
 565         temp |= (1 << (31 - ipic_info[src].bit));
 566         ipic_write(ipic->regs, ipic_info[src].ack, temp);
 567
 568         /* mb() can't guarantee that ack is finished.  But it does finish
 569          * for nearly all cases. */
 570         mb();
 571
 572         spin_unlock_irqrestore(&ipic_lock, flags);
 573 }
 574
 575 static void ipic_mask_irq_and_ack(unsigned int virq)
 576 {
 577         struct ipic *ipic = ipic_from_irq(virq);
 578         unsigned int src = ipic_irq_to_hw(virq);
 579         unsigned long flags;
 580         u32 temp;
 581
 582         spin_lock_irqsave(&ipic_lock, flags);
 583
 584         temp = ipic_read(ipic->regs, ipic_info[src].mask);
 585         temp &= ~(1 << (31 - ipic_info[src].bit));
 586         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 587
 588         temp = ipic_read(ipic->regs, ipic_info[src].ack);
 589         temp |= (1 << (31 - ipic_info[src].bit));
 590         ipic_write(ipic->regs, ipic_info[src].ack, temp);
 591
 592         /* mb() can't guarantee that ack is finished.  But it does finish
 593          * for nearly all cases. */
 594         mb();
 595
 596         spin_unlock_irqrestore(&ipic_lock, flags);
 597 }
 598
 599 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
 600 {
 601         struct ipic *ipic = ipic_from_irq(virq);
 602         unsigned int src = ipic_irq_to_hw(virq);
 603         struct irq_desc *desc = get_irq_desc(virq);
 604         unsigned int vold, vnew, edibit;
 605
 606         if (flow_type == IRQ_TYPE_NONE)
 607                 flow_type = IRQ_TYPE_LEVEL_LOW;
 608
 609         /* ipic supports only low assertion and high-to-low change senses
 610          */
 611         if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
 612                 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
 613                         flow_type);
 614                 return -EINVAL;
 615         }
 616         /* ipic supports only edge mode on external interrupts */
 617         if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
 618                 printk(KERN_ERR "ipic: edge sense not supported on internal "
 619                                 "interrupts\n");
 620                 return -EINVAL;
 621         }
 622
 623         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 624         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 625         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
 626                 desc->status |= IRQ_LEVEL;
 627                 desc->handle_irq = handle_level_irq;
 628                 desc->chip = &ipic_level_irq_chip;
 629         } else {
 630                 desc->handle_irq = handle_edge_irq;
 631                 desc->chip = &ipic_edge_irq_chip;
 632         }
 633
 634         /* only EXT IRQ senses are programmable on ipic
 635          * internal IRQ senses are LEVEL_LOW
 636          */
 637         if (src == IPIC_IRQ_EXT0)
 638                 edibit = 15;
 639         else
 640                 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
 641                         edibit = (14 - (src - IPIC_IRQ_EXT1));
 642                 else
 643                         return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
 644
 645         vold = ipic_read(ipic->regs, IPIC_SECNR);
 646         if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
 647                 vnew = vold | (1 << edibit);
 648         } else {
 649                 vnew = vold & ~(1 << edibit);
 650         }
 651         if (vold != vnew)
 652                 ipic_write(ipic->regs, IPIC_SECNR, vnew);
 653         return 0;
 654 }
 655
 656 /* level interrupts and edge interrupts have different ack operations */
 657 static struct irq_chip ipic_level_irq_chip = {
 658         .typename       = " IPIC  ",
 659         .unmask         = ipic_unmask_irq,
 660         .mask           = ipic_mask_irq,
 661         .mask_ack       = ipic_mask_irq,
 662         .set_type       = ipic_set_irq_type,
 663 };
 664
 665 static struct irq_chip ipic_edge_irq_chip = {
 666         .typename       = " IPIC  ",
 667         .unmask         = ipic_unmask_irq,
 668         .mask           = ipic_mask_irq,
 669         .mask_ack       = ipic_mask_irq_and_ack,
 670         .ack            = ipic_ack_irq,
 671         .set_type       = ipic_set_irq_type,
 672 };
 673
 674 static int ipic_host_match(struct irq_host *h, struct device_node *node)
 675 {
 676         /* Exact match, unless ipic node is NULL */
 677         return h->of_node == NULL || h->of_node == node;
 678 }
 679
 680 static int ipic_host_map(struct irq_host *h, unsigned int virq,
 681                          irq_hw_number_t hw)
 682 {
 683         struct ipic *ipic = h->host_data;
 684
 685         set_irq_chip_data(virq, ipic);
 686         set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
 687
 688         /* Set default irq type */
 689         set_irq_type(virq, IRQ_TYPE_NONE);
 690
 691         return 0;
 692 }
 693
 694 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
 695                            u32 *intspec, unsigned int intsize,
 696                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 697
 698 {
 699         /* interrupt sense values coming from the device tree equal either
 700          * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
 701          */
 702         *out_hwirq = intspec[0];
 703         if (intsize > 1)
 704                 *out_flags = intspec[1];
 705         else
 706                 *out_flags = IRQ_TYPE_NONE;
 707         return 0;
 708 }
 709
 710 static struct irq_host_ops ipic_host_ops = {
 711         .match  = ipic_host_match,
 712         .map    = ipic_host_map,
 713         .xlate  = ipic_host_xlate,
 714 };
 715
 716 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
 717 {
 718         struct ipic     *ipic;
 719         struct resource res;
 720         u32 temp = 0, ret;
 721
 722         ipic = alloc_bootmem(sizeof(struct ipic));
 723         if (ipic == NULL)
 724                 return NULL;
 725
 726         memset(ipic, 0, sizeof(struct ipic));
 727
 728         ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
 729                                        NR_IPIC_INTS,
 730                                        &ipic_host_ops, 0);
 731         if (ipic->irqhost == NULL) {
 732                 of_node_put(node);
 733                 return NULL;
 734         }
 735
 736         ret = of_address_to_resource(node, 0, &res);
 737         if (ret) {
 738                 of_node_put(node);
 739                 return NULL;
 740         }
 741
 742         ipic->regs = ioremap(res.start, res.end - res.start + 1);
 743
 744         ipic->irqhost->host_data = ipic;
 745
 746         /* init hw */
 747         ipic_write(ipic->regs, IPIC_SICNR, 0x0);
 748
 749         /* default priority scheme is grouped. If spread mode is required
 750          * configure SICFR accordingly */
 751         if (flags & IPIC_SPREADMODE_GRP_A)
 752                 temp |= SICFR_IPSA;
 753         if (flags & IPIC_SPREADMODE_GRP_B)
 754                 temp |= SICFR_IPSB;
 755         if (flags & IPIC_SPREADMODE_GRP_C)
 756                 temp |= SICFR_IPSC;
 757         if (flags & IPIC_SPREADMODE_GRP_D)
 758                 temp |= SICFR_IPSD;
 759         if (flags & IPIC_SPREADMODE_MIX_A)
 760                 temp |= SICFR_MPSA;
 761         if (flags & IPIC_SPREADMODE_MIX_B)
 762                 temp |= SICFR_MPSB;
 763
 764         ipic_write(ipic->regs, IPIC_SICFR, temp);
 765
 766         /* handle MCP route */
 767         temp = 0;
 768         if (flags & IPIC_DISABLE_MCP_OUT)
 769                 temp = SERCR_MCPR;
 770         ipic_write(ipic->regs, IPIC_SERCR, temp);
 771
 772         /* handle routing of IRQ0 to MCP */
 773         temp = ipic_read(ipic->regs, IPIC_SEMSR);
 774
 775         if (flags & IPIC_IRQ0_MCP)
 776                 temp |= SEMSR_SIRQ0;
 777         else
 778                 temp &= ~SEMSR_SIRQ0;
 779
 780         ipic_write(ipic->regs, IPIC_SEMSR, temp);
 781
 782         primary_ipic = ipic;
 783         irq_set_default_host(primary_ipic->irqhost);
 784
 785         printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
 786                         primary_ipic->regs);
 787
 788         return ipic;
 789 }
 790
 791 int ipic_set_priority(unsigned int virq, unsigned int priority)
 792 {
 793         struct ipic *ipic = ipic_from_irq(virq);
 794         unsigned int src = ipic_irq_to_hw(virq);
 795         u32 temp;
 796
 797         if (priority > 7)
 798                 return -EINVAL;
 799         if (src > 127)
 800                 return -EINVAL;
 801         if (ipic_info[src].prio == 0)
 802                 return -EINVAL;
 803
 804         temp = ipic_read(ipic->regs, ipic_info[src].prio);
 805
 806         if (priority < 4) {
 807                 temp &= ~(0x7 << (20 + (3 - priority) * 3));
 808                 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
 809         } else {
 810                 temp &= ~(0x7 << (4 + (7 - priority) * 3));
 811                 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
 812         }
 813
 814         ipic_write(ipic->regs, ipic_info[src].prio, temp);
 815
 816         return 0;
 817 }
 818
 819 void ipic_set_highest_priority(unsigned int virq)
 820 {
 821         struct ipic *ipic = ipic_from_irq(virq);
 822         unsigned int src = ipic_irq_to_hw(virq);
 823         u32 temp;
 824
 825         temp = ipic_read(ipic->regs, IPIC_SICFR);
 826
 827         /* clear and set HPI */
 828         temp &= 0x7f000000;
 829         temp |= (src & 0x7f) << 24;
 830
 831         ipic_write(ipic->regs, IPIC_SICFR, temp);
 832 }
 833
 834 void ipic_set_default_priority(void)
 835 {
 836         ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
 837         ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
 838         ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
 839         ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
 840         ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
 841         ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
 842 }
 843
 844 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
 845 {
 846         struct ipic *ipic = primary_ipic;
 847         u32 temp;
 848
 849         temp = ipic_read(ipic->regs, IPIC_SERMR);
 850         temp |= (1 << (31 - mcp_irq));
 851         ipic_write(ipic->regs, IPIC_SERMR, temp);
 852 }
 853
 854 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
 855 {
 856         struct ipic *ipic = primary_ipic;
 857         u32 temp;
 858
 859         temp = ipic_read(ipic->regs, IPIC_SERMR);
 860         temp &= (1 << (31 - mcp_irq));
 861         ipic_write(ipic->regs, IPIC_SERMR, temp);
 862 }
 863
 864 u32 ipic_get_mcp_status(void)
 865 {
 866         return ipic_read(primary_ipic->regs, IPIC_SERMR);
 867 }
 868
 869 void ipic_clear_mcp_status(u32 mask)
 870 {
 871         ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
 872 }
 873
 874 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 875 unsigned int ipic_get_irq(void)
 876 {
 877         int irq;
 878
 879         BUG_ON(primary_ipic == NULL);
 880
 881 #define IPIC_SIVCR_VECTOR_MASK  0x7f
 882         irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
 883
 884         if (irq == 0)    /* 0 --> no irq is pending */
 885                 return NO_IRQ;
 886
 887         return irq_linear_revmap(primary_ipic->irqhost, irq);
 888 }
 889
 890 static struct sysdev_class ipic_sysclass = {
 891         set_kset_name("ipic"),
 892 };
 893
 894 static struct sys_device device_ipic = {
 895         .id             = 0,
 896         .cls            = &ipic_sysclass,
 897 };
 898
 899 static int __init init_ipic_sysfs(void)
 900 {
 901         int rc;
 902
 903         if (!primary_ipic->regs)
 904                 return -ENODEV;
 905         printk(KERN_DEBUG "Registering ipic with sysfs...\n");
 906
 907         rc = sysdev_class_register(&ipic_sysclass);
 908         if (rc) {
 909                 printk(KERN_ERR "Failed registering ipic sys class\n");
 910                 return -ENODEV;
 911         }
 912         rc = sysdev_register(&device_ipic);
 913         if (rc) {
 914                 printk(KERN_ERR "Failed registering ipic sys device\n");
 915                 return -ENODEV;
 916         }
 917         return 0;
 918 }
 919
 920 subsys_initcall(init_ipic_sysfs);