[POWERPC] Add support for mpc512x interrupts to ipic

Added ipic_info entries for vectors used by 512x that
were previously unused by 83xx.

Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 7274750..4c016da 100644 (file)
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -48,6 +48,13 @@ static struct ipic_info ipic_info[] = {
                .bit    = 17,
                .prio_mask = 1,
        },
+       [3] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 18,
+               .prio_mask = 2,
+       },
        [4] = {
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_C,
@@ -55,6 +62,34 @@ static struct ipic_info ipic_info[] = {
                .bit    = 19,
                .prio_mask = 3,
        },
+       [5] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 20,
+               .prio_mask = 4,
+       },
+       [6] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 21,
+               .prio_mask = 5,
+       },
+       [7] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 22,
+               .prio_mask = 6,
+       },
+       [8] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 23,
+               .prio_mask = 7,
+       },
        [9] = {
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
@@ -223,6 +258,20 @@ static struct ipic_info ipic_info[] = {
                .bit    = 7,
                .prio_mask = 7,
        },
+       [40] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 8,
+               .prio_mask = 0,
+       },
+       [41] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 9,
+               .prio_mask = 1,
+       },
        [42] = {
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_B,
@@ -230,6 +279,13 @@ static struct ipic_info ipic_info[] = {
                .bit    = 10,
                .prio_mask = 2,
        },
+       [43] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 11,
+               .prio_mask = 3,
+       },
        [44] = {
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_B,
@@ -387,6 +443,12 @@ static struct ipic_info ipic_info[] = {
                .force  = IPIC_SIFCR_L,
                .bit    = 18,
        },
+       [83] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 19,
+       },
        [84] = {
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,