3 #include <linux/bitmap.h>
4 #include <linux/init.h>
9 #include <asm/gcmpregs.h>
10 #include <asm/mips-boards/maltaint.h>
12 #include <linux/hardirq.h>
13 #include <asm-generic/bitops/find.h>
16 static unsigned long _gic_base;
17 static unsigned int _irqbase, _mapsize, numvpes, numintrs;
18 static struct gic_intr_map *_intrmap;
20 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
21 static struct gic_pending_regs pending_regs[NR_CPUS];
22 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
24 #define gic_wedgeb2bok 0 /*
25 * Can GIC handle b2b writes to wedge register?
27 #if gic_wedgeb2bok == 0
28 static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
31 void gic_send_ipi(unsigned int intr)
33 #if gic_wedgeb2bok == 0
36 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
39 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
40 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
41 if (!gic_wedgeb2bok) {
42 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
43 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
47 /* This is Malta specific and needs to be exported */
48 static void vpe_local_setup(unsigned int numvpes)
51 unsigned long timer_interrupt = 5, perf_interrupt = 5;
55 * Setup the default performance counter timer interrupts
58 for (i = 0; i < numvpes; i++) {
59 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
61 /* Are Interrupts locally routable? */
62 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
63 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
64 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
65 GIC_MAP_TO_PIN_MSK | timer_interrupt);
67 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
68 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
69 GIC_MAP_TO_PIN_MSK | perf_interrupt);
73 unsigned int gic_get_int(void)
76 unsigned long *pending, *intrmask, *pcpu_mask;
77 unsigned long *pending_abs, *intrmask_abs;
79 /* Get per-cpu bitmaps */
80 pending = pending_regs[smp_processor_id()].pending;
81 intrmask = intrmask_regs[smp_processor_id()].intrmask;
82 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
84 pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
85 GIC_SH_PEND_31_0_OFS);
86 intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
87 GIC_SH_MASK_31_0_OFS);
89 for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
90 GICREAD(*pending_abs, pending[i]);
91 GICREAD(*intrmask_abs, intrmask[i]);
96 bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
97 bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
99 i = find_first_bit(pending, GIC_NUM_INTRS);
101 pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
106 static unsigned int gic_irq_startup(unsigned int irq)
108 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
110 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
111 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
116 static void gic_irq_ack(unsigned int irq)
118 #if gic_wedgeb2bok == 0
121 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
123 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
126 if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
128 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
129 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
130 if (!gic_wedgeb2bok) {
131 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
132 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
137 static void gic_mask_irq(unsigned int irq)
139 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
141 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
142 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
146 static void gic_unmask_irq(unsigned int irq)
148 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
150 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
151 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
157 static DEFINE_SPINLOCK(gic_lock);
159 static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
161 cpumask_t tmp = CPU_MASK_NONE;
165 pr_debug(KERN_DEBUG "%s called\n", __func__);
168 cpumask_and(&tmp, cpumask, cpu_online_mask);
172 /* Assumption : cpumask refers to a single CPU */
173 spin_lock_irqsave(&gic_lock, flags);
175 /* Re-route this IRQ */
176 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
179 * FIXME: assumption that _intrmap is ordered and has no holes
182 /* Update the intr_map */
183 _intrmap[irq].cpunum = first_cpu(tmp);
185 /* Update the pcpu_masks */
186 for (i = 0; i < NR_CPUS; i++)
187 clear_bit(irq, pcpu_masks[i].pcpu_mask);
188 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
191 cpumask_copy(irq_desc[irq].affinity, cpumask);
192 spin_unlock_irqrestore(&gic_lock, flags);
198 static struct irq_chip gic_irq_controller = {
200 .startup = gic_irq_startup,
202 .mask = gic_mask_irq,
203 .mask_ack = gic_mask_irq,
204 .unmask = gic_unmask_irq,
205 .eoi = gic_unmask_irq,
207 .set_affinity = gic_set_affinity,
211 static void __init setup_intr(unsigned int intr, unsigned int cpu,
212 unsigned int pin, unsigned int polarity, unsigned int trigtype)
214 /* Setup Intr to Pin mapping */
215 if (pin & GIC_MAP_TO_NMI_MSK) {
216 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
217 /* FIXME: hack to route NMI to all cpu's */
218 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
219 GICWRITE(GIC_REG_ADDR(SHARED,
220 GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
224 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
225 GIC_MAP_TO_PIN_MSK | pin);
226 /* Setup Intr to CPU mapping */
227 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
230 /* Setup Intr Polarity */
231 GIC_SET_POLARITY(intr, polarity);
233 /* Setup Intr Trigger Type */
234 GIC_SET_TRIGGER(intr, trigtype);
236 /* Init Intr Masks */
237 GIC_SET_INTR_MASK(intr, 0);
240 static void __init gic_basic_init(void)
245 for (i = 0; i < GIC_NUM_INTRS; i++) {
246 GIC_SET_POLARITY(i, GIC_POL_POS);
247 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
248 GIC_SET_INTR_MASK(i, 0);
251 /* Setup specifics */
252 for (i = 0; i < _mapsize; i++) {
253 cpu = _intrmap[i].cpunum;
257 setup_intr(_intrmap[i].intrnum,
260 _intrmap[i].polarity,
261 _intrmap[i].trigtype);
262 /* Initialise per-cpu Interrupt software masks */
263 if (_intrmap[i].ipiflag)
264 set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
267 vpe_local_setup(numvpes);
269 for (i = _irqbase; i < (_irqbase + numintrs); i++)
270 set_irq_chip(i, &gic_irq_controller);
273 void __init gic_init(unsigned long gic_base_addr,
274 unsigned long gic_addrspace_size,
275 struct gic_intr_map *intr_map, unsigned int intr_map_size,
276 unsigned int irqbase)
278 unsigned int gicconfig;
280 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
284 _mapsize = intr_map_size;
286 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
287 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
288 GIC_SH_CONFIG_NUMINTRS_SHF;
289 numintrs = ((numintrs + 1) * 8);
291 numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
292 GIC_SH_CONFIG_NUMVPES_SHF;
294 pr_debug("%s called\n", __func__);