arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/cputype.h>
  23
  24 #include <plat/common.h>
  25 #include <plat/cpu.h>
  26
  27 #include <mach/id.h>
  28
  29 #include "control.h"
  30
  31 #define OMAP_SOC_MAX_NAME_LENGTH                16
  32
  33 static unsigned int omap_revision;
  34 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  35 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  36 u32 omap_features;
  37
  38 unsigned int omap_rev(void)
  39 {
  40         return omap_revision;
  41 }
  42 EXPORT_SYMBOL(omap_rev);
  43
  44 int omap_type(void)
  45 {
  46         u32 val = 0;
  47
  48         if (cpu_is_omap24xx()) {
  49                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  50         } else if (cpu_is_omap34xx()) {
  51                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  52         } else if (cpu_is_omap44xx()) {
  53                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  54         } else {
  55                 pr_err("Cannot detect omap type!\n");
  56                 goto out;
  57         }
  58
  59         val &= OMAP2_DEVICETYPE_MASK;
  60         val >>= 8;
  61
  62 out:
  63         return val;
  64 }
  65 EXPORT_SYMBOL(omap_type);
  66
  67
  68 /*----------------------------------------------------------------------------*/
  69
  70 #define OMAP_TAP_IDCODE         0x0204
  71 #define OMAP_TAP_DIE_ID_0       0x0218
  72 #define OMAP_TAP_DIE_ID_1       0x021C
  73 #define OMAP_TAP_DIE_ID_2       0x0220
  74 #define OMAP_TAP_DIE_ID_3       0x0224
  75
  76 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  77 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  78 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  79 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  80
  81 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  82
  83 struct omap_id {
  84         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  85         u8      dev;            /* Device type from production_id reg */
  86         u32     type;           /* Combined type id copied to omap_revision */
  87 };
  88
  89 /* Register values to detect the OMAP version */
  90 static struct omap_id omap_ids[] __initdata = {
  91         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  92         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  93         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  94         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  95         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  96         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  97 };
  98
  99 static void __iomem *tap_base;
 100 static u16 tap_prod_id;
 101
 102 void omap_get_die_id(struct omap_die_id *odi)
 103 {
 104         if (cpu_is_omap44xx()) {
 105                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 106                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 107                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 108                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 109
 110                 return;
 111         }
 112         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 113         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 114         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 115         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 116 }
 117
 118 void __init omap2xxx_check_revision(void)
 119 {
 120         int i, j;
 121         u32 idcode, prod_id;
 122         u16 hawkeye;
 123         u8  dev_type, rev;
 124         struct omap_die_id odi;
 125
 126         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 127         prod_id = read_tap_reg(tap_prod_id);
 128         hawkeye = (idcode >> 12) & 0xffff;
 129         rev = (idcode >> 28) & 0x0f;
 130         dev_type = (prod_id >> 16) & 0x0f;
 131         omap_get_die_id(&odi);
 132
 133         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 134                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 135         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 136         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 137                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 138         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 139         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 140         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 141                  prod_id, dev_type);
 142
 143         /* Check hawkeye ids */
 144         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 145                 if (hawkeye == omap_ids[i].hawkeye)
 146                         break;
 147         }
 148
 149         if (i == ARRAY_SIZE(omap_ids)) {
 150                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 151                 return;
 152         }
 153
 154         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 155                 if (dev_type == omap_ids[j].dev)
 156                         break;
 157         }
 158
 159         if (j == ARRAY_SIZE(omap_ids)) {
 160                 printk(KERN_ERR "Unknown OMAP device type. "
 161                                 "Handling it as OMAP%04x\n",
 162                                 omap_ids[i].type >> 16);
 163                 j = i;
 164         }
 165
 166         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 167         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 168
 169         pr_info("%s", soc_name);
 170         if ((omap_rev() >> 8) & 0x0f)
 171                 pr_info("%s", soc_rev);
 172         pr_info("\n");
 173 }
 174
 175 #define OMAP3_SHOW_FEATURE(feat)                \
 176         if (omap3_has_ ##feat())                \
 177                 printk(#feat" ");
 178
 179 static void __init omap3_cpuinfo(void)
 180 {
 181         const char *cpu_name;
 182
 183         /*
 184          * OMAP3430 and OMAP3530 are assumed to be same.
 185          *
 186          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 187          * on available features. Upon detection, update the CPU id
 188          * and CPU class bits.
 189          */
 190         if (cpu_is_omap3630()) {
 191                 cpu_name = "OMAP3630";
 192         } else if (cpu_is_omap3517()) {
 193                 /* AM35xx devices */
 194                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 195         } else if (cpu_is_ti816x()) {
 196                 cpu_name = "TI816X";
 197         } else if (omap3_has_iva() && omap3_has_sgx()) {
 198                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 199                 cpu_name = "OMAP3430/3530";
 200         } else if (omap3_has_iva()) {
 201                 cpu_name = "OMAP3525";
 202         } else if (omap3_has_sgx()) {
 203                 cpu_name = "OMAP3515";
 204         } else {
 205                 cpu_name = "OMAP3503";
 206         }
 207
 208         sprintf(soc_name, "%s", cpu_name);
 209
 210         /* Print verbose information */
 211         pr_info("%s %s (", soc_name, soc_rev);
 212
 213         OMAP3_SHOW_FEATURE(l2cache);
 214         OMAP3_SHOW_FEATURE(iva);
 215         OMAP3_SHOW_FEATURE(sgx);
 216         OMAP3_SHOW_FEATURE(neon);
 217         OMAP3_SHOW_FEATURE(isp);
 218         OMAP3_SHOW_FEATURE(192mhz_clk);
 219
 220         printk(")\n");
 221 }
 222
 223 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 224         if (((status & OMAP3_ ##feat## _MASK)                           \
 225                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 226                 omap_features |= OMAP3_HAS_ ##feat;                     \
 227         }
 228
 229 void __init omap3xxx_check_features(void)
 230 {
 231         u32 status;
 232
 233         omap_features = 0;
 234
 235         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 236
 237         OMAP3_CHECK_FEATURE(status, L2CACHE);
 238         OMAP3_CHECK_FEATURE(status, IVA);
 239         OMAP3_CHECK_FEATURE(status, SGX);
 240         OMAP3_CHECK_FEATURE(status, NEON);
 241         OMAP3_CHECK_FEATURE(status, ISP);
 242         if (cpu_is_omap3630())
 243                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 244         if (cpu_is_omap3430() || cpu_is_omap3630())
 245                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 246         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 247             omap_rev() == OMAP3430_REV_ES3_1_2)
 248                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 249
 250         omap_features |= OMAP3_HAS_SDRC;
 251
 252         /*
 253          * TODO: Get additional info (where applicable)
 254          *       e.g. Size of L2 cache.
 255          */
 256
 257         omap3_cpuinfo();
 258 }
 259
 260 void __init omap4xxx_check_features(void)
 261 {
 262         u32 si_type;
 263
 264         if (cpu_is_omap443x())
 265                 omap_features |= OMAP4_HAS_MPU_1GHZ;
 266
 267
 268         if (cpu_is_omap446x()) {
 269                 si_type =
 270                         read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
 271                 switch ((si_type & (3 << 16)) >> 16) {
 272                 case 2:
 273                         /* High performance device */
 274                         omap_features |= OMAP4_HAS_MPU_1_5GHZ;
 275                         break;
 276                 case 1:
 277                 default:
 278                         /* Standard device */
 279                         omap_features |= OMAP4_HAS_MPU_1_2GHZ;
 280                         break;
 281                 }
 282         }
 283 }
 284
 285 void __init ti81xx_check_features(void)
 286 {
 287         omap_features = OMAP3_HAS_NEON;
 288         omap3_cpuinfo();
 289 }
 290
 291 void __init omap3xxx_check_revision(void)
 292 {
 293         const char *cpu_rev;
 294         u32 cpuid, idcode;
 295         u16 hawkeye;
 296         u8 rev;
 297
 298         /*
 299          * We cannot access revision registers on ES1.0.
 300          * If the processor type is Cortex-A8 and the revision is 0x0
 301          * it means its Cortex r0p0 which is 3430 ES1.0.
 302          */
 303         cpuid = read_cpuid(CPUID_ID);
 304         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 305                 omap_revision = OMAP3430_REV_ES1_0;
 306                 cpu_rev = "1.0";
 307                 return;
 308         }
 309
 310         /*
 311          * Detection for 34xx ES2.0 and above can be done with just
 312          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 313          * Note that rev does not map directly to our defined processor
 314          * revision numbers as ES1.0 uses value 0.
 315          */
 316         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 317         hawkeye = (idcode >> 12) & 0xffff;
 318         rev = (idcode >> 28) & 0xff;
 319
 320         switch (hawkeye) {
 321         case 0xb7ae:
 322                 /* Handle 34xx/35xx devices */
 323                 switch (rev) {
 324                 case 0: /* Take care of early samples */
 325                 case 1:
 326                         omap_revision = OMAP3430_REV_ES2_0;
 327                         cpu_rev = "2.0";
 328                         break;
 329                 case 2:
 330                         omap_revision = OMAP3430_REV_ES2_1;
 331                         cpu_rev = "2.1";
 332                         break;
 333                 case 3:
 334                         omap_revision = OMAP3430_REV_ES3_0;
 335                         cpu_rev = "3.0";
 336                         break;
 337                 case 4:
 338                         omap_revision = OMAP3430_REV_ES3_1;
 339                         cpu_rev = "3.1";
 340                         break;
 341                 case 7:
 342                 /* FALLTHROUGH */
 343                 default:
 344                         /* Use the latest known revision as default */
 345                         omap_revision = OMAP3430_REV_ES3_1_2;
 346                         cpu_rev = "3.1.2";
 347                 }
 348                 break;
 349         case 0xb868:
 350                 /*
 351                  * Handle OMAP/AM 3505/3517 devices
 352                  *
 353                  * Set the device to be OMAP3517 here. Actual device
 354                  * is identified later based on the features.
 355                  */
 356                 switch (rev) {
 357                 case 0:
 358                         omap_revision = OMAP3517_REV_ES1_0;
 359                         cpu_rev = "1.0";
 360                         break;
 361                 case 1:
 362                 /* FALLTHROUGH */
 363                 default:
 364                         omap_revision = OMAP3517_REV_ES1_1;
 365                         cpu_rev = "1.1";
 366                 }
 367                 break;
 368         case 0xb891:
 369                 /* Handle 36xx devices */
 370
 371                 switch(rev) {
 372                 case 0: /* Take care of early samples */
 373                         omap_revision = OMAP3630_REV_ES1_0;
 374                         cpu_rev = "1.0";
 375                         break;
 376                 case 1:
 377                         omap_revision = OMAP3630_REV_ES1_1;
 378                         cpu_rev = "1.1";
 379                         break;
 380                 case 2:
 381                 /* FALLTHROUGH */
 382                 default:
 383                         omap_revision = OMAP3630_REV_ES1_2;
 384                         cpu_rev = "1.2";
 385                 }
 386                 break;
 387         case 0xb81e:
 388                 switch (rev) {
 389                 case 0:
 390                         omap_revision = TI8168_REV_ES1_0;
 391                         cpu_rev = "1.0";
 392                         break;
 393                 case 1:
 394                 /* FALLTHROUGH */
 395                 default:
 396                         omap_revision = TI8168_REV_ES1_1;
 397                         cpu_rev = "1.1";
 398                         break;
 399                 }
 400                 break;
 401         default:
 402                 /* Unknown default to latest silicon rev as default */
 403                 omap_revision = OMAP3630_REV_ES1_2;
 404                 cpu_rev = "1.2";
 405                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 406         }
 407         sprintf(soc_rev, "ES%s", cpu_rev);
 408 }
 409
 410 void __init omap4xxx_check_revision(void)
 411 {
 412         u32 idcode;
 413         u16 hawkeye;
 414         u8 rev;
 415
 416         /*
 417          * The IC rev detection is done with hawkeye and rev.
 418          * Note that rev does not map directly to defined processor
 419          * revision numbers as ES1.0 uses value 0.
 420          */
 421         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 422         hawkeye = (idcode >> 12) & 0xffff;
 423         rev = (idcode >> 28) & 0xf;
 424
 425         /*
 426          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 427          * Use ARM register to detect the correct ES version
 428          */
 429         if (!rev && (hawkeye != 0xb94e)) {
 430                 idcode = read_cpuid(CPUID_ID);
 431                 rev = (idcode & 0xf) - 1;
 432         }
 433
 434         switch (hawkeye) {
 435         case 0xb852:
 436                 switch (rev) {
 437                 case 0:
 438                         omap_revision = OMAP4430_REV_ES1_0;
 439                         break;
 440                 case 1:
 441                 default:
 442                         omap_revision = OMAP4430_REV_ES2_0;
 443                 }
 444                 break;
 445         case 0xb95c:
 446                 switch (rev) {
 447                 case 3:
 448                         omap_revision = OMAP4430_REV_ES2_1;
 449                         break;
 450                 case 4:
 451                 default:
 452                         omap_revision = OMAP4430_REV_ES2_2;
 453                 }
 454                 break;
 455         case 0xb94e:
 456                 switch (rev) {
 457                 case 0:
 458                 default:
 459                         omap_revision = OMAP4460_REV_ES1_0;
 460                         break;
 461                 }
 462                 break;
 463         default:
 464                 /* Unknown default to latest silicon rev as default */
 465                 omap_revision = OMAP4430_REV_ES2_2;
 466         }
 467
 468         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 469         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 470                                                 (omap_rev() >> 8) & 0xf);
 471         pr_info("%s %s\n", soc_name, soc_rev);
 472 }
 473
 474 /*
 475  * Set up things for map_io and processor detection later on. Gets called
 476  * pretty much first thing from board init. For multi-omap, this gets
 477  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 478  * detect the exact revision later on in omap2_detect_revision() once map_io
 479  * is done.
 480  */
 481 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 482 {
 483         omap_revision = omap2_globals->class;
 484         tap_base = omap2_globals->tap;
 485
 486         if (cpu_is_omap34xx())
 487                 tap_prod_id = 0x0210;
 488         else
 489                 tap_prod_id = 0x0208;
 490 }