arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #ifdef CONFIG_SOC_BUS
  24 #include <linux/sys_soc.h>
  25 #include <linux/err.h>
  26 #endif
  27
  28 #include <asm/cputype.h>
  29
  30 #include <plat/common.h>
  31 #include <plat/cpu.h>
  32
  33 #include <mach/id.h>
  34
  35 #include "control.h"
  36
  37 #define OMAP_SOC_MAX_NAME_LENGTH                16
  38
  39 static unsigned int omap_revision;
  40 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  41 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  42 u32 omap_features;
  43
  44 unsigned int omap_rev(void)
  45 {
  46         return omap_revision;
  47 }
  48 EXPORT_SYMBOL(omap_rev);
  49
  50 #undef omap_type
  51
  52 int omap_type(void)
  53 {
  54         u32 val = 0;
  55
  56         if (cpu_is_omap24xx()) {
  57                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  58         } else if (cpu_is_omap34xx()) {
  59                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  60         } else if (cpu_is_omap44xx()) {
  61                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  62         } else {
  63                 pr_err("Cannot detect omap type!\n");
  64                 goto out;
  65         }
  66
  67         val &= OMAP2_DEVICETYPE_MASK;
  68         val >>= 8;
  69
  70 out:
  71         return val;
  72 }
  73 EXPORT_SYMBOL(omap_type);
  74
  75
  76 /*----------------------------------------------------------------------------*/
  77
  78 #define OMAP_TAP_IDCODE         0x0204
  79 #define OMAP_TAP_DIE_ID_0       0x0218
  80 #define OMAP_TAP_DIE_ID_1       0x021C
  81 #define OMAP_TAP_DIE_ID_2       0x0220
  82 #define OMAP_TAP_DIE_ID_3       0x0224
  83
  84 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  85 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  86 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  87 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  88
  89 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  90
  91 struct omap_id {
  92         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  93         u8      dev;            /* Device type from production_id reg */
  94         u32     type;           /* Combined type id copied to omap_revision */
  95 };
  96
  97 /* Register values to detect the OMAP version */
  98 static struct omap_id omap_ids[] __initdata = {
  99         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
 100         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
 101         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
 102         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
 103         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 104         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 105 };
 106
 107 static void __iomem *tap_base;
 108 static u16 tap_prod_id;
 109
 110 void omap_get_die_id(struct omap_die_id *odi)
 111 {
 112         if (cpu_is_omap44xx()) {
 113                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 114                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 115                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 116                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 117
 118                 return;
 119         }
 120         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 121         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 122         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 123         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 124 }
 125
 126 void __init omap2xxx_check_revision(void)
 127 {
 128         int i, j;
 129         u32 idcode, prod_id;
 130         u16 hawkeye;
 131         u8  dev_type, rev;
 132         struct omap_die_id odi;
 133
 134         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 135         prod_id = read_tap_reg(tap_prod_id);
 136         hawkeye = (idcode >> 12) & 0xffff;
 137         rev = (idcode >> 28) & 0x0f;
 138         dev_type = (prod_id >> 16) & 0x0f;
 139         omap_get_die_id(&odi);
 140
 141         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 142                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 143         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 144         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 145                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 146         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 147         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 148         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 149                  prod_id, dev_type);
 150
 151         /* Check hawkeye ids */
 152         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 153                 if (hawkeye == omap_ids[i].hawkeye)
 154                         break;
 155         }
 156
 157         if (i == ARRAY_SIZE(omap_ids)) {
 158                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 159                 return;
 160         }
 161
 162         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 163                 if (dev_type == omap_ids[j].dev)
 164                         break;
 165         }
 166
 167         if (j == ARRAY_SIZE(omap_ids)) {
 168                 printk(KERN_ERR "Unknown OMAP device type. "
 169                                 "Handling it as OMAP%04x\n",
 170                                 omap_ids[i].type >> 16);
 171                 j = i;
 172         }
 173
 174         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 175         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 176
 177         pr_info("%s", soc_name);
 178         if ((omap_rev() >> 8) & 0x0f)
 179                 pr_info("%s", soc_rev);
 180         pr_info("\n");
 181 }
 182
 183 #define OMAP3_SHOW_FEATURE(feat)                \
 184         if (omap3_has_ ##feat())                \
 185                 printk(#feat" ");
 186
 187 static void __init omap3_cpuinfo(void)
 188 {
 189         const char *cpu_name;
 190
 191         /*
 192          * OMAP3430 and OMAP3530 are assumed to be same.
 193          *
 194          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 195          * on available features. Upon detection, update the CPU id
 196          * and CPU class bits.
 197          */
 198         if (cpu_is_omap3630()) {
 199                 cpu_name = "OMAP3630";
 200         } else if (cpu_is_omap3517()) {
 201                 /* AM35xx devices */
 202                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 203         } else if (cpu_is_ti816x()) {
 204                 cpu_name = "TI816X";
 205         } else if (omap3_has_iva() && omap3_has_sgx()) {
 206                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 207                 cpu_name = "OMAP3430/3530";
 208         } else if (omap3_has_iva()) {
 209                 cpu_name = "OMAP3525";
 210         } else if (omap3_has_sgx()) {
 211                 cpu_name = "OMAP3515";
 212         } else {
 213                 cpu_name = "OMAP3503";
 214         }
 215
 216         sprintf(soc_name, "%s", cpu_name);
 217
 218         /* Print verbose information */
 219         pr_info("%s %s (", soc_name, soc_rev);
 220
 221         OMAP3_SHOW_FEATURE(l2cache);
 222         OMAP3_SHOW_FEATURE(iva);
 223         OMAP3_SHOW_FEATURE(sgx);
 224         OMAP3_SHOW_FEATURE(neon);
 225         OMAP3_SHOW_FEATURE(isp);
 226         OMAP3_SHOW_FEATURE(192mhz_clk);
 227
 228         printk(")\n");
 229 }
 230
 231 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 232         if (((status & OMAP3_ ##feat## _MASK)                           \
 233                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 234                 omap_features |= OMAP3_HAS_ ##feat;                     \
 235         }
 236
 237 void __init omap3xxx_check_features(void)
 238 {
 239         u32 status;
 240
 241         omap_features = 0;
 242
 243         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 244
 245         OMAP3_CHECK_FEATURE(status, L2CACHE);
 246         OMAP3_CHECK_FEATURE(status, IVA);
 247         OMAP3_CHECK_FEATURE(status, SGX);
 248         OMAP3_CHECK_FEATURE(status, NEON);
 249         OMAP3_CHECK_FEATURE(status, ISP);
 250         if (cpu_is_omap3630())
 251                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 252         if (cpu_is_omap3430() || cpu_is_omap3630())
 253                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 254         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 255             omap_rev() == OMAP3430_REV_ES3_1_2)
 256                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 257
 258         omap_features |= OMAP3_HAS_SDRC;
 259
 260         /*
 261          * TODO: Get additional info (where applicable)
 262          *       e.g. Size of L2 cache.
 263          */
 264
 265         omap3_cpuinfo();
 266 }
 267
 268 void __init omap4xxx_check_features(void)
 269 {
 270         u32 si_type;
 271
 272         if (cpu_is_omap443x())
 273                 omap_features |= OMAP4_HAS_MPU_1GHZ;
 274
 275
 276         if (cpu_is_omap446x()) {
 277                 si_type =
 278                         read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
 279                 switch ((si_type & (3 << 16)) >> 16) {
 280                 case 2:
 281                         /* High performance device */
 282                         omap_features |= OMAP4_HAS_MPU_1_5GHZ;
 283                         break;
 284                 case 1:
 285                 default:
 286                         /* Standard device */
 287                         omap_features |= OMAP4_HAS_MPU_1_2GHZ;
 288                         break;
 289                 }
 290         }
 291 }
 292
 293 void __init ti81xx_check_features(void)
 294 {
 295         omap_features = OMAP3_HAS_NEON;
 296         omap3_cpuinfo();
 297 }
 298
 299 void __init omap3xxx_check_revision(void)
 300 {
 301         const char *cpu_rev;
 302         u32 cpuid, idcode;
 303         u16 hawkeye;
 304         u8 rev;
 305
 306         /*
 307          * We cannot access revision registers on ES1.0.
 308          * If the processor type is Cortex-A8 and the revision is 0x0
 309          * it means its Cortex r0p0 which is 3430 ES1.0.
 310          */
 311         cpuid = read_cpuid(CPUID_ID);
 312         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 313                 omap_revision = OMAP3430_REV_ES1_0;
 314                 cpu_rev = "1.0";
 315                 return;
 316         }
 317
 318         /*
 319          * Detection for 34xx ES2.0 and above can be done with just
 320          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 321          * Note that rev does not map directly to our defined processor
 322          * revision numbers as ES1.0 uses value 0.
 323          */
 324         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 325         hawkeye = (idcode >> 12) & 0xffff;
 326         rev = (idcode >> 28) & 0xff;
 327
 328         switch (hawkeye) {
 329         case 0xb7ae:
 330                 /* Handle 34xx/35xx devices */
 331                 switch (rev) {
 332                 case 0: /* Take care of early samples */
 333                 case 1:
 334                         omap_revision = OMAP3430_REV_ES2_0;
 335                         cpu_rev = "2.0";
 336                         break;
 337                 case 2:
 338                         omap_revision = OMAP3430_REV_ES2_1;
 339                         cpu_rev = "2.1";
 340                         break;
 341                 case 3:
 342                         omap_revision = OMAP3430_REV_ES3_0;
 343                         cpu_rev = "3.0";
 344                         break;
 345                 case 4:
 346                         omap_revision = OMAP3430_REV_ES3_1;
 347                         cpu_rev = "3.1";
 348                         break;
 349                 case 7:
 350                 /* FALLTHROUGH */
 351                 default:
 352                         /* Use the latest known revision as default */
 353                         omap_revision = OMAP3430_REV_ES3_1_2;
 354                         cpu_rev = "3.1.2";
 355                 }
 356                 break;
 357         case 0xb868:
 358                 /*
 359                  * Handle OMAP/AM 3505/3517 devices
 360                  *
 361                  * Set the device to be OMAP3517 here. Actual device
 362                  * is identified later based on the features.
 363                  */
 364                 switch (rev) {
 365                 case 0:
 366                         omap_revision = OMAP3517_REV_ES1_0;
 367                         cpu_rev = "1.0";
 368                         break;
 369                 case 1:
 370                 /* FALLTHROUGH */
 371                 default:
 372                         omap_revision = OMAP3517_REV_ES1_1;
 373                         cpu_rev = "1.1";
 374                 }
 375                 break;
 376         case 0xb891:
 377                 /* Handle 36xx devices */
 378
 379                 switch(rev) {
 380                 case 0: /* Take care of early samples */
 381                         omap_revision = OMAP3630_REV_ES1_0;
 382                         cpu_rev = "1.0";
 383                         break;
 384                 case 1:
 385                         omap_revision = OMAP3630_REV_ES1_1;
 386                         cpu_rev = "1.1";
 387                         break;
 388                 case 2:
 389                 /* FALLTHROUGH */
 390                 default:
 391                         omap_revision = OMAP3630_REV_ES1_2;
 392                         cpu_rev = "1.2";
 393                 }
 394                 break;
 395         case 0xb81e:
 396                 switch (rev) {
 397                 case 0:
 398                         omap_revision = TI8168_REV_ES1_0;
 399                         cpu_rev = "1.0";
 400                         break;
 401                 case 1:
 402                 /* FALLTHROUGH */
 403                 default:
 404                         omap_revision = TI8168_REV_ES1_1;
 405                         cpu_rev = "1.1";
 406                         break;
 407                 }
 408                 break;
 409         default:
 410                 /* Unknown default to latest silicon rev as default */
 411                 omap_revision = OMAP3630_REV_ES1_2;
 412                 cpu_rev = "1.2";
 413                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 414         }
 415         sprintf(soc_rev, "ES%s", cpu_rev);
 416 }
 417
 418 void __init omap4xxx_check_revision(void)
 419 {
 420         u32 idcode;
 421         u16 hawkeye;
 422         u8 rev;
 423
 424         /*
 425          * The IC rev detection is done with hawkeye and rev.
 426          * Note that rev does not map directly to defined processor
 427          * revision numbers as ES1.0 uses value 0.
 428          */
 429         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 430         hawkeye = (idcode >> 12) & 0xffff;
 431         rev = (idcode >> 28) & 0xf;
 432
 433         /*
 434          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 435          * Use ARM register to detect the correct ES version
 436          */
 437         if (!rev && (hawkeye != 0xb94e)) {
 438                 idcode = read_cpuid(CPUID_ID);
 439                 rev = (idcode & 0xf) - 1;
 440         }
 441
 442         switch (hawkeye) {
 443         case 0xb852:
 444                 switch (rev) {
 445                 case 0:
 446                         omap_revision = OMAP4430_REV_ES1_0;
 447                         break;
 448                 case 1:
 449                 default:
 450                         omap_revision = OMAP4430_REV_ES2_0;
 451                 }
 452                 break;
 453         case 0xb95c:
 454                 switch (rev) {
 455                 case 3:
 456                         omap_revision = OMAP4430_REV_ES2_1;
 457                         break;
 458                 case 4:
 459                 default:
 460                         omap_revision = OMAP4430_REV_ES2_2;
 461                 }
 462                 break;
 463         case 0xb94e:
 464                 switch (rev) {
 465                 case 0:
 466                 default:
 467                         omap_revision = OMAP4460_REV_ES1_0;
 468                         break;
 469                 }
 470                 break;
 471         default:
 472                 /* Unknown default to latest silicon rev as default */
 473                 omap_revision = OMAP4430_REV_ES2_2;
 474         }
 475
 476         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 477         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 478                                                 (omap_rev() >> 8) & 0xf);
 479         pr_info("%s %s\n", soc_name, soc_rev);
 480 }
 481
 482 /*
 483  * Set up things for map_io and processor detection later on. Gets called
 484  * pretty much first thing from board init. For multi-omap, this gets
 485  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 486  * detect the exact revision later on in omap2_detect_revision() once map_io
 487  * is done.
 488  */
 489 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 490 {
 491         omap_revision = omap2_globals->class;
 492         tap_base = omap2_globals->tap;
 493
 494         if (cpu_is_omap34xx())
 495                 tap_prod_id = 0x0210;
 496         else
 497                 tap_prod_id = 0x0208;
 498 }
 499
 500 #ifdef CONFIG_SOC_BUS
 501
 502 static const char const *omap_types[] = {
 503         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
 504         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
 505         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
 506         [OMAP2_DEVICE_TYPE_GP]          = "GP",
 507         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
 508 };
 509
 510 static const char * __init omap_get_family(void)
 511 {
 512         if (cpu_is_omap24xx())
 513                 return kasprintf(GFP_KERNEL, "OMAP2");
 514         else if (cpu_is_omap34xx())
 515                 return kasprintf(GFP_KERNEL, "OMAP3");
 516         else if (cpu_is_omap44xx())
 517                 return kasprintf(GFP_KERNEL, "OMAP4");
 518         else
 519                 return kasprintf(GFP_KERNEL, "Unknown");
 520 }
 521
 522 static ssize_t omap_get_type(struct device *dev,
 523                                         struct device_attribute *attr,
 524                                         char *buf)
 525 {
 526         return sprintf(buf, "%s\n", omap_types[omap_type()]);
 527 }
 528
 529 static struct device_attribute omap_soc_attr =
 530         __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
 531
 532 int __init omap_soc_device_init(void)
 533 {
 534         struct device *parent;
 535         struct soc_device *soc_dev;
 536         struct soc_device_attribute *soc_dev_attr;
 537         int ret = 0;
 538
 539         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 540         if (!soc_dev_attr)
 541                 return -ENOMEM;
 542
 543         soc_dev_attr->machine  = soc_name;
 544         soc_dev_attr->family   = omap_get_family();
 545         soc_dev_attr->revision = soc_rev;
 546
 547         soc_dev = soc_device_register(soc_dev_attr);
 548         if (IS_ERR_OR_NULL(soc_dev)) {
 549                 kfree(soc_dev_attr);
 550                 return -ENODEV;
 551         }
 552
 553         parent = soc_device_to_device(soc_dev);
 554         if (!IS_ERR_OR_NULL(parent))
 555                 ret = device_create_file(parent, &omap_soc_attr);
 556
 557         return ret;
 558 }
 559 late_initcall(omap_soc_device_init);
 560
 561 #endif /* CONFIG_SOC_BUS */