2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Roy Zang <tie-fei.zang@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/fsl_law.h>
28 #include <asm/fsl_ddr_sdram.h>
29 #include <asm/global_data.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* Fixed sdram init -- doesn't use serial presence detect. */
36 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
38 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
40 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
41 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
42 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
43 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
44 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
45 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
46 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
47 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
48 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
49 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
50 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
51 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
52 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
53 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
54 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
55 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
56 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
57 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
58 out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
59 out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
60 /* Set, but do not enable the memory */
61 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
63 asm volatile("sync;isync");
66 /* Let the controller go */
67 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
70 void board_init_f(ulong bootflag)
73 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
75 /* initialize selected port with appropriate baud rate */
76 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
78 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
79 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
80 gd->bus_clk / 16 / CONFIG_BAUDRATE);
82 puts("\nNAND boot... ");
83 /* Initialize the DDR3 */
85 /* copy code to RAM and jump to it - this should not return */
86 /* NOTE - code has to be copied out of NAND buffer before
87 * other blocks can be read.
89 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
90 CONFIG_SYS_NAND_U_BOOT_RELOC);
93 void board_init_r(gd_t *gd, ulong dest_addr)
101 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
103 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
106 void puts(const char *str)