drivers/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004 Freescale Semiconductor.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
  69         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
  70 #elif defined(CONFIG_MPC86XX_TSEC1)
  71         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
  72 #else
  73         {0, 0, 0},
  74 #endif
  75 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
  76         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
  77 #elif defined(CONFIG_MPC86XX_TSEC2)
  78         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
  79 #else
  80         {0, 0, 0},
  81 #endif
  82 #ifdef CONFIG_MPC85XX_FEC
  83         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
  84 #else
  85 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
  86         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
  87 #else
  88         {0, 0, 0},
  89 #endif
  90 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
  91         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
  92 #else
  93         {0, 0, 0},
  94 #endif
  95 #endif
  96 };
  97
  98 #define MAXCONTROLLERS  (4)
  99
 100 static int relocated = 0;
 101
 102 static struct tsec_private *privlist[MAXCONTROLLERS];
 103
 104 #ifdef __GNUC__
 105 static RTXBD rtx __attribute__ ((aligned(8)));
 106 #else
 107 #error "rtx must be 64-bit aligned"
 108 #endif
 109
 110 static int tsec_send(struct eth_device *dev,
 111                      volatile void *packet, int length);
 112 static int tsec_recv(struct eth_device *dev);
 113 static int tsec_init(struct eth_device *dev, bd_t * bd);
 114 static void tsec_halt(struct eth_device *dev);
 115 static void init_registers(volatile tsec_t * regs);
 116 static void startup_tsec(struct eth_device *dev);
 117 static int init_phy(struct eth_device *dev);
 118 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 119 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 120 struct phy_info *get_phy_info(struct eth_device *dev);
 121 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 122 static void adjust_link(struct eth_device *dev);
 123 static void relocate_cmds(void);
 124 static int tsec_miiphy_write(char *devname, unsigned char addr,
 125                              unsigned char reg, unsigned short value);
 126 static int tsec_miiphy_read(char *devname, unsigned char addr,
 127                             unsigned char reg, unsigned short *value);
 128
 129 /* Initialize device structure. Returns success if PHY
 130  * initialization succeeded (i.e. if it recognizes the PHY)
 131  */
 132 int tsec_initialize(bd_t * bis, int index, char *devname)
 133 {
 134         struct eth_device *dev;
 135         int i;
 136         struct tsec_private *priv;
 137
 138         dev = (struct eth_device *)malloc(sizeof *dev);
 139
 140         if (NULL == dev)
 141                 return 0;
 142
 143         memset(dev, 0, sizeof *dev);
 144
 145         priv = (struct tsec_private *)malloc(sizeof(*priv));
 146
 147         if (NULL == priv)
 148                 return 0;
 149
 150         privlist[index] = priv;
 151         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 152         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 153                                             tsec_info[index].phyregidx *
 154                                             TSEC_SIZE);
 155
 156         priv->phyaddr = tsec_info[index].phyaddr;
 157         priv->flags = tsec_info[index].flags;
 158
 159         sprintf(dev->name, devname);
 160         dev->iobase = 0;
 161         dev->priv = priv;
 162         dev->init = tsec_init;
 163         dev->halt = tsec_halt;
 164         dev->send = tsec_send;
 165         dev->recv = tsec_recv;
 166
 167         /* Tell u-boot to get the addr from the env */
 168         for (i = 0; i < 6; i++)
 169                 dev->enetaddr[i] = 0;
 170
 171         eth_register(dev);
 172
 173         /* Reset the MAC */
 174         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 175         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 176
 177 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
 178         && !defined(BITBANGMII)
 179         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 180 #endif
 181
 182         /* Try to initialize PHY here, and return */
 183         return init_phy(dev);
 184 }
 185
 186 /* Initializes data structures and registers for the controller,
 187  * and brings the interface up.  Returns the link status, meaning
 188  * that it returns success if the link is up, failure otherwise.
 189  * This allows u-boot to find the first active controller.
 190  */
 191 int tsec_init(struct eth_device *dev, bd_t * bd)
 192 {
 193         uint tempval;
 194         char tmpbuf[MAC_ADDR_LEN];
 195         int i;
 196         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 197         volatile tsec_t *regs = priv->regs;
 198
 199         /* Make sure the controller is stopped */
 200         tsec_halt(dev);
 201
 202         /* Init MACCFG2.  Defaults to GMII */
 203         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 204
 205         /* Init ECNTRL */
 206         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 207
 208         /* Copy the station address into the address registers.
 209          * Backwards, because little endian MACS are dumb */
 210         for (i = 0; i < MAC_ADDR_LEN; i++) {
 211                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 212         }
 213         regs->macstnaddr1 = *((uint *) (tmpbuf));
 214
 215         tempval = *((uint *) (tmpbuf + 4));
 216
 217         regs->macstnaddr2 = tempval;
 218
 219         /* reset the indices to zero */
 220         rxIdx = 0;
 221         txIdx = 0;
 222
 223         /* Clear out (for the most part) the other registers */
 224         init_registers(regs);
 225
 226         /* Ready the device for tx/rx */
 227         startup_tsec(dev);
 228
 229         /* If there's no link, fail */
 230         return priv->link;
 231
 232 }
 233
 234 /* Write value to the device's PHY through the registers
 235  * specified in priv, modifying the register specified in regnum.
 236  * It will wait for the write to be done (or for a timeout to
 237  * expire) before exiting
 238  */
 239 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 240 {
 241         volatile tsec_t *regbase = priv->phyregs;
 242         uint phyid = priv->phyaddr;
 243         int timeout = 1000000;
 244
 245         regbase->miimadd = (phyid << 8) | regnum;
 246         regbase->miimcon = value;
 247         asm("sync");
 248
 249         timeout = 1000000;
 250         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 251 }
 252
 253 /* Reads register regnum on the device's PHY through the
 254  * registers specified in priv.  It lowers and raises the read
 255  * command, and waits for the data to become valid (miimind
 256  * notvalid bit cleared), and the bus to cease activity (miimind
 257  * busy bit cleared), and then returns the value
 258  */
 259 uint read_phy_reg(struct tsec_private *priv, uint regnum)
 260 {
 261         uint value;
 262         volatile tsec_t *regbase = priv->phyregs;
 263         uint phyid = priv->phyaddr;
 264
 265         /* Put the address of the phy, and the register
 266          * number into MIIMADD */
 267         regbase->miimadd = (phyid << 8) | regnum;
 268
 269         /* Clear the command register, and wait */
 270         regbase->miimcom = 0;
 271         asm("sync");
 272
 273         /* Initiate a read command, and wait */
 274         regbase->miimcom = MIIM_READ_COMMAND;
 275         asm("sync");
 276
 277         /* Wait for the the indication that the read is done */
 278         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 279
 280         /* Grab the value read from the PHY */
 281         value = regbase->miimstat;
 282
 283         return value;
 284 }
 285
 286 /* Discover which PHY is attached to the device, and configure it
 287  * properly.  If the PHY is not recognized, then return 0
 288  * (failure).  Otherwise, return 1
 289  */
 290 static int init_phy(struct eth_device *dev)
 291 {
 292         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 293         struct phy_info *curphy;
 294         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 295
 296         /* Assign a Physical address to the TBI */
 297         regs->tbipa = TBIPA_VALUE;
 298         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 299         regs->tbipa = TBIPA_VALUE;
 300         asm("sync");
 301
 302         /* Reset MII (due to new addresses) */
 303         priv->phyregs->miimcfg = MIIMCFG_RESET;
 304         asm("sync");
 305         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 306         asm("sync");
 307         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 308
 309         if (0 == relocated)
 310                 relocate_cmds();
 311
 312         /* Get the cmd structure corresponding to the attached
 313          * PHY */
 314         curphy = get_phy_info(dev);
 315
 316         if (curphy == NULL) {
 317                 priv->phyinfo = NULL;
 318                 printf("%s: No PHY found\n", dev->name);
 319
 320                 return 0;
 321         }
 322
 323         priv->phyinfo = curphy;
 324
 325         phy_run_commands(priv, priv->phyinfo->config);
 326
 327         return 1;
 328 }
 329
 330 /*
 331  * Returns which value to write to the control register.
 332  * For 10/100, the value is slightly different
 333  */
 334 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 335 {
 336         if (priv->flags & TSEC_GIGABIT)
 337                 return MIIM_CONTROL_INIT;
 338         else
 339                 return MIIM_CR_INIT;
 340 }
 341
 342 /* Parse the status register for link, and then do
 343  * auto-negotiation
 344  */
 345 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 346 {
 347         /*
 348          * Wait if PHY is capable of autonegotiation and autonegotiation
 349          * is not complete.
 350          */
 351         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 352         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
 353             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 354                 int i = 0;
 355
 356                 puts("Waiting for PHY auto negotiation to complete");
 357                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
 358                          && (mii_reg & MIIM_STATUS_LINK))) {
 359                         /*
 360                          * Timeout reached ?
 361                          */
 362                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 363                                 puts(" TIMEOUT !\n");
 364                                 priv->link = 0;
 365                                 return 0;
 366                         }
 367
 368                         if ((i++ % 1000) == 0) {
 369                                 putc('.');
 370                         }
 371                         udelay(1000);   /* 1 ms */
 372                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 373                 }
 374                 puts(" done\n");
 375                 priv->link = 1;
 376                 udelay(500000); /* another 500 ms (results in faster booting) */
 377         } else {
 378                 priv->link = 1;
 379         }
 380
 381         return 0;
 382 }
 383
 384 /*
 385  * Parse the BCM54xx status register for speed and duplex information.
 386  * The linux sungem_phy has this information, but in a table format.
 387  */
 388 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 389 {
 390
 391         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 392
 393                 case 1:
 394                         printf("Enet starting in 10BT/HD\n");
 395                         priv->duplexity = 0;
 396                         priv->speed = 10;
 397                         break;
 398
 399                 case 2:
 400                         printf("Enet starting in 10BT/FD\n");
 401                         priv->duplexity = 1;
 402                         priv->speed = 10;
 403                         break;
 404
 405                 case 3:
 406                         printf("Enet starting in 100BT/HD\n");
 407                         priv->duplexity = 0;
 408                         priv->speed = 100;
 409                         break;
 410
 411                 case 5:
 412                         printf("Enet starting in 100BT/FD\n");
 413                         priv->duplexity = 1;
 414                         priv->speed = 100;
 415                         break;
 416
 417                 case 6:
 418                         printf("Enet starting in 1000BT/HD\n");
 419                         priv->duplexity = 0;
 420                         priv->speed = 1000;
 421                         break;
 422
 423                 case 7:
 424                         printf("Enet starting in 1000BT/FD\n");
 425                         priv->duplexity = 1;
 426                         priv->speed = 1000;
 427                         break;
 428
 429                 default:
 430                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 431                         priv->duplexity = 0;
 432                         priv->speed = 10;
 433                         break;
 434         }
 435
 436         return 0;
 437
 438 }
 439 /* Parse the 88E1011's status register for speed and duplex
 440  * information
 441  */
 442 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 443 {
 444         uint speed;
 445
 446         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 447
 448         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 449               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 450                 int i = 0;
 451
 452                 puts("Waiting for PHY realtime link");
 453                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 454                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 455                         /*
 456                          * Timeout reached ?
 457                          */
 458                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 459                                 puts(" TIMEOUT !\n");
 460                                 priv->link = 0;
 461                                 break;
 462                         }
 463
 464                         if ((i++ % 1000) == 0) {
 465                                 putc('.');
 466                         }
 467                         udelay(1000);   /* 1 ms */
 468                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 469                 }
 470                 puts(" done\n");
 471                 udelay(500000); /* another 500 ms (results in faster booting) */
 472         }
 473
 474         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 475                 priv->duplexity = 1;
 476         else
 477                 priv->duplexity = 0;
 478
 479         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 480
 481         switch (speed) {
 482         case MIIM_88E1011_PHYSTAT_GBIT:
 483                 priv->speed = 1000;
 484                 break;
 485         case MIIM_88E1011_PHYSTAT_100:
 486                 priv->speed = 100;
 487                 break;
 488         default:
 489                 priv->speed = 10;
 490         }
 491
 492         return 0;
 493 }
 494
 495 /* Parse the cis8201's status register for speed and duplex
 496  * information
 497  */
 498 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 499 {
 500         uint speed;
 501
 502         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 503                 priv->duplexity = 1;
 504         else
 505                 priv->duplexity = 0;
 506
 507         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 508         switch (speed) {
 509         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 510                 priv->speed = 1000;
 511                 break;
 512         case MIIM_CIS8201_AUXCONSTAT_100:
 513                 priv->speed = 100;
 514                 break;
 515         default:
 516                 priv->speed = 10;
 517                 break;
 518         }
 519
 520         return 0;
 521 }
 522
 523 /* Parse the vsc8244's status register for speed and duplex
 524  * information
 525  */
 526 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 527 {
 528         uint speed;
 529
 530         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 531                 priv->duplexity = 1;
 532         else
 533                 priv->duplexity = 0;
 534
 535         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 536         switch (speed) {
 537         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 538                 priv->speed = 1000;
 539                 break;
 540         case MIIM_VSC8244_AUXCONSTAT_100:
 541                 priv->speed = 100;
 542                 break;
 543         default:
 544                 priv->speed = 10;
 545                 break;
 546         }
 547
 548         return 0;
 549 }
 550
 551 /* Parse the DM9161's status register for speed and duplex
 552  * information
 553  */
 554 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 555 {
 556         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 557                 priv->speed = 100;
 558         else
 559                 priv->speed = 10;
 560
 561         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 562                 priv->duplexity = 1;
 563         else
 564                 priv->duplexity = 0;
 565
 566         return 0;
 567 }
 568
 569 /*
 570  * Hack to write all 4 PHYs with the LED values
 571  */
 572 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 573 {
 574         uint phyid;
 575         volatile tsec_t *regbase = priv->phyregs;
 576         int timeout = 1000000;
 577
 578         for (phyid = 0; phyid < 4; phyid++) {
 579                 regbase->miimadd = (phyid << 8) | mii_reg;
 580                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 581                 asm("sync");
 582
 583                 timeout = 1000000;
 584                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 585         }
 586
 587         return MIIM_CIS8204_SLEDCON_INIT;
 588 }
 589
 590 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 591 {
 592         if (priv->flags & TSEC_REDUCED)
 593                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 594         else
 595                 return MIIM_CIS8204_EPHYCON_INIT;
 596 }
 597
 598 /* Initialized required registers to appropriate values, zeroing
 599  * those we don't care about (unless zero is bad, in which case,
 600  * choose a more appropriate value)
 601  */
 602 static void init_registers(volatile tsec_t * regs)
 603 {
 604         /* Clear IEVENT */
 605         regs->ievent = IEVENT_INIT_CLEAR;
 606
 607         regs->imask = IMASK_INIT_CLEAR;
 608
 609         regs->hash.iaddr0 = 0;
 610         regs->hash.iaddr1 = 0;
 611         regs->hash.iaddr2 = 0;
 612         regs->hash.iaddr3 = 0;
 613         regs->hash.iaddr4 = 0;
 614         regs->hash.iaddr5 = 0;
 615         regs->hash.iaddr6 = 0;
 616         regs->hash.iaddr7 = 0;
 617
 618         regs->hash.gaddr0 = 0;
 619         regs->hash.gaddr1 = 0;
 620         regs->hash.gaddr2 = 0;
 621         regs->hash.gaddr3 = 0;
 622         regs->hash.gaddr4 = 0;
 623         regs->hash.gaddr5 = 0;
 624         regs->hash.gaddr6 = 0;
 625         regs->hash.gaddr7 = 0;
 626
 627         regs->rctrl = 0x00000000;
 628
 629         /* Init RMON mib registers */
 630         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 631
 632         regs->rmon.cam1 = 0xffffffff;
 633         regs->rmon.cam2 = 0xffffffff;
 634
 635         regs->mrblr = MRBLR_INIT_SETTINGS;
 636
 637         regs->minflr = MINFLR_INIT_SETTINGS;
 638
 639         regs->attr = ATTR_INIT_SETTINGS;
 640         regs->attreli = ATTRELI_INIT_SETTINGS;
 641
 642 }
 643
 644 /* Configure maccfg2 based on negotiated speed and duplex
 645  * reported by PHY handling code
 646  */
 647 static void adjust_link(struct eth_device *dev)
 648 {
 649         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 650         volatile tsec_t *regs = priv->regs;
 651
 652         if (priv->link) {
 653                 if (priv->duplexity != 0)
 654                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 655                 else
 656                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 657
 658                 switch (priv->speed) {
 659                 case 1000:
 660                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 661                                          | MACCFG2_GMII);
 662                         break;
 663                 case 100:
 664                 case 10:
 665                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 666                                          | MACCFG2_MII);
 667
 668                         /* Set R100 bit in all modes although
 669                          * it is only used in RGMII mode
 670                          */
 671                         if (priv->speed == 100)
 672                                 regs->ecntrl |= ECNTRL_R100;
 673                         else
 674                                 regs->ecntrl &= ~(ECNTRL_R100);
 675                         break;
 676                 default:
 677                         printf("%s: Speed was bad\n", dev->name);
 678                         break;
 679                 }
 680
 681                 printf("Speed: %d, %s duplex\n", priv->speed,
 682                        (priv->duplexity) ? "full" : "half");
 683
 684         } else {
 685                 printf("%s: No link.\n", dev->name);
 686         }
 687 }
 688
 689 /* Set up the buffers and their descriptors, and bring up the
 690  * interface
 691  */
 692 static void startup_tsec(struct eth_device *dev)
 693 {
 694         int i;
 695         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 696         volatile tsec_t *regs = priv->regs;
 697
 698         /* Point to the buffer descriptors */
 699         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 700         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 701
 702         /* Initialize the Rx Buffer descriptors */
 703         for (i = 0; i < PKTBUFSRX; i++) {
 704                 rtx.rxbd[i].status = RXBD_EMPTY;
 705                 rtx.rxbd[i].length = 0;
 706                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 707         }
 708         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 709
 710         /* Initialize the TX Buffer Descriptors */
 711         for (i = 0; i < TX_BUF_CNT; i++) {
 712                 rtx.txbd[i].status = 0;
 713                 rtx.txbd[i].length = 0;
 714                 rtx.txbd[i].bufPtr = 0;
 715         }
 716         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 717
 718         /* Start up the PHY */
 719         if(priv->phyinfo)
 720                 phy_run_commands(priv, priv->phyinfo->startup);
 721         adjust_link(dev);
 722
 723         /* Enable Transmit and Receive */
 724         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 725
 726         /* Tell the DMA it is clear to go */
 727         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 728         regs->tstat = TSTAT_CLEAR_THALT;
 729         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 730 }
 731
 732 /* This returns the status bits of the device.  The return value
 733  * is never checked, and this is what the 8260 driver did, so we
 734  * do the same.  Presumably, this would be zero if there were no
 735  * errors
 736  */
 737 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 738 {
 739         int i;
 740         int result = 0;
 741         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 742         volatile tsec_t *regs = priv->regs;
 743
 744         /* Find an empty buffer descriptor */
 745         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 746                 if (i >= TOUT_LOOP) {
 747                         debug("%s: tsec: tx buffers full\n", dev->name);
 748                         return result;
 749                 }
 750         }
 751
 752         rtx.txbd[txIdx].bufPtr = (uint) packet;
 753         rtx.txbd[txIdx].length = length;
 754         rtx.txbd[txIdx].status |=
 755             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 756
 757         /* Tell the DMA to go */
 758         regs->tstat = TSTAT_CLEAR_THALT;
 759
 760         /* Wait for buffer to be transmitted */
 761         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 762                 if (i >= TOUT_LOOP) {
 763                         debug("%s: tsec: tx error\n", dev->name);
 764                         return result;
 765                 }
 766         }
 767
 768         txIdx = (txIdx + 1) % TX_BUF_CNT;
 769         result = rtx.txbd[txIdx].status & TXBD_STATS;
 770
 771         return result;
 772 }
 773
 774 static int tsec_recv(struct eth_device *dev)
 775 {
 776         int length;
 777         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 778         volatile tsec_t *regs = priv->regs;
 779
 780         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 781
 782                 length = rtx.rxbd[rxIdx].length;
 783
 784                 /* Send the packet up if there were no errors */
 785                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 786                         NetReceive(NetRxPackets[rxIdx], length - 4);
 787                 } else {
 788                         printf("Got error %x\n",
 789                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 790                 }
 791
 792                 rtx.rxbd[rxIdx].length = 0;
 793
 794                 /* Set the wrap bit if this is the last element in the list */
 795                 rtx.rxbd[rxIdx].status =
 796                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 797
 798                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 799         }
 800
 801         if (regs->ievent & IEVENT_BSY) {
 802                 regs->ievent = IEVENT_BSY;
 803                 regs->rstat = RSTAT_CLEAR_RHALT;
 804         }
 805
 806         return -1;
 807
 808 }
 809
 810 /* Stop the interface */
 811 static void tsec_halt(struct eth_device *dev)
 812 {
 813         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 814         volatile tsec_t *regs = priv->regs;
 815
 816         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 817         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 818
 819         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 820
 821         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 822
 823         /* Shut down the PHY, as needed */
 824         if(priv->phyinfo)
 825                 phy_run_commands(priv, priv->phyinfo->shutdown);
 826 }
 827
 828 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 829 struct phy_info phy_info_BCM5461S = {
 830         0x02060c1,      /* 5461 ID */
 831         "Broadcom BCM5461S",
 832         0, /* not clear to me what minor revisions we can shift away */
 833         (struct phy_cmd[]) { /* config */
 834                 /* Reset and configure the PHY */
 835                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 836                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 837                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 838                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 839                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 840                 {miim_end,}
 841         },
 842         (struct phy_cmd[]) { /* startup */
 843                 /* Status is read once to clear old link state */
 844                 {MIIM_STATUS, miim_read, NULL},
 845                 /* Auto-negotiate */
 846                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 847                 /* Read the status */
 848                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 849                 {miim_end,}
 850         },
 851         (struct phy_cmd[]) { /* shutdown */
 852                 {miim_end,}
 853         },
 854 };
 855
 856 struct phy_info phy_info_M88E1011S = {
 857         0x01410c6,
 858         "Marvell 88E1011S",
 859         4,
 860         (struct phy_cmd[]){     /* config */
 861                            /* Reset and configure the PHY */
 862                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 863                            {0x1d, 0x1f, NULL},
 864                            {0x1e, 0x200c, NULL},
 865                            {0x1d, 0x5, NULL},
 866                            {0x1e, 0x0, NULL},
 867                            {0x1e, 0x100, NULL},
 868                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 869                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 870                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 871                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 872                            {miim_end,}
 873                            },
 874         (struct phy_cmd[]){     /* startup */
 875                            /* Status is read once to clear old link state */
 876                            {MIIM_STATUS, miim_read, NULL},
 877                            /* Auto-negotiate */
 878                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 879                            /* Read the status */
 880                            {MIIM_88E1011_PHY_STATUS, miim_read,
 881                             &mii_parse_88E1011_psr},
 882                            {miim_end,}
 883                            },
 884         (struct phy_cmd[]){     /* shutdown */
 885                            {miim_end,}
 886                            },
 887 };
 888
 889 struct phy_info phy_info_M88E1111S = {
 890         0x01410cc,
 891         "Marvell 88E1111S",
 892         4,
 893         (struct phy_cmd[]){     /* config */
 894                            /* Reset and configure the PHY */
 895                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 896                            {0x1d, 0x1f, NULL},
 897                            {0x1e, 0x200c, NULL},
 898                            {0x1d, 0x5, NULL},
 899                            {0x1e, 0x0, NULL},
 900                            {0x1e, 0x100, NULL},
 901                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
 902                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 903                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 904                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 905                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 906                            {miim_end,}
 907                            },
 908         (struct phy_cmd[]){     /* startup */
 909                            /* Status is read once to clear old link state */
 910                            {MIIM_STATUS, miim_read, NULL},
 911                            /* Auto-negotiate */
 912                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 913                            /* Read the status */
 914                            {MIIM_88E1011_PHY_STATUS, miim_read,
 915                             &mii_parse_88E1011_psr},
 916                            {miim_end,}
 917                            },
 918         (struct phy_cmd[]){     /* shutdown */
 919                            {miim_end,}
 920                            },
 921 };
 922
 923 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 924 {
 925         uint mii_data = read_phy_reg(priv, mii_reg);
 926
 927         /* Setting MIIM_88E1145_PHY_EXT_CR */
 928         if (priv->flags & TSEC_REDUCED)
 929                 return mii_data |
 930                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
 931         else
 932                 return mii_data;
 933 }
 934
 935 static struct phy_info phy_info_M88E1145 = {
 936         0x01410cd,
 937         "Marvell 88E1145",
 938         4,
 939         (struct phy_cmd[]){     /* config */
 940                            /* Errata E0, E1 */
 941                            {29, 0x001b, NULL},
 942                            {30, 0x418f, NULL},
 943                            {29, 0x0016, NULL},
 944                            {30, 0xa2da, NULL},
 945
 946                            /* Reset and configure the PHY */
 947                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 948                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 949                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 950                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
 951                             NULL},
 952                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
 953                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 954                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
 955                            {miim_end,}
 956                            },
 957         (struct phy_cmd[]){     /* startup */
 958                            /* Status is read once to clear old link state */
 959                            {MIIM_STATUS, miim_read, NULL},
 960                            /* Auto-negotiate */
 961                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 962                            {MIIM_88E1111_PHY_LED_CONTROL,
 963                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
 964                            /* Read the Status */
 965                            {MIIM_88E1011_PHY_STATUS, miim_read,
 966                             &mii_parse_88E1011_psr},
 967                            {miim_end,}
 968                            },
 969         (struct phy_cmd[]){     /* shutdown */
 970                            {miim_end,}
 971                            },
 972 };
 973
 974 struct phy_info phy_info_cis8204 = {
 975         0x3f11,
 976         "Cicada Cis8204",
 977         6,
 978         (struct phy_cmd[]){     /* config */
 979                            /* Override PHY config settings */
 980                            {MIIM_CIS8201_AUX_CONSTAT,
 981                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
 982                            /* Configure some basic stuff */
 983                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 984                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
 985                             &mii_cis8204_fixled},
 986                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
 987                             &mii_cis8204_setmode},
 988                            {miim_end,}
 989                            },
 990         (struct phy_cmd[]){     /* startup */
 991                            /* Read the Status (2x to make sure link is right) */
 992                            {MIIM_STATUS, miim_read, NULL},
 993                            /* Auto-negotiate */
 994                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 995                            /* Read the status */
 996                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
 997                             &mii_parse_cis8201},
 998                            {miim_end,}
 999                            },
1000         (struct phy_cmd[]){     /* shutdown */
1001                            {miim_end,}
1002                            },
1003 };
1004
1005 /* Cicada 8201 */
1006 struct phy_info phy_info_cis8201 = {
1007         0xfc41,
1008         "CIS8201",
1009         4,
1010         (struct phy_cmd[]){     /* config */
1011                            /* Override PHY config settings */
1012                            {MIIM_CIS8201_AUX_CONSTAT,
1013                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1014                            /* Set up the interface mode */
1015                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1016                             NULL},
1017                            /* Configure some basic stuff */
1018                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1019                            {miim_end,}
1020                            },
1021         (struct phy_cmd[]){     /* startup */
1022                            /* Read the Status (2x to make sure link is right) */
1023                            {MIIM_STATUS, miim_read, NULL},
1024                            /* Auto-negotiate */
1025                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1026                            /* Read the status */
1027                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1028                             &mii_parse_cis8201},
1029                            {miim_end,}
1030                            },
1031         (struct phy_cmd[]){     /* shutdown */
1032                            {miim_end,}
1033                            },
1034 };
1035 struct phy_info phy_info_VSC8244 = {
1036         0x3f1b,
1037         "Vitesse VSC8244",
1038         6,
1039         (struct phy_cmd[]){     /* config */
1040                            /* Override PHY config settings */
1041                            /* Configure some basic stuff */
1042                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1043                            {miim_end,}
1044                            },
1045         (struct phy_cmd[]){     /* startup */
1046                            /* Read the Status (2x to make sure link is right) */
1047                            {MIIM_STATUS, miim_read, NULL},
1048                            /* Auto-negotiate */
1049                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1050                            /* Read the status */
1051                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1052                             &mii_parse_vsc8244},
1053                            {miim_end,}
1054                            },
1055         (struct phy_cmd[]){     /* shutdown */
1056                            {miim_end,}
1057                            },
1058 };
1059
1060 struct phy_info phy_info_dm9161 = {
1061         0x0181b88,
1062         "Davicom DM9161E",
1063         4,
1064         (struct phy_cmd[]){     /* config */
1065                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1066                            /* Do not bypass the scrambler/descrambler */
1067                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1068                            /* Clear 10BTCSR to default */
1069                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1070                             NULL},
1071                            /* Configure some basic stuff */
1072                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1073                            /* Restart Auto Negotiation */
1074                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1075                            {miim_end,}
1076                            },
1077         (struct phy_cmd[]){     /* startup */
1078                            /* Status is read once to clear old link state */
1079                            {MIIM_STATUS, miim_read, NULL},
1080                            /* Auto-negotiate */
1081                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1082                            /* Read the status */
1083                            {MIIM_DM9161_SCSR, miim_read,
1084                             &mii_parse_dm9161_scsr},
1085                            {miim_end,}
1086                            },
1087         (struct phy_cmd[]){     /* shutdown */
1088                            {miim_end,}
1089                            },
1090 };
1091
1092 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1093 {
1094         unsigned int speed;
1095         if (priv->link) {
1096                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1097
1098                 switch (speed) {
1099                 case MIIM_LXT971_SR2_10HDX:
1100                         priv->speed = 10;
1101                         priv->duplexity = 0;
1102                         break;
1103                 case MIIM_LXT971_SR2_10FDX:
1104                         priv->speed = 10;
1105                         priv->duplexity = 1;
1106                         break;
1107                 case MIIM_LXT971_SR2_100HDX:
1108                         priv->speed = 100;
1109                         priv->duplexity = 0;
1110                 default:
1111                         priv->speed = 100;
1112                         priv->duplexity = 1;
1113                         break;
1114                 }
1115         } else {
1116                 priv->speed = 0;
1117                 priv->duplexity = 0;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static struct phy_info phy_info_lxt971 = {
1124         0x0001378e,
1125         "LXT971",
1126         4,
1127         (struct phy_cmd[]){     /* config */
1128                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1129                            {miim_end,}
1130                            },
1131         (struct phy_cmd[]){     /* startup - enable interrupts */
1132                            /* { 0x12, 0x00f2, NULL }, */
1133                            {MIIM_STATUS, miim_read, NULL},
1134                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1135                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1136                            {miim_end,}
1137                            },
1138         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1139                            {miim_end,}
1140                            },
1141 };
1142
1143 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1144  * information
1145  */
1146 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1147 {
1148         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1149
1150         case MIIM_DP83865_SPD_1000:
1151                 priv->speed = 1000;
1152                 break;
1153
1154         case MIIM_DP83865_SPD_100:
1155                 priv->speed = 100;
1156                 break;
1157
1158         default:
1159                 priv->speed = 10;
1160                 break;
1161
1162         }
1163
1164         if (mii_reg & MIIM_DP83865_DPX_FULL)
1165                 priv->duplexity = 1;
1166         else
1167                 priv->duplexity = 0;
1168
1169         return 0;
1170 }
1171
1172 struct phy_info phy_info_dp83865 = {
1173         0x20005c7,
1174         "NatSemi DP83865",
1175         4,
1176         (struct phy_cmd[]){     /* config */
1177                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1178                            {miim_end,}
1179                            },
1180         (struct phy_cmd[]){     /* startup */
1181                            /* Status is read once to clear old link state */
1182                            {MIIM_STATUS, miim_read, NULL},
1183                            /* Auto-negotiate */
1184                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1185                            /* Read the link and auto-neg status */
1186                            {MIIM_DP83865_LANR, miim_read,
1187                             &mii_parse_dp83865_lanr},
1188                            {miim_end,}
1189                            },
1190         (struct phy_cmd[]){     /* shutdown */
1191                            {miim_end,}
1192                            },
1193 };
1194
1195 struct phy_info *phy_info[] = {
1196         &phy_info_cis8204,
1197         &phy_info_cis8201,
1198         &phy_info_BCM5461S,
1199         &phy_info_M88E1011S,
1200         &phy_info_M88E1111S,
1201         &phy_info_M88E1145,
1202         &phy_info_dm9161,
1203         &phy_info_lxt971,
1204         &phy_info_VSC8244,
1205         &phy_info_dp83865,
1206         NULL
1207 };
1208
1209 /* Grab the identifier of the device's PHY, and search through
1210  * all of the known PHYs to see if one matches.  If so, return
1211  * it, if not, return NULL
1212  */
1213 struct phy_info *get_phy_info(struct eth_device *dev)
1214 {
1215         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1216         uint phy_reg, phy_ID;
1217         int i;
1218         struct phy_info *theInfo = NULL;
1219
1220         /* Grab the bits from PHYIR1, and put them in the upper half */
1221         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1222         phy_ID = (phy_reg & 0xffff) << 16;
1223
1224         /* Grab the bits from PHYIR2, and put them in the lower half */
1225         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1226         phy_ID |= (phy_reg & 0xffff);
1227
1228         /* loop through all the known PHY types, and find one that */
1229         /* matches the ID we read from the PHY. */
1230         for (i = 0; phy_info[i]; i++) {
1231                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1232                         theInfo = phy_info[i];
1233         }
1234
1235         if (theInfo == NULL) {
1236                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1237                 return NULL;
1238         } else {
1239                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1240         }
1241
1242         return theInfo;
1243 }
1244
1245 /* Execute the given series of commands on the given device's
1246  * PHY, running functions as necessary
1247  */
1248 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1249 {
1250         int i;
1251         uint result;
1252         volatile tsec_t *phyregs = priv->phyregs;
1253
1254         phyregs->miimcfg = MIIMCFG_RESET;
1255
1256         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1257
1258         while (phyregs->miimind & MIIMIND_BUSY) ;
1259
1260         for (i = 0; cmd->mii_reg != miim_end; i++) {
1261                 if (cmd->mii_data == miim_read) {
1262                         result = read_phy_reg(priv, cmd->mii_reg);
1263
1264                         if (cmd->funct != NULL)
1265                                 (*(cmd->funct)) (result, priv);
1266
1267                 } else {
1268                         if (cmd->funct != NULL)
1269                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1270                         else
1271                                 result = cmd->mii_data;
1272
1273                         write_phy_reg(priv, cmd->mii_reg, result);
1274
1275                 }
1276                 cmd++;
1277         }
1278 }
1279
1280 /* Relocate the function pointers in the phy cmd lists */
1281 static void relocate_cmds(void)
1282 {
1283         struct phy_cmd **cmdlistptr;
1284         struct phy_cmd *cmd;
1285         int i, j, k;
1286
1287         for (i = 0; phy_info[i]; i++) {
1288                 /* First thing's first: relocate the pointers to the
1289                  * PHY command structures (the structs were done) */
1290                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1291                                                   + gd->reloc_off);
1292                 phy_info[i]->name += gd->reloc_off;
1293                 phy_info[i]->config =
1294                     (struct phy_cmd *)((uint) phy_info[i]->config
1295                                        + gd->reloc_off);
1296                 phy_info[i]->startup =
1297                     (struct phy_cmd *)((uint) phy_info[i]->startup
1298                                        + gd->reloc_off);
1299                 phy_info[i]->shutdown =
1300                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1301                                        + gd->reloc_off);
1302
1303                 cmdlistptr = &phy_info[i]->config;
1304                 j = 0;
1305                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1306                         k = 0;
1307                         for (cmd = *cmdlistptr;
1308                              cmd->mii_reg != miim_end;
1309                              cmd++) {
1310                                 /* Only relocate non-NULL pointers */
1311                                 if (cmd->funct)
1312                                         cmd->funct += gd->reloc_off;
1313
1314                                 k++;
1315                         }
1316                         j++;
1317                 }
1318         }
1319
1320         relocated = 1;
1321 }
1322
1323 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1324         && !defined(BITBANGMII)
1325
1326 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1327 {
1328         int i;
1329
1330         for (i = 0; i < MAXCONTROLLERS; i++) {
1331                 if (privlist[i]->phyaddr == phyaddr)
1332                         return privlist[i];
1333         }
1334
1335         return NULL;
1336 }
1337
1338 /*
1339  * Read a MII PHY register.
1340  *
1341  * Returns:
1342  *  0 on success
1343  */
1344 static int tsec_miiphy_read(char *devname, unsigned char addr,
1345                             unsigned char reg, unsigned short *value)
1346 {
1347         unsigned short ret;
1348         struct tsec_private *priv = get_priv_for_phy(addr);
1349
1350         if (NULL == priv) {
1351                 printf("Can't read PHY at address %d\n", addr);
1352                 return -1;
1353         }
1354
1355         ret = (unsigned short)read_phy_reg(priv, reg);
1356         *value = ret;
1357
1358         return 0;
1359 }
1360
1361 /*
1362  * Write a MII PHY register.
1363  *
1364  * Returns:
1365  *  0 on success
1366  */
1367 static int tsec_miiphy_write(char *devname, unsigned char addr,
1368                              unsigned char reg, unsigned short value)
1369 {
1370         struct tsec_private *priv = get_priv_for_phy(addr);
1371
1372         if (NULL == priv) {
1373                 printf("Can't write PHY at address %d\n", addr);
1374                 return -1;
1375         }
1376
1377         write_phy_reg(priv, reg, value);
1378
1379         return 0;
1380 }
1381
1382 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1383                 && !defined(BITBANGMII) */
1384
1385 #endif /* CONFIG_TSEC_ENET */