drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <twl6035.h>
  33 #include <asm/io.h>
  34 #include <asm/arch/mmc_host_def.h>
  35 #include <asm/arch/sys_proto.h>
  36
  37 /* common definitions for all OMAPs */
  38 #define SYSCTL_SRC      (1 << 25)
  39 #define SYSCTL_SRD      (1 << 26)
  40
  41 /* If we fail after 1 second wait, something is really bad */
  42 #define MAX_RETRY_MS    1000
  43
  44 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  45 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  46                         unsigned int siz);
  47 static struct mmc hsmmc_dev[2];
  48
  49 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  50 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  51 {
  52         u32 value = 0;
  53         struct omap_sys_ctrl_regs *const ctrl =
  54                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  55
  56
  57         value = readl(&ctrl->control_pbiaslite);
  58         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  59         writel(value, &ctrl->control_pbiaslite);
  60         /* set VMMC to 3V */
  61         twl6030_power_mmc_init();
  62         value = readl(&ctrl->control_pbiaslite);
  63         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
  64         writel(value, &ctrl->control_pbiaslite);
  65 }
  66 #endif
  67
  68 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
  69 static void omap5_pbias_config(struct mmc *mmc)
  70 {
  71         u32 value = 0;
  72         struct omap_sys_ctrl_regs *const ctrl =
  73                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  74
  75         value = readl(&ctrl->control_pbias);
  76         value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
  77         value |= SDCARD_BIAS_HIZ_MODE;
  78         writel(value, &ctrl->control_pbias);
  79
  80         twl6035_mmc1_poweron_ldo();
  81
  82         value = readl(&ctrl->control_pbias);
  83         value &= ~SDCARD_BIAS_HIZ_MODE;
  84         value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
  85         writel(value, &ctrl->control_pbias);
  86
  87         value = readl(&ctrl->control_pbias);
  88         if (value & (1 << 23)) {
  89                 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
  90                 value |= SDCARD_BIAS_HIZ_MODE;
  91                 writel(value, &ctrl->control_pbias);
  92         }
  93 }
  94 #endif
  95
  96 unsigned char mmc_board_init(struct mmc *mmc)
  97 {
  98 #if defined(CONFIG_OMAP34XX)
  99         t2_t *t2_base = (t2_t *)T2_BASE;
 100         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 101         u32 pbias_lite;
 102
 103         pbias_lite = readl(&t2_base->pbias_lite);
 104         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 105         writel(pbias_lite, &t2_base->pbias_lite);
 106 #endif
 107 #if defined(CONFIG_TWL4030_POWER)
 108         twl4030_power_mmc_init();
 109         mdelay(100);    /* ramp-up delay from Linux code */
 110 #endif
 111 #if defined(CONFIG_OMAP34XX)
 112         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 113                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 114                 &t2_base->pbias_lite);
 115
 116         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 117                 &t2_base->devconf0);
 118 /*
 119         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 120                 &t2_base->devconf1);
 121 */
 122
 123         /* Change from default of 52MHz to 26MHz if necessary */
 124         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
 125                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 126                         &t2_base->ctl_prog_io1);
 127
 128         writel(readl(&prcm_base->fclken1_core) |
 129                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 130                 &prcm_base->fclken1_core);
 131
 132         writel(readl(&prcm_base->iclken1_core) |
 133                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 134                 &prcm_base->iclken1_core);
 135 #endif
 136
 137 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 138         /* PBIAS config needed for MMC1 only */
 139         if (mmc->block_dev.dev == 0)
 140                 omap4_vmmc_pbias_config(mmc);
 141 #endif
 142 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
 143         if (mmc->block_dev.dev == 0)
 144                 omap5_pbias_config(mmc);
 145 #endif
 146
 147         return 0;
 148 }
 149
 150 void mmc_init_stream(struct hsmmc *mmc_base)
 151 {
 152         ulong start;
 153
 154         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 155
 156         writel(MMC_CMD0, &mmc_base->cmd);
 157         start = get_timer(0);
 158         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 159                 if (get_timer(0) - start > MAX_RETRY_MS) {
 160                         printf("%s: timedout waiting for cc!\n", __func__);
 161                         return;
 162                 }
 163         }
 164         writel(CC_MASK, &mmc_base->stat)
 165                 ;
 166         writel(MMC_CMD0, &mmc_base->cmd)
 167                 ;
 168         start = get_timer(0);
 169         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 170                 if (get_timer(0) - start > MAX_RETRY_MS) {
 171                         printf("%s: timedout waiting for cc2!\n", __func__);
 172                         return;
 173                 }
 174         }
 175         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 176 }
 177
 178
 179 static int mmc_init_setup(struct mmc *mmc)
 180 {
 181         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 182         unsigned int reg_val;
 183         unsigned int dsor;
 184         ulong start;
 185
 186         mmc_board_init(mmc);
 187
 188         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 189                 &mmc_base->sysconfig);
 190         start = get_timer(0);
 191         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 192                 if (get_timer(0) - start > MAX_RETRY_MS) {
 193                         printf("%s: timedout waiting for cc2!\n", __func__);
 194                         return TIMEOUT;
 195                 }
 196         }
 197         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 198         start = get_timer(0);
 199         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 200                 if (get_timer(0) - start > MAX_RETRY_MS) {
 201                         printf("%s: timedout waiting for softresetall!\n",
 202                                 __func__);
 203                         return TIMEOUT;
 204                 }
 205         }
 206         reg_val = DTW_1_BITMODE | SDBP_PWROFF;
 207         if (mmc->block_dev.dev == 0)
 208                 reg_val |= SDVS_3V0;
 209         else
 210                 reg_val |= SDVS_1V8;
 211         writel(reg_val, &mmc_base->hctl);
 212
 213         reg_val = readl(&mmc_base->capa) | VS18_1V8SUP;
 214         if (mmc->block_dev.dev == 0)
 215                 reg_val |= VS30_3V0SUP;
 216         writel(reg_val, &mmc_base->capa);
 217
 218         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 219
 220         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 221                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 222                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 223
 224         dsor = 240;
 225         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 226                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 227         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 228                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 229         start = get_timer(0);
 230         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 231                 if (get_timer(0) - start > MAX_RETRY_MS) {
 232                         printf("%s: timedout waiting for ics!\n", __func__);
 233                         return TIMEOUT;
 234                 }
 235         }
 236         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 237
 238         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 239
 240         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 241                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 242                 &mmc_base->ie);
 243
 244         mmc_init_stream(mmc_base);
 245
 246         return 0;
 247 }
 248
 249 /*
 250  * MMC controller internal finite state machine reset
 251  *
 252  * Used to reset command or data internal state machines, using respectively
 253  * SRC or SRD bit of SYSCTL register
 254  */
 255 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 256 {
 257         ulong start;
 258
 259         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 260
 261         start = get_timer(0);
 262         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 263                 if (get_timer(0) - start > MAX_RETRY_MS) {
 264                         printf("%s: timedout waiting for sysctl %x to clear\n",
 265                                 __func__, bit);
 266                         return;
 267                 }
 268         }
 269 }
 270
 271 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 272                         struct mmc_data *data)
 273 {
 274         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 275         unsigned int flags, mmc_stat;
 276         ulong start;
 277
 278         start = get_timer(0);
 279         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 280                 if (get_timer(0) - start > MAX_RETRY_MS) {
 281                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 282                                         __func__);
 283                         return TIMEOUT;
 284                 }
 285         }
 286         writel(0xFFFFFFFF, &mmc_base->stat);
 287         start = get_timer(0);
 288         while (readl(&mmc_base->stat)) {
 289                 if (get_timer(0) - start > MAX_RETRY_MS) {
 290                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 291                                 __func__, readl(&mmc_base->stat));
 292                         return TIMEOUT;
 293                 }
 294         }
 295         /*
 296          * CMDREG
 297          * CMDIDX[13:8] : Command index
 298          * DATAPRNT[5]  : Data Present Select
 299          * ENCMDIDX[4]  : Command Index Check Enable
 300          * ENCMDCRC[3]  : Command CRC Check Enable
 301          * RSPTYP[1:0]
 302          *      00 = No Response
 303          *      01 = Length 136
 304          *      10 = Length 48
 305          *      11 = Length 48 Check busy after response
 306          */
 307         /* Delay added before checking the status of frq change
 308          * retry not supported by mmc.c(core file)
 309          */
 310         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 311                 udelay(50000); /* wait 50 ms */
 312
 313         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 314                 flags = 0;
 315         else if (cmd->resp_type & MMC_RSP_136)
 316                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 317         else if (cmd->resp_type & MMC_RSP_BUSY)
 318                 flags = RSP_TYPE_LGHT48B;
 319         else
 320                 flags = RSP_TYPE_LGHT48;
 321
 322         /* enable default flags */
 323         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 324                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 325
 326         if (cmd->resp_type & MMC_RSP_CRC)
 327                 flags |= CCCE_CHECK;
 328         if (cmd->resp_type & MMC_RSP_OPCODE)
 329                 flags |= CICE_CHECK;
 330
 331         if (data) {
 332                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 333                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 334                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 335                         data->blocksize = 512;
 336                         writel(data->blocksize | (data->blocks << 16),
 337                                                         &mmc_base->blk);
 338                 } else
 339                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 340
 341                 if (data->flags & MMC_DATA_READ)
 342                         flags |= (DP_DATA | DDIR_READ);
 343                 else
 344                         flags |= (DP_DATA | DDIR_WRITE);
 345         }
 346
 347         writel(cmd->cmdarg, &mmc_base->arg);
 348         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 349
 350         start = get_timer(0);
 351         do {
 352                 mmc_stat = readl(&mmc_base->stat);
 353                 if (get_timer(0) - start > MAX_RETRY_MS) {
 354                         printf("%s : timeout: No status update\n", __func__);
 355                         return TIMEOUT;
 356                 }
 357         } while (!mmc_stat);
 358
 359         if ((mmc_stat & IE_CTO) != 0) {
 360                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 361                 return TIMEOUT;
 362         } else if ((mmc_stat & ERRI_MASK) != 0)
 363                 return -1;
 364
 365         if (mmc_stat & CC_MASK) {
 366                 writel(CC_MASK, &mmc_base->stat);
 367                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 368                         if (cmd->resp_type & MMC_RSP_136) {
 369                                 /* response type 2 */
 370                                 cmd->response[3] = readl(&mmc_base->rsp10);
 371                                 cmd->response[2] = readl(&mmc_base->rsp32);
 372                                 cmd->response[1] = readl(&mmc_base->rsp54);
 373                                 cmd->response[0] = readl(&mmc_base->rsp76);
 374                         } else
 375                                 /* response types 1, 1b, 3, 4, 5, 6 */
 376                                 cmd->response[0] = readl(&mmc_base->rsp10);
 377                 }
 378         }
 379
 380         if (data && (data->flags & MMC_DATA_READ)) {
 381                 mmc_read_data(mmc_base, data->dest,
 382                                 data->blocksize * data->blocks);
 383         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 384                 mmc_write_data(mmc_base, data->src,
 385                                 data->blocksize * data->blocks);
 386         }
 387         return 0;
 388 }
 389
 390 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 391 {
 392         unsigned int *output_buf = (unsigned int *)buf;
 393         unsigned int mmc_stat;
 394         unsigned int count;
 395
 396         /*
 397          * Start Polled Read
 398          */
 399         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 400         count /= 4;
 401
 402         while (size) {
 403                 ulong start = get_timer(0);
 404                 do {
 405                         mmc_stat = readl(&mmc_base->stat);
 406                         if (get_timer(0) - start > MAX_RETRY_MS) {
 407                                 printf("%s: timedout waiting for status!\n",
 408                                                 __func__);
 409                                 return TIMEOUT;
 410                         }
 411                 } while (mmc_stat == 0);
 412
 413                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 414                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 415
 416                 if ((mmc_stat & ERRI_MASK) != 0)
 417                         return 1;
 418
 419                 if (mmc_stat & BRR_MASK) {
 420                         unsigned int k;
 421
 422                         writel(readl(&mmc_base->stat) | BRR_MASK,
 423                                 &mmc_base->stat);
 424                         for (k = 0; k < count; k++) {
 425                                 *output_buf = readl(&mmc_base->data);
 426                                 output_buf++;
 427                         }
 428                         size -= (count*4);
 429                 }
 430
 431                 if (mmc_stat & BWR_MASK)
 432                         writel(readl(&mmc_base->stat) | BWR_MASK,
 433                                 &mmc_base->stat);
 434
 435                 if (mmc_stat & TC_MASK) {
 436                         writel(readl(&mmc_base->stat) | TC_MASK,
 437                                 &mmc_base->stat);
 438                         break;
 439                 }
 440         }
 441         return 0;
 442 }
 443
 444 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 445                                 unsigned int size)
 446 {
 447         unsigned int *input_buf = (unsigned int *)buf;
 448         unsigned int mmc_stat;
 449         unsigned int count;
 450
 451         /*
 452          * Start Polled Read
 453          */
 454         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 455         count /= 4;
 456
 457         while (size) {
 458                 ulong start = get_timer(0);
 459                 do {
 460                         mmc_stat = readl(&mmc_base->stat);
 461                         if (get_timer(0) - start > MAX_RETRY_MS) {
 462                                 printf("%s: timedout waiting for status!\n",
 463                                                 __func__);
 464                                 return TIMEOUT;
 465                         }
 466                 } while (mmc_stat == 0);
 467
 468                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 469                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 470
 471                 if ((mmc_stat & ERRI_MASK) != 0)
 472                         return 1;
 473
 474                 if (mmc_stat & BWR_MASK) {
 475                         unsigned int k;
 476
 477                         writel(readl(&mmc_base->stat) | BWR_MASK,
 478                                         &mmc_base->stat);
 479                         for (k = 0; k < count; k++) {
 480                                 writel(*input_buf, &mmc_base->data);
 481                                 input_buf++;
 482                         }
 483                         size -= (count*4);
 484                 }
 485
 486                 if (mmc_stat & BRR_MASK)
 487                         writel(readl(&mmc_base->stat) | BRR_MASK,
 488                                 &mmc_base->stat);
 489
 490                 if (mmc_stat & TC_MASK) {
 491                         writel(readl(&mmc_base->stat) | TC_MASK,
 492                                 &mmc_base->stat);
 493                         break;
 494                 }
 495         }
 496         return 0;
 497 }
 498
 499 static void mmc_set_ios(struct mmc *mmc)
 500 {
 501         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 502         unsigned int dsor = 0;
 503         ulong start;
 504
 505         /* configue bus width */
 506         switch (mmc->bus_width) {
 507         case 8:
 508                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 509                         &mmc_base->con);
 510                 break;
 511
 512         case 4:
 513                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 514                         &mmc_base->con);
 515                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 516                         &mmc_base->hctl);
 517                 break;
 518
 519         case 1:
 520         default:
 521                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 522                         &mmc_base->con);
 523                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 524                         &mmc_base->hctl);
 525                 break;
 526         }
 527
 528         /* configure clock with 96Mhz system clock.
 529          */
 530         if (mmc->clock != 0) {
 531                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 532                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 533                         dsor++;
 534         }
 535
 536         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 537                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 538
 539         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 540                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 541
 542         start = get_timer(0);
 543         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 544                 if (get_timer(0) - start > MAX_RETRY_MS) {
 545                         printf("%s: timedout waiting for ics!\n", __func__);
 546                         return;
 547                 }
 548         }
 549         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 550 }
 551
 552 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
 553 {
 554         struct mmc *mmc;
 555
 556         mmc = &hsmmc_dev[dev_index];
 557
 558         sprintf(mmc->name, "OMAP SD/MMC");
 559         mmc->send_cmd = mmc_send_cmd;
 560         mmc->set_ios = mmc_set_ios;
 561         mmc->init = mmc_init_setup;
 562         mmc->getcd = NULL;
 563
 564         switch (dev_index) {
 565         case 0:
 566                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 567                 break;
 568 #ifdef OMAP_HSMMC2_BASE
 569         case 1:
 570                 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
 571                 break;
 572 #endif
 573 #ifdef OMAP_HSMMC3_BASE
 574         case 2:
 575                 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
 576                 break;
 577 #endif
 578         default:
 579                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 580                 return 1;
 581         }
 582         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 583         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 584                                 MMC_MODE_HC) & ~host_caps_mask;
 585
 586         mmc->f_min = 400000;
 587
 588         if (f_max != 0)
 589                 mmc->f_max = f_max;
 590         else {
 591                 if (mmc->host_caps & MMC_MODE_HS) {
 592                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
 593                                 mmc->f_max = 52000000;
 594                         else
 595                                 mmc->f_max = 26000000;
 596                 } else
 597                         mmc->f_max = 20000000;
 598         }
 599
 600         mmc->b_max = 0;
 601
 602 #if defined(CONFIG_OMAP34XX)
 603         /*
 604          * Silicon revs 2.1 and older do not support multiblock transfers.
 605          */
 606         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 607                 mmc->b_max = 1;
 608 #endif
 609
 610         mmc_register(mmc);
 611
 612         return 0;
 613 }