drivers/clk/rockchip/clk_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <mapmem.h>
  15 #include <syscon.h>
  16 #include <bitfield.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <dm/lists.h>
  22 #include <dt-bindings/clock/rk3399-cru.h>
  23 #include <linux/bitops.h>
  24 #include <linux/delay.h>
  25
  26 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  27 struct rk3399_clk_plat {
  28         struct dtd_rockchip_rk3399_cru dtd;
  29 };
  30
  31 struct rk3399_pmuclk_plat {
  32         struct dtd_rockchip_rk3399_pmucru dtd;
  33 };
  34 #endif
  35
  36 struct pll_div {
  37         u32 refdiv;
  38         u32 fbdiv;
  39         u32 postdiv1;
  40         u32 postdiv2;
  41         u32 frac;
  42 };
  43
  44 #define RATE_TO_DIV(input_rate, output_rate) \
  45         ((input_rate) / (output_rate) - 1)
  46 #define DIV_TO_RATE(input_rate, div)            ((input_rate) / ((div) + 1))
  47
  48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  49         .refdiv = _refdiv,\
  50         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  51         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  52
  53 #if defined(CONFIG_SPL_BUILD)
  54 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  55 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  56 #else
  57 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  58 #endif
  59
  60 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
  61 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  62
  63 static const struct pll_div *apll_l_cfgs[] = {
  64         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  65         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  66 };
  67
  68 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  69 static const struct pll_div *apll_b_cfgs[] = {
  70         [APLL_B_600_MHZ] = &apll_b_600_cfg,
  71 };
  72
  73 enum {
  74         /* PLL_CON0 */
  75         PLL_FBDIV_MASK                  = 0xfff,
  76         PLL_FBDIV_SHIFT                 = 0,
  77
  78         /* PLL_CON1 */
  79         PLL_POSTDIV2_SHIFT              = 12,
  80         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  81         PLL_POSTDIV1_SHIFT              = 8,
  82         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  83         PLL_REFDIV_MASK                 = 0x3f,
  84         PLL_REFDIV_SHIFT                = 0,
  85
  86         /* PLL_CON2 */
  87         PLL_LOCK_STATUS_SHIFT           = 31,
  88         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  89         PLL_FRACDIV_MASK                = 0xffffff,
  90         PLL_FRACDIV_SHIFT               = 0,
  91
  92         /* PLL_CON3 */
  93         PLL_MODE_SHIFT                  = 8,
  94         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  95         PLL_MODE_SLOW                   = 0,
  96         PLL_MODE_NORM,
  97         PLL_MODE_DEEP,
  98         PLL_DSMPD_SHIFT                 = 3,
  99         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
 100         PLL_INTEGER_MODE                = 1,
 101
 102         /* PMUCRU_CLKSEL_CON0 */
 103         PMU_PCLK_DIV_CON_MASK           = 0x1f,
 104         PMU_PCLK_DIV_CON_SHIFT          = 0,
 105
 106         /* PMUCRU_CLKSEL_CON1 */
 107         SPI3_PLL_SEL_SHIFT              = 7,
 108         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 109         SPI3_PLL_SEL_24M                = 0,
 110         SPI3_PLL_SEL_PPLL               = 1,
 111         SPI3_DIV_CON_SHIFT              = 0x0,
 112         SPI3_DIV_CON_MASK               = 0x7f,
 113
 114         /* PMUCRU_CLKSEL_CON2 */
 115         I2C_DIV_CON_MASK                = 0x7f,
 116         CLK_I2C8_DIV_CON_SHIFT          = 8,
 117         CLK_I2C0_DIV_CON_SHIFT          = 0,
 118
 119         /* PMUCRU_CLKSEL_CON3 */
 120         CLK_I2C4_DIV_CON_SHIFT          = 0,
 121
 122         /* CLKSEL_CON0 */
 123         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 124         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 125         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 126         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 127         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 128         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 129         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 130         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 131         CLK_CORE_L_DIV_MASK             = 0x1f,
 132         CLK_CORE_L_DIV_SHIFT            = 0,
 133
 134         /* CLKSEL_CON1 */
 135         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 136         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 137         ATCLK_CORE_L_DIV_SHIFT          = 0,
 138         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 139
 140         /* CLKSEL_CON2 */
 141         ACLKM_CORE_B_DIV_CON_SHIFT      = 8,
 142         ACLKM_CORE_B_DIV_CON_MASK       = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
 143         CLK_CORE_B_PLL_SEL_SHIFT        = 6,
 144         CLK_CORE_B_PLL_SEL_MASK         = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
 145         CLK_CORE_B_PLL_SEL_ALPLL        = 0x0,
 146         CLK_CORE_B_PLL_SEL_ABPLL        = 0x1,
 147         CLK_CORE_B_PLL_SEL_DPLL         = 0x10,
 148         CLK_CORE_B_PLL_SEL_GPLL         = 0x11,
 149         CLK_CORE_B_DIV_MASK             = 0x1f,
 150         CLK_CORE_B_DIV_SHIFT            = 0,
 151
 152         /* CLKSEL_CON3 */
 153         PCLK_DBG_B_DIV_SHIFT            = 0x8,
 154         PCLK_DBG_B_DIV_MASK             = 0x1f << PCLK_DBG_B_DIV_SHIFT,
 155         ATCLK_CORE_B_DIV_SHIFT          = 0,
 156         ATCLK_CORE_B_DIV_MASK           = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
 157
 158         /* CLKSEL_CON14 */
 159         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 160         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 161         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 162         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 163         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 164         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 165         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 166         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 167         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 168         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 169
 170         /* CLKSEL_CON21 */
 171         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 172         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 173         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 174         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 175         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 176
 177         /* CLKSEL_CON22 */
 178         CLK_EMMC_PLL_SHIFT              = 8,
 179         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 180         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 181         CLK_EMMC_PLL_SEL_24M            = 0x5,
 182         CLK_EMMC_DIV_CON_SHIFT          = 0,
 183         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 184
 185         /* CLKSEL_CON23 */
 186         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 187         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 188         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 189         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 190         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 191         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 192         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 193         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 194         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 195         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 196
 197         /* CLKSEL_CON25 */
 198         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 199         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 200         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 201         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 202         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 203         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 204         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 205         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 206
 207         /* CLKSEL_CON26 */
 208         CLK_SARADC_DIV_CON_SHIFT        = 8,
 209         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 210         CLK_SARADC_DIV_CON_WIDTH        = 8,
 211
 212         /* CLKSEL_CON27 */
 213         CLK_TSADC_SEL_X24M              = 0x0,
 214         CLK_TSADC_SEL_SHIFT             = 15,
 215         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 216         CLK_TSADC_DIV_CON_SHIFT         = 0,
 217         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 218
 219         /* CLKSEL_CON47 & CLKSEL_CON48 */
 220         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 221         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 222         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 223         ACLK_VOP_DIV_CON_SHIFT          = 0,
 224         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 225
 226         /* CLKSEL_CON49 & CLKSEL_CON50 */
 227         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 228         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 229         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 230         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 231         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 232         DCLK_VOP_PLL_SEL_VPLL           = 0,
 233         DCLK_VOP_DIV_CON_MASK           = 0xff,
 234         DCLK_VOP_DIV_CON_SHIFT          = 0,
 235
 236         /* CLKSEL_CON57 */
 237         PCLK_ALIVE_DIV_CON_SHIFT        = 0,
 238         PCLK_ALIVE_DIV_CON_MASK         = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
 239
 240         /* CLKSEL_CON58 */
 241         CLK_SPI_PLL_SEL_WIDTH = 1,
 242         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 243         CLK_SPI_PLL_SEL_CPLL = 0,
 244         CLK_SPI_PLL_SEL_GPLL = 1,
 245         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 246         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 247
 248         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 249         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 250
 251         /* CLKSEL_CON59 */
 252         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 253         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 254         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 255         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 256
 257         /* CLKSEL_CON60 */
 258         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 259         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 260         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 261         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 262
 263         /* CLKSEL_CON61 */
 264         CLK_I2C_PLL_SEL_MASK            = 1,
 265         CLK_I2C_PLL_SEL_CPLL            = 0,
 266         CLK_I2C_PLL_SEL_GPLL            = 1,
 267         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 268         CLK_I2C5_DIV_CON_SHIFT          = 8,
 269         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 270         CLK_I2C1_DIV_CON_SHIFT          = 0,
 271
 272         /* CLKSEL_CON62 */
 273         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 274         CLK_I2C6_DIV_CON_SHIFT          = 8,
 275         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 276         CLK_I2C2_DIV_CON_SHIFT          = 0,
 277
 278         /* CLKSEL_CON63 */
 279         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 280         CLK_I2C7_DIV_CON_SHIFT          = 8,
 281         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 282         CLK_I2C3_DIV_CON_SHIFT          = 0,
 283
 284         /* CRU_SOFTRST_CON4 */
 285         RESETN_DDR0_REQ_SHIFT           = 8,
 286         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 287         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 288         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 289         RESETN_DDR1_REQ_SHIFT           = 12,
 290         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 291         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 292         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 293 };
 294
 295 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 296 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 297 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 298 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 299
 300 /*
 301  *  the div restructions of pll in integer mode, these are defined in
 302  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 303  */
 304 #define PLL_DIV_MIN     16
 305 #define PLL_DIV_MAX     3200
 306
 307 /*
 308  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 309  * Formulas also embedded within the Fractional PLL Verilog model:
 310  * If DSMPD = 1 (DSM is disabled, "integer mode")
 311  * FOUTVCO = FREF / REFDIV * FBDIV
 312  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 313  * Where:
 314  * FOUTVCO = Fractional PLL non-divided output frequency
 315  * FOUTPOSTDIV = Fractional PLL divided output frequency
 316  *               (output of second post divider)
 317  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 318  * REFDIV = Fractional PLL input reference clock divider
 319  * FBDIV = Integer value programmed into feedback divide
 320  *
 321  */
 322 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 323 {
 324         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 325         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 326         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 327
 328         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 329                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 330                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 331                            div->postdiv2, vco_khz, output_khz);
 332         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 333                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 334                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 335
 336         /*
 337          * When power on or changing PLL setting,
 338          * we must force PLL into slow mode to ensure output stable clock.
 339          */
 340         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 341                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 342
 343         /* use integer mode */
 344         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 345                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 346
 347         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 348                      div->fbdiv << PLL_FBDIV_SHIFT);
 349         rk_clrsetreg(&pll_con[1],
 350                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 351                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 352                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 353                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 354                      (div->refdiv << PLL_REFDIV_SHIFT));
 355
 356         /* waiting for pll lock */
 357         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 358                 udelay(1);
 359
 360         /* pll enter normal mode */
 361         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 362                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 363 }
 364
 365 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 366 {
 367         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 368         u32 postdiv1, postdiv2 = 1;
 369         u32 fref_khz;
 370         u32 diff_khz, best_diff_khz;
 371         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 372         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 373         u32 vco_khz;
 374         u32 freq_khz = freq_hz / KHz;
 375
 376         if (!freq_hz) {
 377                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 378                 return -1;
 379         }
 380
 381         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 382         if (postdiv1 > max_postdiv1) {
 383                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 384                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 385         }
 386
 387         vco_khz = freq_khz * postdiv1 * postdiv2;
 388
 389         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 390             postdiv2 > max_postdiv2) {
 391                 printf("%s: Cannot find out a supported VCO"
 392                        " for Frequency (%uHz).\n", __func__, freq_hz);
 393                 return -1;
 394         }
 395
 396         div->postdiv1 = postdiv1;
 397         div->postdiv2 = postdiv2;
 398
 399         best_diff_khz = vco_khz;
 400         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 401                 fref_khz = ref_khz / refdiv;
 402
 403                 fbdiv = vco_khz / fref_khz;
 404                 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
 405                         continue;
 406                 diff_khz = vco_khz - fbdiv * fref_khz;
 407                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 408                         fbdiv++;
 409                         diff_khz = fref_khz - diff_khz;
 410                 }
 411
 412                 if (diff_khz >= best_diff_khz)
 413                         continue;
 414
 415                 best_diff_khz = diff_khz;
 416                 div->refdiv = refdiv;
 417                 div->fbdiv = fbdiv;
 418         }
 419
 420         if (best_diff_khz > 4 * (MHz / KHz)) {
 421                 printf("%s: Failed to match output frequency %u, "
 422                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 423                        best_diff_khz * KHz);
 424                 return -1;
 425         }
 426         return 0;
 427 }
 428
 429 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
 430                             enum apll_l_frequencies apll_l_freq)
 431 {
 432         u32 aclkm_div;
 433         u32 pclk_dbg_div;
 434         u32 atclk_div;
 435
 436         /* Setup cluster L */
 437         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 438
 439         aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
 440         assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
 441                aclkm_div < 0x1f);
 442
 443         pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
 444         assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
 445                pclk_dbg_div < 0x1f);
 446
 447         atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
 448         assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
 449                atclk_div < 0x1f);
 450
 451         rk_clrsetreg(&cru->clksel_con[0],
 452                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 453                      CLK_CORE_L_DIV_MASK,
 454                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 455                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 456                      0 << CLK_CORE_L_DIV_SHIFT);
 457
 458         rk_clrsetreg(&cru->clksel_con[1],
 459                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 460                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 461                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 462 }
 463
 464 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
 465                             enum apll_b_frequencies apll_b_freq)
 466 {
 467         u32 aclkm_div;
 468         u32 pclk_dbg_div;
 469         u32 atclk_div;
 470
 471         /* Setup cluster B */
 472         rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
 473
 474         aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
 475         assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
 476                aclkm_div < 0x1f);
 477
 478         pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
 479         assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
 480                pclk_dbg_div < 0x1f);
 481
 482         atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
 483         assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
 484                atclk_div < 0x1f);
 485
 486         rk_clrsetreg(&cru->clksel_con[2],
 487                      ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
 488                      CLK_CORE_B_DIV_MASK,
 489                      aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
 490                      CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
 491                      0 << CLK_CORE_B_DIV_SHIFT);
 492
 493         rk_clrsetreg(&cru->clksel_con[3],
 494                      PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
 495                      pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
 496                      atclk_div << ATCLK_CORE_B_DIV_SHIFT);
 497 }
 498
 499 #define I2C_CLK_REG_MASK(bus) \
 500         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 501          CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 502
 503 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 504         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 505          CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 506
 507 #define I2C_CLK_DIV_VALUE(con, bus) \
 508         ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
 509
 510 #define I2C_PMUCLK_REG_MASK(bus) \
 511         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
 512
 513 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 514         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 515
 516 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 517 {
 518         u32 div, con;
 519
 520         switch (clk_id) {
 521         case SCLK_I2C1:
 522                 con = readl(&cru->clksel_con[61]);
 523                 div = I2C_CLK_DIV_VALUE(con, 1);
 524                 break;
 525         case SCLK_I2C2:
 526                 con = readl(&cru->clksel_con[62]);
 527                 div = I2C_CLK_DIV_VALUE(con, 2);
 528                 break;
 529         case SCLK_I2C3:
 530                 con = readl(&cru->clksel_con[63]);
 531                 div = I2C_CLK_DIV_VALUE(con, 3);
 532                 break;
 533         case SCLK_I2C5:
 534                 con = readl(&cru->clksel_con[61]);
 535                 div = I2C_CLK_DIV_VALUE(con, 5);
 536                 break;
 537         case SCLK_I2C6:
 538                 con = readl(&cru->clksel_con[62]);
 539                 div = I2C_CLK_DIV_VALUE(con, 6);
 540                 break;
 541         case SCLK_I2C7:
 542                 con = readl(&cru->clksel_con[63]);
 543                 div = I2C_CLK_DIV_VALUE(con, 7);
 544                 break;
 545         default:
 546                 printf("do not support this i2c bus\n");
 547                 return -EINVAL;
 548         }
 549
 550         return DIV_TO_RATE(GPLL_HZ, div);
 551 }
 552
 553 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 554 {
 555         int src_clk_div;
 556
 557         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 558         src_clk_div = GPLL_HZ / hz;
 559         assert(src_clk_div - 1 < 127);
 560
 561         switch (clk_id) {
 562         case SCLK_I2C1:
 563                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 564                              I2C_CLK_REG_VALUE(1, src_clk_div));
 565                 break;
 566         case SCLK_I2C2:
 567                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 568                              I2C_CLK_REG_VALUE(2, src_clk_div));
 569                 break;
 570         case SCLK_I2C3:
 571                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 572                              I2C_CLK_REG_VALUE(3, src_clk_div));
 573                 break;
 574         case SCLK_I2C5:
 575                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 576                              I2C_CLK_REG_VALUE(5, src_clk_div));
 577                 break;
 578         case SCLK_I2C6:
 579                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 580                              I2C_CLK_REG_VALUE(6, src_clk_div));
 581                 break;
 582         case SCLK_I2C7:
 583                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 584                              I2C_CLK_REG_VALUE(7, src_clk_div));
 585                 break;
 586         default:
 587                 printf("do not support this i2c bus\n");
 588                 return -EINVAL;
 589         }
 590
 591         return rk3399_i2c_get_clk(cru, clk_id);
 592 }
 593
 594 /*
 595  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 596  * to select either CPLL or GPLL as the clock-parent. The location within
 597  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 598  */
 599
 600 struct spi_clkreg {
 601         u8 reg;  /* CLKSEL_CON[reg] register in CRU */
 602         u8 div_shift;
 603         u8 sel_shift;
 604 };
 605
 606 /*
 607  * The entries are numbered relative to their offset from SCLK_SPI0.
 608  *
 609  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 610  * logic is not supported).
 611  */
 612 static const struct spi_clkreg spi_clkregs[] = {
 613         [0] = { .reg = 59,
 614                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 615                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 616         [1] = { .reg = 59,
 617                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 618                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 619         [2] = { .reg = 60,
 620                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 621                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 622         [3] = { .reg = 60,
 623                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 624                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 625         [4] = { .reg = 58,
 626                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 627                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 628 };
 629
 630 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 631 {
 632         const struct spi_clkreg *spiclk = NULL;
 633         u32 div, val;
 634
 635         switch (clk_id) {
 636         case SCLK_SPI0 ... SCLK_SPI5:
 637                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 638                 break;
 639
 640         default:
 641                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 642                 return -EINVAL;
 643         }
 644
 645         val = readl(&cru->clksel_con[spiclk->reg]);
 646         div = bitfield_extract(val, spiclk->div_shift,
 647                                CLK_SPI_PLL_DIV_CON_WIDTH);
 648
 649         return DIV_TO_RATE(GPLL_HZ, div);
 650 }
 651
 652 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 653 {
 654         const struct spi_clkreg *spiclk = NULL;
 655         int src_clk_div;
 656
 657         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 658         assert(src_clk_div < 128);
 659
 660         switch (clk_id) {
 661         case SCLK_SPI1 ... SCLK_SPI5:
 662                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 663                 break;
 664
 665         default:
 666                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 667                 return -EINVAL;
 668         }
 669
 670         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 671                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 672                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 673                      ((src_clk_div << spiclk->div_shift) |
 674                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 675
 676         return rk3399_spi_get_clk(cru, clk_id);
 677 }
 678
 679 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 680 {
 681         struct pll_div vpll_config = {0};
 682         int aclk_vop = 198 * MHz;
 683         void *aclkreg_addr, *dclkreg_addr;
 684         u32 div;
 685
 686         switch (clk_id) {
 687         case DCLK_VOP0:
 688                 aclkreg_addr = &cru->clksel_con[47];
 689                 dclkreg_addr = &cru->clksel_con[49];
 690                 break;
 691         case DCLK_VOP1:
 692                 aclkreg_addr = &cru->clksel_con[48];
 693                 dclkreg_addr = &cru->clksel_con[50];
 694                 break;
 695         default:
 696                 return -EINVAL;
 697         }
 698         /* vop aclk source clk: cpll */
 699         div = CPLL_HZ / aclk_vop;
 700         assert(div - 1 < 32);
 701
 702         rk_clrsetreg(aclkreg_addr,
 703                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 704                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 705                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 706
 707         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 708         if (pll_para_config(hz, &vpll_config))
 709                 return -1;
 710
 711         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 712
 713         rk_clrsetreg(dclkreg_addr,
 714                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 715                      DCLK_VOP_DIV_CON_MASK,
 716                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 717                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 718                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 719
 720         return hz;
 721 }
 722
 723 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 724 {
 725         u32 div, con;
 726
 727         switch (clk_id) {
 728         case HCLK_SDMMC:
 729         case SCLK_SDMMC:
 730                 con = readl(&cru->clksel_con[16]);
 731                 /* dwmmc controller have internal div 2 */
 732                 div = 2;
 733                 break;
 734         case SCLK_EMMC:
 735                 con = readl(&cru->clksel_con[22]);
 736                 div = 1;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 743         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 744                         == CLK_EMMC_PLL_SEL_24M)
 745                 return DIV_TO_RATE(OSC_HZ, div);
 746         else
 747                 return DIV_TO_RATE(GPLL_HZ, div);
 748 }
 749
 750 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
 751                                 ulong clk_id, ulong set_rate)
 752 {
 753         int src_clk_div;
 754         int aclk_emmc = 198 * MHz;
 755
 756         switch (clk_id) {
 757         case HCLK_SDMMC:
 758         case SCLK_SDMMC:
 759                 /* Select clk_sdmmc source from GPLL by default */
 760                 /* mmc clock defaulg div 2 internal, provide double in cru */
 761                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 762
 763                 if (src_clk_div > 128) {
 764                         /* use 24MHz source for 400KHz clock */
 765                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 766                         assert(src_clk_div - 1 < 128);
 767                         rk_clrsetreg(&cru->clksel_con[16],
 768                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 769                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 770                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 771                 } else {
 772                         rk_clrsetreg(&cru->clksel_con[16],
 773                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 774                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 775                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 776                 }
 777                 break;
 778         case SCLK_EMMC:
 779                 /* Select aclk_emmc source from GPLL */
 780                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
 781                 assert(src_clk_div - 1 < 32);
 782
 783                 rk_clrsetreg(&cru->clksel_con[21],
 784                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 785                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 786                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 787
 788                 /* Select clk_emmc source from GPLL too */
 789                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 790                 assert(src_clk_div - 1 < 128);
 791
 792                 rk_clrsetreg(&cru->clksel_con[22],
 793                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 794                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 795                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 796                 break;
 797         default:
 798                 return -EINVAL;
 799         }
 800         return rk3399_mmc_get_clk(cru, clk_id);
 801 }
 802
 803 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 804 {
 805         ulong ret;
 806
 807         /*
 808          * The RGMII CLK can be derived either from an external "clkin"
 809          * or can be generated from internally by a divider from SCLK_MAC.
 810          */
 811         if (readl(&cru->clksel_con[19]) & BIT(4)) {
 812                 /* An external clock will always generate the right rate... */
 813                 ret = rate;
 814         } else {
 815                 /*
 816                  * No platform uses an internal clock to date.
 817                  * Implement this once it becomes necessary and print an error
 818                  * if someone tries to use it (while it remains unimplemented).
 819                  */
 820                 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
 821                 ret = 0;
 822         }
 823
 824         return ret;
 825 }
 826
 827 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 828 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
 829                                 ulong set_rate)
 830 {
 831         struct pll_div dpll_cfg;
 832
 833         /*  IC ECO bug, need to set this register */
 834         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 835
 836         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 837         switch (set_rate) {
 838         case 50 * MHz:
 839                 dpll_cfg = (struct pll_div)
 840                 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
 841                 break;
 842         case 200 * MHz:
 843                 dpll_cfg = (struct pll_div)
 844                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 845                 break;
 846         case 300 * MHz:
 847                 dpll_cfg = (struct pll_div)
 848                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 849                 break;
 850         case 400 * MHz:
 851                 dpll_cfg = (struct pll_div)
 852                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 853                 break;
 854         case 666 * MHz:
 855                 dpll_cfg = (struct pll_div)
 856                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 857                 break;
 858         case 800 * MHz:
 859                 dpll_cfg = (struct pll_div)
 860                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 861                 break;
 862         case 933 * MHz:
 863                 dpll_cfg = (struct pll_div)
 864                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 865                 break;
 866         default:
 867                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 868         }
 869         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 870
 871         return set_rate;
 872 }
 873
 874 static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
 875 {
 876         u32 div, val;
 877
 878         val = readl(&cru->clksel_con[57]);
 879         div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
 880                PCLK_ALIVE_DIV_CON_SHIFT;
 881
 882         return DIV_TO_RATE(GPLL_HZ, div);
 883 }
 884
 885 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 886 {
 887         u32 div, val;
 888
 889         val = readl(&cru->clksel_con[26]);
 890         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 891                                CLK_SARADC_DIV_CON_WIDTH);
 892
 893         return DIV_TO_RATE(OSC_HZ, div);
 894 }
 895
 896 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 897 {
 898         int src_clk_div;
 899
 900         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 901         assert(src_clk_div < 128);
 902
 903         rk_clrsetreg(&cru->clksel_con[26],
 904                      CLK_SARADC_DIV_CON_MASK,
 905                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 906
 907         return rk3399_saradc_get_clk(cru);
 908 }
 909
 910 static ulong rk3399_clk_get_rate(struct clk *clk)
 911 {
 912         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 913         ulong rate = 0;
 914
 915         switch (clk->id) {
 916         case 0 ... 63:
 917                 return 0;
 918         case HCLK_SDMMC:
 919         case SCLK_SDMMC:
 920         case SCLK_EMMC:
 921                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 922                 break;
 923         case SCLK_I2C1:
 924         case SCLK_I2C2:
 925         case SCLK_I2C3:
 926         case SCLK_I2C5:
 927         case SCLK_I2C6:
 928         case SCLK_I2C7:
 929                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 930                 break;
 931         case SCLK_SPI0...SCLK_SPI5:
 932                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 933                 break;
 934         case SCLK_UART0:
 935         case SCLK_UART1:
 936         case SCLK_UART2:
 937         case SCLK_UART3:
 938                 return 24000000;
 939         case PCLK_HDMI_CTRL:
 940                 break;
 941         case DCLK_VOP0:
 942         case DCLK_VOP1:
 943                 break;
 944         case PCLK_EFUSE1024NS:
 945                 break;
 946         case SCLK_SARADC:
 947                 rate = rk3399_saradc_get_clk(priv->cru);
 948                 break;
 949         case ACLK_VIO:
 950         case ACLK_HDCP:
 951         case ACLK_GIC_PRE:
 952         case PCLK_DDR:
 953                 break;
 954         case PCLK_ALIVE:
 955         case PCLK_WDT:
 956                 rate = rk3399_alive_get_clk(priv->cru);
 957                 break;
 958         default:
 959                 log_debug("Unknown clock %lu\n", clk->id);
 960                 return -ENOENT;
 961         }
 962
 963         return rate;
 964 }
 965
 966 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 967 {
 968         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 969         ulong ret = 0;
 970
 971         switch (clk->id) {
 972         case 0 ... 63:
 973                 return 0;
 974
 975         case ACLK_PERIHP:
 976         case HCLK_PERIHP:
 977         case PCLK_PERIHP:
 978                 return 0;
 979
 980         case ACLK_PERILP0:
 981         case HCLK_PERILP0:
 982         case PCLK_PERILP0:
 983                 return 0;
 984
 985         case ACLK_CCI:
 986                 return 0;
 987
 988         case HCLK_PERILP1:
 989         case PCLK_PERILP1:
 990                 return 0;
 991
 992         case HCLK_SDMMC:
 993         case SCLK_SDMMC:
 994         case SCLK_EMMC:
 995                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 996                 break;
 997         case SCLK_MAC:
 998                 ret = rk3399_gmac_set_clk(priv->cru, rate);
 999                 break;
1000         case SCLK_I2C1:
1001         case SCLK_I2C2:
1002         case SCLK_I2C3:
1003         case SCLK_I2C5:
1004         case SCLK_I2C6:
1005         case SCLK_I2C7:
1006                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
1007                 break;
1008         case SCLK_SPI0...SCLK_SPI5:
1009                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
1010                 break;
1011         case PCLK_HDMI_CTRL:
1012         case PCLK_VIO_GRF:
1013                 /* the PCLK gates for video are enabled by default */
1014                 break;
1015         case DCLK_VOP0:
1016         case DCLK_VOP1:
1017                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
1018                 break;
1019         case ACLK_VOP1:
1020         case HCLK_VOP1:
1021         case HCLK_SD:
1022         case SCLK_UPHY0_TCPDCORE:
1023         case SCLK_UPHY1_TCPDCORE:
1024                 /**
1025                  * assigned-clocks handling won't require for vopl, so
1026                  * return 0 to satisfy clk_set_defaults during device probe.
1027                  */
1028                 return 0;
1029         case SCLK_DDRCLK:
1030                 ret = rk3399_ddr_set_clk(priv->cru, rate);
1031                 break;
1032         case PCLK_EFUSE1024NS:
1033                 break;
1034         case SCLK_SARADC:
1035                 ret = rk3399_saradc_set_clk(priv->cru, rate);
1036                 break;
1037         case ACLK_VIO:
1038         case ACLK_HDCP:
1039         case ACLK_GIC_PRE:
1040         case PCLK_DDR:
1041                 return 0;
1042         default:
1043                 log_debug("Unknown clock %lu\n", clk->id);
1044                 return -ENOENT;
1045         }
1046
1047         return ret;
1048 }
1049
1050 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1051                                                  struct clk *parent)
1052 {
1053         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1054         const char *clock_output_name;
1055         int ret;
1056
1057         /*
1058          * If the requested parent is in the same clock-controller and
1059          * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1060          */
1061         if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1062                 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1063                 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1064                 return 0;
1065         }
1066
1067         /*
1068          * Otherwise, we need to check the clock-output-names of the
1069          * requested parent to see if the requested id is "clkin_gmac".
1070          */
1071         ret = dev_read_string_index(parent->dev, "clock-output-names",
1072                                     parent->id, &clock_output_name);
1073         if (ret < 0)
1074                 return -ENODATA;
1075
1076         /* If this is "clkin_gmac", switch to the external clock input */
1077         if (!strcmp(clock_output_name, "clkin_gmac")) {
1078                 debug("%s: switching RGMII to CLKIN\n", __func__);
1079                 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1080                 return 0;
1081         }
1082
1083         return -EINVAL;
1084 }
1085
1086 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1087                                                 struct clk *parent)
1088 {
1089         switch (clk->id) {
1090         case SCLK_RMII_SRC:
1091                 return rk3399_gmac_set_parent(clk, parent);
1092         }
1093
1094         debug("%s: unsupported clk %ld\n", __func__, clk->id);
1095         return -ENOENT;
1096 }
1097
1098 static int rk3399_clk_enable(struct clk *clk)
1099 {
1100         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1101
1102         switch (clk->id) {
1103         case SCLK_MAC:
1104                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1105                 break;
1106         case SCLK_MAC_RX:
1107                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1108                 break;
1109         case SCLK_MAC_TX:
1110                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1111                 break;
1112         case SCLK_MACREF:
1113                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1114                 break;
1115         case SCLK_MACREF_OUT:
1116                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1117                 break;
1118         case SCLK_USB2PHY0_REF:
1119                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1120                 break;
1121         case SCLK_USB2PHY1_REF:
1122                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1123                 break;
1124         case ACLK_GMAC:
1125                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1126                 break;
1127         case PCLK_GMAC:
1128                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1129                 break;
1130         case SCLK_USB3OTG0_REF:
1131                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1132                 break;
1133         case SCLK_USB3OTG1_REF:
1134                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1135                 break;
1136         case SCLK_USB3OTG0_SUSPEND:
1137                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1138                 break;
1139         case SCLK_USB3OTG1_SUSPEND:
1140                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1141                 break;
1142         case ACLK_USB3OTG0:
1143                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1144                 break;
1145         case ACLK_USB3OTG1:
1146                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1147                 break;
1148         case ACLK_USB3_RKSOC_AXI_PERF:
1149                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1150                 break;
1151         case ACLK_USB3:
1152                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1153                 break;
1154         case ACLK_USB3_GRF:
1155                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1156                 break;
1157         case HCLK_HOST0:
1158                 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1159                 break;
1160         case HCLK_HOST0_ARB:
1161                 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1162                 break;
1163         case HCLK_HOST1:
1164                 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1165                 break;
1166         case HCLK_HOST1_ARB:
1167                 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1168                 break;
1169         case SCLK_UPHY0_TCPDPHY_REF:
1170                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1171                 break;
1172         case SCLK_UPHY0_TCPDCORE:
1173                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1174                 break;
1175         case SCLK_UPHY1_TCPDPHY_REF:
1176                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1177                 break;
1178         case SCLK_UPHY1_TCPDCORE:
1179                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1180                 break;
1181         case SCLK_PCIEPHY_REF:
1182                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1183                 break;
1184         default:
1185                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1186                 return -ENOENT;
1187         }
1188
1189         return 0;
1190 }
1191
1192 static int rk3399_clk_disable(struct clk *clk)
1193 {
1194         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1195
1196         switch (clk->id) {
1197         case SCLK_MAC:
1198                 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1199                 break;
1200         case SCLK_MAC_RX:
1201                 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1202                 break;
1203         case SCLK_MAC_TX:
1204                 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1205                 break;
1206         case SCLK_MACREF:
1207                 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1208                 break;
1209         case SCLK_MACREF_OUT:
1210                 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1211                 break;
1212         case SCLK_USB2PHY0_REF:
1213                 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1214                 break;
1215         case SCLK_USB2PHY1_REF:
1216                 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1217                 break;
1218         case ACLK_GMAC:
1219                 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1220                 break;
1221         case PCLK_GMAC:
1222                 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1223                 break;
1224         case SCLK_USB3OTG0_REF:
1225                 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1226                 break;
1227         case SCLK_USB3OTG1_REF:
1228                 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1229                 break;
1230         case SCLK_USB3OTG0_SUSPEND:
1231                 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1232                 break;
1233         case SCLK_USB3OTG1_SUSPEND:
1234                 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1235                 break;
1236         case ACLK_USB3OTG0:
1237                 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1238                 break;
1239         case ACLK_USB3OTG1:
1240                 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1241                 break;
1242         case ACLK_USB3_RKSOC_AXI_PERF:
1243                 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1244                 break;
1245         case ACLK_USB3:
1246                 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1247                 break;
1248         case ACLK_USB3_GRF:
1249                 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1250                 break;
1251         case HCLK_HOST0:
1252                 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1253                 break;
1254         case HCLK_HOST0_ARB:
1255                 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1256                 break;
1257         case HCLK_HOST1:
1258                 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1259                 break;
1260         case HCLK_HOST1_ARB:
1261                 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1262                 break;
1263         case SCLK_UPHY0_TCPDPHY_REF:
1264                 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1265                 break;
1266         case SCLK_UPHY0_TCPDCORE:
1267                 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1268                 break;
1269         case SCLK_UPHY1_TCPDPHY_REF:
1270                 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1271                 break;
1272         case SCLK_UPHY1_TCPDCORE:
1273                 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1274                 break;
1275         case SCLK_PCIEPHY_REF:
1276                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1277                 break;
1278         default:
1279                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1280                 return -ENOENT;
1281         }
1282
1283         return 0;
1284 }
1285
1286 static struct clk_ops rk3399_clk_ops = {
1287         .get_rate = rk3399_clk_get_rate,
1288         .set_rate = rk3399_clk_set_rate,
1289 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1290         .set_parent = rk3399_clk_set_parent,
1291 #endif
1292         .enable = rk3399_clk_enable,
1293         .disable = rk3399_clk_disable,
1294 };
1295
1296 #ifdef CONFIG_SPL_BUILD
1297 static void rkclk_init(struct rockchip_cru *cru)
1298 {
1299         u32 aclk_div;
1300         u32 hclk_div;
1301         u32 pclk_div;
1302
1303         rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1304         rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1305         /*
1306          * some cru registers changed by bootrom, we'd better reset them to
1307          * reset/default values described in TRM to avoid confusion in kernel.
1308          * Please consider these three lines as a fix of bootrom bug.
1309          */
1310         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1311         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1312         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1313
1314         /* configure gpll cpll */
1315         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1316         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1317
1318         /* configure perihp aclk, hclk, pclk */
1319         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1320         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1321
1322         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1323         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1324                PERIHP_ACLK_HZ && (hclk_div < 0x4));
1325
1326         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1327         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1328                PERIHP_ACLK_HZ && (pclk_div < 0x7));
1329
1330         rk_clrsetreg(&cru->clksel_con[14],
1331                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1332                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1333                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1334                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1335                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1336                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1337
1338         /* configure perilp0 aclk, hclk, pclk */
1339         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1340         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1341
1342         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1343         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1344                PERILP0_ACLK_HZ && (hclk_div < 0x4));
1345
1346         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1347         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1348                PERILP0_ACLK_HZ && (pclk_div < 0x7));
1349
1350         rk_clrsetreg(&cru->clksel_con[23],
1351                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1352                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1353                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1354                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1355                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1356                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1357
1358         /* perilp1 hclk select gpll as source */
1359         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1360         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1361                GPLL_HZ && (hclk_div < 0x1f));
1362
1363         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1364         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1365                PERILP1_HCLK_HZ && (hclk_div < 0x7));
1366
1367         rk_clrsetreg(&cru->clksel_con[25],
1368                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1369                      HCLK_PERILP1_PLL_SEL_MASK,
1370                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1371                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1372                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1373 }
1374 #endif
1375
1376 static int rk3399_clk_probe(struct udevice *dev)
1377 {
1378 #ifdef CONFIG_SPL_BUILD
1379         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1380
1381 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1382         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1383
1384         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1385 #endif
1386         rkclk_init(priv->cru);
1387 #endif
1388         return 0;
1389 }
1390
1391 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1392 {
1393 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1394         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1395
1396         priv->cru = dev_read_addr_ptr(dev);
1397 #endif
1398         return 0;
1399 }
1400
1401 static int rk3399_clk_bind(struct udevice *dev)
1402 {
1403         int ret;
1404         struct udevice *sys_child;
1405         struct sysreset_reg *priv;
1406
1407         /* The reset driver does not have a device node, so bind it here */
1408         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1409                                  &sys_child);
1410         if (ret) {
1411                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1412         } else {
1413                 priv = malloc(sizeof(struct sysreset_reg));
1414                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1415                                                     glb_srst_fst_value);
1416                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1417                                                     glb_srst_snd_value);
1418                 sys_child->priv = priv;
1419         }
1420
1421 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1422         ret = offsetof(struct rockchip_cru, softrst_con[0]);
1423         ret = rockchip_reset_bind(dev, ret, 21);
1424         if (ret)
1425                 debug("Warning: software reset driver bind faile\n");
1426 #endif
1427
1428         return 0;
1429 }
1430
1431 static const struct udevice_id rk3399_clk_ids[] = {
1432         { .compatible = "rockchip,rk3399-cru" },
1433         { }
1434 };
1435
1436 U_BOOT_DRIVER(clk_rk3399) = {
1437         .name           = "rockchip_rk3399_cru",
1438         .id             = UCLASS_CLK,
1439         .of_match       = rk3399_clk_ids,
1440         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1441         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1442         .ops            = &rk3399_clk_ops,
1443         .bind           = rk3399_clk_bind,
1444         .probe          = rk3399_clk_probe,
1445 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1446         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1447 #endif
1448 };
1449
1450 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1451 {
1452         u32 div, con;
1453
1454         switch (clk_id) {
1455         case SCLK_I2C0_PMU:
1456                 con = readl(&pmucru->pmucru_clksel[2]);
1457                 div = I2C_CLK_DIV_VALUE(con, 0);
1458                 break;
1459         case SCLK_I2C4_PMU:
1460                 con = readl(&pmucru->pmucru_clksel[3]);
1461                 div = I2C_CLK_DIV_VALUE(con, 4);
1462                 break;
1463         case SCLK_I2C8_PMU:
1464                 con = readl(&pmucru->pmucru_clksel[2]);
1465                 div = I2C_CLK_DIV_VALUE(con, 8);
1466                 break;
1467         default:
1468                 printf("do not support this i2c bus\n");
1469                 return -EINVAL;
1470         }
1471
1472         return DIV_TO_RATE(PPLL_HZ, div);
1473 }
1474
1475 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1476                                    uint hz)
1477 {
1478         int src_clk_div;
1479
1480         src_clk_div = PPLL_HZ / hz;
1481         assert(src_clk_div - 1 < 127);
1482
1483         switch (clk_id) {
1484         case SCLK_I2C0_PMU:
1485                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1486                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1487                 break;
1488         case SCLK_I2C4_PMU:
1489                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1490                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1491                 break;
1492         case SCLK_I2C8_PMU:
1493                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1494                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1495                 break;
1496         default:
1497                 printf("do not support this i2c bus\n");
1498                 return -EINVAL;
1499         }
1500
1501         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1502 }
1503
1504 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1505 {
1506         u32 div, con;
1507
1508         /* PWM closk rate is same as pclk_pmu */
1509         con = readl(&pmucru->pmucru_clksel[0]);
1510         div = con & PMU_PCLK_DIV_CON_MASK;
1511
1512         return DIV_TO_RATE(PPLL_HZ, div);
1513 }
1514
1515 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1516 {
1517         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1518         ulong rate = 0;
1519
1520         switch (clk->id) {
1521         case PLL_PPLL:
1522                 return PPLL_HZ;
1523         case PCLK_RKPWM_PMU:
1524         case PCLK_WDT_M0_PMU:
1525                 rate = rk3399_pwm_get_clk(priv->pmucru);
1526                 break;
1527         case SCLK_I2C0_PMU:
1528         case SCLK_I2C4_PMU:
1529         case SCLK_I2C8_PMU:
1530                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1531                 break;
1532         default:
1533                 return -ENOENT;
1534         }
1535
1536         return rate;
1537 }
1538
1539 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1540 {
1541         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1542         ulong ret = 0;
1543
1544         switch (clk->id) {
1545         case PLL_PPLL:
1546                 /*
1547                  * This has already been set up and we don't want/need
1548                  * to change it here.  Accept the request though, as the
1549                  * device-tree has this in an 'assigned-clocks' list.
1550                  */
1551                 return PPLL_HZ;
1552         case SCLK_I2C0_PMU:
1553         case SCLK_I2C4_PMU:
1554         case SCLK_I2C8_PMU:
1555                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1556                 break;
1557         default:
1558                 return -ENOENT;
1559         }
1560
1561         return ret;
1562 }
1563
1564 static struct clk_ops rk3399_pmuclk_ops = {
1565         .get_rate = rk3399_pmuclk_get_rate,
1566         .set_rate = rk3399_pmuclk_set_rate,
1567 };
1568
1569 #ifndef CONFIG_SPL_BUILD
1570 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1571 {
1572         u32 pclk_div;
1573
1574         /*  configure pmu pll(ppll) */
1575         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1576
1577         /*  configure pmu pclk */
1578         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1579         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1580                      PMU_PCLK_DIV_CON_MASK,
1581                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1582 }
1583 #endif
1584
1585 static int rk3399_pmuclk_probe(struct udevice *dev)
1586 {
1587 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1588         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1589 #endif
1590
1591 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1592         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1593
1594         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1595 #endif
1596
1597 #ifndef CONFIG_SPL_BUILD
1598         pmuclk_init(priv->pmucru);
1599 #endif
1600         return 0;
1601 }
1602
1603 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1604 {
1605 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1606         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1607
1608         priv->pmucru = dev_read_addr_ptr(dev);
1609 #endif
1610         return 0;
1611 }
1612
1613 static int rk3399_pmuclk_bind(struct udevice *dev)
1614 {
1615 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1616         int ret;
1617
1618         ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1619         ret = rockchip_reset_bind(dev, ret, 2);
1620         if (ret)
1621                 debug("Warning: software reset driver bind faile\n");
1622 #endif
1623         return 0;
1624 }
1625
1626 static const struct udevice_id rk3399_pmuclk_ids[] = {
1627         { .compatible = "rockchip,rk3399-pmucru" },
1628         { }
1629 };
1630
1631 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1632         .name           = "rockchip_rk3399_pmucru",
1633         .id             = UCLASS_CLK,
1634         .of_match       = rk3399_pmuclk_ids,
1635         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1636         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1637         .ops            = &rk3399_pmuclk_ops,
1638         .probe          = rk3399_pmuclk_probe,
1639         .bind           = rk3399_pmuclk_bind,
1640 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1641         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1642 #endif
1643 };