board/icecube/icecube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc5xxx.h>
  26 #include <pci.h>
  27
  28 #ifndef CFG_RAMBOOT
  29 static void sdram_start (int hi_addr)
  30 {
  31         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  32
  33 #ifdef CONFIG_MPC5200_DDR
  34         /* unlock mode register */
  35         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
  36         /* precharge all banks */
  37         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
  38         /* set mode register: extended mode */
  39         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
  40         /* set mode register: reset DLL */
  41         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
  42         /* precharge all banks */
  43         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
  44         /* auto refresh */
  45         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
  46         /* set mode register */
  47         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
  48         /* normal operation */
  49         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
  50 #else
  51         /* unlock mode register */
  52         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
  53         /* precharge all banks */
  54         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
  55         /* set mode register */
  56 #if defined(CONFIG_MPC5200)
  57         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
  58 #elif defined(CONFIG_MGT5100)
  59         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
  60 #endif
  61         /* auto refresh */
  62         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
  63         /* auto refresh */
  64         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
  65         /* set mode register */
  66         *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
  67         /* normal operation */
  68         *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
  69 #endif
  70 }
  71 #endif
  72
  73 long int initdram (int board_type)
  74 {
  75         ulong dramsize = 0;
  76 #ifdef CONFIG_MPC5200_DDR
  77         ulong dramsize2 = 0;
  78 #endif
  79 #ifndef CFG_RAMBOOT
  80         ulong test1, test2;
  81
  82         /* configure SDRAM start/end */
  83 #if defined(CONFIG_MPC5200)
  84         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  85         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  86
  87 #ifdef CONFIG_MPC5200_DDR
  88         /* setup config registers */
  89         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
  90         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
  91
  92         /* set tap delay to 0x10 */
  93         *(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
  94 #else
  95         /* setup config registers */
  96         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800;
  97         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000;
  98 #endif
  99
 100 #elif defined(CONFIG_MGT5100)
 101         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 102         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 103         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 104
 105         /* setup config registers */
 106         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
 107         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
 108
 109         /* address select register */
 110         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
 111 #endif
 112         sdram_start(0);
 113         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 114         sdram_start(1);
 115         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 116         if (test1 > test2) {
 117                 sdram_start(0);
 118                 dramsize = test1;
 119         } else {
 120                 dramsize = test2;
 121         }
 122 #if defined(CONFIG_MPC5200)
 123         *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
 124                 (0x13 + __builtin_ffs(dramsize >> 20) - 1);
 125 #ifdef CONFIG_MPC5200_DDR
 126         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 127         sdram_start(0);
 128         test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 129         sdram_start(1);
 130         test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 131         if (test1 > test2) {
 132                 sdram_start(0);
 133                 dramsize2 = test1;
 134         } else {
 135                 dramsize2 = test2;
 136         }
 137         *(vu_long *)MPC5XXX_SDRAM_CS1CFG =
 138                 dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 139 #else
 140         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 141 #endif
 142 #elif defined(CONFIG_MGT5100)
 143         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 144 #endif
 145
 146 #else   /* CFG_RAMBOOT */
 147 #ifdef CONFIG_MGT5100
 148         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 149         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 150 #else
 151         dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 152 #ifdef CONFIG_MPC5200_DDR
 153         dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
 154 #endif
 155 #endif
 156 #endif /* CFG_RAMBOOT */
 157
 158 #ifdef CONFIG_MPC5200_DDR
 159         dramsize += dramsize2;
 160 #endif
 161         /* return total ram size */
 162         return dramsize;
 163 }
 164
 165 int checkboard (void)
 166 {
 167 #if defined(CONFIG_MPC5200)
 168         puts ("Board: Motorola MPC5200 (IceCube)\n");
 169 #elif defined(CONFIG_MGT5100)
 170         puts ("Board: Motorola MGT5100 (IceCube)\n");
 171 #endif
 172         return 0;
 173 }
 174
 175 void flash_preinit(void)
 176 {
 177         /*
 178          * Now, when we are in RAM, enable flash write
 179          * access for detection process.
 180          * Note that CS_BOOT cannot be cleared when
 181          * executing in flash.
 182          */
 183 #if defined(CONFIG_MGT5100)
 184         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 185         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 186 #endif
 187         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 188 }
 189
 190 void flash_afterinit(ulong size)
 191 {
 192         if (size == 0x800000) { /* adjust mapping */
 193                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 194                         START_REG(CFG_BOOTCS_START | size);
 195                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 196                         STOP_REG(CFG_BOOTCS_START | size, size);
 197         }
 198 }
 199
 200 #ifdef  CONFIG_PCI
 201 static struct pci_controller hose;
 202
 203 extern void pci_mpc5xxx_init(struct pci_controller *);
 204
 205 void pci_init_board(void)
 206 {
 207         pci_mpc5xxx_init(&hose);
 208 }
 209 #endif