board/atmel/at91sam9261ek/at91sam9261ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9261.h>
  27 #include <asm/arch/at91sam9261_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_pmc.h>
  30 #include <asm/arch/at91_rstc.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/io.h>
  33 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  34 #include <net.h>
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /* ------------------------------------------------------------------------- */
  40 /*
  41  * Miscelaneous platform dependent initialisations
  42  */
  43
  44 static void at91sam9261ek_serial_hw_init(void)
  45 {
  46 #ifdef CONFIG_USART0
  47         at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
  48         at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
  49         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  50 #endif
  51
  52 #ifdef CONFIG_USART1
  53         at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
  54         at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
  55         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  56 #endif
  57
  58 #ifdef CONFIG_USART2
  59         at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
  60         at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
  61         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  62 #endif
  63
  64 #ifdef CONFIG_USART3    /* DBGU */
  65         at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
  66         at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
  67         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  68 #endif
  69 }
  70
  71 #ifdef CONFIG_CMD_NAND
  72 static void at91sam9261ek_nand_hw_init(void)
  73 {
  74         unsigned long csa;
  75
  76         /* Enable CS3 */
  77         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  78         at91_sys_write(AT91_MATRIX_EBICSA,
  79                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  80
  81         /* Configure SMC CS3 for NAND/SmartMedia */
  82         at91_sys_write(AT91_SMC_SETUP(3),
  83                        AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  84                        AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  85         at91_sys_write(AT91_SMC_PULSE(3),
  86                        AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
  87                        AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
  88         at91_sys_write(AT91_SMC_CYCLE(3),
  89                        AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
  90         at91_sys_write(AT91_SMC_MODE(3),
  91                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  92                        AT91_SMC_EXNWMODE_DISABLE |
  93 #ifdef CFG_NAND_DBW_16
  94                        AT91_SMC_DBW_16 |
  95 #else /* CFG_NAND_DBW_8 */
  96                        AT91_SMC_DBW_8 |
  97 #endif
  98                        AT91_SMC_TDF_(1));
  99
 100         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
 101
 102         /* Configure RDY/BSY */
 103         at91_set_gpio_input(AT91_PIN_PC15, 1);
 104
 105         /* Enable NandFlash */
 106         at91_set_gpio_output(AT91_PIN_PC14, 1);
 107
 108         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
 109         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
 110 }
 111 #endif
 112
 113 #ifdef CONFIG_HAS_DATAFLASH
 114 static void at91sam9261ek_spi_hw_init(void)
 115 {
 116         at91_set_A_periph(AT91_PIN_PA3, 0);     /* SPI0_NPCS0 */
 117
 118         at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 119         at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 120         at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 121
 122         /* Enable clock */
 123         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
 124 }
 125 #endif
 126
 127 #ifdef CONFIG_DRIVER_DM9000
 128 static void at91sam9261ek_dm9000_hw_init(void)
 129 {
 130         /* Configure SMC CS2 for DM9000 */
 131         at91_sys_write(AT91_SMC_SETUP(2),
 132                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
 133                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
 134         at91_sys_write(AT91_SMC_PULSE(2),
 135                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
 136                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
 137         at91_sys_write(AT91_SMC_CYCLE(2),
 138                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
 139         at91_sys_write(AT91_SMC_MODE(2),
 140                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 141                        AT91_SMC_EXNWMODE_DISABLE |
 142                        AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
 143                        AT91_SMC_TDF_(1));
 144
 145         /* Configure Reset signal as output */
 146         at91_set_gpio_output(AT91_PIN_PC10, 0);
 147
 148         /* Configure Interrupt pin as input, no pull-up */
 149         at91_set_gpio_input(AT91_PIN_PC11, 0);
 150 }
 151 #endif
 152
 153 int board_init(void)
 154 {
 155         /* Enable Ctrlc */
 156         console_init_f();
 157
 158         /* arch number of AT91SAM9261EK-Board */
 159         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 160         /* adress of boot parameters */
 161         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 162
 163         at91sam9261ek_serial_hw_init();
 164 #ifdef CONFIG_CMD_NAND
 165         at91sam9261ek_nand_hw_init();
 166 #endif
 167 #ifdef CONFIG_HAS_DATAFLASH
 168         at91sam9261ek_spi_hw_init();
 169 #endif
 170 #ifdef CONFIG_DRIVER_DM9000
 171         at91sam9261ek_dm9000_hw_init();
 172 #endif
 173         return 0;
 174 }
 175
 176 int dram_init(void)
 177 {
 178         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 179         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 180         return 0;
 181 }
 182
 183 #ifdef CONFIG_RESET_PHY_R
 184 void reset_phy(void)
 185 {
 186 #ifdef CONFIG_DRIVER_DM9000
 187         /*
 188          * Initialize ethernet HW addr prior to starting Linux,
 189          * needed for nfsroot
 190          */
 191         eth_init(gd->bd);
 192 #endif
 193 }
 194 #endif