Octeon: Fix interrupt irq settings for performance counters.

[pandora-kernel.git] / arch / mips / include / asm / mach-cavium-octeon / kernel-entry-init.h

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0b2b5eb..dedef7d 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,11 @@
        # CN30XX Disable instruction prefetching
        or  v0, v0, 0x2000
 skip:
+       # First clear off CvmCtl[IPPCI] bit and move the performance
+       # counters interrupt to IRQ 6
+       li      v1, ~(7 << 7)
+       and     v0, v0, v1
+       ori     v0, v0, (6 << 7)
        # Write the cavium control register
        dmtc0   v0, CP0_CVMCTL_REG
        sync