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Octeon: Fix interrupt irq settings for performance counters.
authorChandrakala Chavva <cchavva@caviumnetworks.com>
Thu, 17 Feb 2011 21:57:52 +0000 (13:57 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 19 May 2011 08:55:49 +0000 (09:55 +0100)
commit7716e6548abed1582a7759666e79d5c612a906c7
treeebd12144faf525408ed82f6415804b02ee712440tree | snapshot
parentb32ee693eb106172f89639acff88dc8fee8ba3e2commit | diff
Octeon: Fix interrupt irq settings for performance counters.

Octeon uses different interrupt irq for timer and performance counters.
Set CvmCtl[IPPCI] to correct irq value very early.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/2085/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/setup.c diff | blob | history
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h diff | blob | history
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